JP2007208713A - Digital video display method and device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To cause no distortion in an OSD image, and to use an OSD generation part of a small scale. <P>SOLUTION: A single screen of such video format as an input video signal has is divided into a plurality of sections, depending on the size of OSD image generated by an OSD generator. At the OSD generator, a plurality of OSD images are generated per a single screen of the input video signal, which are allocated to individual split screens. By compositing a plurality of OSD images, an OSD image of one screen amount of the size is generated corresponding to the image format which the input video signal has. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a digital video display method and apparatus capable of generating a larger size OSD image using a small size OSD image and exhibiting the OSD function.

  FIG. 6 shows a schematic configuration of a conventional digital video display device. 10A is a digital tuner, 20 is a video processing unit, and 40 is a display. In the digital tuner 10A, the down converter 11 converts an RF (high frequency) signal input from the outside into an IF (intermediate frequency) signal. The demodulator 12 converts the IF signal into a TS (Transport Stream) signal in which a video signal, an audio signal, SI (System Information) data, and the like are mixed. The demultiplexer 13 decomposes the TS signal to generate a video TS signal, an audio TS signal, and an SI data TS signal. The MPEG video decoder 14 decodes the MPEG video signal to generate an uncompressed video signal. The MPEG audio decoder 15 decodes the MPEG audio signal and outputs an uncompressed audio signal. The CPU 16A analyzes the SI data received from the demultiplexer 13, extracts Closed Caption, program information, and the like, and outputs an OSD image write command to the OSD generation unit 17 based on the extracted information. The OSD generation unit 17 generates an OSD signal S1 containing an OSD image in accordance with a write command from the CPU 16A, and outputs the OSD signal S1 to the OSD synthesis unit 18. The OSD synthesis unit 18 synthesizes and outputs the video signal received from the MPEG video decoder 14 and the OSD signal S1 received from the OSD generation unit 17. The video processing unit 20 converts the video signal received from the OSD synthesis unit 18 into a video signal having a size corresponding to the number of pixels of the fixed pixel display. The display 40 displays an image.

  Here, the operation around the OSD generation unit 17 will be described in detail with reference to FIG. The MPEG video decoder 14 decodes the MPEG video signal in accordance with the video format signal included in the TS signal, and outputs an uncompressed video signal and a synchronization signal. The CPU 16A selects a character font or icon image having a size corresponding to the video format, and writes OSD data to a VRAM (video RAM) 171 according to the video format. The OSD generation unit 17 reads out the OSD image data written in the VRAM 171 by the VRAM reading unit 172 in synchronization with the synchronization signal supplied from the MPEG video decoder 14 via the OSD synthesis unit 18, and sets it as the OSD signal S1. Is output. The OSD synthesizing unit 18 synthesizes both video signals received from the MPEG video decoder 14 and the OSD generating unit 17 by the synthesizing unit 181 and outputs the synthesized video signals to the video processing unit 20.

  As described above, in the conventional digital video display device, since the video processing unit 20 performs processing such as pixel number conversion after the input video signal and the OSD signal S1 are combined, (1) reduction processing is performed. If this happens, the details of the OSD image will be crushed and difficult to read. Conversely, if the enlargement process is performed, blur will occur. (2) Squeeze signal (video signal with an aspect ratio of 16: 9 is horizontal When the image is compressed in the direction and recorded with the aspect ratio of 4: 3) to the original aspect ratio image, the OSD image is also expanded, resulting in a horizontally distorted OSD display. there were.

Therefore, it has been proposed to perform a process of enlarging or reducing the image size of the OSD image in accordance with the image size of the input video signal before performing the OSD composition (see, for example, Patent Document 1). In addition, before performing OSD synthesis, it has been proposed to convert the video format of an input video signal to the video format of the display unit so that the OSD format is the same as that of the display unit (see, for example, Patent Document 2).
JP 2001-016521 A JP 2000-165770 A

  However, the process of enlarging or reducing the OSD image size according to the image size of the input video signal may cause distortion because the vertical / horizontal size ratio of the OSD image differs from the original size ratio depending on the video format. Further, if the video format of the OSD image is the same as that of the display unit, there is a problem that the display quality deteriorates unless the video format of the OSD generation unit is set for high image quality.

  It is an object of the present invention to provide a digital video display method and apparatus which solves the above-mentioned problems by preventing the OSD image quality from deteriorating and allowing a small-scale OSD generator to be used.

In order to achieve the above object, a digital video display method according to a first aspect of the present invention divides one screen of a video format of an input video signal into a plurality of divided screens according to the size of an OSD image generated by an OSD generation unit. The OSD generation unit generates a plurality of OSD images per screen of the input video signal and assigns them individually to the divided screens, and combines the plurality of OSD images to have a size corresponding to the video format of the input video signal. An OSD image for one screen is created.
According to a second aspect of the present invention, in the digital video display method according to the first aspect, when one screen having the size of the video format of the input video signal is divided into a plurality of divided screens, the size of the divided screens is When the size is smaller than the size of the OSD image generated by the OSD generation unit, the OSD generation unit generates an OSD image having a size corresponding to the size of the small divided screen and assigns it to the small size divided screen. It is characterized by.
According to a third aspect of the present invention, in the digital video display method according to the first or second aspect, when the OSD image generated by the OSD generation unit is an interlace method, and the input video signal is a progressive method, The OSD generation unit generates an OSD image having the same contents in odd and even fields.
According to a fourth aspect of the present invention, in the digital video display method according to the first, second, or third aspect, an OSD pixel effective identification is performed on each pixel signal of the OSD image for one screen according to the video format of the input video signal. A signal is included, and the input video signal and the OSD image signal are selected in units of pixels in accordance with the validity / invalidity of the OSD pixel valid identification signal.
According to a fifth aspect of the present invention, there is provided a digital video display device comprising: an OSD generator having a first VRAM into which an OSD image is written; a video processor for processing an input video signal; and an OSD image signal generated by the OSD generator. And an OSD synthesis unit that selects and outputs one of the input video signals output from the video processing unit, wherein the OSD synthesis unit has a second capacity larger than that of the first VRAM. A plurality of OSD images read from the first VRAM are written to the second VRAM a plurality of times, and an OSD image for one screen of the video format of the input video signal is written to the second VRAM. It is characterized by assembly.
According to a sixth aspect of the present invention, in the digital video display device according to the fifth aspect, an area corresponding to the image size of one screen of the input video signal in the second VRAM is defined in the first VRAM. The OSD image is divided into a plurality of areas according to the area size, and OSD images read out from the first VRAM a plurality of times are written in the divided areas.
According to a seventh aspect of the present invention, in the digital video display device according to the sixth aspect, when the divided area of the second VRAM is smaller than the area size of the first VRAM, the small size of the second VRAM. An OSD image corresponding to a divided region having a region size is written in the first VRAM and transferred to the divided region having the smaller region size in the second VRAM.
According to an eighth aspect of the present invention, in the digital video display device according to the fifth, sixth or seventh aspect, the OSD signal generated by the OSD generation unit is an interlace system, and the input video signal is a progressive system. The OSD generator generates an OSD image signal having the same contents in the odd field and the even field.
According to a ninth aspect of the present invention, in the digital video display device according to the sixth, seventh, or eighth aspect, an OSD pixel valid identification signal is included in a signal written to the second VRAM, and the signal is read from the second VRAM. The input video signal output from the video processing unit and the OSD image signal read from the second VRAM are switched in units of pixels and output in accordance with the validity / invalidity of the OSD pixel valid identification signal of the output pixel. Equipped with a video selector

  According to the present invention, one screen of a video format included in the input video signal is divided into a plurality of screens according to the size of the OSD image, an OSD image is assigned to each divided screen, and an OSD image for one screen is synthesized by combining a plurality of OSD images. Therefore, the synthesized OSD image and the image of the input video signal have the same size, and the OSD image quality does not deteriorate. Even if an OSD generator for generating an OSD image is provided with a small-scale VRAM, an OSD image having a large screen size can be synthesized. For example, an OSD image can be displayed on a high-definition display such as 720i and 1080i without being influenced by the video processing unit while using a small OSD generation unit for 480i. Further, the LSI of the video processing circuit for digital television has an advantage that it is easy to implement in many cases having a video output of 480i for VTR.

  Embodiments of the digital video display apparatus according to the present invention will be described below.

  In the first embodiment, when the display 40 is interlaced, the OSD generation unit uses an OSD image of 480i (interlaced video format with 480 vertical effective lines and 720 horizontal effective pixels), A case will be described in which an OSD image of 1080i (interlaced video format having 1080 vertical effective lines and 1920 horizontal effective pixels) is synthesized.

  FIG. 1 shows the configuration of a digital video display apparatus according to this embodiment. This digital video display apparatus is mainly composed of four blocks, and includes a digital tuner 10, a video processing unit 20, an OSD synthesis unit 30, and a display 40.

  Since the downconverter 11, demodulator 12, demultiplexer 13, MPEG video decoder 14, MPEG audio decoder 15, OSD generation unit 17 and display 40 in the digital tuner 10 are the same as those in FIG. Reference numeral 16 denotes a CPU.

  FIG. 2 shows a detailed configuration around the OSD generator 17 in the present embodiment. The CPU 16 analyzes the SI data received from the demultiplexer 13, extracts Closed Caption, program information, etc., generates an OSD image signal divided into a plurality of screens based on the extracted information, and writes it to the VRAM 171 in the OSD generation unit 17. . The CPU 16 further outputs an OSD position signal S2 indicating which division position signal on the screen of the display 40 the OSD data written on the VRAM 171 is. The VRAM reading unit 172 of the OSD generation unit 17 reads and outputs data from the VRAM 171 in synchronization with the synchronization signal of 480i.

  Based on the OSD position signal S2 received from the CPU 16, the OSD synthesis unit 30 writes the data of the OSD signal S1 read from the VRAM 171 into a predetermined area of the VRAM 31 having a larger storage capacity than the VRAM 171 by the VRAM writing unit 32. The data of the OSD signal S1 written here is read by the VRAM reading unit 33 and input to the video selector 34. The video selector 34 selectively outputs the video signal received from the video processing unit 20 based on the OSD selection signal S3 received from the CPU 16.

  Next, the operation of the OSD generation unit 17 and the OSD synthesis unit 30 directly related to the present embodiment will be described in detail. Since the 1080i signal has the number of pixels per line of the effective image as 1920 and the number of lines as described above, in this embodiment, the number of pixels per line of the effective image is 720 and the number of lines is 480. As shown in FIG. 3, the screen of the 1080i signal is divided into nine sections using the 480i OSD image.

  When displaying the OSD image, the CPU 16 first writes the data of the OSD signal S1 corresponding to the partition (0) in FIG. 3 to the VRAM 171 of the OSD generation unit 17 and indicates that the OSD position signal S2 is the partition (0). The signal is output. The OSD generation unit 17 reads the data of the OSD signal S1 written in the VRAM 171 and outputs it to the OSD synthesis unit 30 in synchronization with the synchronization signal of 480i. The OSD synthesis unit 30 receives the data of the OSD signal S1 from the OSD generation unit 17, and writes it into the area corresponding to the partition (0) of FIG. Thereafter, similarly, the CPU 16 sends the data of the OSD signal S1 corresponding to the partitions (1) to (8) to the OSD generation unit 17, and sequentially writes the data in the VRAM 31 of the OSD synthesis unit 30 in the same manner as described above. At this time, if all the pixels of the 480i signal are not used as in the sections (2), (5), (6) to (8), the OSD is displayed on a part of the screen of the 480i signal (for example, the upper left). The image is written, and the data is transferred from the VRAM 171 of the OSD generation unit 17 to the section of the VRAM 31 of the OSD composition unit 30.

  When the writing of the partitions (0) to (8) to the VRAM 31 is completed, the CPU 16 enables the OSD selection signal S3 so that the video selector 34 selects the signal of the VRAM 31 in the OSD synthesis unit 30. Accordingly, when the OSD synthesis unit 30 starts reading of the VRAM 31 by the VRAM readout unit 33, one OSD synthesized with nine OSD images in the VRAM 31 in synchronization with the synchronization signal from the video processing unit 20. An image signal is output. If the CPU 16 invalidates the OSD selection signal S3, the OSD synthesis unit 30 selects and outputs the video signal from the video processing unit 20.

  In the second embodiment, when the display 40 is progressively driven, the OSD image of the OSD generation unit 17 is 480i (interlaced video format with 480 vertical effective lines and 720 horizontal effective pixels), A case where an OSD image of 720p (progressive video format with 720 vertical effective lines and 1280 horizontal effective pixels) is synthesized will be described. The hardware configuration is the same as in FIGS.

  In the present embodiment, using the 480i OSD signal S1, the display area of the display 40 is divided into six sections (0) to (5) as shown in FIG. Originally, the interlaced signal 480i is composed of an odd field and an even field, which are correlated with each other, so that one frame is formed. However, in this example, each field in 480i is treated as 240 lines, 720 independent from each other. Treat as a frame consisting of pixels.

  The operations of the CPU 16, the OSD generation unit 17, and the OSD synthesis unit 30 are linked in the same procedure as in the first embodiment, and the OSD signal S1 data to the partitions (0) to (5) is written into the VRAM of the OSD synthesis unit 30. The unit 32 writes the area corresponding to the partition (0) to (5) of the VRAM 31, reads it from the OSD synthesis unit 30 by the VRAM reading unit 33, and outputs it to the display 40. Since the data of the OSD signal S1 generated in the OSD generator 17 has no correlation between the odd field and the even field, the CPU 16 writes the same OSD signal S1 data in both fields, and the data of which field is the OSD synthesis unit. 17 may be written to the VRAM 171. That is, OSD data that apparently changes by 2 lines is written on the 480i screen.

  In the first and second embodiments, the OSD image or the normal image of the input video signal (the video signal output from the MPEG video decoder 15 and input to the OSD synthesis unit 30 via the video processing unit 20) over the entire screen. The method of selecting and outputting was explained.

  In the third embodiment, the OSD composition unit 30 selects and outputs an OSD image and a normal image for each pixel, thereby displaying an OSD image on a part of the screen and displaying a normal image on the other part. A method will be described. The overall hardware configuration is the same as in FIG. The screen division is the same as in FIG. 3 or FIG.

  FIG. 5 shows a detailed configuration around the OSD generation unit 30 in this embodiment. In the first and second embodiments, the video selector 34 in the OSD synthesis unit 30 indicates whether the pixel of the data written in the VRAM 31 is display valid in addition to the OSD selection signal S3 output from the CPU 16. The difference is that it is also controlled by the identification signal S4.

  In general, the digital video signal is a digital signal having a total of 24 (8 × 3) bits or 30 (10 × 3) bits composed of three RGB (or YCbCr) signals. Since the OSD signal S1 data does not require as many bits as natural images, in this embodiment, the OSD signal S1 data includes the OSD signal S1 data in the upper 7 bits of the 8-bit 3-channel signal. An OSD pixel valid identification signal S4 for identifying whether or not the corresponding pixel has data of the OSD signal S1 is assigned to the lower 1 bit (LSB) of one channel out of the three channels.

  In the present embodiment, the data of the OSD signal S1 including the OSD pixel valid identification signal S4 is written into the VRAM 31 of the OSD synthesis unit 30 by the method described in the first or second embodiment, and corresponds to the screen configuration illustrated in FIG. 3 or FIG. Assemble the OSD image to the contents. When the CPU 16 validates the OSD selection signal S3, the video selector 34 reads the input video signal from the video processing unit 20 or the VRAM 31 for each read pixel in accordance with the OSD pixel valid identification signal S4 output from the VRAM reading unit 33A. The OSD image signal is selected and output. As a result, the OSD video is displayed only on a part of the screen of the display 40, and the input video is displayed on the remaining part.

It is a block diagram which shows schematic structure of the digital video display apparatus of Example 1 of this invention. It is a block diagram which shows the detailed structure of the OSD generation | occurrence | production part and OSD synthetic | combination part in FIG. It is explanatory drawing which divides the image of a 1080i signal into 9 using a 480i signal. It is explanatory drawing which divides the image of a 720p signal into 6 using the 480i signal in Example 2. FIG. FIG. 10 is a block diagram illustrating a detailed configuration of an OSD generation unit and an OSD synthesis unit in the digital video display apparatus according to the third embodiment. It is a block diagram which shows schematic structure of the conventional digital video display apparatus. It is a block diagram which shows the detailed structure of the OSD generating part and OSD synthetic | combination part in FIG.

Explanation of symbols

10, 10A: Digital tuner, 11: Down converter, 12: Demodulator, 13: Demultiplexer, 14: MPEG video decoder, 15: MPEG audio decoder, 16, 16A: CPU, 17: OSD generator, 171: VRAM, 172: VRAM reading unit, 18: OSD combining unit 20: Video processing unit 30: OSD combining unit, 31: VRAM, 32: VRAM writing unit, 33, 33A: VRAM reading unit, 34: Video selector 40: Display

Claims (9)

  The screen of the video format of the input video signal is divided into a plurality of divided screens according to the size of the OSD image generated by the OSD generation unit, and the OSD generation unit generates a plurality of OSD images per screen of the input video signal. A method for displaying a digital video, comprising: assigning each of the divided screens individually, and generating a single screen OSD image having a size corresponding to a video format of the input video signal by combining a plurality of OSD images. The digital video display method according to claim 1,
When dividing one screen of the size of the video format included in the input video signal into a plurality of divided screens, if the size of the divided screen is smaller than the size of the OSD image generated by the OSD generation unit, the OSD A digital video display method characterized in that an OSD image having a size corresponding to the size of the small divided screen is generated by a generating unit and assigned to the small divided screen. The digital video display method according to claim 1 or 2,
When the OSD image generated in the OSD generation unit is an interlace method and the input video signal is a progressive method, the OSD generation unit generates an OSD image having the same contents in the odd field and the even field. A digital video display method characterized by the above. The digital video display method according to claim 1, 2, or 3,
An OSD pixel valid identification signal is included in each pixel signal of the OSD image for one screen according to the video format of the input video signal, and the input video signal and the input signal are determined according to validity / invalidity of the OSD pixel valid identification signal. A digital video display method, wherein an OSD image signal is selected in units of pixels. One of an OSD generation unit having a first VRAM to which an OSD image is written, a video processing unit for processing an input video signal, an OSD image signal generated by the OSD generation unit, and an input video signal output from the video processing unit A digital video display device having an OSD composition unit for selecting and outputting
The OSD synthesis unit includes a second VRAM having a capacity larger than that of the first VRAM, and writes a plurality of OSD images read from the first VRAM to the second VRAM a plurality of times. A digital video display device comprising an OSD image for one screen of the video format of the input video signal in the VRAM. The digital video display device according to claim 5, wherein
In the second VRAM, an area corresponding to the image size of one screen of the input video signal is divided into a plurality of areas according to the area size of the first VRAM, and the first VRAM is divided into the divided individual areas. A digital video display device, in which OSD images read out a plurality of times are respectively written. The digital video display device according to claim 6, wherein
When the divided area of the second VRAM is smaller than the area size of the first VRAM, an OSD image corresponding to the divided area of the small area size of the second VRAM is written into the first VRAM and the 2. A digital video display device, wherein the second VRAM is transferred to the divided region having the small region size. The digital video display device according to claim 5, 6 or 7,
When the OSD signal generated by the OSD generator is an interlace method and the input video signal is a progressive method, the OSD generator generates an OSD image signal having the same contents in odd and even fields. A digital video display device characterized by the above. The digital video display device according to claim 6, 7 or 8,
An OSD pixel valid identification signal is included in the signal written to the second VRAM, and output from the video processing unit in accordance with the validity / invalidity of the OSD pixel valid identification signal of the pixel read from the second VRAM. A digital video display device comprising a video selector for switching and outputting an input video signal to be output and an OSD image signal read from the second VRAM in units of pixels.

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