JP4460359B2 - Video signal processing apparatus and video signal processing method - Google Patents

Description

  The present invention provides a video signal processing apparatus capable of displaying video on the first and second display areas based on the first and second video signals, respectively, and changing the sizes of the first and second display areas, and The present invention relates to a video signal processing method.

  Conventionally, various video signal processing apparatuses having a function of displaying a main screen and a sub-screen on a display have been developed (see, for example, Patent Documents 1 to 3).

In such a video signal processing apparatus, in order to indicate the positions of the main screen and the sub screen, the area signal indicating the boundary between the display area of the main screen and the display area of the sub screen and the display area of the main screen and the sub screen are displayed. A region signal indicating a region to be excluded is used.
Japanese Patent Laid-Open No. 8-181932 JP 2001-157138 A JP 2003-18493 A

  In the above-described conventional video signal processing apparatus, when processing for changing the size of the main screen or sub-screen (hereinafter referred to as resizing) is performed, the number of scanning lines and one line of pixels constituting the main screen or sub-screen The number changes. In that case, it is necessary to reset the area signal based on the number of scanning lines and the number of pixels in one line constituting the resized main screen or sub-screen. This complicates signal processing.

  An object of the present invention is to provide a video signal processing apparatus and a video signal processing method that do not require resetting of signals indicating the first and second display areas after the sizes of the first and second display areas are changed. That is.

  The video signal processing apparatus according to the present invention displays video on the first and second display areas based on the first and second video signals, respectively, and can change the size of the first and second display areas. A first signal generation circuit for generating a first designation signal for designating the position of the first display area, and a second designation signal for designating the position of the second display area The first display area is changed in size to the second signal generating circuit for generating the first video signal and the first designation signal generated by the first video signal and the first signal generating circuit. A first region changing circuit for outputting one video signal and the first designation signal after the change, and a second designation signal generated by the second video signal and the second signal generating circuit. Change the size of the area, and change the second video And a second region change circuit that outputs the changed second designation signal, a first video signal output from the first region change circuit, and a second output from the second region change circuit And a synthesis circuit for synthesizing the video signal.

  In the video signal processing apparatus according to the present invention, a first designation signal for designating a position of the first display area is generated by the first signal generation circuit, and a second display area is generated by the second signal generation circuit. A second designation signal that designates the position is generated. In addition, the first area change circuit performs a process of changing the size of the first display area on the first video signal and the first designation signal, and the changed first video signal and the changed first video signal. A specified signal is output. The second area change circuit performs a process of changing the size of the second display area on the second video signal and the second designation signal, and the second video signal after the change and the second designation signal after the change are displayed. Is output. Further, the first video signal output from the first region change circuit and the second video signal output from the second region change circuit are combined by the combining circuit.

  In this manner, the first display area size changing process is performed on the first video signal, and the first display area size changing process is performed on the first designation signal. A process for changing the size of the second display area is performed, and a process for changing the size of the second display area is performed on the second designation signal. This eliminates the need to set signals indicating the first and second display areas again after changing the sizes of the first and second display areas.

  Further, the signal processing of the first and second display areas can be performed independently using the first and second designation signals after the size of the first and second display areas is changed.

  Further, the first and second designation signals before the change of the sizes of the first and second display areas correspond to the first and second video signals before the change of the sizes of the first and second display areas, respectively. The first and second designation signals after changing the sizes of the first and second display areas correspond to the first and second video signals after changing the sizes of the first and second display areas, respectively. Therefore, the first and second designation signals before changing the sizes of the first and second display areas or the first and second designation signals after changing the sizes of the first and second display areas. By using, it becomes possible to arbitrarily change the order of signal processing in the first and second display areas.

  A first timing generating circuit for generating a first write control signal and a first read control signal based on first information corresponding to a size of the first display area; In response to a first write control signal generated by one timing generation circuit, a first video signal and a first designation signal are stored, and a first read control signal generated by the first timing generation circuit And a first storage device that outputs a first video signal and a first designation signal stored in response to the second area change circuit, wherein the second area change circuit corresponds to a second display area corresponding to the size of the second display area. A second timing generation circuit for generating a second write control signal and a second read control signal based on the information of the second, and a second timing control circuit in response to the second write control signal generated by the second timing generation circuit 2 The video signal and the second designation signal are stored, and the second video signal and the second designation signal stored in response to the second readout control signal generated by the second timing generation circuit are output. 2 storage devices.

  In this case, the first timing generation circuit generates the first write control signal and the first read control signal based on the first information corresponding to the size of the first display area. In response to the first write control signal, the first video signal and the first designation signal are stored by the first storage device, and the first video signal stored in response to the first read control signal and A first designation signal is output. As a result, the processing for changing the size of the first display area is simultaneously performed on the first video signal and the first designation signal.

  The second timing generation circuit generates a second write control signal and a second read control signal based on the second information corresponding to the size of the second display area. In response to the second write control signal, the second video signal and the second designation signal are stored by the second storage device, and the second video signal stored in response to the second read control signal and A second designation signal is output. As a result, the processing for changing the size of the second display area is simultaneously performed on the second video signal and the second designation signal.

  The first region change circuit includes a first multi-value circuit that multi-values the first designation signal generated by the first signal generation circuit, a first video signal, and a first multi-value circuit. A first band limiting circuit that limits the band of the first designation signal obtained by the above and supplies the limited first video signal and first designation signal to the first storage device, and the first storage device And a first binarization circuit for binarizing the first designation signal output from the second region change circuit, wherein the second region change circuit outputs the second designation signal generated by the second signal generation circuit. A second multi-valued circuit for multi-valued, a second video signal and a second designated signal obtained by the second multi-valued circuit are limited, and the limited second video signal and A second band limiting circuit for supplying a second designation signal to the second storage device; and a second finger output from the second storage device. Signal may further include a second binarization circuit for binarizing.

  In this case, the first designation signal is multi-valued by the first multi-value quantization circuit, and the first video signal and the multi-valued first designation signal bandwidth are limited by the first band limiting circuit. The limited first video signal and the first designation signal are supplied to the first storage device. Further, the first designation signal output from the first storage device is binarized by the first binarization circuit.

  In addition, the second multi-valued circuit multi-values the second designation signal, the second band-limiting circuit limits the second video signal and the multi-valued second designated signal band, The limited second video signal and the second designation signal are supplied to the second storage device. Further, the second designation signal output from the second storage device is binarized by the second binarization circuit.

  As described above, since the band limitation and the first display area size changing process are performed on the multi-valued first designation signal in the same manner as the first video signal, the size of the first display area is changed. After the change, the position of the first designation signal does not shift.

  In addition, since the multi-valued second designation signal is subjected to the band limitation and the size change of the second display area in the same manner as the second video signal, the size of the second display area is changed. A position shift of the second designation signal does not occur.

  The first area change circuit corresponds to a first multiplexing circuit that multiplexes the first designation signal generated by the first signal generation circuit into the first video signal, and the size of the first display area. A first timing generation circuit for generating a first write control signal and a first read control signal based on the first information, and a response to the first write control signal generated by the first timing generation circuit The first video signal obtained by the first multiplexing circuit is stored, and the first video signal stored in response to the first read control signal generated by the first timing generation circuit is stored. A first storage device for outputting, and a first separation circuit for separating the first designation signal from the first video signal output from the first storage device, wherein the second region change circuit includes: The second finger generated by the signal generating circuit 2 A second multiplexing circuit for multiplexing the signal to the second video signal, and a second write control signal and a second read control signal based on the second information corresponding to the size of the second display area. A second timing generation circuit that generates the second video signal obtained by the second multiplexing circuit in response to the second write control signal generated by the second timing generation circuit; A second storage device that outputs a second video signal stored in response to a second read control signal generated by the second timing generation circuit, and a second video output from the second storage device And a second separation circuit for separating the second designation signal from the signal.

  In this case, the first designation signal is multiplexed with the first video signal by the first multiplexing circuit, and based on the first information corresponding to the size of the first display area by the first timing generation circuit. A first write control signal and a first read control signal are generated. Further, a first video signal including a first designation signal is stored in response to the first write control signal by the first storage device, and the first video signal stored in response to the first read control signal is stored. A first video signal including the designation signal is output. The first separation signal is separated from the first video signal output from the first storage device by the first separation circuit. As a result, the process of changing the size of the first display area is performed on the first video signal and the first designation signal.

  Further, the second designation signal is multiplexed with the second video signal by the second multiplexing circuit, and the second timing generating circuit multiplexes the second designation signal based on the second information corresponding to the size of the second display area. Two write control signals and a second read control signal are generated. Further, the second storage device stores the second video signal including the second designation signal in response to the second write control signal, and stores the second video signal stored in response to the second read control signal. A second video signal including the designation signal is output. The second designation signal is separated from the second video signal output from the second storage device by the second separation circuit. Thereby, the second display area size changing process is performed on the second video signal and the second designation signal.

  The first region change circuit includes a first multi-value circuit that multi-values the first designation signal generated by the first signal generation circuit, a first video signal, and a first multi-value circuit. A first band limiting circuit for limiting the band of the first designated signal obtained by the step (1) and supplying the restricted first video signal and the first designated signal to the first multiplexing circuit; And a first binarization circuit that binarizes the first designation signal output from the circuit, wherein the second region change circuit includes a second designation signal generated by the second signal generation circuit. A second multi-valued circuit that multi-values the second video signal and the second video signal and the second designated signal obtained by the second multi-valued circuit are limited to limit the second video signal. And a second band limiting circuit for supplying the second designation signal to the second multiplexing circuit, and a second output from the second separation circuit. The designation signal may further include a second binarization circuit for binarizing.

  In this case, the first designation signal is multi-valued by the first multi-value quantization circuit, and the first video signal and the multi-valued first designation signal bandwidth are limited by the first band limiting circuit. The limited first video signal and the first designation signal are supplied to the first multiplexing circuit. Furthermore, the first designation signal output from the first separation circuit is binarized by the first binarization circuit.

  In addition, the second multi-valued circuit multi-values the second designation signal, the second band-limiting circuit limits the second video signal and the multi-valued second designated signal band, The limited second video signal and the second designation signal are supplied to the second multiplexing circuit. Further, the second designation signal output from the second separation circuit is binarized by the second binarization circuit.

  As described above, since the band limitation and the first display area size changing process are performed on the multi-valued first designation signal in the same manner as the first video signal, the size of the first display area is changed. After the change, the position of the first designation signal does not shift.

  In addition, since the multi-valued second designation signal is subjected to the band limitation and the size change of the second display area in the same manner as the second video signal, the size of the second display area is changed. A position shift of the second designation signal does not occur.

  The first designation signal generated by the first signal generation circuit has a first value at a position corresponding to the first display area, and a second value at a position corresponding to an area other than the first display area. The second designation signal generated by the second signal generation circuit has a first value at a position corresponding to the second display area, and is in an area other than the second display area. It may have a second value at the corresponding position.

  In this case, the position of the first display area is designated by the first and second values of the first designation signal. Further, the position of the second display area is designated by the first and second values of the second designation signal. Therefore, it is possible to easily change the size of the first display area together with the first video signal in the first designation signal, and the second display area together with the second video signal in the second designation signal. The size change process can be easily performed.

  The first designation signal includes a first horizontal designation signal that designates a horizontal range of the first display area, and a first vertical designation signal that designates a vertical range of the first display area. The second designation signal includes a second horizontal designation signal that designates a horizontal range of the second display area, and a second vertical designation signal that designates the vertical range of the second display area. May be included.

  In this case, the horizontal range of the first display area is designated by the first horizontal designation signal, and the vertical range of the first display area is designated by the first vertical designation signal. Thereby, the position of the first display area can be easily specified before the change of the size of the first display area and after the change of the size of the first display area.

  Further, the horizontal range of the second display area is designated by the second horizontal designation signal, and the vertical range of the second display area is designated by the second vertical designation signal. Thereby, the position of the second display area can be easily specified before the change of the size of the second display area and after the change of the size of the second display area.

  A video signal processing apparatus is a processing circuit that performs one or more signal processing based on a first designation signal obtained by a first area change circuit and a second designation signal obtained by a second area change circuit May be further provided.

  In this case, one or more signal processes are performed by the processing circuit based on the first designation signal obtained by the first area changing circuit and the second designation signal obtained by the second area changing circuit. Therefore, after changing the sizes of the first and second display areas, signal processing of the first and second display areas can be performed independently using the changed first and second designation signals.

  Further, the first and second designation signals before the change of the sizes of the first and second display areas or the first and second designation signals after the change of the sizes of the first and second display areas are used. Thus, the order of signal processing in the first and second display areas can be arbitrarily changed.

  Based on the first designation signal obtained by the first area changing circuit and the second designation signal obtained by the second area changing circuit, the video signal processing device has a first display area with the first designation signal. You may further provide the display apparatus which displays a 2nd video signal as a video in a 2nd display area while displaying a video signal as a video.

  In this case, the first and second display areas are displayed by the display device, and the sizes of the first and second display areas can be changed. Further, by using the first and second designation signals after changing the sizes of the first and second display areas, the signal processing of the first and second display areas can be performed independently.

  The video signal processing method according to the present invention displays video on the first and second display areas based on the first and second video signals, respectively, and changes the sizes of the first and second display areas. A method for processing a video signal, the step of generating a first specification signal for specifying the position of a first display region, the step of generating a second specification signal for specifying the position of a second display region, Performing a process of changing the size of the first display area on the first video signal and the generated first designation signal, and outputting the first video signal after the change and the first designation signal after the change; Performing a process of changing the size of the second display area on the second video signal and the generated second designation signal, and outputting the second video signal after the change and the second designation signal after the change And the output first video signal It is obtained by a step of synthesizing the second image signal force.

  In the video signal processing method according to the present invention, a first designation signal for designating the position of the first display area is generated, and a second designation signal for designating the position of the second display area is generated. In addition, the first display area is changed in size for the first video signal and the first designation signal, and the first video signal after the change and the first designation signal after the change are output. A process of changing the size of the second display area is performed on the second video signal and the second designation signal, and the second video signal after the change and the second designation signal after the change are output. Further, the output first video signal and the output second video signal are combined.

  In this manner, the first display area size changing process is performed on the first video signal, and the first display area size changing process is performed on the first designation signal. A process for changing the size of the second display area is performed, and a process for changing the size of the second display area is performed on the second designation signal. This eliminates the need to set signals indicating the first and second display areas again after changing the sizes of the first and second display areas.

  Further, the signal processing of the first and second display areas can be performed independently using the first and second designation signals after the size of the first and second display areas is changed.

  Further, the first and second designation signals before the change of the sizes of the first and second display areas correspond to the first and second video signals before the change of the sizes of the first and second display areas, respectively. The first and second designation signals after changing the sizes of the first and second display areas correspond to the first and second video signals after changing the sizes of the first and second display areas, respectively. Therefore, the first and second designation signals before changing the sizes of the first and second display areas or the first and second designation signals after changing the sizes of the first and second display areas. By using, it becomes possible to arbitrarily change the order of signal processing in the first and second display areas.

  According to the present invention, it is not necessary to set signals indicating the first and second display areas again after changing the sizes of the first and second display areas.

  Further, the signal processing of the first and second display areas can be performed independently using the first and second designation signals after the size of the first and second display areas is changed.

  Further, the first and second designation signals before changing the sizes of the first and second display areas or the first and second designation signals after changing the sizes of the first and second display areas are used. Thus, the signal processing order of the first and second display areas can be arbitrarily changed.

(1) First Embodiment FIG. 1 is a block diagram showing a configuration of a video signal processing apparatus according to a first embodiment of the present invention.

  1 includes a video / region flag resizing circuit (hereinafter abbreviated as a resizing circuit) 1, a video synthesis circuit 2, a color adjustment / offset adjustment circuit (hereinafter abbreviated as an adjustment circuit) 3, an APL ( Average image level) A luminance value / histogram calculation circuit (hereinafter abbreviated as calculation circuit) 4, a horizontal / vertical enhancer 5, a side blanking addition circuit 6, an error diffusion circuit 7, a drive circuit 8 and a display panel 9.

  This video signal processing apparatus has a function of displaying a main screen and a sub screen on the screen of the display panel 9 and a function of performing a process of changing the sizes of the main screen and the sub screen (hereinafter referred to as resize). Have.

  The resizing circuit 1 performs resizing processing on the video signal VDm for the main screen and the video signal VDs for the sub screen, and outputs the resized main screen video signal VDm1 and the resized sub screen video signal VDs1. To do. In addition, the resizing circuit 1 performs resizing processing on the area flags representing the areas of the main screen and the sub screen, and outputs area flags FLVm1, FLHm1, FLVs1, and FLHs1 for the main screen and the sub screen after the resizing. Details of the resizing circuit 1 will be described later. Region flags FLVm1, FLHm1, FLVs1, and FLHs1 are applied to adjustment circuit 3, calculation circuit 4, horizontal / vertical enhancer 5, side blanking addition circuit 6, error diffusion circuit 7, and drive circuit 8.

  The video synthesis circuit 2 synthesizes the video signals VDm1 and VDs1 output from the resizing circuit 1 and gives the synthesized video signal VD to the adjustment circuit 3.

  The adjustment circuit 3 performs color adjustment and offset adjustment of the main screen and the sub screen based on the composite video signal VD, and supplies the adjusted video signal VD1 to the calculation circuit 4.

  The calculation circuit 4 calculates the APL (average image level) of the main screen and the sub screen based on the video signal VD1, and calculates a histogram indicating the luminance distribution of the main screen and the sub screen, and the main screen based on the APL and the histogram. Then, the luminance level and luminance distribution of the sub-screen are controlled, and the controlled video signal VD2 is supplied to the horizontal / vertical enhancer 5.

  The horizontal / vertical enhancer 5 performs contour correction of the main screen and the sub-screen based on the video signal VD 2, and supplies the corrected video signal VD 3 to the side blanking addition circuit 6.

  The side blanking addition circuit 6 performs processing for adding a side blanking region to the main screen and the sub screen based on the video signal VD3, and gives the processed video signal VD4 to the error diffusion circuit 7.

  The error diffusion circuit 7 performs error diffusion processing on the main screen and the sub screen based on the video signal VD4, and gives the processed video signal VD5 to the drive circuit 8.

  The drive circuit 8 gives a drive signal DV to the display panel 9 based on the video signal VD5. Thereby, the video is displayed on the main screen and the sub screen of the display panel 9, respectively.

  The display panel 9 is, for example, a plasma display panel, a liquid crystal display panel, or a CRT (cathode ray tube).

  The order of the adjustment circuit 3, the calculation circuit 4, the horizontal / vertical enhancer 5, the side blanking addition circuit 6, and the error diffusion circuit 7 is not limited to the order shown in FIG.

  FIG. 2 is a diagram showing the relationship between the main screen, the sub-screen, and the area flag. In FIG. 2, a main screen display area 100 m is set in the video valid area 200, and a sub-screen display area 100 s is set in the video valid area 201.

  The area flag FLHm defines the horizontal range of the main screen display area 100m, and the area flag FLVm defines the vertical range of the main screen display area 100m. That is, the area flag FLHm is logic “1” (high level) within the horizontal range of the main screen display area 100 m, and the area flag FLHm is logic “0” (low) outside the horizontal range of the main screen display area 100 m. Level). In addition, the area flag FLVm is logic “1” (high level) within the vertical range of the main screen display area 100m, and the area flag FLVm is logic “0” (low) outside the vertical range of the main screen display area 100m. Level).

  In addition, the horizontal range of the sub-screen display area 100s is defined by the area flag FLHs, and the vertical range of the sub-screen display area 100s is defined by the area flag FLVs. That is, the area flag FLHs is logical “1” (high level) within the horizontal range of the sub-screen display area 100s, and the area flag FLHs is logical “0” (low) outside the horizontal range of the sub-screen display area 100s. Level). In addition, the area flag FLVs is logic “1” (high level) within the vertical range of the sub-screen display area 100s, and the area flag FLVs is logic “0” (low) outside the vertical range of the sub-screen display area 100s. Level).

  Note that the logic “1” and “0” of the region flags FLVm, FLHm, FLVs, and FLHs may be reversed.

  FIG. 3 is a block diagram mainly showing the configuration of the resizing circuit 1 of FIG.

  The resizing circuit 1 includes a main screen resizing circuit 11, a sub screen resizing circuit 12, a main screen region flag generating circuit 13 and a sub screen region flag generating circuit 14.

  The main screen area flag generation circuit 13 is supplied with a main screen horizontal synchronizing signal HSm, a main screen vertical synchronizing signal VSm, start position set values SHm and SVm, and end position set values EHm and EVm.

  The start position set value SHm indicates the horizontal start position (left end position) of the main screen display area 100m, and the start position set value SVm indicates the vertical start position (upper end position) of the main screen display area 100m. The end position setting value EHm indicates the horizontal end position (right end position) of the main screen display area 100m, and the end position set value EVm indicates the vertical end position (lower end position) of the main screen display area 100m. ).

  The main screen area flag generation circuit 13 generates area flags FLHm and FLVm for the main screen based on the horizontal synchronization signal HSm, the vertical synchronization signal VSm, the start position setting values SHm and SVm, and the end position setting values EHm and EVm.

  The main screen resizing circuit 11 is supplied with the enlargement / reduction ratio ERm for the main screen and the video signal VDm for the main screen, and the region flags FLHm and FLVm generated by the main screen region flag generating circuit 13.

  The enlargement / reduction ratio ERm for the main screen is a ratio between the size after the resizing of the main screen display area 100m and the size before the resizing of the main screen display area 100m. In the present embodiment, the horizontal and vertical scaling factors ERm are common, but the horizontal and vertical scaling factors may be set independently.

  The main screen resizing circuit 11 performs a resizing process on the main screen video signal VDm and area flags FLHm and FLVm based on the enlargement / reduction ratio ERm, and outputs the resized main screen video signal VDm1 and area flags FLHm1 and FLVm1. To do.

  Here, in the main screen resizing process, the size of the main screen display area 100m is changed by increasing or decreasing the number of scanning lines and the number of pixels of one line constituting the main screen display area 100m.

  The area flag FLHm1 defines the horizontal range of the resized main screen display area 100m, and the area flag FLVm1 defines the vertical range of the resized main screen display area 100m.

  The sub-screen area flag generation circuit 14 is supplied with a sub-screen horizontal synchronizing signal HSs, a sub-screen vertical synchronizing signal VSs, start position set values SHs and SVs, and end position set values EHs and EVs.

  The start position set value SHs indicates the horizontal start position (left end position) of the sub-screen display area 100s, and the start position set value SVs indicates the vertical start position (upper end position) of the sub-screen display area 100s. The end position setting value EHs indicates the horizontal end position (right end position) of the sub-screen display area 100s, and the end position setting value EVs indicates the vertical end position (lower end position) of the sub-screen display area 100s. ).

  The sub-screen area flag generation circuit 14 generates sub-screen area flags FLHs and FLVs based on the horizontal synchronization signal HSs, the vertical synchronization signal VSs, the start position setting values SHs and SVs, and the end position setting values EHs and EVs.

  The sub-screen resizing circuit 12 is supplied with the sub-screen enlargement / reduction ratio ERs and the sub-screen video signal VDs, as well as the region flags FLHs and FLVs generated by the sub-screen region flag generating circuit 13.

  The sub screen enlargement / reduction ratio ERs is a ratio of the size after the resizing of the sub screen display area 100s to the size of the sub screen display area 100s before the resizing.

  The sub-screen resizing circuit 12 performs resizing processing on the sub-screen video signal VDs and the area flags FLHs and FLVs based on the enlargement / reduction ratio ERs, and outputs the sub-screen video signal VDs1 and area flags FLHs1 and FLVs1 after resizing. To do.

  Here, in the sub-screen resizing process, the size of the sub-screen display area 100s is changed by increasing or decreasing the number of scanning lines and the number of pixels of one line constituting the sub-screen display area 100s.

  The area flag FLHs1 defines the horizontal range of the resized sub-screen display area 100s, and the area flag FLVs1 defines the vertical range of the re-sized sub-screen display area 100s.

  The video synthesis circuit 2 synthesizes the video signal VDm1 output from the main screen resizing circuit 11 and the video signal VDs1 output from the sub-screen resizing circuit 12, and outputs a synthesized video signal VD.

  4A is a block diagram showing a configuration of the main screen area flag generation circuit 13 in FIG. 3, and FIG. 4B is a block diagram showing a configuration of the sub screen area flag generation circuit 14 in FIG.

  As shown in FIG. 4A, the main screen area flag generation circuit 13 includes counters 130 and 132 and selectors 131 and 133.

  The counter 130 counts the pulses of the clock signal CLK for each horizontal scanning period based on the horizontal synchronization signal HSm for the main screen, and gives the count value to the input terminal P of the selector 131. The input terminal Q of the selector 131 is given a start position set value SHm, and the input terminal R is given an end position set value EHm.

  The selector 131 sets the region flag FLHm to logic “1” (high level) when the count value of the input terminal P is equal to or larger than the start position set value SHm of the input terminal Q and smaller than the end position set value EHm of the input terminal R. Otherwise, the region flag FLHm is set to logic “0” (low level).

  The counter 132 counts the pulse of the horizontal synchronizing signal HSm for each vertical scanning period based on the main screen vertical synchronizing signal VSm, and gives the count value to the input terminal P of the selector 133. The input position Q of the selector 133 is given a start position set value SVm, and the input terminal R is given an end position set value EVm.

  The selector 133 sets the area flag FLVm to logic “1” (high level) when the count value of the input terminal P is equal to or larger than the start position set value SVm of the input terminal Q and smaller than the end position set value EVm of the input terminal R. Otherwise, the region flag FLVm is set to logic “0” (low level).

  As shown in FIG. 4B, the sub-screen area flag generation circuit 14 includes counters 140 and 142 and selectors 141 and 143.

  The counter 140 counts the pulses of the clock signal CLK every horizontal scanning period based on the horizontal synchronization signal HSs for the sub-screen, and gives the count value to the input terminal P of the selector 141. A start position set value SHs is given to the input terminal Q of the selector 141, and an end position set value EHs is given to the input terminal R.

  The selector 141 sets the region flag FLHs to logic “1” (high level) when the count value of the input terminal P is equal to or larger than the start position set value SHs of the input terminal Q and smaller than the end position set value EHs of the input terminal R. Otherwise, the region flag FLHs is set to logic “0” (low level).

  The counter 142 counts the pulses of the horizontal synchronization signal HSs for each vertical scanning period based on the vertical synchronization signal VSs for the sub screen, and gives the count value to the input terminal P of the selector 143. The input terminal Q of the selector 143 is given a start position set value SVs, and the input terminal R is given an end position set value EVs.

  The selector 143 sets the region flag FLVs to logic “1” (high level) when the count value of the input terminal P is not less than the start position set value SVs of the input terminal Q and smaller than the end position set value EVs of the input terminal R. Otherwise, the region flag FLVs is set to logic “0” (low level).

  FIG. 5 is a block diagram showing a configuration of the main screen resizing circuit 11 of FIG.

  The main screen resizing circuit 11 in FIG. 5 includes multi-value quantization circuits 111 and 112, band limiting filters 113, 114 and 115, memories 116, 117 and 118, binarization circuits 120 and 121, and a timing generation circuit 122.

  The timing generation circuit 122 responds to the scaling ratio ERm, the clock signal CLK, the horizontal synchronization signal HSm, and the vertical synchronization signal VSm, in a horizontal direction write enable signal WEH, a horizontal direction read enable signal REH, and a vertical direction write enable signal. WEV and vertical read enable signal REV are generated.

  The band limiting filter 113 limits the band of the video signal VDm for the main screen and supplies the video signal VDm0 to the memory 116. The video signal VDm0 is written to the memory 116 in response to the write enable signals WEH and WEV, and the video signal VDm0 stored in the memory 116 is read as the video signal VDm1 in response to the read enable signals REH and REV.

  In this way, the resizing process of the video signal VDm is performed, and the resized video signal VDm1 is output.

  The multi-value quantization circuit 111 multi-values the region flag FLHm and gives the multi-value region flag FLHma to the band limiting filter 114. The band limiting filter 114 limits the band of the area flag FLHma and supplies the area flag FLHmb to the memory 117. In response to the write enable signal WEH, the region flag FLHmb is written into the memory 117, and in response to the read enable signal REH, the region flag FLHmb stored in the memory 117 is read out as the region flag FLHmc. The binarization circuit 120 binarizes the area flag FLHmc read from the memory 117 and outputs a binary area flag FLHm1.

  In this way, the resize processing of the area flag FLHm is performed, and the resized area flag FLHm1 is obtained.

  The multi-value conversion circuit 112 multi-values the region flag FLVm and supplies the multi-value region flag FLVma to the band limiting filter 115. The band limiting filter 115 limits the band of the area flag FLVma and gives the area flag FLVmb to the memory 118. In response to the write enable signal WEV, the region flag FLVmb is written to the memory 118, and in response to the read enable signal REV, the region flag FLVmb stored in the memory 118 is read as the region flag FLVmc. The binarization circuit 121 binarizes the area flag FLVmc read from the memory 118 and outputs a binary area flag FLVm1.

  In this way, the resize processing of the area flag FLVm is performed, and the resized area flag FLVm1 is obtained.

  The sub-screen resizing circuit 12 in FIG. 3 has the same configuration and operation as the main screen resizing circuit 11 in FIG. 5 except for signals given to the respective units. In FIG. 5, signals given to the sub-screen resizing circuit 12 are shown in parentheses.

  The timing generation circuit 122 is supplied with a scaling ratio ERs, a clock signal CLK, a horizontal synchronization signal HSs, and a vertical synchronization signal VSs.

  The band limiting filter 113 is supplied with the video signal VDs for the sub screen, the video signal VDs0 is supplied from the band limiting filter 113 to the memory 116, and the video signal VDs0 stored in the memory 116 is read as the video signal VDs1. It is.

  The multilevel circuit 111 is provided with a region flag FLHs, the multilevel circuit 111 is provided with a region flag FLHsa, and the band limit filter 114 is provided with a region flag FLHsb. The area flag FLHsb stored in is read as the area flag FLHsc. The binarization circuit 120 is given the region flag FLHsc read from the memory 117, and the binarization circuit 120 outputs the region flag FLHs 1.

  The multilevel circuit 112 is given a region flag FLVs, the multilevel circuit 112 is given a region flag FLVsa to the band limiting filter 115, and the band limiting filter 115 is given a region flag FLVsa to the memory 118. The area flag FLVsb stored in is read as the area flag FLVsc. The binarization circuit 121 is given the region flag FLVsc read from the memory 118, and the binarization circuit 121 outputs the region flag FLVs1.

  FIG. 6 is a timing chart showing an example of signals in the main screen resizing circuit 11 of FIG. FIG. 6 shows a case where the horizontal direction of the main screen display area 100m is resized at a scaling factor ERm of 1/2.

  The video signal VDm is supplied to the band limiting filter 113 in synchronization with the clock signal CLK. The video signal VDm includes values “0”, “y1” to “y10”.

  Region flag FLHm is applied to multilevel circuit 111. The area flag FLHm changes from logic “0” (low level) to logic “1” (high level) at the horizontal start position of the main screen display area 100m.

  A multi-value area flag FLHma is output from the multi-value circuit 111. Region flag FLHma includes values “0” and “128”. The multi-value region flag FLHma is given to the band limiting filter 114.

  On the other hand, the video signal VDm0 output from the band limiting filter 113 includes values “0”, “y1 ″”, and “y1 ′” to “y10 ′”. The region flag FLHmb output from the band limiting filter 114 includes values “0”, “32”, “96”, and “128”.

  The write enable signal WEH changes at a cycle twice that of the clock signal CLK. When the write enable signal WEH is at a high level, the video signal VDm0 is written into the memory 116 and the region flag FLHmb is written into the memory 117. When the read enable signal REH is at a high level, the video signal VDm0 in the memory 116 is read as the video signal VDm1, and the area flag FLHmb in the memory 117 is read as the area flag FLHmc.

  The video signal VDm1 includes values “0”, “y1 ′”, “y3 ′”, “y5 ′”, “y7 ′”, “y9 ′”. The region flag FLHmc includes values “0”, “96”, and “128”.

  Region flag FLHmc is applied to binarization circuit 120. The region flag FLHm1 output from the binarization circuit 120 includes logic “0” (low level) and logic “1” (high level).

  In this manner, the region flag FLHm is resized together with the video signal VDm, and the region flag FLHm1 is obtained together with the resized video signal VDm1.

  As described above, according to the resizing circuit 1 in the present embodiment, the resizing processing of the area flags FLHm, FLVm, FLHs, and FLVs is performed together with the resizing processing of the video signals VDm and VDs. This eliminates the need to set the region flag again after resizing the main screen and the sub screen.

  Therefore, after the main screen and the sub screen are resized, the signal processing of the main screen and the sub screen can be performed independently by using the resized area flags FLHm1, FLVm1, FLHs1, and FLVs1 in the subsequent circuit.

  Also, the area flags FLHm, FLVm, FLHs, FLVs before resizing correspond to the video signals VDm, VDs before resizing, and the area flags FLHm1, FLVm1, FLHs1, FLVs1 after resizing correspond to the video signals VDm1, VDs1 after resizing. Therefore, the order of signal processing on the main screen and the sub-screen can be arbitrarily changed by using the area flags FLHm, FLVm, FLHs, FLVs, FLHm1, FLVm1, FLHs1, and FLVs1 before or after resizing. It becomes.

  Further, by using the resized area flags FLHm1, FLVm1, FLHs1, and FLVs1, it is possible to unify the processing ranges of the main screen, the sub-screen, and the side blanking area throughout the video signal processing apparatus.

  FIG. 7 is a diagram for explaining the operation of the adjustment circuit 3 of FIG.

  As described above, the resized region flags FLHm1, FLVm1, FLHs1, and FLVs1 are supplied to the adjustment circuit 3. Thereby, the adjustment circuit 3 identifies the main screen display area 100m in the video valid area 200 and the sub-screen display area 100s in the video valid area 201 based on the resized area flags FLHm1, FLVm1, FLHs1, and FLVs1. be able to.

  Therefore, as shown in FIG. 7, the adjustment circuit 3 can independently perform color adjustment and offset value adjustment of the video signal VD in the main screen display area 100m and color adjustment and offset value adjustment in the sub-screen display area 100s. it can.

  FIG. 8 is a diagram for explaining the operation of the calculation circuit 4 of FIG. In the example of FIG. 8A, the main screen display area 100m is set in the video effective area 200, and the sub-screen display area 100s is set in the video effective area 201. In the example of FIG. 8B, a main screen display area 100 m and a sub screen display area 100 s are set in the video effective area 200.

  As described above, the calculation circuit 4 is provided with the resized region flags FLHm1, FLVm1, FLHs1, and FLVs1. Accordingly, in the example of FIG. 8A, the calculation circuit 4 has the main screen display area 100m and the video valid area 201 in the video valid area 200 based on the resized area flags FLHm1, FLVm1, FLHs1, and FLVs1. Can be identified. In the example of FIG. 8B, the calculation circuit 4 calculates the main screen display area 100m and the sub screen display area 100s in the video effective area 200 based on the resized area flags FLHm1, FLVm1, FLHs1, and FLVs1. Can be identified.

  Therefore, the calculation circuit 4 can independently calculate the APL and the luminance distribution indicating the luminance distribution of the main screen display area 100m and the APL and the histogram indicating the luminance distribution of the sub-screen display area 100s, respectively. Correction of the luminance level and luminance distribution of the area 100m and correction of the luminance level and luminance distribution of the sub-screen display area 100s can be performed independently.

  In particular, the calculation circuit 4 can select a mode that includes the luminance of the sub-screen display area 100s and a mode that does not include the luminance of the sub-screen display area 100s when calculating the APL of the entire screen. Further, the calculation circuit 4 can select a mode that includes the luminance of the sub-screen display area 100s and a mode that does not include the luminance of the sub-screen display area 100s when calculating a histogram indicating the luminance distribution of the entire screen.

  Furthermore, the calculation circuit 4 selects a mode for correcting the luminance or luminance distribution of the sub-screen display area 100s and a mode for not correcting the luminance or luminance distribution of the sub-screen display area 100s when correcting the luminance level or luminance distribution. be able to.

  9 and 10 are diagrams for explaining the operation of the horizontal / vertical enhancer 5 shown in FIG. In the lower part of FIGS. 9 and 10, a gain signal GP indicating the degree of enhancement of the video signal is shown.

  In the example of FIG. 9, the main screen display area 100 m is set in the video effective area 200, and the sub-screen display area 100 s is set in the video effective area 201. In the example of FIG. 10, a main screen display area 100 m and a sub screen display area 100 s are set in the video effective area 200.

  As described above, the resized region flags FLHm1, FLVm1, FLHs1, and FLVs1 are given to the horizontal and vertical enhancer 5. Accordingly, the horizontal / vertical enhancer 5 identifies the main screen display area 100m in the video effective area 200 and the sub-screen display area 100s in the video effective area 201 based on the resized area flags FLHm1, FLVm1, FLHs1, and FLVs1. can do.

  Accordingly, as shown in FIGS. 9 and 10, the horizontal / vertical enhancer 5 has the main screen display area 100m and the sub screen display in the areas e1, e2, and e3 at the boundary between the main screen display area 100m and the sub screen display area 100s. The gain signal GP can be controlled so that the outline of the region 100s is not emphasized. For example, the level of the gain signal GP can be continuously decreased from both ends to the boundary line in a region having a constant width (for example, 4 pixels) centered on the boundary line. Accordingly, the outline is not emphasized at the boundary between the main screen display area 100m and the sub screen display area 100s, and the images of the main screen display area 100m and the sub screen display area 100s change smoothly at the boundary.

  FIG. 11 is a diagram for explaining the operation of the side blanking addition circuit 6 of FIG.

  As described above, the re-sized region flags FLHm1, FLVm1, FLHs1, and FLVs1 are supplied to the side blanking addition circuit 6. Thereby, the side blanking addition circuit 6 can identify the main screen display area 100m and the sub-screen display area 100s in the video effective area 201 based on the resized area flags FLHm1, FLVm1, FLHs1, and FLVs1. .

  Therefore, as shown in FIG. 11, the side blanking addition circuit 6 can add the side blanking area 300 to an area excluding the main screen display area 100m and the sub screen display area 100s. In the side blanking region 300, for example, a black background is displayed.

  12 and 13 are diagrams for explaining operations of the side blanking addition circuit 6 and the error diffusion circuit 7 of FIG.

  As described above, the re-sized region flags FLHm1, FLVm1, FLHs1, and FLVs1 are supplied to the side blanking addition circuit 6 and the error diffusion circuit 7. Accordingly, the side blanking addition circuit 6 and the error diffusion circuit 7 can identify the main screen display area 100m and the sub screen display area 100s based on the resized area flags FLHm1, FLVm1, FLHs1, and FLVs1.

  Therefore, in the example of FIG. 12, the side blanking addition circuit 6 can add the side blanking area 300 to an area excluding the main screen display area 100m and the sub screen display area 100s, and the error diffusion circuit 7 Except for the blanking area 300, error diffusion processing can be performed on the main screen display area 100m and the sub-screen display area 100s.

  In the example of FIG. 13, the error diffusion circuit 7 sets the start point of the error diffusion area 400 to the upper left position of the main screen display area 100m. This prevents the influence of error diffusion from appearing in the upper left corner of the main screen display area 100m. In this case, the side blanking addition circuit 6 can set the side blanking region 300 outside the error diffusion region 400.

  In the present embodiment, the main screen area flag generation circuit 13 corresponds to the first signal generation circuit, the sub screen area flag generation circuit 14 corresponds to the second signal generation circuit, and the main screen resize circuit 11 corresponds to the first signal generation circuit. The sub-screen resizing circuit 12 corresponds to the second area changing circuit, and the video composition circuit 2 corresponds to the composition circuit. The timing generation circuit 122 corresponds to first and second timing generation circuits, and the memories 116 to 118 correspond to first and second storage devices. Further, the multi-value quantization circuits 111 and 112 correspond to the first and second multi-value quantization circuits, the band limitation filters 113 to 115 correspond to the first and second band limitation circuits, and the binarization circuit 120, 121 corresponds to the first and second binarization circuits.

  The resizing circuit 1 constitutes first and second region changing circuits, and the adjusting circuit 3, the calculating circuit 4, the horizontal / vertical enhancer 5, the side blanking adding circuit 6 and the error diffusion circuit 7 correspond to a processing circuit, The drive circuit 8 and the display panel 9 correspond to a display device.

  The main screen display area 100m corresponds to the first display area, the sub screen display area 100s corresponds to the second display area, and the main screen video signals VDm and VDm1 correspond to the first video signal. The sub-screen video signals VDs and VDs1 correspond to the second video signal, the region flags FLVm, FLHm, FLVm1 and FLHm1 correspond to the first designation signal, and the region flags FLVs, FLHs, FLVs1 and FLHs1 correspond to the first. 2, the scaling ratio ERm corresponds to the first information, the scaling ratio ERs corresponds to the second information, and the write enable signals WEV and WEV correspond to the first and second write control signals. The read enable signals REH and REV correspond to the first and second read control signals.

(2) Second Embodiment The video signal processing apparatus according to the second embodiment of the present invention differs from the video signal processing apparatus according to the first embodiment in that the main screen resizing circuit 11 and the sub-screen This is the configuration of the resizing circuit 12.

  FIG. 14 is a block diagram showing the configuration of the main screen resizing circuit 11 in the video signal processing apparatus according to the second embodiment.

  In the main screen resizing circuit 11 of FIG. 14, a multiplexing circuit 123 and a separation circuit 124 are further provided. A band limiting filter 125 is provided instead of the band limiting filters 113 to 115 in FIG. 5, and a memory 126 is provided instead of the memories 116 to 118.

  The multiplexing circuit 123 multiplexes the region flag FLHma given from the multi-valued circuit 111 and the region flag FLVma given from the multi-valued circuit 112 to the video signal VDm for the main screen, and band the multiplexed video signal VDm2 This is given to the limiting filter 125.

  The band limiting filter 125 limits the band of the video signal VDm 2 and supplies the video signal VDm 3 to the memory 126. In response to the write enable signals WEH and WEV, the video signal VDm3 is written into the memory 126, and in response to the read enable signals REH and REV, the video signal VDm3 stored in the memory 126 is read out as the video signal VDm4.

  The separation circuit 124 separates the region flags FLHmc and FLVmc from the video signal VDm4 read from the memory 126, and outputs the video signal VDm1 and the region flags FLHmc and FLVmc.

  The binarization circuit 120 binarizes the region flag FLHmc output from the separation circuit 124 and outputs a binary region flag FLHm1. The binarization circuit 121 binarizes the region flag FLVmc output from the separation circuit 124 and outputs a binary region flag FLVm1.

  In this way, the resizing process of the video signal VDm is performed, and the resized video signal VDm1 is output. In addition, the area flags FLHm and FLVm are resized, and the resized area flags FLHm1 and FLVm1 are obtained.

  The sub-screen resizing circuit 12 in the second embodiment has the same configuration and operation as the main screen resizing circuit 11 of FIG. 14 except for signals given to the respective units. In FIG. 14, signals given to the sub-screen resizing circuit 12 are shown in parentheses.

  The timing generation circuit 122 is supplied with a scaling ratio ERs, a clock signal CLK, a horizontal synchronization signal HSs, and a vertical synchronization signal VSs.

  The multi-value quantization circuit 111 is given a region flag FLHs, and the multi-value digitization circuit 112 is given a region flag FLVs. The multiplexing circuit 123 is supplied with the video signal VDs for the sub screen, the region flag FLHsa from the multi-level circuit 111, and the region flag FLVsa from the multi-level circuit 112.

  The band limiting filter 125 is supplied with the multiplexed video signal VDs2 from the multiplexing circuit 123, the band limiting filter 125 is supplied with the video signal VDs3 to the memory 126, and the video signal VDs3 stored in the memory 126 is the video signal. Read as VDs4.

  The video signal VDs4 read from the memory 126 is supplied to the separation circuit 124, the video signal VDs1 is output from the separation circuit 124, the region flag FLHsc is supplied to the binarization circuit 120, and the binarization circuit 121 is supplied. A region flag FLVsc is provided. The binarization circuit 120 outputs a region flag FLHs1, and the binarization circuit 121 outputs a region flag FLVs1.

  FIG. 15 is a timing chart showing an example of signals in the main screen resizing circuit 11 of FIG. FIG. 15 shows a clock signal CLK and a video signal VDm2 multiplexed with a plurality of lines. m, n, and k are each an arbitrary integer.

  In the example of FIG. 15, a multi-valued area flag FLHma is multiplexed on the video signal of the nth line. Region flag FLHma includes values “0” and “128”. In addition, a multi-value region flag FLVma is multiplexed on the m-th pixel of the video signals of the n-th line to the (k + 2) -th line. Region flag FLVma includes values “0” and “128”.

  In this way, the region flags FLHma and FLVma are multiplexed with the video signal VDm2.

  FIG. 16 is a diagram showing multiplexing of video signals and area flags in the main screen resizing circuit 11 of FIG. FIG. 17 is a diagram showing resizing processing and separation of video signals and area flags in the main screen resizing circuit 11 of FIG. 16 and 17 show a main screen display area 100m, a horizontal synchronization signal HSm, and a vertical synchronization signal VSm.

  First, as shown in the upper part of FIG. 16, a main screen video signal VDm and area flags FLHm and FLVm are applied. The area flags FLHm and FLVm are multiplexed with the main screen video signal VDm, and the video signal VDm2 shown in the lower part of FIG. 16 is obtained.

  Next, a resize process is performed on the video signal VDm2, and a resized video signal VDm4 is obtained as shown in the upper part of FIG. Further, the resized area flags FLHm1 and FLVm1 shown in the lower part of FIG. 17 are separated from the video signal VDm4.

  As described above, according to the resizing circuit 1 in the present embodiment, the resizing processing of the area flags FLHm, FLVm, FLHs, and FLVs is performed together with the resizing processing of the video signals VDm and VDs. This eliminates the need to set the region flag again after resizing the main screen and the sub screen.

  Therefore, after the main screen and the sub screen are resized, the signal processing of the main screen and the sub screen can be performed independently by using the resized area flags FLHm1, FLVm1, FLHs1, and FLVs1 in the subsequent circuit.

  Also, the area flags FLHm, FLVm, FLHs, FLVs before resizing correspond to the video signals VDm, VDs before resizing, and the area flags FLHm1, FLVm1, FLHs1, FLVs1 after resizing correspond to the video signals VDm1, VDs1 after resizing. Therefore, the order of signal processing on the main screen and the sub-screen can be arbitrarily changed by using the area flags FLHm, FLVm, FLHs, FLVs, FLHm1, FLVm1, FLHs1, and FLVs1 before or after resizing. It becomes.

  Further, by using the resized area flags FLHm1, FLVm1, FLHs1, and FLVs1, it is possible to unify the processing ranges of the main screen, the sub-screen, and the side blanking area throughout the video signal processing apparatus.

  In this embodiment, the multiplexing circuit 123 corresponds to first and second multiplexing circuits, the separation circuit 124 corresponds to first and second separation circuits, and the memory 126 stores first and second memories. The band limiting filter 125 corresponds to the first and second band limiting circuits.

  The present invention can be used in various video signal processing devices such as a television receiver using a CRT (cathode ray tube), a plasma display device, and a liquid crystal display device.

1 is a block diagram showing a configuration of a video signal processing apparatus according to a first embodiment of the present invention. Diagram showing the relationship between the main screen, subscreen, and area flag FIG. 1 is a block diagram mainly showing the configuration of the resizing circuit. 3 is a block diagram showing the configuration of the main screen area flag generation circuit in FIG. 3 and the block diagram showing the configuration of the sub screen area flag generation circuit in FIG. The block diagram which shows the structure of the main screen resizing circuit of FIG. FIG. 5 is a timing chart showing an example of signals in the main screen resizing circuit of FIG. The figure for demonstrating operation | movement of the adjustment circuit of FIG. The figure for demonstrating operation | movement of the calculation circuit of FIG. The figure for demonstrating operation | movement of the horizontal / vertical enhancer of FIG. The figure for demonstrating operation | movement of the horizontal / vertical enhancer of FIG. The figure for demonstrating operation | movement of the side blanking addition circuit of FIG. The figure for demonstrating operation | movement of the side blanking addition circuit and error diffusion circuit of FIG. The figure for demonstrating operation | movement of the side blanking addition circuit and error diffusion circuit of FIG. The block diagram which shows the structure of the main screen resizing circuit in the video signal processing apparatus which concerns on 2nd Embodiment. 14 is a timing chart showing an example of signals in the main screen resizing circuit of FIG. The figure which shows the multiplexing of the video signal and area flag in the main screen resizing circuit of FIG. The figure which shows the resize process in the main screen resize circuit of FIG. 14, and isolation | separation of a video signal and an area flag

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image | video / area flag resizing circuit 2 Image composition circuit 3 Color adjustment / offset adjustment circuit 4 APL luminance value / histogram calculation circuit 5 Horizontal / vertical enhancer 6 Side blanking addition circuit 7 Error diffusion circuit 8 Drive circuit 9 Display panel 11 Main screen resizing Circuit 12 Sub-screen resizing circuit 13 Main screen area flag generating circuit 14 Sub-screen area flag generating circuit 130, 132, 140, 142 Counter 131, 133, 141, 143 Selector 100m Main screen display area 100s Sub-screen display area 200, 201 Video Effective region VDm, VDm0, VDm1, VDm2, VDm3 Video signal for main screen VDs, VDs0, VDs1, VDs2, VDs3 Video signal for sub-screen VD Composite video signal VD1, VD2, VD3, VD4, VD5 Video signal DV drive No. FLVm, FLVm1, FLVma, FLVmb, FLVmc, FLHm, FLHm1, FLHmb, FLHmc, FLHmc, FLVs, FLVs1, FLVsa, FLVsb, FLVsc, FLHs, FLHs1, FLHsa, FLHsb, FLHsc ERm area ERm Horizontal synchronization signal for HSs Horizontal synchronization signal for sub screen VSm Vertical synchronization signal for main screen VSs Vertical synchronization signal for sub screen CLK clock signal WEH Horizontal write enable signal REH Horizontal read enable signal WEV Vertical write enable signal REV Vertical read Enable signal

Claims (10)

A video signal processing apparatus that displays video on the first and second display areas based on the first and second video signals, respectively, and is capable of changing the size of the first and second display areas,
A first signal generation circuit for generating a first designation signal for designating a position of the first display area;
A second signal generation circuit for generating a second designation signal for designating a position of the second display area;
The first display signal is changed in size to the first video signal and the first designation signal generated by the first signal generation circuit, and the changed first video signal and the changed first video signal are changed. A first region changing circuit that outputs a designation signal of
The second display area is changed in size to the second video signal and the second designation signal generated by the second signal generation circuit, the changed second video signal and the changed second video signal. A second region changing circuit that outputs a designation signal of
Video signal processing comprising: a synthesis circuit for synthesizing the first video signal output from the first area change circuit and the second video signal output from the second area change circuit apparatus. The first region change circuit includes:
A first timing generation circuit for generating a first write control signal and a first read control signal based on first information corresponding to a size of the first display area;
In response to the first write control signal generated by the first timing generation circuit, the first video signal and the first designation signal are stored, and the first timing signal generated by the first timing generation circuit is stored. A first storage device that outputs a first video signal and a first designation signal stored in response to the read control signal;
The second region change circuit includes:
A second timing generation circuit for generating a second write control signal and a second read control signal based on second information corresponding to the size of the second display area;
A second video signal and a second designation signal are stored in response to the second write control signal generated by the second timing generation circuit, and the second video signal generated by the second timing generation circuit is stored. The video signal processing apparatus according to claim 1, further comprising: a second storage device that outputs a second video signal and a second designation signal stored in response to the read control signal. The first region change circuit includes:
A first multi-valued circuit that multi-values the first designation signal generated by the first signal generating circuit;
Bands of the first video signal and the first designation signal obtained by the first multilevel circuit are limited, and the limited first video signal and first designation signal are stored in the first storage device. A first band limiting circuit for
A first binarization circuit that binarizes the first designation signal output from the first storage device;
The second region change circuit includes:
A second multi-valued circuit that multi-values the second designation signal generated by the second signal generating circuit;
The second video signal and the second designation signal obtained by the second multilevel circuit are limited in bandwidth, and the limited second video signal and second designation signal are stored in the second storage device. A second band limiting circuit for
The second video signal processing apparatus according to claim 1 or 2, wherein the second designation signal, characterized in that it further includes a second binarization circuit for binarizing the output from the storage device. The first region change circuit includes:
A first multiplexing circuit that multiplexes a first designation signal generated by the first signal generation circuit into a first video signal;
A first timing generation circuit for generating a first write control signal and a first read control signal based on first information corresponding to a size of the first display area;
A first video signal obtained by the first multiplexing circuit is stored in response to a first write control signal generated by the first timing generation circuit, and is generated by the first timing generation circuit. A first storage device for outputting a first video signal stored in response to the read first read control signal;
A first separation circuit for separating a first designation signal from a first video signal output from the first storage device;
The second region change circuit includes:
A second multiplexing circuit that multiplexes a second designation signal generated by the second signal generation circuit into a second video signal;
A second timing generation circuit for generating a second write control signal and a second read control signal based on second information corresponding to the size of the second display area;
A second video signal obtained by the second multiplexing circuit is stored in response to a second write control signal generated by the second timing generation circuit, and is generated by the second timing generation circuit. A second storage device for outputting a second video signal stored in response to the second read control signal,
The video signal processing apparatus according to claim 1, further comprising: a second separation circuit that separates a second designation signal from the second video signal output from the second storage device. The first region change circuit includes:
A first multi-valued circuit that multi-values the first designation signal generated by the first signal generating circuit;
The first video signal and the first designated signal obtained by the first multilevel circuit are limited in bandwidth, and the limited first video signal and first designated signal are multiplexed in the first A first band limiting circuit applied to the circuit;
A first binarization circuit that binarizes the first designation signal output from the first separation circuit;
The second region change circuit includes:
A second multi-valued circuit that multi-values the second designation signal generated by the second signal generating circuit;
The second video signal and the second designated signal obtained by the second multilevel circuit are limited in bandwidth, and the limited second video signal and second designated signal are multiplexed in the second A second band limiting circuit applied to the circuit;
5. The video signal processing apparatus according to claim 4, further comprising a second binarization circuit that binarizes the second designation signal output from the second separation circuit. The first designation signal generated by the first signal generation circuit has a first value at a position corresponding to the first display area, and a position corresponding to an area other than the first display area. And has a second value,
The second designation signal generated by the second signal generation circuit has a first value at a position corresponding to the second display area, and a position corresponding to an area other than the second display area. The video signal processing apparatus according to claim 1, wherein the video signal processing apparatus has a second value. The first designation signal includes a first horizontal designation signal that designates a horizontal range of the first display area, and a first vertical designation signal that designates a vertical range of the first display area. Including
The second designation signal includes a second horizontal designation signal that designates a horizontal range of the second display area, and a second vertical designation signal that designates a vertical range of the second display area. The video signal processing apparatus according to claim 1, comprising: And a processing circuit that performs one or more signal processing based on the first designation signal obtained by the first area change circuit and the second designation signal obtained by the second area change circuit. The video signal processing apparatus according to claim 1, wherein the video signal processing apparatus is a video signal processing apparatus. Based on the first designation signal obtained by the first area change circuit and the second designation signal obtained by the second area change circuit, a first video signal is displayed on the first display area. The video signal processing apparatus according to claim 1, further comprising a display device that displays the second video signal as a video in the second display area. A video signal processing method capable of displaying video on the first and second display areas based on the first and second video signals, respectively, and changing the size of the first and second display areas,
Generating a first designation signal for designating a position of the first display area;
Generating a second designation signal for designating a position of the second display area;
A step of changing the size of the first display area on the first video signal and the generated first designation signal, and outputting the changed first video signal and the changed first designation signal When,
A step of changing the size of the second display area on the second video signal and the generated second designation signal, and outputting the second video signal after the change and the second designation signal after the change. When,
A video signal processing method comprising: a step of synthesizing the output first video signal and the output second video signal.

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