JP2007208161A - Manufacturing method of semiconductor device and semiconductor substrate - Google Patents

Manufacturing method of semiconductor device and semiconductor substrate Download PDF

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Publication number
JP2007208161A
JP2007208161A JP2006027880A JP2006027880A JP2007208161A JP 2007208161 A JP2007208161 A JP 2007208161A JP 2006027880 A JP2006027880 A JP 2006027880A JP 2006027880 A JP2006027880 A JP 2006027880A JP 2007208161 A JP2007208161 A JP 2007208161A
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insulating film
interlayer insulating
semiconductor substrate
film
polishing
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Hiroshi Oshita
博史 大下
Kenji Kobayashi
健司 小林
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Renesas Technology Corp
Panasonic Holdings Corp
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Renesas Technology Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device, in which a laminated film including an inter-layer insulating film is prevented from peeling at a wafer end edge part in the manufacturing process of the semiconductor device using the inter-layer insulating film of low adhesion, and to provide a semiconductor substrate. <P>SOLUTION: When removing the inter-layer insulating film 4 formed on a bevel part BV1, polishing is performed to a part indicated by a line L1, and not only the inter-layer insulating film 4 but also a part of the semiconductor substrate 1 are removed. An angle α formed by the line L1 with the main surface of the semiconductor substrate 1 is set to be >0° and ≤30° and is appropriately set matched with the angle of the bevel part BV1 of the semiconductor substrate 1. A polishing drum RD is constituted by sticking polishing cloth to the side face of a cylindrical drum, and polishing is performed by pressing the polishing drum RD to the end edge part of the semiconductor substrate 1 while rotating the drum around a center shaft and also rotating the semiconductor substrate 1 in-plane. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は半導体装置の製造方法および半導体基板に関し、特に層間絶縁膜の平坦化プロセスにおける薄膜剥離の防止処理および薄膜剥離を防止した半導体基板に関する。   The present invention relates to a method of manufacturing a semiconductor device and a semiconductor substrate, and more particularly to a thin film peeling prevention process and a semiconductor substrate in which thin film peeling is prevented in an interlayer insulating film planarization process.

半導体素子の集積度が高くなった近年の半導体装置においては、配線層を多層化した多層配線構造が採用されている。   In recent semiconductor devices in which the degree of integration of semiconductor elements has increased, a multilayer wiring structure in which wiring layers are multilayered is employed.

多層配線においては、配線層間に層間絶縁膜を配設しているが、層間絶縁膜上に配線層を形成する際には、層間絶縁膜をＣＭＰ（Chemical Mechanical Polishing）処理等の平坦化技術を用いて平坦化することが一般的に行われている。   In multilayer wiring, an interlayer insulating film is disposed between wiring layers. However, when forming a wiring layer on the interlayer insulating film, a planarization technique such as CMP (Chemical Mechanical Polishing) is applied to the interlayer insulating film. It is generally performed to flatten by using.

ＣＭＰ処理を施す場合に、ウエハ端縁部と、ウエハを保持しているリング状保持具の内壁とが接触すると、ウエハ端縁部に存在する層間絶縁膜が剥離することがある。   When the CMP process is performed, if the wafer edge and the inner wall of the ring-shaped holder holding the wafer come into contact with each other, the interlayer insulating film existing on the wafer edge may be peeled off.

また、ウエハ運搬時に搬送用カセットの溝に、ウエハ端縁部に存在する層間絶縁膜が接触するなどして圧力が加わった場合にも層間絶縁膜の剥離が発生する。   In addition, the interlayer insulating film is peeled off when a pressure is applied to the groove of the transfer cassette when the wafer is transported by contact with the interlayer insulating film existing at the edge of the wafer.

ここで、特許文献１には、ウエハの側面のラウンド部分において薄膜が剥離して、異物の発生源となることを防止するために、ウエハの側面のラウンド部分に形成された薄膜を、ＣＭＰ処理に先立って機械的に研磨する技術が開示されている。   Here, in Patent Document 1, in order to prevent the thin film from peeling off at the round portion on the side surface of the wafer and becoming a source of foreign matter, the thin film formed on the round portion on the side surface of the wafer is subjected to CMP treatment. Prior to this, a technique of mechanical polishing is disclosed.

特開2002-313757号公報（図１〜図７）JP 2002-313757 A (FIGS. 1 to 7)

以上説明したように、従来はウエハの側面の薄膜を研磨することで、側面に形成された薄膜が剥離することを防止しているが、発明者達はこれだけでは薄膜の剥離を完全に防止できないという知見を得た。   As described above, conventionally, the thin film on the side surface of the wafer is polished to prevent the thin film formed on the side surface from peeling, but the inventors cannot completely prevent the peeling of the thin film by itself. I got the knowledge.

すなわち、近年では層間絶縁膜の比誘電率を低くする傾向にあるが、比誘電率の低下に伴って層間絶縁膜の疎水性が高まり、疎水性が高まるにつれて層間絶縁膜どうしや、層間絶縁膜と他の膜との密着性が低下し、また膜強度も低下することが確認されている。   That is, in recent years, there is a tendency to lower the relative dielectric constant of the interlayer insulating film. However, as the relative dielectric constant decreases, the hydrophobicity of the interlayer insulating film increases, and as the hydrophobicity increases, the interlayer insulating films and interlayer insulating films are increased. It has been confirmed that the adhesion between the film and other films decreases and the film strength also decreases.

このような密着性の低い層間絶縁膜に対してＣＭＰ処理を施すと、ウエハ端縁部に存在する層間絶縁膜が剥離することが予想されるので、ＣＭＰ処理に先立って、ウエハ端縁部に存在する層間絶縁膜を研磨除去したが、発明者達の試験では、いわゆるＬｏｗ−ｋ膜と呼称される比誘電率が２．９以下の層間絶縁膜を含んだ積層膜に対してＣＭＰ処理を施した場合、ＣＭＰ処理の研磨条件における研磨圧力を低くしても剥離をゼロにすることはできなかった。   When CMP processing is performed on such an interlayer insulating film having low adhesion, it is expected that the interlayer insulating film existing at the edge of the wafer is peeled off. Although the existing interlayer insulating film was removed by polishing, in the inventors' tests, a CMP process was performed on a laminated film including an interlayer insulating film having a relative dielectric constant of 2.9 or less, which is called a so-called Low-k film. When applied, the peeling could not be made zero even if the polishing pressure was lowered under the CMP treatment polishing conditions.

この原因としては、従来の方法では層間絶縁膜の端面が、ウエハの素子形成主面（すなわち主面）に対して５°〜７５°の角度を有して傾斜したテーパー面となるように研磨を行うが、このようにテーパーを付けたとしても層間絶縁膜の傾斜端面とウエハ主面との間には段差が存在するので、当該段差に起因して層間絶縁膜が剥離するものと考えられる。   This is because, in the conventional method, the end surface of the interlayer insulating film is polished so as to be a tapered surface inclined at an angle of 5 ° to 75 ° with respect to the element formation main surface (ie, main surface) of the wafer. However, even if the taper is applied in this way, there is a step between the inclined end surface of the interlayer insulating film and the main surface of the wafer, and it is considered that the interlayer insulating film is peeled off due to the step. .

本発明は上記のような問題点を解消するためになされたもので、密着性の低い層間絶縁膜を使用する半導体装置の製造過程において、ウエハ端縁部で層間絶縁膜を含む積層膜が剥離することを防止した半導体装置の製造方法および半導体基板を得ることを目的とする。   The present invention has been made to solve the above-described problems. In the manufacturing process of a semiconductor device using an interlayer insulating film with low adhesion, the laminated film including the interlayer insulating film is peeled off at the edge of the wafer. It is an object of the present invention to obtain a semiconductor device manufacturing method and a semiconductor substrate which are prevented from being formed.

本発明に係る請求項１記載の半導体装置の製造方法は、半導体基板上に層間絶縁膜を間に介して配線層が多層に配設された多層配線構造の半導体装置の製造方法であって、前記半導体基板の上方に前記層間絶縁膜を形成する工程(ａ)と、前記層間絶縁膜上に導体膜を形成して前記配線層を形成する工程(ｂ)とを備え、前記工程(ａ)は、前記半導体基板の端縁部において、半導体素子が形成される素子形成主面側の前記層間絶縁膜および前記半導体基板の一部を除去して、当該除去の結果得られる前記層間絶縁膜の端面および前記半導体基板のエッジ部を少なくとも含んで構成される面が、前記素子形成主面に対して０°よりも大きく３０°以下の角度の傾斜を有するように加工する工程(ａ−１)を含み、前記工程(ｂ)は、前記端縁部において、前記素子形成主面側の少なくとも前記導体膜の一部を除去して、当該除去の結果得られる前記導体膜の端面、前記層間絶縁膜の端面および前記半導体基板のエッジ部を少なくとも含んで構成される面が、前記素子形成主面に対して０°よりも大きく３０°以下の角度の傾斜を有するように加工する工程(ｂ−１)を含んでいる。   A method for manufacturing a semiconductor device according to claim 1 of the present invention is a method for manufacturing a semiconductor device having a multilayer wiring structure in which wiring layers are arranged in multiple layers on a semiconductor substrate with an interlayer insulating film therebetween. A step (a) of forming the interlayer insulating film above the semiconductor substrate; and a step (b) of forming a conductive film on the interlayer insulating film to form the wiring layer. Is formed by removing a portion of the interlayer insulating film on the element formation main surface side where the semiconductor element is formed and a part of the semiconductor substrate at an edge portion of the semiconductor substrate, and removing the interlayer insulating film obtained as a result of the removal. A step (a-1) of processing so that an end surface and a surface including at least the edge portion of the semiconductor substrate have an inclination of an angle greater than 0 ° and 30 ° or less with respect to the element formation main surface; And the step (b) includes the step of: At least a part of the conductor film on the element formation main surface side is removed, and at least an end face of the conductor film obtained as a result of the removal, an end face of the interlayer insulating film, and an edge portion of the semiconductor substrate are included. A step (b-1) of processing so that the surface has an inclination of an angle greater than 0 ° and 30 ° or less with respect to the element formation main surface.

本発明に係る請求項９記載の半導体基板は、層間絶縁膜を間に介して配線層が多層に配設された多層配線構造の半導体装置を有した半導体基板であって、前記半導体基板の端縁部において、半導体素子が形成される素子形成主面側の前記層間絶縁膜の端面および前記半導体基板のエッジ部を少なくとも含んで構成される一面が、前記素子形成主面に対して０°よりも大きく３０°以下の角度の傾斜を有している。   According to a ninth aspect of the present invention, there is provided a semiconductor substrate having a semiconductor device having a multilayer wiring structure in which wiring layers are arranged in multiple layers with an interlayer insulating film interposed therebetween, the end of the semiconductor substrate being In the edge portion, one surface including at least the end surface of the interlayer insulating film on the element formation main surface side on which the semiconductor element is formed and the edge portion of the semiconductor substrate is from 0 ° with respect to the element formation main surface. And has an inclination of an angle of 30 ° or less.

本発明に係る請求項１記載の半導体装置の製造方法によれば、ＣＭＰ処理の対象となる層間絶縁膜や導体膜等の研磨対象膜が、半導体基板の端縁部にも形成されている場合、層間絶縁膜の端面および半導体基板のエッジ部を少なくとも含んで構成される面が、素子形成主面に対して０°よりも大きく３０°以下の角度の傾斜を有するように加工し、また、導体膜の端面、層間絶縁膜の端面および半導体基板のエッジ部を少なくとも含んで構成される面が、素子形成主面に対して０°よりも大きく３０°以下の角度の傾斜を有するように加工することで、研磨対象膜と下部層との間で段差が生じることが防止され、研磨対象膜に対して面内方向の応力が加わりにくくなる。このため、層間絶縁膜としてＳｉＯＣ膜等の、いわゆるＬｏｗ−ｋ膜を使用した場合でも、ＣＭＰ処理に際して当該層間絶縁膜が剥離することを防止できる。   According to the method for manufacturing a semiconductor device according to claim 1 of the present invention, the polishing target film such as an interlayer insulating film or a conductor film to be subjected to the CMP process is also formed on the edge portion of the semiconductor substrate. The surface including at least the end face of the interlayer insulating film and the edge portion of the semiconductor substrate is processed so as to have an inclination of an angle greater than 0 ° and not more than 30 ° with respect to the element formation main surface. Processing is performed so that the end surface of the conductor film, the end surface of the interlayer insulating film, and the surface including at least the edge portion of the semiconductor substrate have an inclination of an angle greater than 0 ° and not more than 30 ° with respect to the element formation main surface. By doing so, it is possible to prevent a step between the polishing target film and the lower layer, and it is difficult to apply stress in the in-plane direction to the polishing target film. Therefore, even when a so-called Low-k film such as a SiOC film is used as the interlayer insulating film, it is possible to prevent the interlayer insulating film from being peeled off during the CMP process.

本発明に係る請求項９記載の半導体基板によれば、半導体基板の端縁部において、半導体素子が形成される素子形成主面側の層間絶縁膜の端面および半導体基板のエッジ部を少なくとも含んで構成される一面が、素子形成主面に対して０°よりも大きく３０°以下の角度の傾斜を有しているので、層間絶縁膜と半導体基板との間で段差が生じることが防止され、層間絶縁膜に対して面内方向の応力が加わりにくくなる。このため、層間絶縁膜としてＳｉＯＣ膜等の、いわゆるＬｏｗ−ｋ膜を使用した場合でも、ＣＭＰ処理に際して当該層間絶縁膜が剥離することを防止できる。   According to the semiconductor substrate of the ninth aspect of the present invention, the edge portion of the semiconductor substrate includes at least the edge surface of the interlayer insulating film on the element formation main surface side where the semiconductor element is formed and the edge portion of the semiconductor substrate. Since the formed surface has an inclination of an angle greater than 0 ° and 30 ° or less with respect to the element formation main surface, it is possible to prevent a step from being generated between the interlayer insulating film and the semiconductor substrate, In-plane stress is less likely to be applied to the interlayer insulating film. Therefore, even when a so-called Low-k film such as a SiOC film is used as the interlayer insulating film, it is possible to prevent the interlayer insulating film from being peeled off during the CMP process.

＜実施の形態＞
＜Ａ．製造方法＞
本発明に係る実施の形態の半導体装置の製造方法について、図１〜図１７を用いて説明する。 <Embodiment>
<A. Manufacturing method>
A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS.

図１に、シリコン基板等の半導体基板１上にＭＯＳトランジスタ３が配設された構成を示している。なお、ＭＯＳトランジスタ３は、半導体基板１上に配設される半導体集積回路を構成する半導体素子の一例である。   FIG. 1 shows a configuration in which a MOS transistor 3 is disposed on a semiconductor substrate 1 such as a silicon substrate. The MOS transistor 3 is an example of a semiconductor element that forms a semiconductor integrated circuit disposed on the semiconductor substrate 1.

ＭＯＳトランジスタ３は、素子分離絶縁膜２で規定される活性領域に、半導体基板１上にゲート絶縁膜３１を介して配設されたゲート電極３２と、ゲート電極３２の側面に配設されたサイドウォール絶縁膜３３と、ゲート電極３２のゲート長方向の両側面外方の半導体基板１の表面内にそれぞれ配設されたソース・ドレイン層３４とを有して構成されている。なお、ＭＯＳトランジスタ３等の半導体素子は周知の技術により形成するので、製造方法の説明は省略する。   The MOS transistor 3 includes a gate electrode 32 disposed on the semiconductor substrate 1 via a gate insulating film 31 in an active region defined by the element isolation insulating film 2, and a side disposed on a side surface of the gate electrode 32. The wall insulating film 33 and the source / drain layers 34 respectively disposed in the surface of the semiconductor substrate 1 outside both side surfaces of the gate electrode 32 in the gate length direction are configured. Since semiconductor elements such as the MOS transistor 3 are formed by a known technique, description of the manufacturing method is omitted.

そして、ＭＯＳトランジスタ３を覆うように半導体基板１上に層間絶縁膜４が配設されている。ここで、層間絶縁膜４は、例えばプラズマＣＶＤ法で形成された比誘電率２．９〜２．７のＳｉＯＣ（カーボン含有ＳｉＯ2）膜で形成されている。 An interlayer insulating film 4 is disposed on the semiconductor substrate 1 so as to cover the MOS transistor 3. Here, the interlayer insulating film 4 is formed of, for example, a SiOC (carbon-containing SiO 2 ) film having a relative dielectric constant of 2.9 to 2.7 formed by a plasma CVD method.

なお、比誘電率２．９以下の、いわゆるＬｏｗ−ｋ膜を層間絶縁膜として使用することで、配線容量を低下させて半導体装置の動作を高速化することができる。   Note that by using a so-called Low-k film having a relative dielectric constant of 2.9 or less as an interlayer insulating film, the wiring capacitance can be reduced and the operation of the semiconductor device can be speeded up.

層間絶縁膜４は、ＭＯＳトランジスタ３等の半導体基板１上に配設された構成により凹凸を有しており、ＣＭＰ（Chemical Mechanical Polishing）処理等の平坦化処理を行うが、その前に、半導体基板１のエッジ研磨を行う。   The interlayer insulating film 4 has irregularities due to the configuration disposed on the semiconductor substrate 1 such as the MOS transistor 3 and is subjected to a planarization process such as a CMP (Chemical Mechanical Polishing) process. Edge polishing of the substrate 1 is performed.

図２は、層間絶縁膜４が形成された状態の半導体基板１の全体を示す断面図である。
図２に示すように、半導体基板１の２つの主面のうち、半導体素子が配設される側の主面（素子形成主面）上には層間絶縁膜４が配設され、その反対側の主面（裏面）には層間絶縁膜４は配設されていない。 FIG. 2 is a cross-sectional view showing the entire semiconductor substrate 1 with the interlayer insulating film 4 formed thereon.
As shown in FIG. 2, an interlayer insulating film 4 is disposed on the main surface (element formation main surface) on the side where the semiconductor element is disposed, out of the two main surfaces of the semiconductor substrate 1, and on the opposite side. The interlayer insulating film 4 is not disposed on the main surface (back surface).

図２において領域“Ａ”として示す端縁部の詳細を図３に示す。
図３に示すように半導体基板１の端縁部は、半導体基板１の素子形成主面側および反対主面（裏面）側にそれぞれ設けられ、主面に対して傾斜したベベル部ＢＶ１およびＢＶ２と、ベベル部ＢＶ１およびＢＶ２に連続する半導体基板１の最外周面ＴＰとを有している。 FIG. 3 shows details of the edge portion shown as the region “A” in FIG.
As shown in FIG. 3, the edge portions of the semiconductor substrate 1 are provided on the element formation main surface side and the opposite main surface (back surface) side of the semiconductor substrate 1, respectively, and bevel portions BV1 and BV2 inclined with respect to the main surface; And the outermost peripheral surface TP of the semiconductor substrate 1 continuous with the bevel portions BV1 and BV2.

層間絶縁膜４は半導体基板１の素子形成主面からベベル部ＢＶ１および最外周面ＴＰにかけて形成されている。ベベル部ＢＶ１および最外周面ＴＰに形成された層間絶縁膜４が剥離しやすいとされている。   The interlayer insulating film 4 is formed from the element formation main surface of the semiconductor substrate 1 to the bevel portion BV1 and the outermost peripheral surface TP. It is supposed that the interlayer insulating film 4 formed on the bevel portion BV1 and the outermost peripheral surface TP is easy to peel off.

そこで、図４に示すように、研磨ドラムＲＤを用いて半導体基板１の端縁部に形成された層間絶縁膜４を研磨して除去する。   Therefore, as shown in FIG. 4, the interlayer insulating film 4 formed on the edge portion of the semiconductor substrate 1 is polished and removed using a polishing drum RD.

この研磨においては、ベベル部ＢＶ１上に形成された層間絶縁膜４を除去する際には、図４にラインＬ１で示す部分まで研磨を行い、層間絶縁膜４だけでなく半導体基板１の一部も除去するものとする。   In this polishing, when the interlayer insulating film 4 formed on the bevel portion BV1 is removed, the polishing is performed up to the portion indicated by the line L1 in FIG. Shall also be removed.

ここで、ラインＬ１が半導体基板１の主面となす角度αは０°よりも大きく３０°以下に設定され、半導体基板１のベベル部ＢＶ１の角度に合わせて適宜設定される。   Here, the angle α formed by the line L1 with the main surface of the semiconductor substrate 1 is set to be greater than 0 ° and 30 ° or less, and is appropriately set according to the angle of the bevel portion BV1 of the semiconductor substrate 1.

また、研磨ドラムＲＤは、円筒状のドラムの側面に研磨布を貼り付けて構成され、ドラムを中心軸の回りに回転させるとともに半導体基板１も面内回転させながら、研磨ドラムＲＤを半導体基板１の端縁部に押し当てることで研磨を行う。   The polishing drum RD is configured by attaching a polishing cloth to the side surface of a cylindrical drum. The polishing drum RD is rotated around the central axis and the semiconductor substrate 1 is also rotated in-plane while the polishing drum RD is moved to the semiconductor substrate 1. Polishing is performed by pressing against the edge of the surface.

なお、研磨に際しては、シリカ、酸化アルミナおよびセリア等の砥粒を溶剤に混ぜたスラリを研磨部分に供給しながら行うが、これらのスラリは、研磨対象膜をＣＭＰ処理する際に使用されるスラリでもあり、研磨対象膜に合わせて新たに調整する必要もないので、製造コストの増加を抑制することができる。   In polishing, a slurry in which abrasive grains such as silica, alumina oxide, and ceria are mixed with a solvent is supplied to the polishing portion. These slurries are used for CMP processing of a film to be polished. However, since it is not necessary to make a new adjustment according to the film to be polished, an increase in manufacturing cost can be suppressed.

ベベル部ＢＶ１上に形成された層間絶縁膜４を研磨した後は、図５に示す工程において、研磨ドラムＲＤが層間絶縁膜４に接触する角度を変えて、最外周面ＴＰに形成された層間絶縁膜４を除去する。   After polishing the interlayer insulating film 4 formed on the bevel portion BV1, the interlayer formed on the outermost peripheral surface TP is changed in the step shown in FIG. 5 by changing the angle at which the polishing drum RD contacts the interlayer insulating film 4. The insulating film 4 is removed.

この場合は、最外周面ＴＰが研磨されるほど研磨を進める必要はないが、最外周面ＴＰが多少研磨されても問題はない。   In this case, it is not necessary to advance the polishing so that the outermost peripheral surface TP is polished, but there is no problem even if the outermost peripheral surface TP is somewhat polished.

なお、図３においては、層間絶縁膜４は半導体基板１の裏面側のベベル部ＢＶ２には形成されていないものとして示したが、層間絶縁膜４がベベル部ＢＶ２上に形成される場合もあり、その場合は研磨ドラムＲＤが層間絶縁膜４に接触する角度を変えて、ベベル部ＢＶ２上の層間絶縁膜４を除去する。   3 shows that the interlayer insulating film 4 is not formed on the bevel portion BV2 on the back surface side of the semiconductor substrate 1, the interlayer insulating film 4 may be formed on the bevel portion BV2. In that case, the angle at which the polishing drum RD contacts the interlayer insulating film 4 is changed, and the interlayer insulating film 4 on the bevel portion BV2 is removed.

図６には、半導体基板１の端縁部上の層間絶縁膜４を全て除去した状態を示す。
図６においては、研磨後のベベル部ＢＶ１（図３）をエッジ部ＥＤと呼称し、エッジ部ＥＤの傾斜角度は、領域“Ｘ”で囲まれた部分の詳細図に示されるように、半導体基板１の主面に対して角度αをなしている。 FIG. 6 shows a state in which all of the interlayer insulating film 4 on the edge portion of the semiconductor substrate 1 has been removed.
In FIG. 6, the beveled part BV1 (FIG. 3) after polishing is referred to as an edge part ED, and the inclination angle of the edge part ED is a semiconductor as shown in the detailed view of the part surrounded by the region “X”. An angle α is formed with respect to the main surface of the substrate 1.

また、図４を用いて説明したように、層間絶縁膜４だけでなく半導体基板１の一部も研磨することで、層間絶縁膜４の傾斜端面４Ｓの傾斜角度と半導体基板１のエッジ部ＥＤの傾斜角度とが一致するとともに、層間絶縁膜４の傾斜端面４Ｓの先端位置と半導体基板１のエッジ部ＥＤの起点位置とがほぼ一致することとなる。   Further, as described with reference to FIG. 4, not only the interlayer insulating film 4 but also a part of the semiconductor substrate 1 is polished so that the inclined angle of the inclined end surface 4S of the interlayer insulating film 4 and the edge portion ED of the semiconductor substrate 1 are increased. And the tip position of the inclined end surface 4S of the interlayer insulating film 4 and the starting position of the edge portion ED of the semiconductor substrate 1 substantially match.

ここで、エッジ部ＥＤの起点位置とは、半導体基板１の素子形成主面とエッジ部ＥＤの傾斜面とが交わる位置であり、層間絶縁膜４の傾斜端面４Ｓの先端位置とは、半導体基板１の素子形成主面と層間絶縁膜４の傾斜端面４Ｓとが接触する位置である。   Here, the starting position of the edge portion ED is a position where the element formation main surface of the semiconductor substrate 1 and the inclined surface of the edge portion ED intersect, and the tip position of the inclined end surface 4S of the interlayer insulating film 4 is the semiconductor substrate. 1 is a position where the element formation main surface 1 and the inclined end surface 4S of the interlayer insulating film 4 are in contact with each other.

このため、層間絶縁膜４が半導体基板１の主面に対して段差を有さず、両者が一体化した構成となる。従って、層間絶縁膜４としてＳｉＯＣ膜等の、いわゆるＬｏｗ−ｋ膜を使用した場合でも、ＣＭＰ処理に際して層間絶縁膜４が剥離することを防止できる。   For this reason, the interlayer insulating film 4 does not have a step with respect to the main surface of the semiconductor substrate 1, and the both are integrated. Therefore, even when a so-called Low-k film such as a SiOC film is used as the interlayer insulating film 4, it is possible to prevent the interlayer insulating film 4 from being peeled off during the CMP process.

なお、図４に示したラインＬ１は、半導体基板１の主面となす角度αが０°よりも大きく３０°以下となるように設定されるとともに、層間絶縁膜４が半導体基板１の主面に対して段差を有さず、両者が一体化した構成となるように研磨深さが設定される。   4 is set such that an angle α formed with the main surface of the semiconductor substrate 1 is greater than 0 ° and not more than 30 °, and the interlayer insulating film 4 is formed on the main surface of the semiconductor substrate 1. However, the polishing depth is set so that there is no level difference and the two are integrated.

半導体基板１の端縁部に形成された層間絶縁膜４の除去が終了した後は、ＣＭＰ処理により、半導体基板１の素子形成主面上の層間絶縁膜４を平坦化する。   After the removal of the interlayer insulating film 4 formed on the edge portion of the semiconductor substrate 1 is completed, the interlayer insulating film 4 on the element formation main surface of the semiconductor substrate 1 is planarized by CMP processing.

その後、図７に示す工程において層間絶縁膜４を貫通してＭＯＳトランジスタ３のソース・ドレイン層３４に達するホール４ｂを設け、スパッタリング法によりホール４ｂの内面を覆うようにＴａＮ（窒化タンタル）を形成してバリアメタル膜ＢＭを設ける。続いて、ホール４ｂ内にＣＶＤ法あるいはメッキ法によりタングステン（Ｗ）等の導体膜ＭＬを充填する。   Thereafter, in the step shown in FIG. 7, holes 4b are formed through the interlayer insulating film 4 to reach the source / drain layers 34 of the MOS transistor 3, and TaN (tantalum nitride) is formed so as to cover the inner surface of the holes 4b by sputtering. Then, a barrier metal film BM is provided. Subsequently, the hole 4b is filled with a conductor film ML such as tungsten (W) by a CVD method or a plating method.

ここで、バリアメタル膜ＢＭおよび導体膜ＭＬは、層間絶縁膜４の全面に渡って形成されるとともに、図８に示すように半導体基板１の端縁部上にも形成される。   Here, the barrier metal film BM and the conductor film ML are formed over the entire surface of the interlayer insulating film 4 and also formed on the edge of the semiconductor substrate 1 as shown in FIG.

なお、バリアメタル膜ＢＭとしてはＴａＮの他に、ＴｉＮ（窒化チタン）を使用しても良いし、ＴａとＴａＮとの２層膜、ＴｉとＴｉＮとの２層膜で構成しても良い。   In addition to TaN, TiN (titanium nitride) may be used as the barrier metal film BM, or a two-layer film of Ta and TaN, or a two-layer film of Ti and TiN.

バリアメタル膜ＢＭおよび導体膜ＭＬは、Ｌｏｗ−ｋ膜に比べて密着性は高いが、ＣＭＰ処理時や搬送時に、半導体基板１の端縁部において機械的な衝撃により剥離が発生する可能性は有するので、端縁部のバリアメタル膜ＢＭおよび導体膜ＭＬは層間絶縁膜４と同様に除去することが望ましい。   The barrier metal film BM and the conductor film ML have higher adhesion than the low-k film, but there is a possibility that peeling occurs due to mechanical impact at the edge of the semiconductor substrate 1 at the time of CMP processing or transportation. Therefore, it is desirable to remove the barrier metal film BM and the conductor film ML at the edge portion in the same manner as the interlayer insulating film 4.

そこで、図９に示すように、研磨ドラムＲＤを用いて半導体基板１の端縁部に形成されたバリアメタル膜ＢＭおよび導体膜ＭＬを研磨して除去する。   Therefore, as shown in FIG. 9, the barrier metal film BM and the conductor film ML formed on the edge portion of the semiconductor substrate 1 are polished and removed using the polishing drum RD.

この研磨においては、エッジ部ＥＤ上に形成されたバリアメタル膜ＢＭおよび導体膜ＭＬを除去する際には、図９にラインＬ２で示す部分まで研磨を行う。なお、層間絶縁膜４の研磨の場合と同様に、研磨に際してはスラリを使用する。   In this polishing, when removing the barrier metal film BM and the conductor film ML formed on the edge portion ED, the polishing is performed up to the portion indicated by the line L2 in FIG. As in the polishing of the interlayer insulating film 4, a slurry is used for polishing.

ここで、ラインＬ２が半導体基板１の主面となす角度は、０°よりも大きく３０°以下に設定され、基本的にはエッジ部ＥＤの角度と同じ程度に設定される。   Here, the angle formed by the line L2 with the main surface of the semiconductor substrate 1 is set to be greater than 0 ° and 30 ° or less, and is basically set to the same degree as the angle of the edge portion ED.

また、研磨深さは、層間絶縁膜４上のバリアメタル膜ＢＭおよび導体膜ＭＬが層間絶縁膜４の主面に対して段差を有さず、層間絶縁膜４と一体化した構成となるように設定すればよく、エッジ部ＥＤが露出するまで研磨すれば目的は達するが、層間絶縁膜４の傾斜端面４Ｓおよびエッジ部ＥＤを多少研磨するように設定することで、確実に目的の構成を得ることができる。   The polishing depth is such that the barrier metal film BM and the conductor film ML on the interlayer insulating film 4 have no step with respect to the main surface of the interlayer insulating film 4 and are integrated with the interlayer insulating film 4. If the polishing is performed until the edge portion ED is exposed, the purpose is achieved. However, by setting the inclined end surface 4S of the interlayer insulating film 4 and the edge portion ED to be slightly polished, the target configuration can be surely achieved. Obtainable.

エッジ部ＥＤに形成されたバリアメタル膜ＢＭおよび導体膜ＭＬを研磨した後は、図１０に示す工程において、研磨ドラムＲＤがバリアメタル膜ＢＭおよび導体膜ＭＬに接触する角度を変えて、最外周面ＴＰに形成されたバリアメタル膜ＢＭおよび導体膜ＭＬを除去する。   After polishing the barrier metal film BM and the conductor film ML formed on the edge portion ED, in the step shown in FIG. 10, the angle at which the polishing drum RD contacts the barrier metal film BM and the conductor film ML is changed to change the outermost periphery. The barrier metal film BM and the conductor film ML formed on the surface TP are removed.

この場合は、最外周面ＴＰが研磨されるほど研磨を進める必要はないが、最外周面ＴＰが多少研磨されても問題はない。   In this case, it is not necessary to advance the polishing so that the outermost peripheral surface TP is polished, but there is no problem even if the outermost peripheral surface TP is somewhat polished.

図１１には、半導体基板１の端縁部上のバリアメタル膜ＢＭおよび導体膜ＭＬを全て除去した状態を示す。
図１１におけるエッジ部ＥＤの傾斜角度は、図６に示した角度αと同程度であり、バリアメタル膜ＢＭおよび導体膜ＭＬだけでなく、層間絶縁膜４の傾斜端面４Ｓおよびエッジ部ＥＤも研磨することで、バリアメタル膜ＢＭおよび導体膜ＭＬのそれぞれの傾斜端面ＢＭＳおよび導体膜ＭＬＳ、層間絶縁膜４の傾斜端面４Ｓの傾斜角度と半導体基板１のエッジ部ＥＤの傾斜角度とが一致するとともに、層間絶縁膜４の傾斜端面４Ｓの先端位置と半導体基板１のエッジ部ＥＤの起点位置とがほぼ一致することとなる。 FIG. 11 shows a state where the barrier metal film BM and the conductor film ML on the edge portion of the semiconductor substrate 1 are all removed.
The inclination angle of the edge portion ED in FIG. 11 is about the same as the angle α shown in FIG. 6, and not only the barrier metal film BM and the conductor film ML but also the inclined end surface 4S and the edge portion ED of the interlayer insulating film 4 are polished. As a result, the inclination angle of the inclined end face BMS and the conductive film MLS of the barrier metal film BM and the conductor film ML, and the inclination angle of the inclined end face 4S of the interlayer insulating film 4 coincide with the inclination angle of the edge portion ED of the semiconductor substrate 1. Thus, the tip position of the inclined end surface 4S of the interlayer insulating film 4 and the starting position of the edge portion ED of the semiconductor substrate 1 substantially coincide.

このため、層間絶縁膜４が半導体基板１の主面に対して段差を有さず、両者が一体化した構成となる。   For this reason, the interlayer insulating film 4 does not have a step with respect to the main surface of the semiconductor substrate 1, and the both are integrated.

また、導体膜ＭＬの傾斜端面ＭＬＳの先端位置とバリアメタル膜ＢＭの傾斜端面ＢＭＳの起点位置とがほぼ一致し、バリアメタル膜ＢＭの傾斜端面ＢＭＳの先端位置と層間絶縁膜４の傾斜端面４Ｓの起点位置とがほぼ一致するので、バリアメタル膜ＢＭおよび導体膜ＭＬも、それぞれの傾斜端面ＢＭＳおよびＭＬＳが下部層の主面に対して段差を有さず、３者が一体化した構成となる。   Further, the tip position of the inclined end face MLS of the conductor film ML and the starting position of the inclined end face BMS of the barrier metal film BM substantially coincide, and the tip position of the inclined end face BMS of the barrier metal film BM and the inclined end face 4S of the interlayer insulating film 4 Therefore, the barrier metal film BM and the conductor film ML also have a configuration in which the inclined end surfaces BMS and MLS have no step with respect to the main surface of the lower layer, and the three members are integrated. Become.

ここで、導体膜ＭＬの傾斜端面ＭＬＳの先端位置とは、バリアメタル膜ＢＭの上主面と導体膜ＭＬの傾斜端面ＭＬＳとが接触する位置であり、層間絶縁膜４の傾斜端面４Ｓの起点位置とは、層間絶縁膜４の上主面と傾斜端面４Ｓとが交わる位置である。   Here, the tip position of the inclined end surface MLS of the conductor film ML is a position where the upper main surface of the barrier metal film BM and the inclined end surface MLS of the conductor film ML are in contact with each other, and the starting point of the inclined end surface 4S of the interlayer insulating film 4 The position is a position where the upper main surface of the interlayer insulating film 4 and the inclined end surface 4S intersect.

従って、層間絶縁膜４としてＳｉＯＣ膜等の、いわゆるＬｏｗ−ｋ膜を使用し、当該層間絶縁膜４上にバリアメタル膜ＢＭおよび導体膜ＭＬを形成した場合でも、ＣＭＰ処理に際してバリアメタル膜ＢＭおよび導体膜ＭＬが剥離することを防止できる。   Therefore, even when a so-called Low-k film such as a SiOC film is used as the interlayer insulating film 4 and the barrier metal film BM and the conductor film ML are formed on the interlayer insulating film 4, the barrier metal film BM and The conductor film ML can be prevented from peeling off.

半導体基板１の端縁部に形成されたバリアメタル膜ＢＭおよび導体膜ＭＬの除去が終了した後は、ＣＭＰ処理により、半導体基板１の素子形成主面上のバリアメタル膜ＢＭおよび導体膜ＭＬを除去することで、図１２に示すように内面がバリアメタル膜ＢＭで覆われたホール４ｂ内にタングステンが充填されたコンタクト部４ａを得る。   After the removal of the barrier metal film BM and the conductor film ML formed on the edge portion of the semiconductor substrate 1 is completed, the barrier metal film BM and the conductor film ML on the element formation main surface of the semiconductor substrate 1 are removed by CMP processing. By removing the contact portion 4a, tungsten is filled in the hole 4b whose inner surface is covered with the barrier metal film BM as shown in FIG.

次に、図１３に示す工程において、例えばＣＶＤ法により層間絶縁膜４の主面全面を覆うようにＳｉＮ（窒化シリコン）膜を形成してエッチングストッパ膜ＥＳを設ける。   Next, in the process shown in FIG. 13, an SiN (silicon nitride) film is formed so as to cover the entire main surface of the interlayer insulating film 4 by, eg, CVD, and an etching stopper film ES is provided.

その後、エッチングストッパ膜ＥＳ上に、例えばプラズマＣＶＤ法によりＳｉＯＣ膜を形成して層間絶縁膜５を設ける。   Thereafter, an interlayer insulating film 5 is provided on the etching stopper film ES by forming a SiOC film, for example, by plasma CVD.

層間絶縁膜５は、層間絶縁膜４の全面に渡って形成されるとともに、図１４に示すように半導体基板１の端縁部上にも形成される。   The interlayer insulating film 5 is formed over the entire surface of the interlayer insulating film 4 and is also formed on the edge portion of the semiconductor substrate 1 as shown in FIG.

そこで、図１４に示すように、研磨ドラムＲＤを用いて半導体基板１の端縁部に形成された層間絶縁膜５を研磨して除去する。なお、層間絶縁膜５の下にはエッチングストッパ膜ＥＳが存在しているが、層間絶縁膜５に比べて薄い膜であるので、図示は省略している。   Therefore, as shown in FIG. 14, the interlayer insulating film 5 formed on the edge portion of the semiconductor substrate 1 is polished and removed using a polishing drum RD. Although an etching stopper film ES exists below the interlayer insulating film 5, it is not shown because it is thinner than the interlayer insulating film 5.

この研磨においては、エッジ部ＥＤ上に形成された層間絶縁膜５を除去する際には、図１４にラインＬ３で示す部分まで研磨を行う。なお、層間絶縁膜４の研磨の場合と同様に、研磨に際してはスラリを使用する。   In this polishing, when the interlayer insulating film 5 formed on the edge portion ED is removed, the polishing is performed up to the portion indicated by the line L3 in FIG. As in the polishing of the interlayer insulating film 4, a slurry is used for polishing.

ここで、ラインＬ３が半導体基板１の主面となす角度は、０°よりも大きく３０°以下に設定され、基本的にはエッジ部ＥＤの角度と同じ程度に設定される。   Here, the angle formed by the line L3 with the main surface of the semiconductor substrate 1 is set to be greater than 0 ° and 30 ° or less, and is basically set to the same degree as the angle of the edge portion ED.

また、研磨深さは、層間絶縁膜４上の層間絶縁膜５が層間絶縁膜４の主面に対して段差を有さず、層間絶縁膜４と一体化した構成となるように設定すればよく、エッジ部ＥＤが露出するまで研磨すれば目的は達するが、層間絶縁膜４の傾斜端面４Ｓおよびエッジ部ＥＤを多少研磨するように設定することで、確実に目的の構成を得ることができる。   The polishing depth is set so that the interlayer insulating film 5 on the interlayer insulating film 4 does not have a step with respect to the main surface of the interlayer insulating film 4 and is integrated with the interlayer insulating film 4. Although the purpose is achieved if the polishing is performed until the edge portion ED is exposed, the target configuration can be surely obtained by setting the inclined end surface 4S of the interlayer insulating film 4 and the edge portion ED to be slightly polished. .

エッジ部ＥＤに形成された層間絶縁膜５を研磨した後は、図１５に示す工程において、研磨ドラムＲＤが層間絶縁膜５に接触する角度を変えて、最外周面ＴＰに形成された層間絶縁膜５を除去する。   After the interlayer insulating film 5 formed on the edge portion ED is polished, the interlayer insulating film formed on the outermost peripheral surface TP is changed by changing the angle at which the polishing drum RD contacts the interlayer insulating film 5 in the step shown in FIG. The film 5 is removed.

この場合は、最外周面ＴＰが研磨されるほど研磨を進める必要はないが、最外周面ＴＰが多少研磨されても問題はない。   In this case, it is not necessary to advance the polishing so that the outermost peripheral surface TP is polished, but there is no problem even if the outermost peripheral surface TP is somewhat polished.

図１６には、半導体基板１の端縁部上の層間絶縁膜５を全て除去した状態を示す。
図１６におけるエッジ部ＥＤの傾斜角度は、図６に示した角度αと同程度であり、層間絶縁膜５だけでなく、層間絶縁膜４の傾斜端面４Ｓおよびエッジ部ＥＤも研磨することで、層間絶縁膜５および４のそれぞれの傾斜端面５Ｓおよび４Ｓの傾斜角度と、半導体基板１のエッジ部ＥＤの傾斜角度とが一致するとともに、層間絶縁膜４の傾斜端面４Ｓの先端位置と半導体基板１のエッジ部ＥＤの起点位置とがほぼ一致することとなる。このため、層間絶縁膜４が半導体基板１の主面に対して段差を有さず、両者が一体化した構成となる。 FIG. 16 shows a state in which all of the interlayer insulating film 5 on the edge portion of the semiconductor substrate 1 has been removed.
The inclination angle of the edge portion ED in FIG. 16 is substantially the same as the angle α shown in FIG. 6, and not only the interlayer insulating film 5 but also the inclined end surface 4S and the edge portion ED of the interlayer insulating film 4 are polished. The inclination angles of the inclined end faces 5S and 4S of the interlayer insulating films 5 and 4 coincide with the inclination angle of the edge portion ED of the semiconductor substrate 1, and the tip position of the inclined end face 4S of the interlayer insulating film 4 and the semiconductor substrate 1 The starting position of the edge portion ED substantially coincides. For this reason, the interlayer insulating film 4 does not have a step with respect to the main surface of the semiconductor substrate 1, and the both are integrated.

また、層間絶縁膜５の傾斜端面５Ｓの先端位置と層間絶縁膜４の傾斜端面４Ｓの起点位置とがほぼ一致するので、層間絶縁膜５の傾斜端面５Ｓが層間絶縁膜４の主面に対して段差を有さず、両者が一体化した構成となる。   In addition, since the tip position of the inclined end face 5S of the interlayer insulating film 5 and the starting position of the inclined end face 4S of the interlayer insulating film 4 substantially coincide, the inclined end face 5S of the interlayer insulating film 5 is in relation to the main surface of the interlayer insulating film 4. Therefore, there is no step and both are integrated.

従って、層間絶縁膜４および５としてＳｉＯＣ膜等の、いわゆるＬｏｗ−ｋ膜を使用して積層した場合でも、ＣＭＰ処理に際して層間絶縁膜４および５が剥離することを防止できる。   Therefore, even when the interlayer insulating films 4 and 5 are stacked using a so-called Low-k film such as a SiOC film, the interlayer insulating films 4 and 5 can be prevented from peeling off during the CMP process.

ここで、層間絶縁膜５の傾斜端面５Ｓの先端位置とは、層間絶縁膜４の上主面と層間絶縁膜５の傾斜端面５Ｓとが接触する位置である。   Here, the tip position of the inclined end surface 5S of the interlayer insulating film 5 is a position where the upper main surface of the interlayer insulating film 4 and the inclined end surface 5S of the interlayer insulating film 5 are in contact with each other.

なお、第１層の層間絶縁膜である層間絶縁膜４には、必ずしもＬｏｗ−ｋ膜を使用せずとも良く、例えば、ＴＥＯＳ（tetra ethyl orthosilicate）を用いて形成されたシリコン酸化膜（ＴＥＯＳ酸化膜）を使用しても良い。また、層間絶縁膜５以上の層間絶縁膜は、ＳｉＯＣ膜に限定されるものではなく、比誘電率２．９以下（現状で比誘電率が最も低い絶縁膜としては比誘電率１．５程度を想定しているが、本発明はこれ以下の絶縁膜に対しても有効である）のＬｏｗ−ｋ膜であれば良い。   Note that the interlayer insulating film 4 which is the first layer interlayer insulating film does not necessarily need to use a low-k film, for example, a silicon oxide film (TEOS oxide film) formed using TEOS (tetraethyl orthosilicate). Membrane) may be used. In addition, the interlayer insulating film of the interlayer insulating film 5 or more is not limited to the SiOC film, and has a relative dielectric constant of 2.9 or less (as an insulating film having the lowest relative dielectric constant at present, the relative dielectric constant is about 1.5). However, the present invention may be any low-k film which is also effective for insulating films below this.

半導体基板１の端縁部に形成された層間絶縁膜５（およびエッチングストッパ膜ＥＳ）の除去が終了した後は、ＣＭＰ処理により、半導体基板１の素子形成主面上の層間絶縁膜５を平坦化する。   After the removal of the interlayer insulating film 5 (and the etching stopper film ES) formed on the edge of the semiconductor substrate 1 is completed, the interlayer insulating film 5 on the element formation main surface of the semiconductor substrate 1 is flattened by CMP processing. Turn into.

その後は、図７〜図１２を用いて説明した工程と同様の工程を経ることで、図１７に示すように、層間絶縁膜５およびエッチングストッパ膜ＥＳを貫通してコンタクト部４ａに達する配線溝５ｂの内面がバリアメタル膜ＢＭで覆われ、その内部に銅（Ｃｕ）が充填された配線層５ａを得る。   Thereafter, through the same process as described with reference to FIG. 7 to FIG. 12, as shown in FIG. 17, the wiring trench that reaches the contact portion 4a through the interlayer insulating film 5 and the etching stopper film ES is obtained. An inner surface of 5b is covered with a barrier metal film BM, and a wiring layer 5a filled with copper (Cu) is obtained.

また、図１３〜図１６を用いて説明した工程と同様の工程を経ることで、層間絶縁膜５上にエッチングストッパ膜ＥＳおよび層間絶縁膜６が積層された構成を得る。   Further, through a process similar to that described with reference to FIGS. 13 to 16, a configuration in which the etching stopper film ES and the interlayer insulating film 6 are stacked on the interlayer insulating film 5 is obtained.

なお、層間絶縁膜６中には、層間絶縁膜６およびエッチングストッパ膜ＥＳを貫通して配線層５ａに達するホール６ｂの内面がバリアメタル膜ＢＭで覆われ、その内部に銅が充填されたコンタクト部６ａが形成され、層間絶縁膜６上にもさらに層間絶縁膜が形成され、その内部には、コンタクト部や配線層が形成されて多層配線構造の半導体装置が完成するが、それらの製造方法は図７〜図１６を用いて説明した工程と同様の工程の繰り返しであるので、図示および説明は省略する。   In the interlayer insulating film 6, the inner surface of the hole 6b reaching the wiring layer 5a through the interlayer insulating film 6 and the etching stopper film ES is covered with the barrier metal film BM, and the contact filled with copper therein A portion 6a is formed, and an interlayer insulating film is further formed on the interlayer insulating film 6, and a contact portion and a wiring layer are formed therein to complete a semiconductor device having a multilayer wiring structure. Is a repetition of the same steps as those described with reference to FIGS.

層間絶縁膜６以上の層間絶縁膜中には、いわゆるデュアルダマシン法により配線層とコンタクト部とが同時に形成されるが、デュアルダマシン法は周知の技術であるので、説明は省略する。   In the interlayer insulating film of the interlayer insulating film 6 or more, a wiring layer and a contact portion are simultaneously formed by a so-called dual damascene method. However, the dual damascene method is a well-known technique, and thus description thereof is omitted.

なお、デュアルダマシン法以外の方法で配線層およびコンタクト部を形成しても良く、配線層もＣｕに限定されるものではなく、最上層の配線層を、例えばアルミニウム（Ａｌ）で構成しても良い。   Note that the wiring layer and the contact portion may be formed by a method other than the dual damascene method. The wiring layer is not limited to Cu, and the uppermost wiring layer may be made of, for example, aluminum (Al). good.

ここで、ソース・ドレイン層３４との接続部分にタングステンを使用する理由の１つには、電気抵抗が低いということが挙げられ、また、バリアメタル膜としてＴａＮや、ＴｉＮ、Ｔａ、Ｔｉ等を使用するのは、タングステンと酸化シリコンとの密着性が低いので、両者と密着性の良いこれらの金属を使用して、密着性を改善するためである。また、配線層に銅を使用するのは、アルミニウムに比べて電気抵抗が低いためである。また、アルミニウムは、酸化シリコンとの密着性が良いのでバリアメタル膜が不要であるという利点や、低融点であるので形成が容易という利点がある。   Here, one of the reasons for using tungsten for the connection portion with the source / drain layer 34 is that the electric resistance is low, and TaN, TiN, Ta, Ti, etc. are used as the barrier metal film. The reason for this is that the adhesion between tungsten and silicon oxide is low, so that these metals having good adhesion with both are used to improve the adhesion. Moreover, the reason why copper is used for the wiring layer is that the electric resistance is lower than that of aluminum. Aluminum has an advantage that a barrier metal film is unnecessary because it has good adhesion to silicon oxide and an advantage that it can be easily formed because it has a low melting point.

以上説明した本発明に係る半導体装置の製造方法を使用することで、半導体基板１の素子形成主面上には、半導体基板１の平面図である図１８に示すように、半導体チップ領域ＳＲ内に多層配線構造の半導体装置が複数形成されることになり、それらをチップ単位に分割することで、複数の半導体チップを得ることができる。   By using the semiconductor device manufacturing method according to the present invention described above, the element formation main surface of the semiconductor substrate 1 is placed in the semiconductor chip region SR as shown in FIG. 18 which is a plan view of the semiconductor substrate 1. A plurality of semiconductor devices having a multilayer wiring structure are formed, and a plurality of semiconductor chips can be obtained by dividing them into chips.

なお、図１８に示すように、ウエハ段階の最終工程に至るまで、半導体基板１の少なくとも素子形成主面側の端縁部にはエッジ部ＥＤが存在している。なお、エッジ部ＥＤは最外周面ＴＰから５ｍｍ程度の領域内に配設されることになる。   As shown in FIG. 18, the edge portion ED exists at least at the edge portion on the element formation main surface side of the semiconductor substrate 1 until the final process of the wafer stage. Note that the edge portion ED is disposed in an area of about 5 mm from the outermost peripheral surface TP.

＜Ｂ．効果＞
以上説明した本発明に係る実施の形態の半導体装置の製造方法においては、ＣＭＰ処理の対象となる絶縁膜および導体膜等の研磨対象膜が、半導体基板１の端縁部にも形成されている場合、ＣＭＰ処理に先立って当該端縁部の研磨対象膜を機械的に研磨するが、この研磨においては、半導体基板１の主面となす角度αが０°よりも大きく３０°以下となるように研磨面を設定し、かつ研磨対象膜が下部層の主面に対して段差を有さず、下部層と研磨対象膜とが一体化した構成となるように研磨深さを設定する。 <B. Effect>
In the semiconductor device manufacturing method according to the embodiment of the present invention described above, the polishing target film such as the insulating film and the conductor film to be subjected to the CMP process is also formed on the edge portion of the semiconductor substrate 1. In this case, the polishing target film at the edge portion is mechanically polished prior to the CMP process. In this polishing, the angle α formed with the main surface of the semiconductor substrate 1 is larger than 0 ° and not larger than 30 °. The polishing depth is set such that the polishing surface is set, the polishing target film has no step with respect to the main surface of the lower layer, and the lower layer and the polishing target film are integrated.

この結果、研磨対象膜に対して面内方向の応力が加わりにくくなるので、層間絶縁膜としてＳｉＯＣ膜等の、いわゆるＬｏｗ−ｋ膜を使用した場合でも、ＣＭＰ処理に際して当該層間絶縁膜が剥離することを防止できる。   As a result, stress in the in-plane direction is not easily applied to the film to be polished. Therefore, even when a so-called Low-k film such as a SiOC film is used as the interlayer insulating film, the interlayer insulating film is peeled off during the CMP process. Can be prevented.

なお、研磨ドラムを用いた機械的な研磨方法は、いわゆるベベル研磨と呼称される半導体基板のベベル加工に使用される研磨方法であり、技術的に確立されているので、それをエッジ研磨に転用することで、容易にエッジ研磨を実行することができるという利点がある。   The mechanical polishing method using a polishing drum is a polishing method used for bevel processing of a semiconductor substrate called so-called bevel polishing, and since it has been technically established, it can be used for edge polishing. By doing so, there is an advantage that edge polishing can be easily performed.

＜Ｃ．エッジ研磨方法の変形例＞
以上説明した実施の形態においては、エッジ研磨の方法として、円筒状のドラムの側面に研磨布を貼り付けた研磨ドラムを用いて半導体基板１の端縁部を研磨する方法を説明したが、エッジ研磨の方法はこれに限定されるものではない。 <C. Modification of edge polishing method>
In the embodiment described above, as the edge polishing method, the method of polishing the edge portion of the semiconductor substrate 1 using the polishing drum in which the polishing cloth is attached to the side surface of the cylindrical drum has been described. The polishing method is not limited to this.

例えば、図１９に示されるように、平面部に研磨布ＰＰを貼り付けた研磨台ＢＤを半導体基板１の端縁部に押し当て、半導体基板１の主面に対して交差する方向に揺動させるとともに、半導体基板１を面内回転させることで、半導体基板１の端縁部に形成された層間絶縁膜４等の膜を研磨しても良い。   For example, as shown in FIG. 19, the polishing table BD with the polishing pad PP attached to the flat surface is pressed against the edge of the semiconductor substrate 1 and swings in a direction intersecting the main surface of the semiconductor substrate 1. In addition, the film such as the interlayer insulating film 4 formed on the edge portion of the semiconductor substrate 1 may be polished by rotating the semiconductor substrate 1 in-plane.

この場合も、図１９にラインＬ１で示す部分まで研磨を行い、層間絶縁膜４だけでなく半導体基板１の一部も除去する。   Also in this case, polishing is performed up to a portion indicated by a line L1 in FIG. 19 to remove not only the interlayer insulating film 4 but also a part of the semiconductor substrate 1.

ベベル部ＢＶ１上に形成された層間絶縁膜４を研磨した後は、研磨台ＢＤが層間絶縁膜４に接触する角度を変えて、最外周面ＴＰに形成された層間絶縁膜４を除去する。   After polishing the interlayer insulating film 4 formed on the bevel portion BV1, the angle at which the polishing table BD contacts the interlayer insulating film 4 is changed, and the interlayer insulating film 4 formed on the outermost peripheral surface TP is removed.

なお、研磨に際してスラリを研磨部分に供給しながら行うことは研磨ドラムを使用する場合と同じである。   Note that performing polishing while supplying slurry to the polishing portion is the same as when using a polishing drum.

この方法を採用した場合、研磨深さの制御が容易であるとともに、より平坦な研磨面を得ることができる。   When this method is employed, the polishing depth can be easily controlled and a flatter polished surface can be obtained.

また、エッジ研磨の方法としては、図２０に示されるように、砥粒粉が埋め込まれた研磨テープＴＡを半導体基板１の端縁部に押し当て、半導体基板１の主面に対して交差する方向に揺動させるとともに、半導体基板１を面内回転させることで、半導体基板１の端縁部に形成された層間絶縁膜４等の膜を研磨しても良い。   As an edge polishing method, as shown in FIG. 20, the polishing tape TA in which abrasive powder is embedded is pressed against the edge of the semiconductor substrate 1 and intersects the main surface of the semiconductor substrate 1. The film such as the interlayer insulating film 4 formed on the edge portion of the semiconductor substrate 1 may be polished by swinging in the direction and rotating the semiconductor substrate 1 in the plane.

研磨テープＴＡの両端はそれぞれテープリールＴＲに巻き付けられており、研磨テープＴＡは研磨を所定時間実行するごとに一方のテープリールＴＲに所定量巻き取られる構成を採っており、長時間に渡って研磨能力を維持できる構成となっている。   Both ends of the polishing tape TA are wound around the tape reel TR, and the polishing tape TA is wound around one tape reel TR every time the polishing is performed for a predetermined time. It has a configuration capable of maintaining the polishing ability.

この場合も、図２０にラインＬ１で示す部分まで研磨を行い、層間絶縁膜４だけでなく半導体基板１の一部も除去する。   Also in this case, polishing is performed up to a portion indicated by a line L1 in FIG. 20 to remove not only the interlayer insulating film 4 but also a part of the semiconductor substrate 1.

ベベル部ＢＶ１上に形成された層間絶縁膜４を研磨した後は、研磨テープＴＡが層間絶縁膜４に接触する角度を変えて、最外周面ＴＰに形成された層間絶縁膜４を除去する。   After polishing the interlayer insulating film 4 formed on the bevel portion BV1, the angle at which the polishing tape TA contacts the interlayer insulating film 4 is changed, and the interlayer insulating film 4 formed on the outermost peripheral surface TP is removed.

この方法を採用した場合、研磨深さの制御が容易であるとともに、スラリを供給する必要がないので、研磨作業が簡略化される。   When this method is adopted, it is easy to control the polishing depth and it is not necessary to supply slurry, so that the polishing operation is simplified.

以上説明したエッジ研磨は、機械的な手法で研磨を行う方法であったが、以下に説明するように化学的な手法で研磨を行っても良い。   The edge polishing described above is a method of polishing by a mechanical method, but may be performed by a chemical method as described below.

すなわち、図２１に示されるように、反応性ガスのプラズマＰＬを発生させる反応室ＲＣと半導体基板１を収容する処理室ＰＣとの間にシールドＳＨを設け、当該シールドＳＨにはプラズマＰＬの一部、あるいはイオンを通過させる開口部ＯＰを有する構成とする。   That is, as shown in FIG. 21, a shield SH is provided between a reaction chamber RC that generates a plasma PL of a reactive gas and a processing chamber PC that accommodates the semiconductor substrate 1, and the shield SH has a plasma PL. Or an opening OP that allows ions to pass therethrough.

処理室ＰＣ内では半導体基板１が回転台ＲＳ上に搭載され、半導体基板１の端縁部がシールドＳＨの近傍に位置するように配設される。   In the processing chamber PC, the semiconductor substrate 1 is mounted on the turntable RS, and the edge portion of the semiconductor substrate 1 is disposed in the vicinity of the shield SH.

回転台ＲＳは半導体基板１を搭載して面内回転することが可能であるとともに、回転軸を所望の角度に傾けることができ、半導体基板１の端縁部、例えばベベル部ＢＶ１が開口部ＯＰに対して対面するように配置することができる。   The turntable RS can be rotated in-plane with the semiconductor substrate 1 mounted thereon, and the rotation axis can be tilted to a desired angle. The edge portion of the semiconductor substrate 1, for example, the bevel portion BV1 is opened to the opening OP. It can arrange | position so that it may face.

このように配置された半導体基板１に対して、シールドＳＨの開口部ＯＰを介して反応性ガスのプラズマＰＬの一部、あるいは反応性ガスのイオンが供給されると、開口部ＯＰに対面するベベル部ＢＶ１上に形成された層間絶縁膜４等の膜が、ドライエッチングにより除去される。   When a part of the reactive gas plasma PL or reactive gas ions is supplied to the semiconductor substrate 1 arranged in this way through the opening OP of the shield SH, the semiconductor substrate 1 faces the opening OP. A film such as the interlayer insulating film 4 formed on the bevel portion BV1 is removed by dry etching.

ここで、使用する反応性ガスは除去する膜の材質によって選択すれば良く、ＳｉＯＣ膜やシリコン酸化膜に対してはＣＦ4やＣ2Ｆ6を使用することができる。なお、各種エッチング対象に対する反応性ガスの選択に際しては、周知の情報を利用すれば良い。 Here, the reactive gas to be used may be selected depending on the material of the film to be removed, and CF 4 or C 2 F 6 can be used for the SiOC film or the silicon oxide film. It should be noted that well-known information may be used in selecting reactive gases for various etching targets.

なお、半導体基板１にイオンを引きつけるバイアス電圧を印加することで、異方性ドライエッチングを行うことができる。   Note that anisotropic dry etching can be performed by applying a bias voltage for attracting ions to the semiconductor substrate 1.

ベベル部ＢＶ１上に形成された層間絶縁膜４を除去した後は、回転台ＲＳの傾き角度を変えて、最外周面ＴＰが開口部ＯＰに対面するように配置して、最外周面ＴＰに形成された層間絶縁膜４を除去する。   After removing the interlayer insulating film 4 formed on the bevel portion BV1, the tilt angle of the turntable RS is changed, and the outermost peripheral surface TP is disposed so as to face the opening OP. The formed interlayer insulating film 4 is removed.

ドライエッチング技術は確立された技術であるので、確実に層間絶縁膜４を除去できるとともに、比較的制御性良く半導体基板１をエッチングすることができる。   Since the dry etching technique is an established technique, the interlayer insulating film 4 can be reliably removed, and the semiconductor substrate 1 can be etched with relatively high controllability.

また、化学的な手法によるエッジ研磨としては、図２２に示されるように、ウエットエッチングを使用することもできる。   Further, as edge polishing by a chemical method, wet etching can be used as shown in FIG.

すなわち、図２２に示されるように、半導体基板１の端縁部に対してエッチング液の噴射角度が変更可能なノズルＮＺからエッチング液を局所的に噴射することで、半導体基板１の端縁部に形成された層間絶縁膜４等の膜を除去することも可能である。   That is, as shown in FIG. 22, the edge of the semiconductor substrate 1 is locally sprayed from the nozzle NZ that can change the spray angle of the etchant to the edge of the semiconductor substrate 1. It is also possible to remove the film such as the interlayer insulating film 4 formed in (1).

ここで、使用するエッチング液は除去する膜の材質によって選択すれば良く、ＳｉＯＣ膜やシリコン酸化膜に対してはフッ酸（ＨＦ）やフッ化アンモニウム、シリコンに対してはフッ酸および硝酸の混合液を使用することができる。なお、各種エッチング対象に対するエッチング液の選択に際しては、周知の情報を利用すれば良い。   Here, the etching solution to be used may be selected according to the material of the film to be removed. Hydrofluoric acid (HF) or ammonium fluoride is used for the SiOC film or silicon oxide film, and hydrofluoric acid and nitric acid are mixed for silicon. Liquid can be used. It should be noted that well-known information may be used when selecting an etching solution for various etching targets.

ベベル部ＢＶ１上に形成された層間絶縁膜４を除去した後は、ノズルＮＺの傾き角度を変えて、最外周面ＴＰに対してエッチング液を噴射し、最外周面ＴＰに形成された層間絶縁膜４を除去する。   After the interlayer insulating film 4 formed on the bevel portion BV1 is removed, the tilt angle of the nozzle NZ is changed, and an etching solution is sprayed onto the outermost peripheral surface TP, and the interlayer insulating formed on the outermost peripheral surface TP. The film 4 is removed.

ウエットエッチング技術は確立された技術であるので、確実に層間絶縁膜４を除去できるとともに、エッチング装置が比較的簡便な構成で済むという利点がある。   Since the wet etching technique is an established technique, there are advantages that the interlayer insulating film 4 can be removed reliably and the etching apparatus can be configured with a relatively simple structure.

本発明に係る実施の形態の半導体装置の製造工程を説明する断面図である。It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. 本発明に係る実施の形態の半導体装置の製造工程を説明する断面図である。It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. 本発明に係る実施の形態の半導体装置の製造工程を説明する断面図である。It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. 本発明に係る実施の形態の半導体装置の製造工程を説明する断面図である。It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. 本発明に係る実施の形態の半導体装置の製造工程を説明する断面図である。It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. 本発明に係る実施の形態の半導体装置の製造工程を説明する断面図である。It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. 本発明に係る実施の形態の半導体装置の製造工程を説明する断面図である。It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. 本発明に係る実施の形態の半導体装置の製造工程を説明する断面図である。It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. 本発明に係る実施の形態の半導体装置の製造工程を説明する断面図である。It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. 本発明に係る実施の形態の半導体装置の製造工程を説明する断面図である。It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. 本発明に係る実施の形態の半導体装置の製造工程を説明する断面図である。It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. 本発明に係る実施の形態の半導体装置の製造工程を説明する断面図である。It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. 本発明に係る実施の形態の半導体装置の製造工程を説明する断面図である。It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. 本発明に係る実施の形態の半導体装置の製造工程を説明する断面図である。It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. 本発明に係る実施の形態の半導体装置の製造工程を説明する断面図である。It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. 本発明に係る実施の形態の半導体装置の製造工程を説明する断面図である。It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. 本発明に係る実施の形態の半導体装置の製造工程を説明する断面図である。It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. 本発明に係る実施の形態の半導体装置の製造方法により、多層配線構造の半導体装置が形成された半導体基板を示す平面図である。It is a top view which shows the semiconductor substrate with which the semiconductor device of the multilayer wiring structure was formed by the manufacturing method of the semiconductor device of embodiment which concerns on this invention. エッジ研磨方法の変形例を説明する図である。It is a figure explaining the modification of an edge grinding | polishing method. エッジ研磨方法の変形例を説明する図である。It is a figure explaining the modification of an edge grinding | polishing method. エッジ研磨方法の変形例を説明する図である。It is a figure explaining the modification of an edge grinding | polishing method. エッジ研磨方法の変形例を説明する図である。It is a figure explaining the modification of an edge grinding | polishing method.

符号の説明Explanation of symbols

１ 半導体基板、４，５，６ 層間絶縁膜、４Ｓ，５Ｓ 傾斜端面、ＥＤ エッジ部、ＭＬ 導体膜、ＢＭ バリアメタル膜。
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 4, 5, 6 interlayer insulation film, 4S, 5S inclined end surface, ED edge part, ML conductor film, BM barrier metal film.

Claims (11)

半導体基板上に層間絶縁膜を間に介して配線層が多層に配設された多層配線構造の半導体装置の製造方法であって、
(ａ)前記半導体基板の上方に前記層間絶縁膜を形成する工程と、
(ｂ)前記層間絶縁膜上に導体膜を形成して前記配線層を形成する工程と、を備え、
前記工程(ａ)は、
(ａ−１)前記半導体基板の端縁部において、半導体素子が形成される素子形成主面側の前記層間絶縁膜および前記半導体基板の一部を除去して、当該除去の結果得られる前記層間絶縁膜の端面および前記半導体基板のエッジ部を少なくとも含んで構成される面が、前記素子形成主面に対して０°よりも大きく３０°以下の角度の傾斜を有するように加工する工程を含み、
前記工程(ｂ)は、
(ｂ−１)前記端縁部において、前記素子形成主面側の少なくとも前記導体膜の一部を除去して、当該除去の結果得られる前記導体膜の端面、前記層間絶縁膜の端面および前記半導体基板のエッジ部を少なくとも含んで構成される面が、前記素子形成主面に対して０°よりも大きく３０°以下の角度の傾斜を有するように加工する工程を含む、半導体装置の製造方法。 A method of manufacturing a semiconductor device having a multilayer wiring structure in which wiring layers are arranged in multiple layers with an interlayer insulating film therebetween on a semiconductor substrate,
(a) forming the interlayer insulating film above the semiconductor substrate;
(b) forming a conductive film on the interlayer insulating film to form the wiring layer,
The step (a)
(a-1) At the edge portion of the semiconductor substrate, the interlayer insulating film on the element formation main surface side where the semiconductor element is formed and a part of the semiconductor substrate are removed, and the interlayer obtained as a result of the removal And a step of processing so that an end surface of the insulating film and a surface including at least the edge portion of the semiconductor substrate have an inclination of an angle greater than 0 ° and not more than 30 ° with respect to the element formation main surface. ,
The step (b)
(b-1) At the edge portion, at least a part of the conductor film on the element formation main surface side is removed, the end face of the conductor film obtained as a result of the removal, the end face of the interlayer insulating film, and the A method of manufacturing a semiconductor device, comprising a step of processing a surface configured to include at least an edge portion of a semiconductor substrate so as to have an inclination of an angle greater than 0 ° and 30 ° or less with respect to the element formation main surface. . 前記工程(ａ−１)は、
機械的な研磨により前記層間絶縁膜および前記半導体基板を除去する工程を含み、
前記工程(ｂ−１)は、
前記機械的な研磨により少なくとも前記導体膜を除去する工程を含む、請求項１記載の半導体装置の製造方法。 The step (a-1)
Removing the interlayer insulating film and the semiconductor substrate by mechanical polishing,
The step (b-1)
The method for manufacturing a semiconductor device according to claim 1, comprising a step of removing at least the conductor film by the mechanical polishing. 前記機械的な研磨は、
シリカ、酸化アルミナおよびセリアから選択される砥粒を含むスラリを研磨部分に供給しながら研磨部材により研磨を行う、請求項２記載の半導体装置の製造方法。 The mechanical polishing is
3. The method of manufacturing a semiconductor device according to claim 2, wherein polishing is performed by a polishing member while supplying a slurry containing abrasive grains selected from silica, alumina oxide and ceria to the polishing portion. 前記機械的な研磨は、シリカ、酸化アルミナおよびセリアから選択される砥粒を含むテープ状の研磨部材により研磨を行う、請求項２記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 2, wherein the mechanical polishing is performed by a tape-shaped polishing member including abrasive grains selected from silica, alumina oxide, and ceria. 前記工程(ａ−１)は、
ドライエッチングにより前記層間絶縁膜および前記半導体基板を除去する工程を含み、
前記工程(ｂ−１)は、
前記ドライエッチングにより少なくとも前記導体膜を除去する工程を含む、請求項１記載の半導体装置の製造方法。 The step (a-1)
Removing the interlayer insulating film and the semiconductor substrate by dry etching,
The step (b-1)
The method for manufacturing a semiconductor device according to claim 1, further comprising a step of removing at least the conductor film by the dry etching. 前記工程(ａ−１)は、
ウエットエッチングにより前記層間絶縁膜および前記半導体基板を除去する工程を含み、
前記工程(ｂ−１)は、
前記ウエットエッチングにより少なくとも前記導体膜を除去する工程を含む、請求項１記載の半導体装置の製造方法。 The step (a-1)
Removing the interlayer insulating film and the semiconductor substrate by wet etching,
The step (b-1)
The method for manufacturing a semiconductor device according to claim 1, further comprising a step of removing at least the conductor film by the wet etching. 前記工程(ａ)は、
前記層間絶縁膜を比誘電率２．９以下の絶縁膜で形成する工程を含む、請求項１ないし請求項６の何れかに記載の半導体装置の製造方法。 The step (a)
The method for manufacturing a semiconductor device according to claim 1, comprising a step of forming the interlayer insulating film with an insulating film having a relative dielectric constant of 2.9 or less. 前記工程(ｂ)は、
前記導体膜をＴａ、ＴａＮ、Ｔｉ、ＴｉＮ、Ｗ、ＡｌおよびＣｕから選択される１種類の材料で構成される単層膜、あるいは複数の材料で構成される多層膜として形成する工程を含む、請求項１ないし請求項７の何れかに記載の半導体装置の製造方法。 The step (b)
Forming the conductor film as a single layer film composed of one kind of material selected from Ta, TaN, Ti, TiN, W, Al and Cu, or a multilayer film composed of a plurality of materials; A method for manufacturing a semiconductor device according to claim 1. 層間絶縁膜を間に介して配線層が多層に配設された多層配線構造の半導体装置を有した半導体基板であって、
前記半導体基板の端縁部において、半導体素子が形成される素子形成主面側の前記層間絶縁膜の端面および前記半導体基板のエッジ部を少なくとも含んで構成される一面が、前記素子形成主面に対して０°よりも大きく３０°以下の角度の傾斜を有する半導体基板。 A semiconductor substrate having a semiconductor device having a multilayer wiring structure in which wiring layers are arranged in multiple layers with an interlayer insulating film interposed therebetween,
At the edge portion of the semiconductor substrate, one surface including at least the edge surface of the interlayer insulating film on the element formation main surface side on which the semiconductor element is formed and the edge portion of the semiconductor substrate is the element formation main surface. A semiconductor substrate having an inclination of greater than 0 ° and 30 ° or less. 前記層間絶縁膜は、前記半導体基板上に配設される第１層の層間絶縁膜であって、
前記第１層の層間絶縁膜の傾斜端面の先端位置と、前記エッジ部の傾斜面の起点位置とがほぼ一致する、請求項９記載の半導体基板。 The interlayer insulating film is a first interlayer insulating film disposed on the semiconductor substrate,
The semiconductor substrate according to claim 9, wherein a tip position of the inclined end surface of the first-layer interlayer insulating film substantially coincides with a starting position of the inclined surface of the edge portion. 前記層間絶縁膜の下に配設された下部層をさらに備え、
前記半導体基板の前記端縁部において、前記層間絶縁膜の下部層の端面が、前記素子形成主面に対して０°よりも大きく３０°以下の角度の傾斜を有して前記一面を構成し、
前記層間絶縁膜の傾斜端面の先端位置と、前記下部層の傾斜端面の起点位置とがほぼ一致する、請求項９記載の半導体基板。
Further comprising a lower layer disposed under the interlayer insulating film;
In the edge portion of the semiconductor substrate, the end surface of the lower layer of the interlayer insulating film forms the one surface with an inclination of an angle of greater than 0 ° and 30 ° or less with respect to the element formation main surface. ,
The semiconductor substrate according to claim 9, wherein a tip position of the inclined end face of the interlayer insulating film substantially coincides with a starting position of the inclined end face of the lower layer.
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