JP2007208013A - High-frequency circuit board - Google Patents
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- JP2007208013A JP2007208013A JP2006025273A JP2006025273A JP2007208013A JP 2007208013 A JP2007208013 A JP 2007208013A JP 2006025273 A JP2006025273 A JP 2006025273A JP 2006025273 A JP2006025273 A JP 2006025273A JP 2007208013 A JP2007208013 A JP 2007208013A
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Abstract
Description
本発明は高周波回路基板に関し、特に、該高周波回路基板のシールド構造に係るものである。 The present invention relates to a high-frequency circuit board, and particularly relates to a shield structure for the high-frequency circuit board.
高周波回路基板は、図4に示すように、表面の誘電体基板1、内層のベタパターン2及び裏面の誘電体基板3から成り、基板の外周を接地導体4,5とし、表面の接地導体4にシールドケース7を取り付けて、基板上の高周波回路を、外部空間及び基板内を伝搬する電磁波から遮蔽するシールド構造が採用されている。外周に配置した表面及び裏面の接地導体4,5は、内層のベタパターン2と共に接地用スルーホール6を介した導体により接続される。
As shown in FIG. 4, the high-frequency circuit board is composed of a
本発明に関連する先行技術文献として、マイクロ波帯及びミリ波帯における半導体素子を含むモジュール用の多層高周波回路基板に関し、特に不要結合による高周波回路の特性の劣化を少なくした高周波回路基板について下記の特許文献1などに記載されている。
前述した従来のシールド構造の高周波回路基板では、内層のベタパターン2も接地導体となり、該ベタパターン2に電源電圧又は任意の電圧を印加することができない。本発明は、シールド効果を保持したまま、高周波回路基板の内層のベタパターン2を接地導体としてではなく、電源電圧又は他の任意の電圧の給電導体として用いることを可能にし、それにより、高周波回路基板の小型化及び回路動作の安定化を図ることを目的とする。 In the above-described conventional high-frequency circuit board having a shield structure, the solid pattern 2 in the inner layer is also a ground conductor, and a power supply voltage or an arbitrary voltage cannot be applied to the solid pattern 2. The present invention makes it possible to use the solid pattern 2 on the inner layer of the high-frequency circuit board as a power supply voltage or a power supply conductor of any other voltage, not as a ground conductor, while maintaining the shielding effect, The purpose is to reduce the size of the substrate and stabilize the circuit operation.
本発明の高周波回路基板は、(1)内層にベタパターンを有する多層構造の高周波回路基板において、前記ベタパターンの外周端から、高周波回路基板上で使用される高周波の電気信号の電磁波の波長の4分の1の長さ分、内側の領域を素子実装領域とし、該ベタパターンに接地電圧とは異なる電圧を印加する構成を有するものである。 The high-frequency circuit board according to the present invention is (1) a multi-layer high-frequency circuit board having a solid pattern in an inner layer, and the wavelength of an electromagnetic wave of a high-frequency electric signal used on the high-frequency circuit board from the outer peripheral edge of the solid pattern. The inner region is used as an element mounting region by a quarter length, and a voltage different from the ground voltage is applied to the solid pattern.
また、(2)前記高周波回路基板の表面及び裏面に設けた接地導体を接続するスルーホールの導体が通過する前記ベタパターンの箇所に、該ベタパターンが該スルーホールの導体と接触しないよう、該スルーホールより大きい穴を穿設したことを特徴とする。 (2) The solid pattern does not come into contact with the conductor of the through-hole at the location of the solid pattern through which the conductor of the through-hole connecting the ground conductor provided on the front and back surfaces of the high-frequency circuit board passes. It is characterized in that a hole larger than the through hole is formed.
また、(3)前記高周波回路基板の表面又は裏面のパターンと前記内層のベタパターンとをインナービアにより接続し、該高周波回路基板の表面又は裏面に実装した素子に、該ベタパターンに印加された電圧を付与する構成を有することを特徴とする。 (3) The pattern on the front or back surface of the high-frequency circuit board and the solid pattern on the inner layer are connected by an inner via, and applied to the solid pattern on an element mounted on the front or back surface of the high-frequency circuit board. It has the structure which provides a voltage, It is characterized by the above-mentioned.
また、(4)前記内層のベタパターンは複数の層のベタパターンから成り、各ベタパターンにそれぞれ異なる電圧を印加する構成を有することを特徴とする。 (4) The solid pattern of the inner layer is composed of a solid pattern of a plurality of layers, and has a configuration in which different voltages are applied to the solid patterns.
また、(5)前記内層のベタパターンと前記接地導体とを、コンデンサを介して接続したことを特徴とする (5) The solid pattern of the inner layer and the ground conductor are connected via a capacitor.
本発明によれば、内層のベタパターンの外周端から、高周波回路基板上で使用される高周波の電気信号の電磁波の波長の4分の1の長さ分、内側の領域を素子実装領域としたことにより、内層のベタパターンを接地導体と接続せずに、内層のベタパターンに電源電圧又は他の任意の電圧を印加した場合でも、ベタパターンの外周端からλ/4(λ:使用する周波数の波長)のところで短絡状態となるため、良好なシールド効果が得られ、これによりシールド効果を維持したまま、ベタパターンを電源電圧又は他の任意の電圧の給電導体として用いることができる。 According to the present invention, from the outer peripheral edge of the solid pattern of the inner layer, the inner region is set as the element mounting region by a length that is a quarter of the wavelength of the electromagnetic wave of the high-frequency electric signal used on the high-frequency circuit board. Thus, even when a power supply voltage or any other voltage is applied to the solid pattern of the inner layer without connecting the solid pattern of the inner layer to the ground conductor, λ / 4 (λ: frequency used) Therefore, a good shielding effect can be obtained, so that the solid pattern can be used as a power supply conductor for a power supply voltage or any other voltage while maintaining the shielding effect.
それにより、高周波回路基板の表面又は裏面に配置した素子に印加するバイアス電圧の給電線を、高周波回路基板の表面又は裏面で引き回すことが不要となり、回路基板を小型化すると共に、給電線の引き回しにより発生するノイズを抑えることができる。 This eliminates the need to route the bias voltage feed line applied to the elements disposed on the front or back surface of the high-frequency circuit board on the front or back surface of the high-frequency circuit board, thereby reducing the size of the circuit board and routing the feed line. It is possible to suppress noise generated by.
図1は本発明による高周波回路基板の基本構成を示す。同図(a)は、高周波回路基板の表面及び裏面を示し、表面又は裏面の誘電体基板1又は3の外周に接地導体4又は5が配置され、該接地導体4又は5に接地用スルーホール6が設けられている様態を示している。
FIG. 1 shows a basic configuration of a high-frequency circuit board according to the present invention. FIG. 2A shows the front and back surfaces of a high-frequency circuit board, and a ground conductor 4 or 5 is disposed on the outer periphery of the
同図(b)は、高周波回路基板の内層パターンを示し、同図に示すように、内層のベタパターン2は、前述の接地用スルーホール6の導体と接触しないように、接地用スルーホール6より径の大きい穴21が穿設される。以下、内層のベタパターンを内層パターンという。 FIG. 5B shows the inner layer pattern of the high-frequency circuit board. As shown in the figure, the inner layer solid pattern 2 is not in contact with the conductor of the above-described grounding through hole 6. A hole 21 having a larger diameter is formed. Hereinafter, the solid pattern of the inner layer is referred to as an inner layer pattern.
同図(c)は、同図(a)及び(b)に示す切断位置A−A’で、高周波回路基板を切断したとき、即ち、接地用スルーホール6が存在しない箇所で切断したときの断面図を示している。同図(d)は、同図(a)及び(b)に示す切断位置B−B’で、高周波回路基板を切断したとき、即ち、接地用スルーホール6の存在する箇所で切断したときの断面図を示している。 FIG. 6C shows a state when the high-frequency circuit board is cut at the cutting position AA ′ shown in FIGS. 6A and 6B, that is, when the ground through hole 6 is not cut. A cross-sectional view is shown. FIG. 6D shows a state when the high-frequency circuit board is cut at the cutting position BB ′ shown in FIGS. 6A and 6B, that is, when it is cut at a location where the grounding through hole 6 exists. A cross-sectional view is shown.
図1(d)に示しているように、本発明による高周波回路基板の内層パターン2には、接地用スルーホール6の周辺にそれより大きい穴21が空けられているので、内層パターン2は、表面及び裏面の接地導体4及び5と接続されない。なお、表面及び裏面の接地導体4,5は、誘電体基板1,3の外周に配置され、従来と同様にスルーホール6を通して接続される。内層パターン2は接地用スルーホール6の導体に接続されないので、内層パターン2に電源電圧又は他の任意の電圧を印加することができる。
As shown in FIG. 1D, the inner layer pattern 2 of the high-frequency circuit board according to the present invention has a larger hole 21 around the grounding through hole 6, so that the inner layer pattern 2 is It is not connected to the ground conductors 4 and 5 on the front and back surfaces. The ground conductors 4 and 5 on the front and back surfaces are arranged on the outer periphery of the
本発明による高周波回路基板は、シールド効果を有するようにするために、内層パターン2にチョーク構造を用いる。チョーク構造とは、特定の周波数でのみ電磁波を遮蔽する構造である。以下、図2を参照して本発明の原理を説明する。図2は前述の図1(b)及び(d)に該当する。 The high-frequency circuit board according to the present invention uses a choke structure for the inner layer pattern 2 in order to have a shielding effect. The choke structure is a structure that shields electromagnetic waves only at a specific frequency. The principle of the present invention will be described below with reference to FIG. FIG. 2 corresponds to FIG. 1 (b) and (d) described above.
図2において、内層パターン2の端部C点は、高周波回路としてインピーダンスが無限大(open)の点であり、C点からλ/4(λは使用される高周波電気信号の電磁波の波長)離れたD点(破線部)では、短絡(short)状態となる。従って、D点を接地導体で接続してシールドしなくても、内層パターン2は、D点より内側の領域において良好なシールド効果が得られる。 In FIG. 2, the end C point of the inner layer pattern 2 is a point where the impedance of the high frequency circuit is infinite (open), and is away from the C point by λ / 4 (λ is the wavelength of the electromagnetic wave of the high frequency electric signal used). Further, at point D (broken line portion), a short circuit state occurs. Therefore, even if the D point is not connected and shielded by the ground conductor, the inner layer pattern 2 can obtain a good shielding effect in the region inside the D point.
ここで、誘電体基板の誘電率εrが3.6、厚さが0.4mmであるとすると、使用される高周波電気信号の周波数fがそれぞれ、f=1GHzのときλ/4=44.9mm、f=10GHzのときλ/4=4.4mm、f=30GHzのときλ/4=1.4mm、f=50GHzのときλ/4=0.8mmとなる。従って、本発明による高周波回路基板は、数ギガヘルツ以上の高い周波数帯域で使用される回路基板に好適に適用することができる。 Here, assuming that the dielectric constant εr of the dielectric substrate is 3.6 and the thickness is 0.4 mm, λ / 4 = 44.9 mm when the frequency f of the high-frequency electrical signal used is f = 1 GHz, respectively. Λ / 4 = 4.4 mm when f = 10 GHz, λ / 4 = 1.4 mm when f = 30 GHz, and λ / 4 = 0.8 mm when f = 50 GHz. Therefore, the high-frequency circuit board according to the present invention can be suitably applied to a circuit board used in a high frequency band of several gigahertz or more.
図3は本発明の実施例であり、図1(d)に示した基本構成に種々の改変を加えた構成例を示している。図3(a)に示す第1の実施例は、内層パターン2に接地電圧とは異なる電圧を印加し、表面の誘電体基板1のパターンと内層パターン2とをインナービア8で繋ぐことにより、高周波回路基板の表面に配置したデバイスや部品などの素子9に、内層パターン2に印加された電圧を付与する実施例を示している。
FIG. 3 is an embodiment of the present invention, and shows a configuration example in which various modifications are made to the basic configuration shown in FIG. In the first embodiment shown in FIG. 3A, a voltage different from the ground voltage is applied to the inner layer pattern 2, and the pattern of the
この構成を用いることにより、高周波回路基板の表面又は裏面に配置したデバイスや部品等の素子9に印加するバイアス電圧の給電線を、高周波回路基板の表面又は裏面で引き回すことが不要となり、回路基板を小型化すると共に、給電線の引き回しにより発生するノイズを抑えることができ、回路動作が安定な回路基板が得られる。 By using this configuration, it is not necessary to draw a bias voltage feeding line to be applied to the element 9 such as a device or a component disposed on the front or back surface of the high-frequency circuit board on the front or back surface of the high-frequency circuit board. As well as reducing the size of the circuit board, it is possible to suppress noise generated by routing the power supply line, and to obtain a circuit board with stable circuit operation.
図3(b)に示す第2の実施例は、図1(d)に示す基本構成に更に誘電体基板10を1層追加し、該誘電体基板10に第2の内層パターン11を設けた実施例である。第1の内層パターン2と第2の内層パターン11はそれぞれ互いに独立しているので、それぞれに異なる電圧を印加することができる。この構成を用いることにより、高周波回路基板の表面又は裏面にあるデバイスや部品に複数の異なる電圧を印加することができる。 In the second embodiment shown in FIG. 3B, a dielectric substrate 10 is further added to the basic structure shown in FIG. 1D, and a second inner layer pattern 11 is provided on the dielectric substrate 10. This is an example. Since the first inner layer pattern 2 and the second inner layer pattern 11 are independent of each other, different voltages can be applied to each. By using this configuration, a plurality of different voltages can be applied to devices and components on the front or back surface of the high-frequency circuit board.
図3(c)に示す第3の実施例は、図1(d)に示す基本構成に、内層パターン2と接地導体4とを、インナービア8を介して接続するコンデンサ12を追加した実施例である。この構成を用いることにより、コンデンサ12をバイパスコンデンサとして作用させ、内層パターン2で発生する低周波によるノイズをコンデンサ12で吸収することでノイズの影響を軽減し、内層パターン2の電圧をより安定な状態に維持することができる。 The third embodiment shown in FIG. 3 (c) is an embodiment in which a capacitor 12 for connecting the inner layer pattern 2 and the ground conductor 4 via the inner via 8 is added to the basic configuration shown in FIG. 1 (d). It is. By using this configuration, the capacitor 12 acts as a bypass capacitor, and the noise caused by the low frequency generated in the inner layer pattern 2 is absorbed by the capacitor 12, thereby reducing the influence of the noise and making the voltage of the inner layer pattern 2 more stable. Can be maintained in a state.
また、内層パターン2がパッチアンテナ構造として作用し、共振により発振することがあるが、コンデンサ12を介して内層パターン2を接地導体4に接続し、発振を起こす高周波成分を接地導体に導くことにより、このような発振現象を防止することができる。 Further, the inner layer pattern 2 acts as a patch antenna structure and may oscillate due to resonance. However, by connecting the inner layer pattern 2 to the ground conductor 4 via the capacitor 12 and guiding a high frequency component causing oscillation to the ground conductor. Such an oscillation phenomenon can be prevented.
1,3 誘電体基板
2 内層パターン
21 内層パターンの穴
4,5 接地導体
6 接地用スルーホール
7 シールドケース
8 インナービア
9 デバイス又は部品等の素子
10 誘電体基板
11 内層パターン
12 コンデンサ
DESCRIPTION OF
Claims (5)
前記ベタパターンの外周端から、高周波回路基板上で使用される高周波の電気信号の電磁波の波長の4分の1の長さ分、内側の領域を素子実装領域とし、該ベタパターンに接地電圧とは異なる電圧を印加する構成を有することを特徴とする高周波回路基板。 In a high-frequency circuit board with a multilayer structure having a solid pattern in the inner layer,
From the outer peripheral edge of the solid pattern, the inner region is an element mounting region corresponding to the length of one quarter of the wavelength of the electromagnetic wave of the high-frequency electric signal used on the high-frequency circuit board. A high frequency circuit board characterized by having a configuration for applying different voltages.
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011040703A (en) * | 2009-08-10 | 2011-02-24 | Samsung Electro-Mechanics Co Ltd | Emi noise reduction printed circuit board |
WO2014027457A1 (en) * | 2012-08-15 | 2014-02-20 | 日本電気株式会社 | Current suppression element and current suppression method |
JP6490255B1 (en) * | 2018-01-16 | 2019-03-27 | 三菱電機株式会社 | Automotive electronics |
JP7502491B2 (en) | 2020-06-04 | 2024-06-18 | 株式会社藤商事 | Gaming Machines |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07263871A (en) * | 1994-03-18 | 1995-10-13 | Fujitsu Ltd | Printed wiring board |
JPH09223905A (en) * | 1996-02-16 | 1997-08-26 | Nippon Telegr & Teleph Corp <Ntt> | High frequency suppression circuit |
JPH09246776A (en) * | 1996-03-14 | 1997-09-19 | Oki Electric Ind Co Ltd | Printed wiring board |
JPH09275278A (en) * | 1996-04-05 | 1997-10-21 | Hitachi Ltd | Printed wiring board, electronic equipment device, and design support system |
JPH09283974A (en) * | 1996-04-19 | 1997-10-31 | Hitachi Ltd | Low-emi multilayer circuit board and electronic apparatus using the same |
JPH10190237A (en) * | 1996-12-20 | 1998-07-21 | Nec Corp | Printed circuit board |
JP2000183541A (en) * | 1998-12-11 | 2000-06-30 | Toshiba Iyo System Engineering Kk | Multilayer printed board |
JP2000307203A (en) * | 1999-04-22 | 2000-11-02 | Denso Corp | Board for mounting electronic parts |
JP2001244582A (en) * | 2000-02-29 | 2001-09-07 | Kyocera Corp | Wiring board |
JP2004363392A (en) * | 2003-06-05 | 2004-12-24 | Hitachi Ltd | Printed wiring board and radio communication apparatus |
WO2005036737A1 (en) * | 2003-09-17 | 2005-04-21 | Raytheon Company | Monolithic array amplifier with periodic bias-line bypassing structure and method |
JP2005302799A (en) * | 2004-04-07 | 2005-10-27 | Canon Inc | Multilayered printed wiring board |
-
2006
- 2006-02-02 JP JP2006025273A patent/JP5082250B2/en not_active Expired - Fee Related
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07263871A (en) * | 1994-03-18 | 1995-10-13 | Fujitsu Ltd | Printed wiring board |
JPH09223905A (en) * | 1996-02-16 | 1997-08-26 | Nippon Telegr & Teleph Corp <Ntt> | High frequency suppression circuit |
JPH09246776A (en) * | 1996-03-14 | 1997-09-19 | Oki Electric Ind Co Ltd | Printed wiring board |
JPH09275278A (en) * | 1996-04-05 | 1997-10-21 | Hitachi Ltd | Printed wiring board, electronic equipment device, and design support system |
JPH09283974A (en) * | 1996-04-19 | 1997-10-31 | Hitachi Ltd | Low-emi multilayer circuit board and electronic apparatus using the same |
JPH10190237A (en) * | 1996-12-20 | 1998-07-21 | Nec Corp | Printed circuit board |
JP2000183541A (en) * | 1998-12-11 | 2000-06-30 | Toshiba Iyo System Engineering Kk | Multilayer printed board |
JP2000307203A (en) * | 1999-04-22 | 2000-11-02 | Denso Corp | Board for mounting electronic parts |
JP2001244582A (en) * | 2000-02-29 | 2001-09-07 | Kyocera Corp | Wiring board |
JP2004363392A (en) * | 2003-06-05 | 2004-12-24 | Hitachi Ltd | Printed wiring board and radio communication apparatus |
WO2005036737A1 (en) * | 2003-09-17 | 2005-04-21 | Raytheon Company | Monolithic array amplifier with periodic bias-line bypassing structure and method |
JP2005302799A (en) * | 2004-04-07 | 2005-10-27 | Canon Inc | Multilayered printed wiring board |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011040703A (en) * | 2009-08-10 | 2011-02-24 | Samsung Electro-Mechanics Co Ltd | Emi noise reduction printed circuit board |
WO2014027457A1 (en) * | 2012-08-15 | 2014-02-20 | 日本電気株式会社 | Current suppression element and current suppression method |
JP6490255B1 (en) * | 2018-01-16 | 2019-03-27 | 三菱電機株式会社 | Automotive electronics |
CN110049615A (en) * | 2018-01-16 | 2019-07-23 | 三菱电机株式会社 | Car-mounted electronic device |
JP2019125668A (en) * | 2018-01-16 | 2019-07-25 | 三菱電機株式会社 | On-vehicle electronic device |
CN110049615B (en) * | 2018-01-16 | 2022-03-01 | 三菱电机株式会社 | Vehicle-mounted electronic device |
JP7502491B2 (en) | 2020-06-04 | 2024-06-18 | 株式会社藤商事 | Gaming Machines |
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