JP2007207816A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can easily increase the thickness of a stress application film, and to provide a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device is provided with, as shown in Fig. 2H, a semiconductor substrate 101, a gate insulation film 102A, a gate electrode 102B, a gate side wall insulation film, an interlayer insulation film 112, a wiring layer, an interlayer connection part, and a stress application film. The stress application film has a first section arranged between the semiconductor substrate 101 and the interlayer insulation film 112, a second section arranged between the gate electrode 102B and the interlayer insulation film 112, a third section arranged between the gate side wall insulation film 104 and the interlayer insulation film 112, and a fourth section arranged between the inner face of a through-hole and the interlayer connection part. The stress appliction film applies stress to the semiconductor substrate. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

With the increase in processing capability required for semiconductor devices such as FETs, the operation speed of semiconductor devices has been increased.
Here, a technique for increasing the speed of the transistor by increasing the carrier mobility by applying a stress to the channel region of the semiconductor device by an internal stress film is disclosed (see Patent Document 1).
JP-A-2005-57301

As the stress applied to the channel region increases, the carrier mobility increases. In order to increase the applied stress, it is conceivable to increase the thickness of the internal stress film.
However, since miniaturization of semiconductor devices is progressing, it is not always easy to increase the thickness of the internal stress film.
In view of the above, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device in which the thickness of the stress application film can be easily increased.

  A semiconductor device according to one embodiment of the present invention includes a semiconductor substrate having a source region, a drain region, and a channel region disposed between the source region and the drain region, and a gate disposed on the channel region. An insulating film; a gate electrode disposed on the gate insulating film; a gate sidewall insulating film disposed on a side surface of the gate electrode; covering the semiconductor substrate, the gate electrode, and the gate sidewall insulating film; An interlayer insulating film having a through hole disposed in at least one of the source region and the drain region; a wiring layer disposed on the interlayer insulating film; and the source region and the drain disposed in the through hole. An interlayer connection portion for electrically connecting at least one of the regions and the wiring layer; and a first portion disposed between the semiconductor substrate and the interlayer insulating film. A second portion disposed between the gate electrode and the interlayer insulating film, a third portion disposed between the gate sidewall insulating film and the interlayer insulating film, and the through-hole And a fourth portion disposed between the inner surface of the hole and the side surface of the interlayer connection portion, and a stress applying film that applies stress to the semiconductor substrate.

  A method of manufacturing a semiconductor device according to an aspect of the present invention includes a step of forming a gate insulating film on a semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and gate sidewall insulation on a side surface of the gate electrode. Forming a film; forming a diffusion layer having a source region and a drain region by implanting and diffusing impurities into the semiconductor substrate; and electrically connecting to at least one of the source region and the drain region. Forming an interlayer connection portion, and a stress applying film for applying stress to the semiconductor substrate on the source region, the drain region, the gate sidewall insulating film, and the side surface of the interlayer connection portion. Forming an interlayer insulating film on the stress applying film; electrically connecting the interlayer connection portion on the interlayer insulating film; Characterized by comprising the steps of: forming a wiring layer connected

  According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing the semiconductor device in which the thickness of the stress application film can be easily increased.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
FIG. 1 is a flowchart showing a procedure for manufacturing a semiconductor device according to the first embodiment of the present invention. 2A to 2H are cross-sectional views showing an example of a semiconductor device manufactured by the manufacturing procedure shown in FIG.
Here, as a semiconductor device, a MIS (Metal-Insulator-Semiconductor) field effect transistor (MIS-FET) is taken as an example and a manufacturing method thereof is shown.

(1) Formation of gate 102, diffusion layer 103, sidewall insulating film 104, and silicide film 105 (step S11 and FIG. 2A)
For example, a gate 102 (gate insulating film 102A, gate electrode 102B), a diffusion layer 103, and a silicide film 105 (105A, 105B) are formed on a semiconductor substrate 101 made of silicon. For example, the gate 102 and the like can be formed by the following procedure.

1) Formation of the gate 102-Prior to the formation of the gate 102, an element isolation region having an STI (Shallow Trench Isolation) structure is formed in the semiconductor substrate 101. A trench is formed in the semiconductor substrate 101, and the inside of the trench is filled with, for example, a silicon oxide film, thereby forming an element isolation region. This is because a plurality of MIS-FETs formed on the semiconductor substrate 101 are separated as elements. In FIG. 2A to FIG. 2H, the element isolation region is not shown for ease of viewing.

  A gate 102 (gate insulating film 102A, gate electrode 102B) is formed. A pattern of the gate insulating film 102A is formed on the semiconductor substrate 101, and a pattern of the gate electrode 102B made of, for example, polysilicon and having a thickness of about 150 nm is selectively formed on the gate insulating film 102A.

2) Formation of diffusion layer 103 and sidewall insulating film 104 The diffusion layer 103 and the sidewall insulating film 104 are formed. A diffusion layer 103 including source / drain regions is formed by ion implantation and diffusion into the semiconductor substrate 101. Specifically, the diffusion layer 103 and the sidewall insulating film 104 are formed as follows.

Using the gate 102 as a mask, impurity ions having a low impurity concentration are implanted into the semiconductor substrate 101 and diffused (formation of a diffusion layer having a low impurity concentration).
An insulating film, for example, a silicon oxide film is formed on the semiconductor substrate 101 and selectively removed, so that a side wall insulating film 104 is formed on the side wall of the gate 102. The sidewall insulating film 104 is used as a mask for implanting impurity ions having a high impurity concentration.
High impurity concentration impurity ions are implanted into the semiconductor substrate 101 and diffused using the gate 102 and the sidewall insulating film 104 as a mask (formation of a high impurity concentration diffusion layer).

  The diffusion layer 103 including the source / drain regions is formed by the above two ion implantations and diffusions. Since the diffusion layer 103 is formed using the gate 102 as a mask, the gate 102 is disposed in the channel region between the two source / drain regions. That is, a plurality of MIS-FETs including a source, a drain, and a gate are formed.

3) Formation of Silicide Film 105 A metal film, for example, a titanium thin film is formed on the semiconductor substrate 101 and heated, whereby the metal and the semiconductor (silicon) react to form the silicide film 105. Silicide films 105A and 105B are formed on the gate electrode 102B and the source / drain regions. Since the semiconductor substrate 101 is not exposed on the sidewall insulating film 104, the silicide film 105 is not formed. The unreacted titanium thin film is selectively removed by etching.

(2) Formation of contact 109 (step S12 and FIGS. 2B to 2F)
Contact 109 (109A, 109B) is formed on semiconductor substrate 101 as follows. This is for electrical connection between different layers. The contact 109 is disposed in a contact hole 108 described later and functions as an interlayer connection portion that electrically connects a source / drain region and an upper wiring layer 113 described later.

1) An etching stop film, for example, a silicon nitride film 106 having a film thickness T11 is uniformly formed on the entire surface of the semiconductor substrate 101 including the gate electrode 102B (FIG. 2B).
At this time, the film thickness T11 (for example, about 20 nm) of the silicon nitride film 106 is smaller than ½ of the minimum distance D1 (for example, about 50 nm) (2 * T11 <D1). This is to prevent the gap between the gate electrodes 102B facing each other across the contact 109 from being blocked by the silicon nitride film 106.
Note that the minimum distance D1 between the side walls is the minimum value of the distance between the gate electrodes 102B (more precisely, the side wall insulating film 104) facing each other with the contact 109 formed later.

  2) A dummy interlayer insulating film 107 made of, for example, a silicon oxide film is formed on the silicon nitride film 106. The dummy interlayer insulating film 107 is planarized, and the dummy interlayer insulating film 107 and the silicon nitride film 106 are etched by RIE (Reactive Ion Etching) or the like using the resist pattern as a mask to form contact holes 108 (108A, 108B) ( (FIG. 2C, FIG. 2D).

  Here, a contact hole (through hole) 108 is formed by two-stage etching. That is, the dummy interlayer insulating film 107 is etched under the first etching condition in which the etching speed of the dummy interlayer insulating film 107 is higher than the etching speed of the silicon nitride film 106 (the selectivity of the dummy interlayer insulating film 107 is high). . At this time, the etching is temporarily stopped by the silicon nitride film 106 (FIG. 2C). That is, the silicon nitride film 106 is used as an etching stop layer for stopping the etching of the dummy interlayer insulating film 107. Thereafter, the etching condition is changed to the second etching condition, and the silicon nitride film 106 is etched (FIG. 2D).

As a result, it is easy to open contact holes 108 having different depths at once. For example, the depth of the contact hole 108 required for forming the contact 109 is different between the gate electrode 102B and the semiconductor substrate 101 (on the source / drain region) (the latter is deeper than the former). That is, the thickness of the dummy interlayer insulating film 107 is not uniform.
Although the thickness of the dummy interlayer insulating film 107 is not uniform, the silicon nitride film 106 functions as an etching stop layer for the first etching. Therefore, the first through hole can be formed in the dummy interlayer insulating film 107 having different thicknesses by the first etching.
On the other hand, the thickness of the silicon nitride film 106 is substantially uniform, for example, on the semiconductor substrate 101 and on the gate electrode 102B. For this reason, the second through hole can be formed in the silicon nitride film 106 substantially simultaneously by the second etching. As described above, the contact hole 108 formed by coupling the first and second through holes is formed.

Here, as in the following methods 1 to 3, the contact hole 108 can be formed without using an etching stop layer such as the silicon nitride film 106.
・ Method 1
Each contact hole 108 having a different depth is formed by a separate process.

・ Method 2
When the silicon nitride film 106 is etched, a member (for example, the silicide film 105) disposed at the bottom of the contact hole 108 is made difficult to be etched. That is, the selection ratio between the bottom portion of the contact hole 108 and the dummy interlayer insulating film 107 is greatly different.
Since the dummy interlayer insulating film 107 is removed later and is not directly related to the operation of the semiconductor device, its constituent material can be selected relatively freely. For this reason, for example, a material having a significantly higher etching rate than the silicide film 105 can be used for the dummy interlayer insulating film 107.
It is also possible to adjust the selection ratio between the member at the bottom of the contact hole 108 and the dummy interlayer insulating film 107 by the combination of the member disposed at the bottom of the contact hole 108 and the etching conditions.

・ Method 3
The thickness of the silicide film 105A on the gate electrode 102B is made larger than that of the silicide film 105B on the semiconductor substrate 101 (on the source / drain regions).
As described above, the depth of the contact hole 108 necessary for forming the contact 109 is different between the gate electrode 102B and the semiconductor substrate 101 (on the source / drain region) (the latter is deeper than the former). . In consideration of this difference in depth, by increasing the thickness of the silicide film 105A, it is possible to protect the gate electrode 102B from etching during the formation of the contact hole 108.
In order to change the thickness of the silicide films 105A and 105B, for example, the silicide films 105A and 105B may be formed by separate processes.

  3) By burying a wiring material in these contact holes 108, contacts 109 are formed (FIG. 2E), and the dummy interlayer insulating film 107 is removed by, for example, wet etching (FIG. 2F).

(3) Formation of stress applying film (step S13 and FIG. 2G)
For example, a silicon nitride film 110 of about 50 nm is formed as a stress liner (stress application film) so as to cover the silicon nitride film 106 and the contact 109. If the etching stop layer and the stress liner are made of substantially the same material, they all function as a stress liner. That is, the silicon nitride film 106 functions as both an etching stop layer and a stress liner. Here, in consideration of the unity of the silicon nitride films 106 and 110, these boundaries are illustrated by broken lines.

  Even if the etching stop layer and the stress liner are not made of the same material, it is possible to make the whole function as a stress liner. That is, if the etching stop layer has the same stress (tensile stress or compressive stress) as the stress liner, the stress in the semiconductor substrate 101 is not canceled by the stress of the etching stop layer. Increase.

  At this time, the deposition rate of the silicon nitride film 110 on the upper part of the side surface of the gate electrode 102B (exactly, on the side wall insulating film 104) is lower than the lower part of the side surface of the gate electrode 102B (exactly, the side wall insulating film 104). It is possible to adopt a deposition condition that is larger than the deposition rate of the silicon nitride film 110 in the lower part (at this time, the deposition rate on the semiconductor substrate 101 is smaller than the deposition rate on the upper part of the side surface of the gate electrode 102B). By doing so, the space between the side wall insulating films 104 or between the side wall insulating film 104 and the contacts 109 (hereinafter referred to as “between the side wall insulating films 104”) is blocked by the silicon nitride film 110, and voids are formed in the silicon nitride film 110. 111 is formed.

  As the above-described deposition conditions, so-called supply rate limiting can be mentioned. Supply rate limiting means that the controlling factor of the film deposition rate is the supply amount of the constituent material of the film, and is contrasted with surface reaction rate limiting (the controlling factor of the film deposition rate is the reaction on the surface of the film). Under the supply rate limiting condition, the film forming material is consumed from the upper part to the lower part such as between the side wall insulating films 104, and the deposition rate decreases.

In order to achieve supply rate control, it is conceivable to form a film under conditions of high temperature and high pressure. For example, LPCVD (Low Pressure CVD) is used to form the silicon nitride film 110 under relatively high temperature and high pressure conditions. By doing so, the deposition rate at the upper part of the sidewall insulating film 104 can be made larger than the deposition rate at the lower part thereof.
Moreover, plasma CVD can be mentioned as a method that does not necessarily depend on supply rate control. In plasma CVD, the deposition rate at the upper part of the sidewall insulating film 104 can be made larger than the deposition rate at the lower part thereof due to the concentration of the electric field on the square shape.

(4) Formation of interlayer insulating film 112 and upper wiring layer 113 (step S14 and FIG. 2H)
An interlayer insulating film 112 is formed so as to cover the silicon nitride film 110. Unnecessary interlayer insulating film 112 and silicon nitride film 110 above contact 109 are planarized by CMP (Chemical-Mechanical Polishing), and upper wiring layer 113 is formed thereon.

  The silicon nitride film 110 can be divided into a first portion 110 (1) to a fourth portion 110 (4). The first portion 110 (1) is disposed between the semiconductor substrate 101 and the interlayer insulating film 112. The second portion 110 (2) is disposed between the gate electrode 102 and the interlayer insulating film 112. The third portion 110 (3) is disposed between the sidewall insulating film 104 and the interlayer insulating film 112. The fourth portion 110 (4) is disposed between the inner surface of the through hole of the interlayer insulating film 112 and the interlayer connection portion (contact 109).

  The formed silicon nitride films 106 and 110 are attached to the semiconductor substrate 101 with internal stress (attached in a stretched state). Therefore, stress is applied to the channel layer in the semiconductor substrate 101 by the silicon nitride films 106 and 110 (the silicon nitride films 106 and 110 function as a stress liner (stress application film)). By increasing the internal stress of the channel layer, the carrier mobility is increased and the drive current is increased. Here, generally, the thicker the stress liner, the greater the internal stress applied to the channel layer.

The stress liner (stress application film) is a film that is attached to the semiconductor substrate 101 with internal stress and applies stress to the semiconductor substrate 101. For example, a film having an internal stress F of 0.5 GPa or more (more preferably 1 GPa or more) functions as a stress application film.
The internal stress of a film such as a stress liner can be calculated from the amount of curvature (curvature radius) of a substrate (for example, a silicon substrate) on which the film is formed on one side and the film thickness of the film. That is, when a stress liner or the like is formed, a film is formed on a stress measurement substrate, and the stress is measured using the substrate.

As shown in FIG. 2B and Comparative Examples 1 and 2 to be described later, a certain limitation is imposed on the thickness of the silicon nitride film 106. For this reason, if only the silicon nitride film 106 is used as the stress application film, the thickness of the stress application film is limited. That is, in order to prevent damage caused by RIE when the contact hole 108 is opened, the thickness T11 of the silicon nitride film 106 is limited to approximately half or less of the minimum side wall distance D1.
However, such a restriction is not imposed on the silicon nitride film 110 formed after the contact 109 is formed. Therefore, if the optimum thickness of the stress liner is T, the thickness T12 of the silicon nitride film 110 can be easily set to (T−T11).

  In this embodiment, a silicon nitride film 106 having a thickness of T11 is used as an etching stop layer for the dummy interlayer insulating film 107 when the contact 109 is formed. A silicon nitride film 110 is formed after the contact 109 is formed. As a result, the entire silicon nitride films 106 and 110 can be used as the stress liner, and the sum of these film thicknesses (T11 + T12) is the effective thickness of the stress liner.

  In the present embodiment, the void 111 is formed in the stress liner (silicon nitride film 110) between the gate electrodes 102B, and the stress can be increased. The stress liner is disposed on the sidewall insulating film 104 and the diffusion layer 103. For this reason, as shown in FIG. 2H, as the internal stress of the stress liner, the first stress F1 (stress in the vertical direction of the semiconductor substrate 101) on the sidewall insulating film 104 and the second stress on the diffusion layer 103 are used. There are two types of stress F2 (stress in the horizontal direction of the semiconductor substrate 101). When the air gap 111 is present, the first and second stresses F1 and F2 are separated (cancellation between the first and second stresses is prevented), and the first and second stresses F1 and F2 The resultant force F3 is applied to the channel layer in the semiconductor substrate 101. As a result, the internal stress of the channel layer is further increased.

(Comparative Example 1)
FIG. 3 is a flowchart showing a procedure for manufacturing a semiconductor device according to a comparative example of the present invention. Here, the stress liner is not formed after the contact 509 is formed. 4A to 4E are sectional views showing an example of a semiconductor device manufactured according to the manufacturing method shown in FIG.
(1) Formation of gate 502, diffusion layer 503, sidewall insulating film 504, and silicide film 505 (step S51 and FIG. 4A)
A gate 502 (gate insulating film 502A, gate electrode 502B), a diffusion layer 503, and a silicide film 505 (505A, 505B) are formed on the semiconductor substrate 501. Since this procedure is not essentially different from that of the first embodiment, description thereof is omitted.

(2) Formation of stress applying film (step S22 and FIG. 4B)
A silicon nitride film 506 covering the diffusion layer 103 and the gate electrode 102B is uniformly formed. The silicon nitride film 506 functions as a stress application film and an etching stop layer.

(3) Formation of contact 509 (step S23 and FIGS. 4C to 4E)
Contact 509 (509A, 509B) is formed on the semiconductor substrate 501 as follows.
1) An interlayer insulating film 507 made of, for example, a silicon oxide film is formed on the silicon nitride film 506. By flattening the interlayer insulating film 507 and etching the interlayer insulating film 507 and the silicon nitride film 106 using the resist pattern as a mask, a contact hole 108 is formed (opened) (FIGS. 4C and 4D).

  2) A contact 509 is formed by embedding a wiring material in these contact holes 508 (FIG. 4E).

  In the above comparative example, the film thickness T51 of the silicon nitride film 506 is smaller than about half of the minimum distance D5 between the side walls (T51 <D5 / 2), and the silicon nitride film 506 is not blocked between the side wall insulating films 504. Is assumed.

(Comparative Example 2)
4A to 4H, when a plurality of gate electrodes 102B are arranged on the same semiconductor substrate 501, the distance between these gate electrodes 502B is not always constant. That is, there may be a pattern layout in which a plurality of distances between the gate electrodes 502B are mixed. In this case, this assumption may be satisfied at a location where the distance between the sidewall insulating films 104 is large, and this assumption may not be satisfied at a location where the distance between the sidewall insulating films 504 is narrow.

The following describes the adverse effects that can occur if this assumption is not met.
5A to 5E are cross-sectional views showing other examples of the semiconductor device manufactured according to the manufacturing method shown in FIG. 3, and show a semiconductor device having a silicon nitride film 506 thicker than those in FIGS. 4A to 4E.

  Here, the film thickness T52 of the silicon nitride film 506 is larger than approximately ½ of the minimum distance D5 between the sidewalls (T52> D5 / 2), and the silicon nitride film 506 is in contact with the sidewall insulating film 504 or in contact with the sidewall insulating film 504. 509 (hereinafter referred to as “between the side wall insulating films 504 and the like”). Accordingly, as shown in FIG. 5A, the film thickness T53 of the silicon nitride film 506 on the semiconductor substrate 501 at the closed position is equal to the sum of the height H of the vertical portion of the sidewall insulating film 504 and the film thickness T52 ( T53 = H + T52).

On the other hand, there are places where the distance D51 between the sidewall insulating films 504 is smaller than the film thickness T52 of the silicon nitride film 506 (T52 <D51 / 2). That is, the silicon nitride film 506 is not blocked at this location.
As described above, in FIGS. 5A to 5E, the thickness of the silicon nitride film 506 is not uniform with T51 and T52.

  As described above, the contact hole 508 is formed by two-stage etching. That is, when the dummy interlayer insulating film 507 is etched and the silicon nitride film 506 is exposed on the bottom surface of the contact hole 108, the etching is stopped (FIG. 5B). Thereafter, the silicon nitride film 506 is etched.

  Here, since the thickness of the silicon nitride film 506 is not uniform, there is a possibility that damage due to etching may occur when the silicon nitride film 506 is etched. That is, the silicon nitride film 506 is etched at the location of the thickness T52 before the location of the thickness T53, and the contact hole 508A is opened (FIG. 5C).

When the silicon nitride film 506 is further etched to the depth H, a contact hole 508B is opened at the position of the thickness T53 of the silicon nitride film 506 (FIG. 5D).
In this case, the bottom of the contact hole 508A opened earlier continues to be damaged by RIE. As a result, depending on the RIE etching conditions, the lower portion of the silicon nitride film 506 in the contact hole 508A (for example, the semiconductor substrate 501, the gate electrode 502B, the element isolation region) may be excessively etched (FIG. 5E).

  Damage caused by RIE causes adhesion of foreign matter to the bottom of the contact hole 108A, causing the interface of the contact 109 to become electrically high resistance. Excessive etching of the semiconductor substrate 501 and the silicon nitride film 506 in the element isolation region causes leakage current from the contact 509 to the well portion in the semiconductor substrate 101 (the bulk portion of the semiconductor substrate 101 below the diffusion layer 503). Cause.

As described above, if the film thickness T52 of the silicon nitride film 506 is set to be larger than about half of the minimum side-wall distance D5 (T52> D5 / 2), it causes a defect in the semiconductor device.
As described above, in the first and second comparative examples, it is difficult to form the silicon nitride film 506 with a thickness approximately half or more of the minimum distance D5 between the side walls. For this reason, the internal stress that can be generated in the channel layer in the semiconductor substrate 501 is limited by the silicon nitride film 506.

(Contrast between the first embodiment and the comparative example)
When the stress liner is formed thick, the stress liner is blocked at a place where the interval between the gate electrodes is narrow, so that the thickness of the stress liner becomes nonuniform on the semiconductor substrate.

In the comparative example, the contact 509 is formed after the stress liner (silicon nitride film 506) is formed. In forming the contact 509, a dummy interlayer insulating film 507 is formed, and a contact hole 508 penetrating the dummy interlayer insulating film 507 and the stress liner is formed.
At this time, since the thickness of the stress liner is not uniform, it is difficult to form a plurality of contact holes 508 at the same time. As a result, there is a possibility that the performance of the semiconductor device is deteriorated due to poor formation of the contact 509 due to the non-opening of the contact hole 508 or excessive etching of the semiconductor substrate 501 or the like.

  On the other hand, in the first embodiment, a stress liner (silicon nitride film 110) is formed after the contact 109 is formed. Accordingly, the nonuniformity of the silicon nitride film 110 does not affect the formation of the contact hole 108. For this reason, simultaneous formation of contact holes 108 having different depths from the upper wiring layer 113 and an increase in the thickness of the stress liner can be achieved.

  Further, since the stress liner has the air gap 111, the stress applied to the channel layer is further increased. That is, the internal stress of the stress liner is divided into the first and second stresses in the vertical direction and the horizontal direction of the semiconductor substrate 101 by the gap 111. By applying these resultant forces to the channel layer in the semiconductor substrate 101, the internal stress of the channel layer can be increased.

(Second Embodiment)
6A to 6F are cross-sectional views showing an example of a semiconductor device manufactured according to the manufacturing method according to the second embodiment of the present invention. An outline of the semiconductor device manufacturing procedure at this time is shown in FIG.

(1) Formation of gate 202, diffusion layer 203, sidewall insulating film 204, and silicide film 205 (step S11 and FIG. 6A)
A gate 202 (gate insulating film 202A, gate electrode 202B), a diffusion layer 103, a sidewall insulating film 204, and a silicide film 205 (205A, 205B) are formed on the semiconductor substrate 101.

  Here, unlike the first embodiment, in this embodiment, the width of the upper portion of the gate 202 is larger than the width of the lower portion thereof. For this reason, the width of the upper part of the outer shape of the sidewall insulating film 204 is larger than the width of the lower part. As a result, the space between the sidewall insulating films 204 and the like is blocked by the silicon nitride film 210, and the gap 211 is easily formed in the silicon nitride film 210 between the sidewall insulating films 204 and the like. For example, even when the silicon nitride film 210 is deposited on the sidewall insulating film 204 with a uniform thickness, the upper portion of the sidewall insulating film 204 is blocked by the silicon nitride film 110.

1) Formation of the gate 202-Prior to the formation of the gate 202, an element isolation region having an STI (Shallow Trench Isolation) structure is formed in the semiconductor substrate 101.
A gate 202 (gate insulating film 202A, gate electrode 202B) is formed. A gate insulating film 202A is formed on the semiconductor substrate 101, and a gate electrode 202B made of, for example, polysilicon and having a thickness of about 150 nm is selectively formed on the gate insulating film 202A.

As described above, the upper portion of the gate 202 is wider than the lower portion. The gate 202 having such a shape can be formed by, for example, embedding a dummy film in a groove.
Prior to the formation of the gate 202, a dummy layer for forming a gate is formed, and this dummy layer is etched to form a groove (recess) serving as a mold of the gate 102. The gate 202 is formed by embedding the constituent material of the gate 202 in this groove and removing the dummy film.

  At this time, by making the shape of the groove wider at the upper part (opening part) than at the lower part (bottom part), the gate 202 having a wider upper part can be formed. Note that it is relatively easy to form a wider groove at the top if isotropic etching conditions are used.

2) Formation of diffusion layer 103 and sidewall insulating film 204 As in the first embodiment, the diffusion layer 103 and the sidewall insulating film 204 are formed. The sidewall insulating film 204 is not substantially different from the sidewall insulating film 104 according to the first embodiment, and the film thickness is substantially uniform.

Here, the thickness of the upper portion of the sidewall insulating film 204 may be made larger than the thickness of the lower portion thereof. By doing so, the outer shape of the sidewall insulating film 204 can be widened without making the upper portion of the gate 202 wide. That is, in order to make the outer shape of the sidewall insulating film 204 wider, any of the following three may be adopted.
-Control of the shape of the gate 2102 (the upper part is wider than the lower part)
-Control of the shape of the sidewall insulating film 204 (the film thickness at the upper part is made larger than the film thickness at the lower part)
Control of both gate 202 and sidewall insulating film 204 shapes

  FIG. 6G is a cross-sectional view illustrating an example of a semiconductor device in which the shape of the sidewall insulating film 304 is controlled to make the outer shape of the sidewall insulating film 304 wider. That is, the shape of the gate 102 is the same as that in the first embodiment, and the shape of the sidewall insulating film 304 is wide. Even if the semiconductor device of FIG. 6G is used instead of the semiconductor device of FIG. 6A, the following steps S13 and S14 can be executed.

3) Formation of Silicide Film 205 As in the first embodiment, silicide films 205 (205A, 205B) are formed on the gate electrode 202B and the source / drain regions.

(2) Contact formation (step S12 and FIGS. 6B to 6D)
A contact 209 is formed on the semiconductor substrate 101 as follows.
1) An etching stop film, for example, a silicon nitride film 206 having a thickness of 20 nm is uniformly formed on the entire surface of the semiconductor substrate 101 including the gate electrode 202B (FIG. 6B).
2) A dummy interlayer insulating film 207 made of, for example, a silicon oxide film is formed on the silicon nitride film 206. The dummy interlayer insulating film 207 is planarized, and the dummy interlayer insulating film 207 and the silicon nitride film 206 are etched by RIE or the like using the resist pattern as a mask, thereby forming (opening) the contact hole 208 (FIG. 6C).
3) A contact 209 is formed by embedding a wiring material in these contact holes 208, and the dummy interlayer insulating film 207 is removed by, for example, wet etching (FIG. 6D).

(3) Formation of stress applying film (step S13 and FIG. 6E)
As a stress liner (stress application film), for example, a silicon nitride film 210 is further formed to a thickness of about 50 nm so as to cover the silicon nitride film 206 and the contact 209.
At this time, the silicon nitride film 210 can be deposited on the sidewall insulating film 204 with a uniform film thickness. For example, when the silicon nitride film 210 is deposited at a surface reaction rate-determining rate, the thickness of the silicon nitride film 210 can be made uniform. However, the silicon nitride film 110 may be deposited at a rate-determining rate and the film thickness may be nonuniform.
The space between the sidewall insulating films 204 and the like is blocked by the silicon nitride film 210, and a gap 211 is formed in the silicon nitride film 210.

(4) Formation of interlayer insulating film 212 and upper wiring layer 213 (step S14 and FIG. 6F)
An interlayer insulating film 212 is formed so as to cover the silicon nitride film 210. Unnecessary interlayer insulating film 212 and silicon nitride film 210 on contact 209 are removed by CMP to planarize, and upper wiring layer 213 is formed thereon.

(Other embodiments)
Embodiments of the present invention are not limited to the above-described embodiments, and can be expanded and modified. The expanded and modified embodiments are also included in the technical scope of the present invention.
(1) For example, in the above embodiment, the etching stop film (silicon nitride film 106) and the stress liner (silicon nitride film 110) are made of the same material, but they can also be made of different materials. Even if the material is not the same, the entire etching stop film and the stress liner can function as a stress liner if the positive and negative stresses are at the same position. Further, the constituent material of these films is not necessarily silicon nitride.

(2) For example, the stress liner can be composed of only one layer as follows.
-The etching stop film may not have a function as a stress liner. As the etching stop film, a film having a small internal stress or an internal stress having a sign opposite to that of the stress liner can be used.
The contact 109 can be formed without using an etching stop film (silicon nitride film 106). As an example, the contacts 109 having different depths are formed by another process.

It is a flowchart showing the procedure of manufacture of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing showing an example of the semiconductor device manufactured by the manufacturing procedure shown in FIG. It is sectional drawing showing an example of the semiconductor device manufactured by the manufacturing procedure shown in FIG. It is sectional drawing showing an example of the semiconductor device manufactured by the manufacturing procedure shown in FIG. It is sectional drawing showing an example of the semiconductor device manufactured by the manufacturing procedure shown in FIG. It is sectional drawing showing an example of the semiconductor device manufactured by the manufacturing procedure shown in FIG. It is sectional drawing showing an example of the semiconductor device manufactured by the manufacturing procedure shown in FIG. It is sectional drawing showing an example of the semiconductor device manufactured by the manufacturing procedure shown in FIG. It is sectional drawing showing an example of the semiconductor device manufactured by the manufacturing procedure shown in FIG. It is a flowchart showing the procedure of manufacture of the semiconductor device which concerns on the comparative example of this invention. It is sectional drawing showing an example of the semiconductor device manufactured according to the manufacturing method shown in FIG. It is sectional drawing showing an example of the semiconductor device manufactured according to the manufacturing method shown in FIG. It is sectional drawing showing an example of the semiconductor device manufactured according to the manufacturing method shown in FIG. It is sectional drawing showing an example of the semiconductor device manufactured according to the manufacturing method shown in FIG. It is sectional drawing showing an example of the semiconductor device manufactured according to the manufacturing method shown in FIG. FIG. 4 is a cross-sectional view illustrating another example of a semiconductor device manufactured according to the manufacturing method illustrated in FIG. 3. FIG. 4 is a cross-sectional view illustrating another example of a semiconductor device manufactured according to the manufacturing method illustrated in FIG. 3. FIG. 4 is a cross-sectional view illustrating another example of a semiconductor device manufactured according to the manufacturing method illustrated in FIG. 3. FIG. 4 is a cross-sectional view illustrating another example of a semiconductor device manufactured according to the manufacturing method illustrated in FIG. 3. FIG. 4 is a cross-sectional view illustrating another example of a semiconductor device manufactured according to the manufacturing method illustrated in FIG. 3. It is sectional drawing showing an example of the semiconductor device manufactured according to the manufacturing method which concerns on the 2nd Embodiment of this invention. It is sectional drawing showing an example of the semiconductor device manufactured according to the manufacturing method which concerns on the 2nd Embodiment of this invention. It is sectional drawing showing an example of the semiconductor device manufactured according to the manufacturing method which concerns on the 2nd Embodiment of this invention. It is sectional drawing showing an example of the semiconductor device manufactured according to the manufacturing method which concerns on the 2nd Embodiment of this invention. It is sectional drawing showing an example of the semiconductor device manufactured according to the manufacturing method which concerns on the 2nd Embodiment of this invention. It is sectional drawing showing an example of the semiconductor device manufactured according to the manufacturing method which concerns on the 2nd Embodiment of this invention. It is sectional drawing showing an example of the semiconductor device manufactured according to the manufacturing method which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

 DESCRIPTION OF SYMBOLS 101 ... Semiconductor substrate, 102 ... Gate, 102A Gate insulating film, 102B ... Gate electrode, 103 ... Diffusion layer, 104 ... Side wall insulating film, 105 (105A, 105B) ... Silicide film, 106 ... Silicon nitride film, 107 ... Dummy layer Insulating film, 108 (108A, 108B) ... contact hole, 109 (109A, 109B) ... contact, 110 ... silicon nitride film, 111 ... gap, 112 ... interlayer insulating film, 113 ... upper wiring layer

Claims (6)

A semiconductor substrate having a source region, a drain region, and a channel region disposed between the source region and the drain region;
A gate insulating film disposed on the channel region;
A gate electrode disposed on the gate insulating film;
A gate sidewall insulating film disposed on a side surface of the gate electrode;
An interlayer insulating film covering the semiconductor substrate, the gate electrode, and the gate sidewall insulating film, and having a through hole disposed in at least one of the source region and the drain region;
A wiring layer disposed on the interlayer insulating film;
An interlayer connection part disposed in the through hole and electrically connecting at least one of the source region and the drain region and the wiring layer;
A first portion disposed between the semiconductor substrate and the interlayer insulating film; a second portion disposed between the gate electrode and the interlayer insulating film; the gate sidewall insulating film; A third portion disposed between the insulating film and a fourth portion disposed between the inner surface of the through hole and the interlayer connection portion, and applying stress to the semiconductor substrate; Stress applying film,
A semiconductor device comprising: The semiconductor device according to claim 1, wherein the stress application film has a gap. The semiconductor device according to claim 2, wherein the air gap is disposed between the gate sidewall insulating film and the interlayer connection portion. The distance between the upper portion of the gate sidewall insulating film and the side surface of the interlayer connection portion is smaller than the distance between the lower portion of the gate sidewall insulating film and the side surface of the interlayer connection portion. The semiconductor device described. Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a gate sidewall insulating film on a side surface of the gate electrode;
Forming a diffusion layer having a source region and a drain region by implanting and diffusing impurities into the semiconductor substrate;
Forming an interlayer connection electrically connected to at least one of the source region and the drain region;
Forming a stress applying film for applying stress to the semiconductor substrate on the source region, the drain region, the gate sidewall insulating film, and a side surface of the interlayer connection;
Forming an interlayer insulating film on the stress applying film;
Forming a wiring layer electrically connected to the interlayer connection on the interlayer insulating film;
A method for manufacturing a semiconductor device, comprising: 6. The method of manufacturing a semiconductor device according to claim 5, wherein an upper portion of the formed gate electrode is larger than a lower portion thereof.

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