JP2007206835A - Memory controller and flash memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory controller and a flash memory system, so as not to search only a specific physical block for an empty block. <P>SOLUTION: An address conversion table 100 which is stored in a work area and formed for each set of corresponding logical zone and physical zone stores the correspondence between logical block number LZIBN in the logical zone and physical block number PZIBN in the physical zone. When a certain logical block is accessed, LZIBN of this logical block is inspected, and PZIBN of a physical block corresponding to this logical block is acquired using the address conversion table 100. Search of empty block is started from a physical block having a PZIBN obtained by adding one to the acquired PZIBN of the physical block in the order of PZIBN. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory controller and a flash memory system including the memory controller.

In recent years, a flash memory, which is a non-volatile storage medium, has been developed and is widely used as a storage medium for information devices (host systems) such as digital cameras.
As the data handled by such devices has increased in capacity, the storage capacity of flash memory has also increased. In order to smoothly manage the flash memory having such a large capacity, a method of managing this storage area by dividing it into a plurality of zones has been used in recent years (see, for example, Patent Document 1).

  More specifically, the storage area of the conventional flash memory having a plurality of zones is partitioned and managed in the form shown in FIG. 11, for example.

  That is, a specific physical block address (PBA) is assigned to each physical block that is a unit of data erasing and includes a predetermined number of pages that are units of physical data reading and writing. Each physical block is classified into one of a plurality of physical zones, and a unique physical zone number (PZN) is assigned to each physical zone. In the example of FIG. 11, continuous PBAs # 0 to # 2047 are assigned to a total of 2048 physical blocks, and a total of 512 physical blocks PBA # 0 to # 511 belong to the physical zone of PZN # 0. , PBA # 512 to # 1023 total 512 physical blocks belong to PZN # 1 physical zone, and PBA # 1024 to # 1535 total 512 physical blocks belong to PZN # 2 physical zone, PBA # 1536 A total of 512 physical blocks of ˜ # 2047 belong to the physical zone of PZN # 3.

  Each page is assigned a physical page address (PPA). The PPA has a form in which a page number (PN), which is a serial number of the page in the physical block, is added to the lower level of the PBA of the physical block to which the page belongs.

  On the other hand, the address space on the host system side is managed by an LBA (Logical Block Address) which is a serial number assigned to an area divided in units of sectors (512 bytes). Further, a group of a plurality of sectors is called a logical block, and a group of a plurality of logical blocks is called a logical zone. The serial number assigned to the logical block is called a logical block number (LBN), and the serial number assigned to the logical zone is called a logical zone number (LZN). Further, the serial number in each logical zone of the logical block included in each logical zone is called a logical zone block number (LZIBN).

  Therefore, when the number of logical blocks included in each logical zone is n, the quotient when LBN is divided by n corresponds to LZN, and the remainder corresponds to LZIBN.

  In addition, one physical zone is allocated to each logical zone, and data corresponding to each logical block included in the logical zone is written to a physical block included in the physical zone allocated to the logical zone. Further, LZIBN (or LBN) of the logical block corresponding to the data is written in the redundant area of the physical block in which the data is written.

  Note that the correspondence between the physical block and the logical block changes every time data is written or erased. Therefore, an address conversion table is created in order to manage the correspondence between the two at each time point, and the address conversion table is updated each time the correspondence changes. This address conversion table can be created for each logical zone. That is, since the correspondence relationship between the logical zone and the physical zone is set in advance, an address conversion table is created by referring to the LZIBN written in the redundant area of the physical block included in the physical zone to be accessed. Can do.

  Here, even if the information (hereinafter referred to as logical address information) specifying the logical block to be written in the redundant area is LBN, an address conversion table can be created, but generally LZIBN with a small amount of data is used. Is written in the redundant area as logical address information.

  In general, a plurality of sectors having consecutive LBAs are allocated to each logical zone. In the example of FIG. 11, LBA # 0 to # 15999 sectors are in the LZN # 0 logical zone, LBA # 16000 to # 31999 sectors are in the LZN # 1 logical zone, and LBA # 32000 is in the LZN # 2 logical zone. ... To # 47999, and LBA # 48000 to # 63999 are assigned to the logical zone of LZN # 3, respectively. In this example, one page of the flash memory corresponds to one sector, and each physical block is composed of 32 pages.

The 16000 sectors assigned to each logical zone are managed as logical blocks in units of 32 sectors in which LBAs are continuous in the logical zone. Therefore, in other words, 32 sectors with consecutive LBAs are assigned as logical blocks, and 500 logical blocks with consecutive LBNs (LZIBN # 0 to # 499) are allocated to each logical zone. Here, the number of sectors included in the logical block is set as appropriate so that the capacities of one logical block and one or a plurality of physical blocks coincide. In addition, since data is stored in the LBA order in each page of the physical block, based on the correspondence between the logical block included in each logical zone and the physical block included in the physical zone corresponding to the logical zone. The access destination in the flash memory can be specified.
JP 2005-18490 A

  When writing new data to the flash memory, the physical zone corresponding to the logical zone to be written is searched, the unused physical block (empty block) in the physical zone is searched, and the data for the empty block is searched. Need to write. In this free block search, a free block is usually detected by scanning the usage status of physical blocks included in each physical zone in the order of physical block addresses. Also, this usage status scan starts from the physical block address next to the empty block detected in the previous search. In other words, the scan of this usage status is completed when an empty block is detected, and the next scan is started from the physical block address next to this empty block. However, in order to start scanning from the physical block address next to the free block detected in the previous search in the first search after turning on the power (after startup), the free block detected in the previous search The information specifying the physical block address must be stored in the nonvolatile memory. In addition, for the first search after the power is turned on (after startup), the search may be started from a predetermined physical block address. In this case, the search for an empty block is biased to a specific physical block. End up.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a memory controller and a flash memory system that do not bias the search for an empty block to a specific physical block.

In order to solve the above problems, a memory controller according to the first aspect of the present invention provides:
A memory controller that controls access to a flash memory in response to a command from a host system,
Zone management means for managing a correspondence relationship between a physical zone that collects a plurality of physical blocks that are erase units in the flash memory and a logical zone that collects a plurality of sectors that are access units in the host system;
Address management means for managing the correspondence between the logical address in the logical zone and the physical address in the physical zone between the logical zone and the physical zone in a correspondence relationship;
Empty block search means for detecting empty blocks by sequentially scanning the usage status of physical blocks in the physical zone;
With
The empty block search means starts scanning the usage status from the physical block next to the empty block detected in the previous scan when information on the empty block detected in the previous scan is held. If the information about the free block detected in the previous scan is not retained, the usage status scan starts from the physical block next to the physical block in which the old data corresponding to the new data to be written to the detected free block is stored. Is configured to start,
It is characterized by that.

In order to solve the above problems, a memory controller according to a second aspect of the present invention provides:
A memory controller that controls access to a flash memory in response to a command from a host system,
Zone management means for managing a correspondence relationship between a physical zone that collects a plurality of physical blocks that are erase units in the flash memory and a logical zone that collects a plurality of sectors that are access units in the host system;
Address management means for managing the correspondence between the logical address in the logical zone and the physical address in the physical zone between the logical zone and the physical zone in a correspondence relationship;
Empty block search means for detecting empty blocks by sequentially scanning the usage status of physical blocks in the physical zone;
With
The empty block search means is configured to start a scan of usage status from a physical block next to a physical block in which old data that is associated with new data to be written to the detected empty block is stored.
It is characterized by that.

The free block search means creates a free block search table composed of a plurality of bits of storage area indicating the usage status of the physical block in which the logical value of each bit is in a correspondence relationship after startup, and the free block search Scan the physical block usage status using a table,
You may do it.

In order to solve the above problem, a flash memory system according to a third aspect of the present invention provides:
The above memory controller;
Flash memory,
It is comprised from these.

  According to the present invention, in the memory controller configured to detect the empty blocks by sequentially scanning the usage status of the physical blocks in the physical zone, information on the empty blocks detected in the previous search is stored. If not, the search for the empty block is started from the physical block next to the physical block in which the old data corresponding to the rewrite data to be written to the empty block is stored. Therefore, the empty block search is biased to a specific physical block. Memory controller and flash memory system can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a controller 3 that controls the flash memory 2.

  The flash memory system 1 is connected to the host system 4 via the external bus 13. The host system 4 includes a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the flash memory system 1, and the like. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various types of information such as characters, sounds, and image information.

  The flash memory 2 is a non-volatile memory and includes a register and a memory cell array. The flash memory 2 writes or reads data by copying data between a register and a memory cell.

  The memory cell array includes a plurality of memory cell groups and word lines. Each memory cell group includes a plurality of memory cells connected in series. The word line is for selecting a specific memory cell in the memory cell group. Data is copied between the selected memory cell and the register via the word line, that is, data is copied from the register to the selected memory cell, or data is copied from the selected memory cell to the register. .

  A memory cell constituting the memory cell array is constituted by a MOS transistor having two gates. Here, the upper gate and the lower gate are referred to as a control gate and a floating gate, respectively. By injecting charges (electrons) into the floating gate or discharging charges (electrons) from the floating gate, data can be obtained. Is written or data is erased.

  Since the floating gate is surrounded by an insulator, the injected electrons are held for a long period of time. Note that, when electrons are injected into the floating gate, a high voltage at which the control gate is on the high potential side is applied between the control gate and the floating gate. Further, when electrons are discharged from the floating gate, a high voltage at which the control gate becomes a low potential side is applied between the control gate and the floating gate.

  Here, a state where electrons are injected into the floating gate is a write state, which corresponds to a logical value “0”. The state in which electrons are discharged from the floating gate is an erased state, which corresponds to a logical value “1”.

  Such an address space of the flash memory 2 is shown in FIG. The address space of the flash memory 2 is composed of “pages” and “blocks (physical blocks)”.

  A page is a processing unit in a data read operation and a data write operation performed in the flash memory 2. The physical block is a processing unit in the data erasing operation performed in the flash memory 2, and is composed of a plurality of pages.

  In the flash memory 2 shown in FIG. 2, one page is composed of a user area 25 of 1 sector (512 bytes) and a redundant area 26 of 16 bytes, and one physical block is composed of 32 pages. Yes. There is a flash memory in which one page is composed of a 4-sector user area and a 64-byte redundant area, and one physical block is composed of 64 pages. The user area 25 is an area for storing user data supplied from the host system 4.

  The redundant area 26 is an area for storing additional data such as ECC (Error Correcting Code), logical address information, and block status (flag).

  The ECC is data for detecting and correcting an error included in the data stored in the user area 25.

  The logical address information is information for specifying a logical block corresponding to the data when valid data is stored in the user area 25 of at least one page included in each physical block of the flash memory 2. It is.

  For a physical block in which valid data is not stored in the user area 25, logical address information is not stored in the redundant area 26 of the block.

  Therefore, by determining whether or not logical address information is stored in the redundant area 26, it is possible to determine whether or not valid data is stored in the physical block including the redundant area 26. . That is, when logical address information is not stored in the redundant area 26, it is determined that valid data is not stored in the physical block.

  As described above, one physical block includes a plurality of pages. Data cannot be overwritten on these pages. For this reason, even when only the data stored in one page is rewritten, the data stored in all the pages in the physical block including the page must be rewritten.

  That is, in normal data rewriting, data stored in all pages of a physical block including a page to be rewritten is written to another erased physical block. At this time, as for the data stored in the page where the data is not changed, the previously stored data is rewritten as it is.

  In rewriting data as described above, normally, the rewritten data is written in a physical block different from the physical block stored previously. For this reason, the correspondence relationship between the logical block address and the physical block address dynamically changes every time data is rewritten in the flash memory 2.

  Therefore, it is necessary to manage the correspondence between the logical block and the physical block, and this correspondence is usually managed by the address conversion table. This address conversion table is configured for each pair of logical zones and physical zones corresponding to each other, and shows the correspondence between the logical blocks included in the logical zone and the physical blocks included in the physical zone. The address conversion table is created based on logical address information (LZIBN or LBN) stored in the redundant area 26 of each physical block.

  The block status (flag) is a flag indicating whether the block is good or bad. A block in which data cannot be normally written is determined as a defective block, and a block status (flag) indicating a defective block is written in the redundant area 26.

  Such a flash memory 2 receives data, address information, internal commands, and the like from the controller 3 and performs various processes such as a data read process, a write process, a block erase process, and a transfer process.

  Here, the internal command is a command for the controller 3 to instruct the flash memory 2 to execute processing, and the flash memory 2 operates in accordance with the internal command given from the controller 3. In contrast, the external command is a command for the host system 4 to instruct the flash memory system 1 to execute processing.

  As shown in FIG. 1, the controller 3 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC block 11, and a ROM (Read Only Memory) 12. And. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Each functional block will be described below.

The microprocessor 6 controls the overall operation of the controller 3 in accordance with a program stored in the ROM 12. For example, the microprocessor 6 reads a command set defining various processes from the ROM 12, supplies the command set to the flash memory interface block 10, and causes the flash memory interface block 10 to execute processes.
The microprocessor 6 includes, for example, a shift register and a flag register, and the flag register sets a carry flag when a carry is generated by the operation of the shift register.

  The host interface block 7 exchanges data, address information, status information, external commands, and the like with the host system 4. Data or the like supplied from the host system 4 to the flash memory system 1 is taken into the flash memory system 1 (for example, the buffer 9) using the host interface block 7 as an entrance. Data supplied from the flash memory system 1 to the host system 4 is supplied to the host system 4 through the host interface block 7 as an exit.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is composed of a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 temporarily stores data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive the data, and data to be written to the flash memory 2 is stored until the flash memory 2 becomes writable. It is held in the buffer 9.

  The flash memory interface block 10 exchanges data, address information, status information, internal commands, and the like with the flash memory 2 via the internal bus 14. More specifically, the flash memory interface block 10 includes an address processing unit, a command register, an instruction processing block, and the like.

  The flash memory interface block 10 supplies the flash memory 2 with internal commands, address information, and the like output from the instruction processing block, thereby causing the flash memory 2 to execute reading and writing.

  The ECC block 11 generates an ECC added to data to be written to the flash memory 2 and detects and corrects an error included in the read data based on the ECC added to the read data.

  The ROM 12 is a non-volatile storage element that stores a program that defines a processing procedure performed by the microprocessor 6. Specifically, the ROM 12 stores a program that defines a processing procedure such as creation of an address conversion table, for example.

An example of the above-described address conversion table is shown in FIG. This address conversion table 100 shows the correspondence between the logical blocks included in the logical zone and the physical blocks included in the physical zone.
The block number LZIBN in the logical zone and the block number PZIBN in the physical zone are used. Here, the intra-physical zone block number PZIBN is a serial number in each physical zone assigned to a physical block included in each physical zone.

  The address translation table 100 may be created at the time of startup, or may be created for a logical zone when the address translation table 100 is accessed for an uncreated logical zone. The address conversion table 100 is created in the work area 8.

  Further, in the flash memory system 1 of the present embodiment, the logical zone is composed of 1000 logical blocks and the physical zone is composed of 1024 physical blocks, so the address conversion table 100 shown in FIG. 4 shows the correspondence between the logical blocks of LZIBN # 0 to # 999 and the physical blocks of PZIBN # 0 to # 1023. For example, the data corresponding to the logical block of LZIBN # 0 is the physical block of PZIBN # 35, the data corresponding to the logical block of LZIBN # 1 is the physical block of PZIBN # 10, and the data corresponds to the logical block of LZIBN # 2. Is stored in the physical block of PZIBN # 15. Data corresponding to the logical block of LZIBN # 13 is not stored.

  Further, in the flash memory system 1 of the present embodiment, an empty block search table 200 as shown in FIG. 4 is created together with the address conversion table 100. This free block search table 200 is used when searching for a free block as a data write destination. That is, when new data is written by data rewriting or the like, data is written in the empty block detected using this empty block search table 200.

  This free block search table 200 is a table showing the usage status of physical blocks included in the physical zone, and is created on the work area 8 for each physical zone. Each of the 1024 physical blocks included in the physical zone is assigned to one bit on the empty block search table 200, and the physical value corresponding to the bit is determined by the logical value (“0” or “1”) of each bit. Indicates whether the block is an empty block. In the free block search table 200 shown in FIG. 4, the case where a physical block is used or a bad block is indicated by a logical value “0”, and the physical block is a free block (writable). Is represented by a logical value “1”. In the empty block search table 200, the upper bit string (row) is changed to the lower bit string (row), and the 8 bits of each bit string (each row) are assigned in the order of PZIBN from the lower side (right side) to the upper side (left side). Each physical block is allocated.

  Next, a process for creating the address conversion table 100 and the empty block search table 200 will be described.

  In this creation process, the microprocessor 6 secures an area for creating the address conversion table 100 and an area for creating the free block search table 200 in the work area 8. Regarding the area for creating the address conversion table 100, an area for writing PZIBN corresponding to each of LZIBN # 0 to # 999 is secured. As an area for creating the free block search table 200, an area of 128 bytes (1024 bits) corresponding to the physical blocks of PZIBN # 0 to # 1023 is secured. Further, all bits in the area for creating this empty block search table 200 are initialized to a logical value “0”. When the empty block search table 200 is created, a pointer area for setting information indicating a bit to start scanning is secured when searching for an empty block using the empty block search table 200. The area is initialized to a clear state (a state in which information indicating a bit for starting scanning is not set).

  Subsequently, the microprocessor 6 sequentially reads the logical address information (LZIBN) and the block status written in the redundant areas 26 of the physical blocks PZIBN # 0 to # 1023, and the logical address information (LZIBN) is written. If there is, the PZIBN of the physical block in which the LZIBN has been written is written in a location corresponding to the LZIBN in the area for creating the address conversion table 100. On the other hand, when the logical address information (LZIBN) is not written, it is determined whether or not the physical block is a bad block based on the block status. As a result, when it is determined that the block is not a bad block, the logical value of the bit corresponding to PZIBN of the physical block in the area for creating the empty block search table 200 is changed to “1”.

  Here, the process of creating the empty block search table 200 will be described in detail with reference to the flowchart shown in FIG. In this flowchart, processing for creating other tables (such as the address conversion table 100) is omitted.

  First, the microprocessor 6 creates an area for setting PZIBN #n (#n is # 0 to # 1023) of the physical block being referred to in the creation process of the empty block search table 200 (hereinafter, this area is referred to as the physical reference). Block setting area) is secured in the work area 8, and "0" is set (n = 0) in this reference physical block setting area (step S1).

  Subsequently, the microprocessor 6 refers to the area in which the logical address information of the redundant area 26 of the PZIBN physical block (PZIBN # n physical block) set in the reference physical block setting area is written, and stores the logical address in that area. It is determined whether or not address information is stored (step S2). When the logical address information is stored, it is determined that the physical block is used, and the process proceeds to step S4 (step S2; Yes). If the logical address information is not stored, it is determined that the physical block is not used, and the process proceeds to step S3 (step S2; No).

  When the logical address information is not stored in the redundant area 26 of the physical block (step S2; No), the microprocessor 6 refers to the block status stored in the redundant area 26 of the physical block, and It is determined whether or not the physical block is a bad block (step S3). If it is determined that the physical block is a defective block, the process proceeds to step S4 (step S3; Yes), and if it is determined that the physical block is not a defective block, the process proceeds to step S5 (step S3; No).

  When logical address information is stored in the redundant area 26 of the physical block (step S2; Yes) or when the block status indicates a bad block (step S3; Yes), the microprocessor 6 “0” is set to the bit corresponding to the physical block (physical block being referred to) in the search table 200 (step S4). Here, the corresponding bit is the quotient (the upper 7 bits of n) when n (10-bit value) set in the reference physical block setting area is divided by 8 which is the number of bits included in the bit string. It corresponds to the value) and the remainder (corresponding to the value of the lower 3 bits of n). For example, when the quotient is l and the remainder is m, the bit of the (m + 1) th bit from the lower order of the l + 1th bit string from the top of the empty block search table 200 becomes the bit corresponding to the physical block being referred to.

  When the logical address information is not stored in the redundant area 26 of the physical block (step S2; No) and the block status does not indicate that it is a bad block (step S3; No), that is, the physical block (reference) When it is determined that the (internal physical block) is an empty block, the microprocessor 6 sets “1” in the bit corresponding to the physical block (the physical block being referred to) in the empty block search table 200 ( Step S5).

  The process proceeds to step S6 after the process of step S4 or step S5, but if the area for creating the empty block search table 200 is initially set to the logical value “0”, the process of step S4 is performed. Without proceeding to step S6.

  Since the setting of the bit corresponding to the physical block being referred to is completed when the processing of step S4 or step S5 is completed, the microprocessor 6 increases the value of n set in the reference physical block setting area by one. (Step S6), the process proceeds to Step S7.

  The microprocessor 6 determines whether or not the value of n set in the reference physical block setting area, that is, the value of n increased by 1 in step S6 exceeds the number of physical blocks included in the physical zone. To do. That is, it is determined whether or not the value of n exceeds 1023 (step S7). When the value of n is 1023 or less, the process proceeds to step S2 (step S7; Yes), and when the value of n exceeds 1023, the creation process of the empty block search table 200 ends (step S7; No).

  Next, the empty block search process using the empty block search table 200 will be described with reference to the flowcharts of FIGS.

  When starting the free block search, the pointer area provided in the work area 8 is referred to, and the microprocessor 6 reads the bit next to the bit on the free block search table 200 corresponding to the value set in the pointer area. From this point, scanning of the usage status (information indicated by logical values “0” or “1”) is started. Here, if the empty block search is performed for the second time or later, the PZIBN value of the empty block detected in the previous empty block search is set in the pointer area, but in the case of the first empty block search, No value is set in the pointer area. Therefore, in the flash memory system according to the present invention, in such a case, from the bit corresponding to the physical block next to the physical block in which the old data having a correspondence relationship with the new data to be written to the detected empty block is stored. It is configured to start scanning. In other words, scanning is started from the bit corresponding to the physical block next to the physical block in which the old data to be rewritten with new data is stored, and new data which is data after rewriting is written in the detected empty block.

  For example, a specific description will be given of a case where a write process to a logical block of LZIBN # 5 included in LZN # 3 is given from the host system 4 and the free block search table 200 of PZN # 3 is created in response to this access request To do. In this case, the PZIBN of the physical block corresponding to the logical block of LZIBN # 5 is obtained with reference to the address conversion table 100. When the logical block of LZIBN # 5 corresponds to the physical block of PZIBN # 11, scanning is started from the bit corresponding to the physical block of PZIBN # 12.

  The scan for detecting the bit corresponding to the empty block on the empty block search table 200 can be performed by using, for example, an 8-bit shift register (not shown). In the scan using this shift register, the bit string is referred to in order from the bit string including the next bit of the bit corresponding to the value set in the pointer area, and the value is 0 (binary notation; 000 0000) Otherwise, the value of the bit string is written into the shift register. If the bit for starting scanning is not the least significant bit of the bit string, mask processing is performed so that all the bits on the lower side of the bit for starting scanning become “0”. For example, when the bit to start scanning is the fifth bit from the lower order of the bit string, a mask process is performed so that the bits from the fourth bit to the first bit from the lower order of the bit string become “0”. . In other words, in this mask processing, an AND operation is executed with mask data in which the lower bits from the bit to start scanning are “0” and the other bits are “1”.

  Subsequently, the bit string set in the shift register is shifted in the lower direction, and it is determined how many bits from the lower order correspond to the empty block by the number of shifts. That is, by the above processing, it is determined which bit sequence the bit corresponding to the empty block is and what bit is the lower bit of the bit sequence. After determining the bit corresponding to the empty block in this way, the PZIBN of the physical block assigned to this bit is obtained. Here, when the number of bits included in the bit string is k and the bit from the lower bit of the a-th bit string is a bit corresponding to an empty block, the PZIBN of the physical block corresponding to that bit is k × ( a-1) + (b-1). Further, the value of PZIBN obtained in this way is set in the pointer area.

  First, the microprocessor 6 refers to the pointer area (step S102), and the PZIBN value of the empty block detected in the previous empty block search (hereinafter, the PZIBN value set in the pointer area is referred to as pb). Is set (step S102; Yes), and if the value of PZIBN is not set, the process proceeds to step S108 (No). Here, the pointer area is provided with a bit (flag bit) for indicating whether or not pb is set, and it is determined whether or not pb is set based on the information of the flag bit. The Therefore, when the value of PZIBN is first written in the pointer area, the information indicated by this flag bit is changed to information indicating that pb is set.

  If pb is set in the pointer area (step S102; Yes), the microprocessor 6 sets a start pointer area (hereinafter, a value set in the start pointer area) for setting the PZIBN of the physical block from which scanning is started. j)), the value of pb + 1 is written (step S103). In the start pointer area, only the lower 10 bits of pb + 1 are set. Therefore, when pb is 1023 (binary notation; 11 1111 1111), j is 0 (binary notation; 00 0000 0000).

  When pb is not set in the pointer area (step S102; No), the LZIBN value set in the access target instruction area is referred to (step S108), and there is a PZIBN corresponding to the LZIBN value. Proceeds to step S112 (step S108; Yes), and if there is no PZIBN corresponding to this LZIBN, proceeds to step S109 (step S108; No).

  If there is a PZIBN corresponding to the LZIBN set in the access target instruction area (step S108; Yes), a value obtained by adding 1 to the PZIBN is written in the start pointer area (step S112). That is, a value obtained by adding 1 to PZIBN corresponding to LZIBN set in the access target instruction area is set as the value of j. Similarly to the above, when the value of PZIBN corresponding to LZIBN set in the access target instruction area is 1023 (binary notation; 11 1111 1111), j is 0 (binary notation; 00 0000 0000). .

  If there is no PZIBN corresponding to LZIBN set in the access target instruction area (step S108; No), 0 is written in the start pointer area (step S109). That is, 0 is set as the value of j.

  To simplify the explanation, when there is no PZIBN corresponding to the LZIBN set in the access target instruction area, 0 is set in the start pointer area, but the PZIBN is set in the access target instruction area. The LZIBN may be subtracted one by one, and when there is a PZIBN corresponding to the subtracted LZIBN, the PZIBN may be set as the access target instruction area. For example, if there is no PZIBN corresponding to LZIBN subtracted once, there is no PZIBN corresponding to LZIBN subtracted twice, and there is PZIBN corresponding to LZIBN subtracted three times, PZIBN corresponding to LZIBN subtracted three times A value obtained by adding 1 to is set in the start pointer area. In addition, LZIBN is sequentially subtracted by 1 in this way, and if the corresponding PZIBN is not found even when LZIBN becomes 0, 0 is set in the start pointer area.

  In step S103, step S109, or step S112, the PZIBN value of the physical block for starting the empty block search is set in the start pointer area, and then the process proceeds to step S115 to specify the bit string to be searched and the number of bits masked by the bit string. Set the information.

  Since each bit string is 8 bits in the free block search table 200 shown in FIG. 4, the value of the upper 7 bits of j (10-bit value) is written to the bit string designating area for designating the bit string, and j (10-bit value) ) Is written in the mask information area for designating the number of bits to be masked (step S115). In the following description, it is assumed that a value set in the bit string designation area is p and a value written in the mask information area is q. Here, the quotient obtained by dividing the value j set in the start pointer area by the number of bits included in each bit string corresponds to the value of the upper 7 bits of j (10-bit value), and the remainder is j ( Corresponds to the value of the lower 3 bits of the 10-bit value). Further, the (q + 1) -th bit from the lower order of the (p + 1) -th bit string corresponds to a bit for starting scanning.

  Subsequently, the lower q bits of the (p + 1) th bit string are masked. If the bit string data subjected to the mask process is 0 (binary notation; 0000 0000), the process proceeds to step S121 (step S120; Yes). ) If the bit string data subjected to the mask processing is not 0 (binary notation; 0000 0000), the process proceeds to step S124 (No in step S120). Note that when q = 0, mask processing is not performed, so it is determined whether or not the data of the bit string is 0 as it is.

  When the bit string data subjected to the mask processing or the bit string data as it is is 0 (step S120; Yes), 1 is added to the value set in the bit string designation area, and the mask information area is set. Is changed to 0, and the process proceeds to step S120 (step S121). Here, since the value p set in the bit string designation area is a 7-bit value, when the value set in the bit string designation area is 127 (binary notation; 111 1111), the lower 7 bits of the added value are Corresponding 0 (binary notation; 000 0000) is written in the bit string designation area. When the process proceeds to step S120 after step S121, since q = 0, the mask process is not performed and the data of the (p + 1) th bit string (p is a value newly set in the bit string designation area) is 0. It is determined whether or not there is.

  If the bit string data subjected to the mask processing or the bit string data as it is is not 0 (step S120; No), the bit string data is written to the shift register, and the process proceeds to step S125 (step S124).

  The bit string data written in the shift register is shifted in the lower (right) direction until the carry flag is set, and the number of shifts until the carry flag is set is counted (step S125).

  Subsequently, a 10-bit value obtained by adding a value k (3 bits) obtained by subtracting 1 from the number of shifts until the carry flag is set to the lower side of the value p (7 bits) set in the bit string specifying area is a pointer. Write in the area (step S128). The 10-bit value written in the pointer area corresponds to the detected empty block PZIBN.

  Next, processing performed when data is written to the flash memory 2 will be described with reference to the flowchart of FIG. Note that the process of writing data to the flash memory 2 itself is the same as the conventional process, and therefore the process of changing the contents of the empty block search table 200 will be described in particular.

  The microprocessor 6 searches for a free block, acquires the PZIBN of the free block (step S201), and obtains the PBA of this free block based on the acquired PZIBN.

  Subsequently, the microprocessor 6 supplies the flash memory interface block 10 with address information including the PBA of the empty block detected in step S201, a command set read from the ROM 12, and the like. The flash memory interface block 10 executes a process of writing data to the empty block detected in step S201 according to the given address information and command set (step S202).

  When data is written in the empty block, the microprocessor 6 rewrites the bit of the empty block search table 200 corresponding to PZIBN of this empty block to “0” (step S203), and ends the process.

  Next, processing performed when data is erased from the flash memory 2 will be described with reference to the flowchart of FIG. Since the process itself for erasing data from the flash memory 2 is the same as the conventional process, the process for changing the contents of the empty block search table 200 will be described in particular.

  The erasing process is performed, for example, when rewritten data is written in an empty block and old data becomes unnecessary. In such a case, after the rewrite data is written in the empty block, the physical block in which the old data is stored is erased, and then the PZIBN in the rewrite-related portion of the address translation table is stored in the old data. The PZIBN of the physical block that has been changed is changed to PZIBN of the physical block in which the new data after rewriting is stored.

  When erasing data of a physical block in which old data is stored, first, the PBIZN of the physical block in which the old data is stored is obtained using the address conversion table, and further, the old data is obtained based on the acquired PBIZN. The PBA of the physical block storing the data is obtained (step S301).

  Subsequently, the microprocessor 6 supplies the PBA of the physical block in which the old data is stored, the command set read from the ROM 12 and the like to the flash memory interface block 10. The flash memory interface block 10 erases the stored data of the physical block in which the old data is stored in accordance with the given PBA and command set (step S302).

  After the erasure process in step S302 is completed, the process status is read from the flash memory 2, and the physical block in which the old data is stored based on the process status (status including information indicating whether the process has been completed normally) It is determined whether or not the block is a bad block (step S303).

  When it is determined that the physical block in which the old data is stored is not a bad block (step S303; No), the bit on the empty block search table 200 corresponding to this physical block is rewritten to “1” (step S304).

  If it is determined that the physical block in which the old data is stored is a bad block (step S303; Yes), the process is terminated without updating the free block search table 200. Note that a block status indicating a defective block is written in the redundant area 26 of the physical block in which the old data was stored.

  As described above, the controller 3 according to the present invention, when the information about the empty block detected in the previous search is not held, the old data (new data in the new data) corresponding to the new data to be written in the empty block. The search for an empty block is started from the physical block next to the physical block storing the data to be rewritten. Therefore, it is possible to avoid that the physical block for starting the empty block search is biased to a specific physical block when the information regarding the empty block detected in the previous search is not held.

  In the above embodiment, the new data to be written into the empty block only when the information about the empty block detected in the previous search is not held, that is, only in the case of the first empty block search after starting. The search for the empty block is started from the physical block next to the physical block in which the old data (data to be rewritten with the new data) is stored, but the physical in which the old data is stored each time The search for an empty block may be started from the physical block next to the block.

  The present invention is not limited to the above-described embodiment, and various modifications and applications are possible.

  The number of physical blocks in each physical zone is not limited to 1024 and can be set freely. Similarly, the number of logical blocks in each logical zone is not limited to 1000 and can be set freely.

  In the present embodiment, each bit string of the empty block search table 200 is 8 bits, but is not limited to 8 bits and may be set freely. Note that the bit length of the shift register must be appropriately set according to the number of bits of the bit string.

  Instead of creating the free block search table 200, the free block search may be performed by directly referring to the logical address information and block status stored in the redundant area 26.

1 is a block diagram illustrating an example of a flash memory system. It is a figure which shows an example of the structure of the address space of flash memory. It is a figure which shows the structure of an address conversion table. It is a figure which shows the structure of an empty block search table. It is a flowchart of the process which creates an empty block search table. It is a flowchart of the process which searches an empty block. It is a flowchart of the process which searches an empty block. It is a flowchart of the process which searches an empty block. It is a flowchart of the process which writes data in flash memory. 4 is a flowchart of processing for erasing data from a flash memory. It is a figure which shows schematically the structure of the address space of the conventional flash memory.

Explanation of symbols

1 Flash memory system 2 Flash memory 3 Controller 4 Host system 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 ROM
25 User area 26 Redundant area

Claims (4)

A memory controller that controls access to a flash memory in response to a command from a host system,
Zone management means for managing a correspondence relationship between a physical zone that collects a plurality of physical blocks that are erase units in the flash memory and a logical zone that collects a plurality of sectors that are access units in the host system;
Address management means for managing the correspondence between the logical address in the logical zone and the physical address in the physical zone between the logical zone and the physical zone in a correspondence relationship;
Empty block search means for detecting empty blocks by sequentially scanning the usage status of physical blocks in the physical zone;
With
The empty block search means starts scanning the usage status from the physical block next to the empty block detected in the previous scan when information on the empty block detected in the previous scan is held. If the information about the free block detected in the previous scan is not retained, the usage status scan starts from the physical block next to the physical block in which the old data corresponding to the new data to be written to the detected free block is stored. Is configured to start,
A memory controller characterized by that. A memory controller that controls access to a flash memory in response to a command from a host system,
Zone management means for managing a correspondence relationship between a physical zone that collects a plurality of physical blocks that are erase units in the flash memory and a logical zone that collects a plurality of sectors that are access units in the host system;
Address management means for managing the correspondence between the logical address in the logical zone and the physical address in the physical zone between the logical zone and the physical zone in a correspondence relationship;
Empty block search means for detecting empty blocks by sequentially scanning the usage status of physical blocks in the physical zone;
With
The empty block search means is configured to start a scan of usage status from a physical block next to a physical block in which old data that is associated with new data to be written to the detected empty block is stored.
A memory controller characterized by that. The free block search means creates a free block search table composed of a plurality of bits of storage area indicating the usage status of the physical block in which the logical value of each bit is in a correspondence relationship after startup, and the free block search Scan the physical block usage status using a table,
The memory controller according to claim 1, wherein the memory controller is a memory controller. The memory controller according to any one of claims 1 to 3,
Flash memory,
A flash memory system comprising:

Images