JP2007203565A - Electrooptic device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress unevenness in gradation of each electrooptic element while controlling the scale of the peripheral circuit. <P>SOLUTION: Surface of a substrate 12 on which a plurality of unit circuits U are arranged is sectioned into a first region R1, a second region R2, and an element region R0 between them. Correction data A of each unit circuit U is supplied to signal line La, and gradation data D of each unit circuit U is supplied to signal line Ld. A first selecting circuit 21 is arranged in the first region R1 and selects the unit circuits U sequentially, and a second selecting circuit 22 is arranged in the second region R2 and selects the unit circuits U sequentially. Each selecting circuit Ui is arranged in the element region R0 and includes an electrooptic element E exhibiting gradation dependent on a drive current Idr, and supplies the electrooptic element E with a drive current Idr dependent on correction data Ai acquired from the signal line La upon selection by the first selecting circuit 21, and gradation data Di acquired from the signal line Lb upon selection by the second selecting circuit 22. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to an organic light emitting diode (hereinafter referred to as “OLED (Organic Light Emitting Diode)”.
The present invention relates to a technique for controlling an electro-optical element such as an element.

Conventionally, an electro-optical device having a configuration in which a plurality of unit circuits including an electro-optical element and a circuit for controlling the electro-optical element are arranged has been proposed. In this type of electro-optical device, gradations of a plurality of electro-optical elements are caused by variations in characteristics of each electro-optical element (for example, light emission efficiency) and characteristics of transistors constituting each unit circuit (for example, threshold voltage). (Brightness) unevenness may occur. In order to suppress such unevenness of gradation (brightness), for example, in Patent Document 1, gradation data (data for designating gradation) of each electro-optic element is corrected based on correction data, and each A configuration for driving an electro-optic element is disclosed.
JP 2005-283816 A

However, in the configuration of Patent Document 1, an arithmetic circuit for correcting gradation data based on correction data is indispensable.
There is a problem that the scale of the “peripheral circuit” is enlarged. In view of such circumstances, an object of the present invention is to solve the problem of suppressing gradation unevenness of each electro-optical element while suppressing the scale of peripheral circuits.

In order to solve the above problems, an electro-optical device according to the present invention includes a first region (for example, the first region R1) and a second region (for example, the second region R2) and an element region (for example, an element region) between the two regions. R
0), a plurality of unit circuits, a first signal line (for example, signal line La) to which correction data for each unit circuit is sequentially supplied, and gradation data for each unit circuit are sequentially supplied. A second signal line (for example, signal line Ld), a first selection unit (for example, the first selection circuit 21) which is arranged in the first region and sequentially selects each of the plurality of unit circuits, and is arranged in the second region. The second selection means for sequentially selecting each of the plurality of unit circuits (for example, the second selection circuit in FIG. 2 or the selection signal SEL1 in FIG. 10).
Each of the plurality of unit circuits is arranged in the element region and has a gradation corresponding to the drive current, and the first selection unit selects the unit circuit. When the correction data acquired from the first signal line and the second selection means select the unit circuit (that is, the second selection means causes the selection of the unit circuit by the first selection means) Control means (for example, the data acquisition circuit 30 and the correction circuit 50) for supplying a drive current corresponding to the gradation data acquired from the second signal line to the electro-optical element (in response to selection of the unit circuit)
A drive transistor Tdr).

In this configuration, since the control means for controlling the drive current supplied to the electro-optic element according to the gradation data and the correction data is installed in each unit circuit, the gradation data is corrected based on the correction data. Peripheral circuits are not necessary in principle. Accordingly, the scale of the peripheral circuit of the electro-optical device can be reduced.

Although the peripheral circuit for correcting the gradation data based on the correction data is not necessary in principle, the control means of each unit circuit adjusts the reference current based on the correction data (ie, the drive current) Is not intended to exclude from the scope of the present invention an electro-optical device having a configuration in which the peripheral circuit corrects gradation data. In an electro-optical device in which a plurality of types of correction is performed, according to the configuration in which at least one correction is performed by the control unit of each unit circuit, it is not necessary to perform the correction in the peripheral circuit. Compared with the conventional configuration in which the above correction is performed in the peripheral circuit, the expected effect of the present invention that the scale of the peripheral circuit can be reduced is certainly exhibited. For example, the variation of the characteristics of each electro-optical element can be suppressed by the correction by the control means of each unit circuit, and the peripheral circuit can execute gamma correction on the gradation data.

Further, in a configuration in which both the first selection unit and the second selection unit are formed only in one region across the arrangement of the electro-optical elements, each electro-optical element is unevenly distributed in the vicinity of one peripheral edge of the substrate. There are various problems caused by this. On the other hand, in the present invention, the element region in which each electro-optic element is arranged is defined by the gap between the first region and the second region, and the first selection means for sequentially selecting each unit circuit is the first region. And the second unit circuit sequentially selects each unit circuit.
The selection means is arranged in the second area. According to this configuration, since the scales of the elements in the respective regions located on both sides of the electro-optic element (the area where each element is arranged) are equalized, it is possible to solve the problem caused by the uneven distribution of the electro-optic element. (FIG. 6).

The electro-optical element in the present invention is an element (so-called current-driven electro-optical element) in which optical characteristics such as luminance and transmittance are changed by supplying current. A typical example of the electro-optical device according to the present invention is a light-emitting device that employs, as an electro-optical element, a light-emitting element (for example, an OLED element) that emits light with luminance corresponding to the current value of the drive current. The present invention is also applied to the adopted electro-optical device.

The “plurality of unit circuits” in the present invention may be all unit circuits included in the electro-optical device or a part of unit circuits. For example, the dummy circuit is excluded even in a configuration in which a dummy circuit (a unit circuit that is exclusively used for inspection and testing and is not actually driven) is included in all the unit circuits included in the electro-optical device. If the requirements of the present invention are satisfied for “a plurality of unit circuits”, the electro-optical device is naturally included in the scope of the present invention, without needing to discuss the feasibility of the requirements for other unit circuits (dummy circuits). It is. In addition, for example, in an electro-optical device including a plurality of electro-optical elements having different display colors (for example, red, green, and blue), for example, correction may be performed only for electro-optical elements having a specific display color. Good.
In this configuration, if the requirements of the present invention are satisfied for the “plurality of unit circuits” corresponding to the electro-optical elements of a specific display color, the unit circuits corresponding to other display colors satisfy the requirements of the present invention. Regardless of whether the electro-optical device is included in the scope of the present invention.

The control means in the present invention includes drive means for generating a drive current. A typical example of the driving means is a transistor (for example, the driving transistor Tdr in FIG. 2) interposed on the path of the driving current. However, the form of the drive means is arbitrary. For example, in an electro-optical device in which correction means for generating a reference current according to correction data (for example, the correction circuit 50 in FIG. 2) is arranged, the electro-optic is on a path branched from the path from the correction circuit to the electro-optical element. A transistor arranged in parallel with the element may be used as the driving means. In this configuration, the ratio of the drive current flowing through the electro-optic element to the current flowing through the transistor in the reference current is changed by controlling the conduction state (resistance between the source and drain) of the transistor according to the gradation data. Therefore, the electro-optic element can be driven to a gradation corresponding to the gradation data.

In a specific aspect of the present invention, the control unit of each unit circuit includes a data acquisition unit (for example, the data acquisition circuit 30) that acquires gradation data from the second signal line when the second selection unit selects the unit circuit. ) And the drive current is controlled according to the correction data and the gradation data acquired by the data acquisition means. In a more preferred aspect, the data acquisition means is arranged in the second area.
According to this aspect, even when the elements arranged in the first area (for example, the first selection means and the means for acquiring correction data) have a relatively large scale, the elements of the first area and the second area It is possible to make the scale (area) closer to each other. Note that the timing of selection by the second selection means and the timing of acquisition of gradation data are arbitrary. That is, any configuration may be used as long as gradation data is acquired in response to selection by the second selection unit.

In a more preferred aspect, the control unit of each unit circuit includes a correction unit that generates a reference current according to correction data acquired from the first signal line when the first selection unit selects the unit circuit.
For example, a correction circuit 50) is included, and the drive current is controlled according to the gradation data and the reference current generated by the correction means. The correction means in this aspect is arranged in either the first area or the second area (for example, FIG. 2 or FIG. 12). In particular, in the configuration in which the correction unit is arranged in the first region, it is not necessary to form a wiring from the first selection unit to the correction unit in the element region. Therefore,
There is an advantage that the degree of freedom of design of the electro-optic element is improved (typically, the area of the electro-optic element is increased). The relationship between the timing of selection by the first selection means and the timing of acquisition of correction data is arbitrary. That is, any configuration may be used as long as the correction data is acquired in response to selection by the first selection unit.

In another aspect, the correction means includes a plurality of current generation units (for example, current generation units C1 to C3) each generating a current corresponding to the correction data, and the reference current is obtained by adding the currents generated by the current generation units. Is generated. More specifically, each of the plurality of current generation units includes a holding unit (for example, storage elements Ma1 to Ma3) that holds bits corresponding to the current generation unit in the correction data.
And a current source (for example, current source transistors TR1 to TR3) that generates a current corresponding to the bit held by the holding means. In the above aspect, if all of the large number of current generating units constituting the correcting unit are arranged in the first area, the circuit arranged in the first area is larger than the second area. There is a possibility. Therefore, in a more preferable aspect, some of the current generators are arranged in the first region, and some of the other current generators are arranged in the second region. Focusing on the first current generator (for example, current generator C2 in FIG. 9) and the second current generator (for example, current generator C1 in FIG. 9) among the plurality of current generators, the first current The generation unit is disposed in the first region, and the second current generation unit is disposed in the second region. According to this aspect, it is possible to precisely equalize the circuit scale between the first region and the second region. In addition,
Examples of the holding means include SRAM (Static Random Access Memory) and DRAM (Dynam).
Various memory elements such as ic Random Access Memory) are adopted.

The light emitting device according to the present invention is used in various electronic devices. A typical example of this electronic apparatus is an image forming apparatus using the light emitting device of the present invention as an exposure device (exposure head). This image forming apparatus includes an image carrier (for example, the photosensitive drum 110 in FIG. 1) on which a latent image is formed on an image forming surface by exposure, the electro-optical device of the present invention that exposes the image forming surface, and a latent image. And a developing device (for example, the developing device 114 in FIG. 13 or the developing device 163 in FIG. 14) that forms a visible image by adhesion of a developer (for example, toner). However, the use of the electro-optical device according to the present invention is not limited to exposure. For example, the electro-optical device of the present invention can be used as a display device for various electronic devices. Examples of this type of electronic device include a personal computer and a mobile phone.
In addition, the present invention can be applied to various illumination devices such as a device (backlight) that is disposed on the back side of the liquid crystal device and illuminates the device, and a device that is mounted on an image reading device such as a scanner and irradiates light on a document. An optical device can be employed.

<A: First Embodiment>
FIG. 1 is a perspective view showing a partial configuration of an image forming apparatus using the electro-optical device according to the first embodiment of the present invention as an optical head (exposure device). As shown in the figure, the image forming apparatus includes an electro-optical device 10, a condensing lens array 15, and a photosensitive drum 110. The electro-optical device 10 includes a number of electro-optical elements (not shown in FIG. 1) arranged linearly on the surface of the substrate 12. These electro-optical elements emit light selectively according to the form of an image to be printed on a recording material such as paper. The photosensitive drum 110 is supported by a rotating shaft extending in the main scanning direction, and rotates in the sub-scanning direction (the direction in which the recording material is conveyed) with the outer peripheral surface facing the electro-optical device 10.

The condensing lens array 15 is disposed in the gap between the electro-optical device 10 and the photosensitive drum 110. The condensing lens array 15 includes a large number of gradient index lenses arranged in an array with each optical axis directed to the electro-optical device 10. Such a condensing lens array 15
For example, SLA (Selfoc Lens Array) available from Nippon Sheet Glass Co., Ltd. (Selfoc / SELFOC is a registered trademark of Nippon Sheet Glass Co., Ltd.).

Light emitted from each electro-optical element of the electro-optical device 10 passes through each refractive index distribution type lens of the condensing lens array 15 and then reaches the surface of the photosensitive drum 110. By this exposure, a latent image (electrostatic latent image) corresponding to a desired image is formed on the surface of the photosensitive drum 110. In the present embodiment, it is assumed that a latent image in which pixels are arranged in a matrix form in a horizontal (main scanning direction) n columns × vertical (sub scanning direction) m rows is formed (each of n and m is 2). More natural numbers).

FIG. 2 is a block diagram illustrating an electrical configuration of the electro-optical device 10, and FIG. 3 is a timing chart illustrating waveforms of signals used for driving the electro-optical device 10. As shown in FIG. 2, the electro-optical device 10 includes a first selection circuit 21 and a second selection circuit 22, and n unit circuits U (U 1 to Un) each including an electro-optical element E. The structure is arranged on the surface. The unit circuits U1 to Un are arranged along the X direction (main scanning direction). The electro-optical device 10 includes a clock signal (for example, a clock signal CLKa and a clock signal CLKb) and various data (for example, correction data) from a control device (for example, a CPU or a controller. A1 to An and gradation data D1 to Dn) are supplied.

The substrate 12 is a plate-like member made of an insulating material such as glass or plastic. Board 1
One surface 2 is divided into an element region R0, a first region R1, and a second region R2. The element region R0 is a band-like region extending in the X direction in the vicinity of the center in the Y direction (sub-scanning direction) on the surface of the substrate 12. The electro-optical elements E of the unit circuits U1 to Un are formed in the element region R0 and arranged in the X direction. The first region R1 is Y on the surface of the substrate 12 when viewed from the element region R0.
This is a band-like region extending in the X direction on the positive side of the direction. The second region R2 is a band-like region extending in the X direction on the negative side in the Y direction as viewed from the element region R0 on the surface of the substrate 12. Therefore, the element region R0 is located in the gap between the first region R1 and the second region R2. Here, a region including the electro-optical element E and the drive transistor Tdr is defined as an element region R0 for convenience, but the “element region” of the present invention is specified as a region where the electro-optical element is disposed, and the drive transistor It does not matter whether an active element such as Tdr is included in the element region.

As shown in FIG. 2, the first selection circuit 21 is arranged in the first region R1, and the second selection circuit 22 is arranged in the second region R2. Each of the first selection circuit 21 and the second selection circuit 22 is mounted on the substrate 12 in the form of an IC chip, for example. However, a structure (unit circuit) in which the first selection circuit 21 and the second selection circuit 22 are configured by elements (for example, active elements such as thin film transistors) formed on the surface of the substrate 12 together with the elements constituting the unit circuits U1 to Un. U1-Un and the first
The structure in which the selection circuit 21 and the second selection circuit 22 are integrally formed on the surface of the substrate 12)
Is also adopted.

As shown in FIG. 3, the period during which the electro-optical device 10 operates is divided into a first period Pa and a second period Pb. The second period Pb is a period during which the luminance of each electro-optical element E is actually controlled according to the image to be formed on the recording material (for example, paper). In other words, the second period Pb is a period in which an image corresponding to the light emission of each electro-optical element E within that period is actually formed on the recording material and output. On the other hand, the first period Pa is a period in which the gradation control of each electro-optical element E is stopped. For example, a period for initializing the state of each part of the electro-optical device 10 immediately after the power is turned on, or a period during which the gradation of each electro-optical element E is not reflected in an image output to the outside (for example, a plurality of recording materials The first interval Pa corresponds to the interval (interval between sheets) when an image is formed on the first interval Pa.

The first selection circuit 21 in FIG. 2 is means (for example, an n-bit shift register) for sequentially selecting the n unit circuits U1 to Un in the order of arrangement in the first period Pa, and is shown in FIG. As described above, the selection signals SA1 to SAn are output by sequentially shifting a predetermined pulse signal (not shown) in synchronization with the clock signal CLKa. Therefore, the selection signals SA1 to SAn are sequentially shifted to the high level every cycle T1 of the clock signal CLKa. The second selection circuit 22 includes a first
Similar to the selection circuit 21, it is means for sequentially selecting each of the n unit circuits U1 to Un, and as shown in FIG. 3, a selection signal SB1 that sequentially becomes high at every cycle T2 of the clock signal CLKb. ~ SBn is generated and output. The transition of the selection signal SAi (i is an integer satisfying 1 ≦ i ≦ n) or the selection signal SBi to the high level means selection of the unit circuit Ui.

As shown in FIG. 3, the cycle T1 of the clock signal CLKa is longer than the cycle T2 of the clock signal CLKb (that is, the operating frequency of the first selection circuit 21 is lower than the operating frequency of the second selection circuit 22). Therefore, the period (T1) with which the first selection circuit 21 selects each unit circuit U is:
It is longer than the period (T2) at which the second selection circuit 22 selects each unit circuit U.

As shown in FIG. 2, each of the unit circuits U1 to Un includes an electro-optic element E and a data acquisition circuit 30.
And a correction circuit 50 and a drive transistor Tdr. Electro-optic element E and drive transistor T
dr is arranged in the element region R0. The correction circuit 50, together with the first selection circuit 21, is a first region R1.
Placed inside. The data acquisition circuit 30 is disposed in the second region R2 together with the second selection circuit 22.

The electro-optical element E is a current-driven light-emitting element having a gradation (luminance) corresponding to the current value of the drive current Idr supplied thereto. The electro-optical element E of the present embodiment is an OLED element in which a light emitting layer of an organic EL (ElectroLuminescent) material is interposed in a gap between an anode and a cathode facing each other. The cathode of the electro-optic element E is grounded (Gnd).

The data acquisition circuit 30 in each of the unit circuits U1 to Un is connected in common to the signal line Ld. The signal line Ld is connected to the array of the data acquisition circuits 30 and the second selection circuit 2 in the second region R2.
2 is a wiring extending in the X direction with a gap to 2. The gradation data D (D1 to Dn) of each unit circuit U is serially supplied to the signal line Ld in the second period Pb. The gradation data Di is data specifying the gradation of the electro-optic element E in the unit circuit Ui. The gradation data Di of the present embodiment is for turning on (high gradation) and turning off (low gradation) the electro-optic element E with respect to the unit circuit Ui.
1-bit digital data for designating any one of the above. As shown in FIG. 3, the second period Pb
In the period during which the selection signal SBi maintains a high level, the gradation data Di is applied to the signal line Ld.
Is supplied. The data acquisition circuit 30 of the unit circuit Ui is means for acquiring the gradation data Di from the signal line Ld triggered by selection by the second selection circuit 22. The data acquisition circuit 30 of this embodiment is a 1-bit latch circuit, samples and outputs the gradation data Di from the signal line Ld at the timing when the selection signal SBi transitions to a high level, and the selection signal SBi is high next time. The output is maintained until the level transitions. Note that latch circuits arranged in two stages may be employed as the data acquisition circuit 30. In this configuration, the gradation data D is latched dot-sequentially by the first-stage latch circuit, and the gradation data D1 to Dn are latched all at once (line-sequentially) by the second-stage latch circuit. Is done.

The correction circuit 50 of the unit circuit Ui shown in FIG. 2 has a reference current Is serving as a reference for the drive current Idr.
[i] is a means for generating (the detailed configuration will be described later). Drive transistor Td
r is means for generating a drive current Idr having a current value corresponding to the reference current Is [i] output from the correction circuit 50 and the gradation data Di output from the data acquisition circuit 30 (ie, the reference current Is [i]). Means for driving the electro-optical element E based on the gradation data Di. The drive transistor Tdr of the present embodiment is a p-channel thin film transistor interposed between the correction circuit 50 and the anode of the electro-optic element E, and a potential corresponding to the gradation data Di is supplied to the gate. Is controlled to either the on state (low resistance state) or the off state (high resistance state). When the drive transistor Tdr is controlled to be in the on state, the electro-optical element E is lit by supplying the reference current Is [i] as the drive current Idr. In contrast, when the drive transistor Tdr is turned off and the path of the reference current Is is interrupted, the current value of the drive current Idr becomes zero and the electro-optical element E is turned off.

By the way, an error due to the manufacturing technique may occur in the characteristics of the electro-optical element E in each unit circuit U. As described above, if the drive current Idr having the same current value is supplied to all the electro-optical elements E to which the same gradation is specified, although the respective characteristics (for example, light emission efficiency) are different, The actual luminance (gradation) of the electro-optic element E varies. In order to suppress the brightness variation as described above, in the present embodiment, the correction circuit 5 of each unit circuit Ui.
The reference current Is [i] generated by 0 is set to a current value corresponding to the correction data Ai generated for the unit circuit Ui.

The correction data Ai corresponding to one unit circuit Ui is 3-bit digital data composed of the most significant bit a1 [i], the next bit a2 [i], and the least significant bit a3 [i]. It is generated in advance for each electro-optical element E according to the result of measuring the luminance of each electro-optical element E in advance or the operation of the electro-optical device 10 by the user. For example, after supplying the drive current Idr having the same current value to each, the actual luminance of all the electro-optic elements E is measured, and all the results are based on the measurement results (the luminance variation at the time of non-correction). Correction data A (A1 to An) is determined so that the luminance of the electro-optical element E is equalized.

The correction data A1 to An are sequentially input to the signal line La in the first period Pa. The signal line La is
As shown in FIG. 2, the wiring extends in the X direction in the gap between the array of the correction circuits 50 and the first selection circuit 21 in the first region R1. Each bit of the correction data A is supplied to the signal line La in synchronization with the clock signal CLKa. The cycle T1 of the clock signal CLKa is the clock signal CLKb
Therefore, the transmission frequency of each bit of the correction data A is lower than the transmission frequency of the gradation data D. As shown in FIG. 3, in the period P1 of the first period Pa, the correction data A
The most significant bits a1 [1] to a1 [n] in each of 1 to An are sequentially supplied to the signal line La in this order. Similarly, the next bits a2 [1] to a2 [n] in each of the correction data A1 to An are supplied to the signal line La in the period P2, and the least significant bits a3 [1] to a3 in the period P3. [
n] is supplied to the signal line La.

Next, FIG. 4 is a block diagram showing a specific configuration of the correction circuit 50. In FIG. 4, only the correction circuit 50 in the i-th unit circuit Ui is shown, but all the correction circuits 50 have the same configuration. As shown in FIGS. 2 and 4, one correction circuit 50 includes three current generators C1 to C3 corresponding to the number of bits of the correction data A. The current generation unit Ck (k is an integer satisfying 1 ≦ k ≦ 3) of the unit circuit Ui is means for generating a current Ik according to the bit ak [i] of the correction data Ai, and includes a storage element Mak and a NAND gate Gk. And a current source transistor TRk.

As shown in FIGS. 2 and 4, the unit circuits U1 to Un have three memory selection lines Ls1 to Ls3.
Is wired. The memory selection line Lsk includes a storage element Mak in each of the unit circuits U1 to Un.
A memory selection signal MSk for selecting (current generator Ck) is supplied. Unit circuit U1〜
The first input terminal of the NAND gate G1 in each of Un is commonly connected to the memory selection line Ls1. Similarly, the first input terminal of each NAND gate G2 is connected to the memory selection line Ls2, and each N gate
A first input terminal of the AND gate G3 is connected to the memory selection line Ls3. A selection signal S is sent from the first selection circuit 21 to the second input terminals of the NAND gates G1 to G3 in the unit circuit Ui.
Ai is supplied in common. Therefore, the output of the NAND gate Gk of each unit circuit Ui is at a low level only when both the memory selection signal MSk and the selection signal SAi are at a high level, and is maintained at a high level in other cases.

The memory element Mak is means for holding the bit ak [i] of the correction data Ai. Specifically, a 1-bit SRAM can be adopted as the storage element Mak. All unit circuits U1 to Un
The memory elements Ma1 to Ma3 are commonly connected to the signal line La. The memory element Mak receives each bit ak [i] of the correction data Ai as a signal line at the timing when the output of the NAND gate Gk transitions to the low level (the timing when both the memory selection signal MSk and the selection signal SAi become high level). Capture from La and store.

The memory selection signals MS1 to MS3 are sequentially shifted to a high level in the first period Pa (second
The low level is maintained during the period Pb). That is, as shown in FIG. 3, the memory selection signal MS1 is set to the high level during the period P1 during which the most significant bits a1 [1] to a1 [n] of the correction data A1 to An are transmitted to the signal line La. Become. Similarly, the memory selection signal MS2 becomes high level during the period P2 when the next bits a2 [1] to a2 [n] are transmitted to the signal line La, and the memory selection signal MS3 becomes high level during the period P3. Become. Therefore, when the selection signal SAi transits to a high level during the period Pk in which the storage element Mak is selected by the memory selection signal MSk, the bit ak [i] of the correction data Ai is taken into the storage element Mak of the unit circuit Ui. Held in. When the above operation is executed in each of the periods P1 to P3, all the unit circuits U1 to Un have 3
Bit correction data A1 to An are held. In the present embodiment, the period T1 for inputting the correction data A to the correction circuit 50 is the period T2 for inputting the gradation data D to the data acquisition circuit 30.
Therefore, the correction data A can be accurately written in the storage elements Ma1 to Ma3.

The current source transistors TR1 to TR3 are p-channel transistors whose sources are connected to the power supply line (power supply potential Vdd) and whose drains are connected to the source of the drive transistor Tdr. A potential corresponding to the bit ak [i] held in the memory element Mak is supplied to the gate of the current source transistor TRk. Bit ak [i] held in the memory element Mak
Is “1”, the current source transistor TRk is turned on. At this time, a current Ik flows through the current source transistor TRk. On the other hand, when the bit ak [i] of the memory element Mak is “0”, the current source transistor TRk transitions to the off state and the current Ik is cut off.

As described above, each of the three current source transistors TR1 to TR3 is selectively turned on according to the correction data Ai. One or more current source transistors T that are turned on
The reference current Is [i] is generated by adding the current Ik flowing through Rk. The size (channel length and channel width) and characteristics of the current source transistors TR1 to TR3 in the present embodiment are such that the relative ratio of the current values of the currents I1 to I3 that flow when each of the current source transistors TR1 to TR3 is turned on is “I1: I2: I3 = 4:
2: 1 ". Therefore, the reference current Is [i] is set at any one of the seven levels according to the correction data Ai. As described above, the current source transistors TR1 to TR3 function as means for generating a plurality of currents I1 to I3 each weighted by a separate weight value.

Here, the configuration in which the characteristics of the current source transistors TR1 to TR3 are made different is illustrated, but each of the currents I1 to I3 can also be obtained by arranging a number of transistors having the same characteristics in parallel according to the weight value. Can be a current value corresponding to a desired weight value. For example, instead of the current source transistor TR2 of FIG. 4, two transistors having the same characteristics as the current source transistor TR3 are arranged in parallel, and instead of the current source transistor TR1, four transistors having the same characteristics as the current source transistor TR3 are arranged. The currents I1 to I are also affected by the configuration in which transistors are arranged in parallel.
The relative ratio of 3 can be set to “I1: I2: I3 = 4: 2: 1”.

According to the above configuration, the current value of the drive current Idr that determines the gradation of the electro-optical element E of the unit circuit Ui depends on the reference current Is [i] corresponding to the correction data Ai and the gradation data Di. Be controlled. Therefore, even if the characteristics of the electro-optical elements E and the characteristics of the elements (particularly the drive transistors Tdr) constituting the unit circuits U1 to Un vary, by appropriately selecting the correction data A1 to An Variation in gradation of each electro-optic element E can be suppressed. A correction circuit 50 that generates a reference current Is [i] corresponding to the correction data Ai is installed in each unit circuit U. Therefore, a peripheral circuit (correction data Ai) that corrects the gradation data Di based on the correction data Ai. And the circuit for calculating the gradation data Di) are not necessary in principle. Therefore, according to this embodiment, the scale of the peripheral circuit of the electro-optical device 10 can be reduced.

Note that the same operation as described above is also realized by the configuration illustrated in FIG. 5 (hereinafter referred to as “comparative”). In the configuration of FIG. 5, the surface of the substrate 12 is divided into an element region R0 and a circuit region Rc located on the negative side in the Y direction. In the element region R0, the electro-optic element E and the drive transistor Tdr in each of the unit circuits U1 to Un are arranged. In the circuit region Rc, the first selection circuit 21 and the second selection circuit 22, the signal line La and the signal line Ld, the data acquisition circuit 30 of the unit circuits U1 to Un, and the correction circuit 50 are arranged. Therefore, each electro-optic element E
Is unevenly distributed in the vicinity of the peripheral edge on the positive side in the Y direction of the substrate 12.

Now, as shown in FIG. 6, it is assumed that a sealing body 14 is formed on the surface of the substrate 12 for sealing each electro-optical element E and isolating it from the outside air and moisture. In order to realize effective sealing of each electro-optical element E, as shown in part (a) and part (b) of FIG. 6, not only the area overlapping each electro-optical element E but also each electro-optical element E A region extending from the peripheral edge e1 to a predetermined dimension M (
It is also necessary to form the sealing body 14 (hereinafter referred to as “sealing maintenance region”). If the dimension M (distance from the peripheral edge e1 of the electro-optic element E to the peripheral edge e2 of the sealing body 14) is insufficient, the sealing body 14 is easily peeled off from the substrate 12, and the sealing body 14 and This is because moisture or outside air that has entered from the gap with the substrate 12 may deteriorate the electro-optic element E.

Since the sealing body 14 is formed so as to satisfy the above conditions, the electro-optical element E is sandwiched between the substrates 12 in the comparative configuration of FIG. 5 as shown in part (a) of FIG. The area opposite to the circuit area Rc (the area on the left side of the electro-optical element E in FIG. 6) needs to be secured only for setting the sealing maintenance area of the sealing body 14. Therefore, there is a problem that the reduction of the width dimension W along the Y direction of the substrate 12 (and consequently the miniaturization of the electro-optical device 10) is hindered.

On the other hand, in this embodiment, as shown in part (b) of FIGS. 2 and 6, the element region R0 in which each electro-optic element E is arranged is in the gap between the first region R1 and the second region R2. After being defined, the first selection circuit 21, the signal line La, and each correction circuit 50 are disposed in the first region R1, and the second selection circuit 22, the signal line Ld, and each data acquisition circuit 30 are second. Arranged in region R2. According to this configuration, the electro-optic element E in the element region R0 and the elements in the first region R1 (the first selection circuit 21).
-Sealing is maintained by forming the sealing body 14 so as to cover the signal line La, the correction circuit 50) and the elements of the second region R2 (second selection circuit 22, signal line Ld, data acquisition circuit 30). Since the size M of the region is sufficiently secured, the width W of the substrate 12 can be reduced and the electro-optical device 10 can be easily downsized as compared with the comparative example illustrated in part (a) of FIG. There is an advantage of being.

In the comparative configuration, the data acquisition circuit 30 and the correction circuit 50 are arranged on the opposite side (negative side in the Y direction) from the electro-optical element E and the drive transistor Tdr with the first selection circuit 21 interposed therebetween. Therefore, as shown in FIG. 5, the potential corresponding to the gradation data Di is applied to the data acquisition circuit 3.
It is necessary to form the wiring F1 supplied from 0 to the gate of the driving transistor Tdr and the wiring F2 supplying the reference current Is [i] from the correction circuit 50 to the driving transistor Tdr so as to overlap the first selection circuit 21. Therefore, in the comparative configuration, there may be a problem that the configuration of the electro-optical device 10 becomes complicated, and a problem that the wiring F1 and the wiring F2 are electrically short-circuited to the first selection circuit 21 due to a defect in the insulating layer. . On the other hand, in the present embodiment, as shown in FIG. 2, since the electro-optic element E is arranged on the data acquisition circuit 30 and the correction circuit 50 side as viewed from the first selection circuit 21, the wiring F1 and the wiring F2 are arranged. In principle, the lamination with the first selection circuit 21 is unnecessary. Therefore, the problem caused by this lamination can be solved.

As described above, according to the present embodiment, both sides of the electro-optical element E are compared with the comparative configuration in which elements related to driving of the electro-optical element E are arranged only on one side of the electro-optical element E. (First
Since the scales of the elements arranged in the region R1 and the second region R2 (the area where each element is arranged) are equalized, various problems resulting from the configuration in which the electro-optical elements E are unevenly distributed on the periphery of the substrate 12 Can be eliminated.

<B: Second Embodiment>
Next, a second embodiment of the present invention will be described.
In the first embodiment, the correction data A1 to An are digital data, and the electro-optical device 1
The configuration supplied to 0 is illustrated. On the other hand, in the present embodiment, the correction data A1 to
An is supplied to the signal line La as an analog voltage signal. The elements constituting the electro-optical device 10 according to this embodiment and the arrangement (layout) of each are the same as those in the first embodiment except for the correction circuit 50. In each of the following embodiments, elements having the same functions and operations as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

FIG. 7 is a circuit diagram showing a configuration of the correction circuit 50 in one unit circuit Ui. As shown in FIG. 7, the correction circuit 50 of the present embodiment includes a current source transistor TR, a storage element Mb, and a switching element SW, and is arranged in the first region R1 as in the first embodiment. The current source transistor TR is interposed between the power supply line (power supply potential Vdd) and the drive transistor Tdr.
It is a channel type transistor. The storage element Mb is a capacitive element interposed between the gate and source (power supply line) of the current source transistor TR and functions as a means for holding the potential of the gate of the current source transistor TR. Current source transistor TR to drive transistor Tdr
The current value of the reference current Is [i] supplied to is controlled according to the potential held in the memory element Mb.

The switching element SW is means for controlling the electrical connection (conduction / non-conduction) between the gate of the current source transistor TR and the signal line La in accordance with the selection signal SAi supplied from the first selection circuit 21. When the selection signal SAi transitions to a high level, the switching element SW changes to an on state, whereby the gate of the current source transistor TR is electrically connected to the signal line La. On the other hand, when the selection signal SAi is kept at the low level, the switching element SW is changed to the OFF state, and thereby the gate of the current source transistor TR is electrically insulated from the signal line La.

Next, FIG. 8 is a timing chart for explaining the operation of the present embodiment. As shown in the figure, the first selection circuit 21 selects each of the unit circuits U1 to Un in this order by sequentially transitioning the selection signals SA1 to SAn to the high level as in the first embodiment. . However, in the present embodiment, a predetermined interval P0 is inserted between a period during which the selection signal SAi transitions to a high level and a period during which the selection signal SAi + 1 at the next stage transitions to a high level.

The correction signal S supplied to the signal line La is an analog voltage signal that changes to a voltage value corresponding to the correction data Ai for each period in which each of the selection signals SA1 to SAn is at a high level. More specifically, the correction signal S maintains a voltage value corresponding to the correction data Ai during a period (time length T1) when the selection signal SAi is at a high level. The voltage value of the correction signal S is selected so that the current source transistor TR operates in the saturation region when it is applied to the gate of the current source transistor TR.

As shown in FIG. 8, when the selection signal SAi transits to a high level in the first period Pa, the switching element SW of the unit circuit Ui is turned on. Accordingly, in the unit circuit Ui, the voltage of the signal line La (that is, the correction data Ai) at that time is taken into the correction circuit 50 and applied to the gate of the current source transistor TR. Since the voltage of the signal line La at this time is held in the storage element Mb, the gate of the current source transistor TR is corrected even after the selection signal SAi changes to the low level and the switching element SW changes to the OFF state. A voltage corresponding to the data Ai is continuously applied. Since the current source transistor TR operates in the saturation region, the drive transistor Tdr has a current value corresponding to the voltage of the gate of the current source transistor TR (that is, a current value corresponding to the correction data Ai) as in the first embodiment. ) Reference current Is [i]
Is supplied.

By the way, the voltage held in the memory element Mb gradually decreases due to charge leakage or the like. In this embodiment, in order to maintain the reference current Is [i] used in the unit circuit Ui at a current value corresponding to the correction data Ai, refresh is performed by reapplying a voltage corresponding to the correction data Ai to the storage element Mb. Operations are performed at any time. As shown in FIG.
It is executed at any time in the second period Pb in parallel with the fetching of the gradation data Di by each data acquisition circuit 30. That is, in the second period Pb, each of the selection signals SA1 to SAn sequentially transitions to a high level with a predetermined interval P0, while the voltage of the correction signal S (correction data) when the selection signal SAi transitions to a high level. Ai) is taken into the correction circuit 50 from the signal line La and held in the storage element Mb.

The correction signal S gradually changes from the voltage value Vi corresponding to the correction data Ai and converges to the voltage value Vi + 1 corresponding to the correction data Ai + 1. Therefore, for example, in the configuration in which the interval P0 is not interposed between the period in which the selection signal SAi maintains the high level and the period in which the selection signal SAi + 1 in the next stage maintains the high level, the selection signal SAi + 1 is Even at the timing of transition to the high level, the correction signal S may not yet reach the voltage value Vi + 1. In this case, a voltage in the middle of the change from the voltage Vi to the voltage Vi + 1 (that is, a voltage different from the original voltage Vi + 1) is applied to the gate of the current source transistor TR of the unit circuit Ui + 1. Because
There is a problem that an error (so-called crosstalk) occurs in the current value of the reference current Is [i].
In contrast, in the present embodiment, each of the selection signals SA1 to SAn transitions to a high level with an interval P0. According to this configuration, the gate of the current source transistor TR can be connected to the signal line La after the correction signal S is reliably changed from the voltage Vi to the voltage Vi + 1 within the interval P0. An error in the current value of the reference current Is [i] due to the voltage fluctuation can be effectively eliminated.

<C: Third Embodiment>
FIG. 9 is a block diagram illustrating the configuration of the electro-optical device 10 according to the third embodiment of the invention. As shown in the figure, in the present embodiment, the three current generators C1 to C3 constituting the correction circuit 50 are distributed and arranged in the first region R1 and the second region R2. More specifically, the current generators C2 and C3 are arranged in the first region R1 as in the first embodiment, whereas the current generator C1 is viewed from the data acquisition circuit 30 in the second region R2. It is arranged in a region on the element region R0 side. By adding each of the current generating units C1 to C3 and the currents I1 to I3, the reference current Is [
The configuration in which i] is generated is the same as in the first embodiment.

The data acquisition circuit 30 is a circuit that simply holds 1-bit gradation data D, whereas the correction circuit 50 is a circuit that includes a number of current generation units Ck corresponding to the number of bits of the correction data A. Therefore, in the configuration in which the entire correction circuit 50 is arranged in the first region R1 as in the first embodiment, an imbalance may occur in which the elements of the first region R1 become larger than the second region R2. On the other hand, in the present embodiment, since the correction circuit 50 is partially disposed also in the second region R2, there is an advantage that such an imbalance can be suppressed. Since one correction circuit 50 includes the number of current generation units Ck corresponding to the number of bits of the correction data A, the number of bits of the correction data A increases as the scale imbalance between the first region R1 and the second region R2 increases. It becomes more noticeable. Therefore, in the present embodiment, the number of bits of the correction data Ai is increased in order to refine the step size of the current value of the reference current Is [i] (to improve the correction accuracy of the drive current Idr). Particularly preferred.

Although FIG. 9 illustrates the configuration in which only one current generator C1 among the three current generators C1 to C3 is arranged in the second region R2, each of the first region R1 and the second region R2 is illustrated. The number of the current generation units Ck arranged in is arbitrary. However, as can be understood from the above description, the number of current generators Ck arranged in each region is corrected data A so that the circuit scale is equalized in the first region R1 and the second region R2. It is desirable to select according to the number of bits.

<D: Fourth Embodiment>
Next, a fourth embodiment of the present invention will be described.
In the first embodiment, the unit circuit U to which the gradation data D is supplied is the second selection circuit 22.
However, the method and configuration for selecting each unit circuit U are arbitrary. In the present embodiment, the second selection circuit 22 is not installed on the substrate 12, and the unit circuits U are sequentially selected by a signal supplied from the host device. Note that the configuration of the present embodiment is applied to any of the forms exemplified above.

FIG. 10 is a block diagram illustrating a configuration of the electro-optical device 10 according to the present embodiment.
These are timing charts for explaining operations related to acquisition of gradation data D. FIG. FIG.
As shown in 0, the n unit circuits U1 to Un are divided into M (M = n / 3) blocks B1 to BM in units of three. In the second region R2 of the substrate 12, M signal lines Ld1 to LdM each corresponding to a separate block are formed. A signal line Ldj corresponding to one block Bj (j is an integer satisfying 1 ≦ j ≦ M) is commonly connected to the data acquisition circuit 30 in each of the three unit circuits U belonging to the block Bj.

In addition, the first unit circuit U (U1, U4,..., Un-) belonging to each of the blocks B1 to BM.
In 2), the selection signal SEL1 is supplied from the host device. Similarly, the selection signal SEL2 is supplied to the second unit circuits U (U2, U5,..., Un-1) of the blocks B1 to BM, and the third unit circuits U (U3, U6,...) Are supplied. .., Un) are supplied with a selection signal SEL3. As shown in FIG. 11, the selection signals SEL1 to SEL3 sequentially become high level in the period T2 in the second period Pb. On the other hand, as shown in FIG. 11, the gradation data D corresponding to the three unit circuits U of the block Bj is sequentially supplied to the signal line Ldj in the second period Pb.

When the selection signal SEL1 transitions to a high level, the gradation data D (D1, D4,..., Dn) is supplied to the first unit circuit U (U1, U4,..., Un-2) in each of the blocks B1 to BM. -2) is captured. Similarly, when the selection signal SEL2 transitions to a high level, the second unit circuits U (U
2, U5,..., Un-1) is incorporated with gradation data D (D2, D5,..., Dn-1), and when the selection signal SEL3 transits to a high level, the third unit circuit U ( The gradation data D (D3, D6,..., Dn) is taken into U3, U6,. As described above, the selection signals SEL1 to SEL3 in this embodiment and the wiring for transmitting each function as means for sequentially selecting the unit circuits U.

Also in this embodiment, the same operation and effect as the first embodiment are exhibited. Further, in the present embodiment, data is taken in parallel to one unit circuit U belonging to each of the blocks B1 to BM, so that it is necessary to supply the gradation data D to all the unit circuits U. There is an advantage that the time length to be shorter than the first embodiment and the third embodiment.

<E: Modification>
Various modifications can be made to each of the above embodiments. An example of a specific modification is as follows. In addition, you may combine each following aspect suitably.

(1) Modification 1
The relationship between each element constituting the electro-optical device 10 and each region defined on the substrate 12 is not limited to the above examples. For example, as shown in FIG. 12, a configuration in which each correction circuit 50 is disposed in the second region R2 (more specifically, the gap between the data acquisition circuit 30 and the element region R0) is also employed.
Each data acquisition circuit 30 may be arranged in the first region R1 (for example, the gap between the correction circuit 50 and the element region R0).

(2) Modification 2
Of course, the number of bits of the correction data A is not limited to the above example. Therefore, the number of current generation units Ck (NAND gate Gk, storage element Mak, number of current source transistors TRk) included in one unit circuit U is appropriately changed from the above examples.

In the above description, a configuration in which the gradation of the electro-optic element E is binary-controlled by the 1-bit gradation data D is illustrated, but the gradation data D may be 2 bits or more. In this configuration, the drive current Idr flowing through the drive transistor Tdr is controlled stepwise according to the gradation data D, whereby the gradation of the electro-optic element E is multivalued (any one of three or more gradations). To)
Be controlled. Further, instead of the signal line La and the signal line Ld, there are a plurality of signal lines to which signals of each system obtained by phase-expanding (serial-parallel conversion) a signal (for example, an image signal) output serially from the host device is supplied. Arranged configurations are also employed.

(3) Modification 3
In each of the above embodiments, the configuration in which the OLED element is employed as the electro-optical element E is exemplified, but the present invention is also applied to various electro-optical devices using other electro-optical elements.
For example, a light emitting device using an inorganic EL element, a field emission display (FED: Field Emi)
ssion display (SED), surface-conduction electron emission display (SED)
ectron-emitter display), ballistic electron emission display (BSD)
Surface emitting display) and light emitting devices using light emitting diodes can be applied to the present invention in the same manner as the above embodiments.

<F: Electronic equipment>
Next, with reference to FIG. 13, an image forming apparatus which is one aspect of the electronic apparatus according to the invention will be described. This image forming apparatus is a tandem type full-color image forming apparatus using a belt intermediate transfer body system.

In this image forming apparatus, four electro-optical devices 10K, 10C, each having the same configuration.
10M and 10Y are four photosensitive drums (image carriers) 110K having the same configuration.
110C, 110M, and 110Y are disposed at positions facing the image forming surface 110A. The electro-optical devices 10K, 10C, 10M, and 10Y have the same configuration as the electro-optical device 10 according to each of the above embodiments.

As shown in FIG. 13, this image forming apparatus is provided with a driving roller 121 and a driven roller 122, and an endless intermediate transfer belt 120 is wound around these rollers 121 and 122, as indicated by arrows. As shown, the periphery of the rollers 121 and 122 is rotated. Although not shown, tension applying means such as a tension roller that applies tension to the intermediate transfer belt 120 may be provided.

Around the intermediate transfer belt 120, there are four photosensitive drums 1 each having a photosensitive layer on the outer peripheral surface.
10K, 110C, 110M, and 110Y are arranged at predetermined intervals. Subscript "
"K", "C", "M", and "Y" mean that they are used to form black, cyan, magenta, and yellow visible images, respectively. The same applies to other members. The photosensitive drums 110K, 110C, 110M, and 110Y are rotationally driven in synchronization with the driving of the intermediate transfer belt 120.

Around each photosensitive drum 110 (K, C, M, Y), a corona charger 111 (K, C,
M, Y), the electro-optical device 10 (K, C, M, Y), and the developing device 114 (K, C, M, Y)
And are arranged. The corona charger 111 (K, C, M, Y) uniformly charges the image forming surface 110A (outer peripheral surface) of the corresponding photosensitive drum 110 (K, C, M, Y). The electro-optical device 10 (K, C, M, Y) writes an electrostatic latent image on the charged image forming surface 110A of each photosensitive drum. In each electro-optical device 10 (K, C, M, Y), the photosensitive drum 1
A plurality of light emitting elements E are arranged along a 10 (K, C, M, Y) bus (in the main scanning direction). The electrostatic latent image is written by the photosensitive drums 110 (K, C, M, Y) by a plurality of light emitting elements E.
This is performed by irradiating light. The developing device 114 (K, C, M, Y) has a visible image (on the photosensitive drum 110 (K, C, M, Y)) by attaching toner as a developer to the electrostatic latent image.
That is, a visible image) is formed.

Black, cyan, magenta, and black formed by such a four-color monochromatic image forming station
The yellow visible images are sequentially transferred onto the intermediate transfer belt 120 to be superposed on the intermediate transfer belt 120. As a result, a full-color visible image is formed. Inside the intermediate transfer belt 120, four primary transfer corotrons (transfer devices) 112 (K, C,
M, Y) are arranged. The primary transfer corotrons 112 (K, C, M, Y) are respectively arranged in the vicinity of the photosensitive drums 110 (K, C, M, Y), and the photosensitive drums 110 (
By electrostatically attracting the visible image from K, C, M, Y), the visible image is transferred to the intermediate transfer belt 120 passing between the photosensitive drum and the primary transfer corotron.

A sheet 102 as an object (recording material) on which an image is to be finally formed is fed one by one from the sheet feeding cassette 101 by the pickup roller 103 and is subjected to secondary transfer with the intermediate transfer belt 120 in contact with the driving roller 121. Sent to the nip between the rollers 126. The full-color visible image on the intermediate transfer belt 120 is secondarily transferred to one side of the sheet 102 by the secondary transfer roller 126 and fixed on the sheet 102 by passing through a fixing roller pair 127 as a fixing unit. . Thereafter, the sheet 102 is discharged onto a paper discharge cassette formed on the upper part of the apparatus by a paper discharge roller pair 128.

Next, another embodiment of the image forming apparatus according to the present invention will be described with reference to FIG. This image forming apparatus is a rotary developing type full-color image forming apparatus using a belt intermediate transfer body system. As shown in FIG. 14, around the photosensitive drum 110, a corona charger 16 is provided.
8, a rotary developing unit 161, and the electro-optical device 10 according to the above embodiment,
An intermediate transfer belt 169 is provided.

The corona charger 168 uniformly charges the outer peripheral surface of the photosensitive drum 110. The electro-optical device 10 writes an electrostatic latent image on the charged image forming surface 110 </ b> A (outer peripheral surface) of the photosensitive drum 110. In the electro-optical device 10, a plurality of light emitting elements E are arranged along the bus (main scanning direction) of the photosensitive drum 110. The electrostatic latent image is written by irradiating the photosensitive drum 110 with light from the light emitting elements E.

The developing unit 161 includes four developing units 163Y, 163C, 163M, and 163K.
The drums are arranged at an angular interval of ° and can be rotated counterclockwise about the shaft 161a. The developing units 163Y, 163C, 163M, and 163K supply yellow, cyan, magenta, and black toner to the photosensitive drum 110, respectively, and attach the toner as a developer to the electrostatic latent image, thereby causing the photosensitive drum 110 to adhere. A visible image (ie, a visible image) is formed.

The endless intermediate transfer belt 169 is wound around a driving roller 170a, a driven roller 170b, a primary transfer roller 166, and a tension roller, and is rotated around these rollers in a direction indicated by an arrow. The primary transfer roller 166 transfers the visible image to the intermediate transfer belt 169 that passes between the photosensitive drum 110 and the primary transfer roller 166 by electrostatically attracting the visible image from the photosensitive drum 110.

Specifically, in the first rotation of the photosensitive drum 110, an electrostatic latent image for a yellow (Y) image is written by the electro-optical device 10, and a developer image of the same color is formed by the developing unit 163Y.
Further, the image is transferred to the intermediate transfer belt 169. Further, in the next rotation, an electrostatic latent image for a cyan (C) image is written by the electro-optical device 10 and a developer image of the same color is formed by the developing device 163C, and the intermediate image is overlapped with the yellow image. The image is transferred to the transfer belt 169. In this way, during four rotations of the photosensitive drum 110, yellow, cyan, magenta,
The black visible image is sequentially superimposed on the intermediate transfer belt 169, and as a result, a full-color visible image is formed on the transfer belt 169. When images are finally formed on both sides of a sheet as an object on which an image is to be formed, the same color images of the front and back surfaces are transferred to the intermediate transfer belt 169, and then the front and back surfaces are transferred to the intermediate transfer belt 169. A full-color visible image is formed on the intermediate transfer belt 169 in such a manner that the visible image of the next color is transferred.

The image forming apparatus is provided with a sheet conveyance path 174 through which a sheet passes. The sheets are picked up one by one from the paper feed cassette 178 by the pick-up roller 179, advanced through the sheet transport path 174 by the transport roller, and between the intermediate transfer belt 169 and the secondary transfer roller 171 in contact with the drive roller 170a. Pass through the nip. The secondary transfer roller 171 transfers the developed image to one side of the sheet by electrostatically attracting a full-color developed image from the intermediate transfer belt 169 collectively. The secondary transfer roller 171 can be moved closer to and away from the intermediate transfer belt 169 by a clutch (not shown). And
The secondary transfer roller 171 moves the intermediate transfer belt 169 when transferring a full-color visible image onto the sheet.
And is separated from the secondary transfer roller 171 while the visible image is superimposed on the intermediate transfer belt 169.

The sheet on which the image has been transferred as described above is conveyed to the fixing device 172 and is passed between the heating roller 172a and the pressure roller 172b of the fixing device 172, whereby the visible image on the sheet is fixed. The sheet after the fixing process is drawn into the discharge roller pair 176 and proceeds in the direction of arrow F. In the case of double-sided printing, after most of the sheet passes through the paper discharge roller pair 176, the paper discharge roller pair 176 is rotated in the reverse direction.
75. Then, the visible image is transferred to the other surface of the sheet by the secondary transfer roller 171, the fixing process is performed again by the fixing device 172, and then the sheet is discharged by the discharge roller pair 176.

Since the image forming apparatus illustrated in FIGS. 13 and 14 uses a light source (exposure means) employing an OLED element as the light emitting element E, the apparatus is made smaller than when a laser scanning optical system is used. . Note that the electro-optical device of the present invention can also be employed in electrophotographic image forming apparatuses other than those exemplified above. For example, the electro-optical device according to the present invention may be applied to an image forming apparatus that directly transfers a visible image from a photosensitive drum to a sheet without using an intermediate transfer belt, and an image forming apparatus that forms a monochrome image. It is possible to apply the device.

In the above, an electro-optical device used as an exposure head has been exemplified, but the use of the electro-optical device of the present invention is not limited to exposure of a photoreceptor. For example, the electro-optical device of the present invention is employed in an image reading device such as a scanner as a line-type optical head (illumination device) that irradiates a reading target such as a document with light. As this type of image reading apparatus, there is a scanner, a copying machine or a reading part of a facsimile, a barcode reader, or a two-dimensional image code reader for reading a two-dimensional image code such as a QR code (registered trademark). An electro-optical device in which a plurality of light emitting elements are arranged in a planar shape is also used as a backlight unit disposed on the back side of the liquid crystal panel.

The electro-optical device of the present invention is also employed as a display device that displays an image. In this display device, a plurality of light emitting elements E are arranged in a matrix in the row direction and the column direction. Then, the scanning line driving circuit selects each row for each unit period (horizontal scanning period), and the correction data A or the gradation data D is supplied to each light emitting element E in the selected row. Examples of the electronic device in which the electro-optical device of the present invention is used for displaying an image include a portable personal computer, a mobile phone, a personal digital assistant (PDA),
Digital still camera, TV, video camera, car navigation system, pager, electronic notebook, electronic paper, calculator, word processor, workstation, videophone, P
Examples include an OS terminal, a printer, a scanner, a copier, a video player, and a device provided with a touch panel.

1 is a perspective view showing a partial configuration of an image forming apparatus according to a first embodiment. It is a block diagram which shows the structure of an electro-optical apparatus. It is a timing chart for demonstrating operation | movement of 1st Embodiment. It is a circuit diagram which shows the structure of one unit circuit. FIG. 2 is a block diagram illustrating a configuration of an electro-optical device according to a comparative example. It is sectional drawing for demonstrating the effect of embodiment. It is a circuit diagram which shows the structure of the correction circuit which concerns on 2nd Embodiment. It is a timing chart for demonstrating operation | movement of 2nd Embodiment. FIG. 10 is a block diagram illustrating a configuration of an electro-optical device according to a third embodiment. FIG. 10 is a block diagram illustrating a configuration of an electro-optical device according to a fourth embodiment. It is a timing chart for demonstrating operation | movement of 4th Embodiment. FIG. 10 is a block diagram illustrating a configuration of an electro-optical device according to a modification. It is a perspective view which shows the specific example (image forming apparatus) of the electronic device which concerns on this invention. It is a perspective view which shows the specific example (image forming apparatus) of the electronic device which concerns on this invention.

Explanation of symbols

10: electro-optical device, 15: condensing lens array, 110: photosensitive drum, 12 ...
... substrate, R0 ... element region, R1 ... first region, R2 ... second region, 14 ... sealing body, 21
... First selection circuit, 22... Second selection circuit, U (U1 to Un)... Unit circuit, Tdr... Drive transistor, E. Circuit, Ma
1 to Ma3, Mb: Memory element, TR1 to TR3: Current source transistor, La, Ld: Signal line, Ls1 to Ls3: Memory selection line, Is [1] to Is [n]: Reference current, Idr …… Drive current,
A (A1 to An): correction data, D (D1 to Dn): gradation data.

Claims (8)

A substrate including a first region and a second region, and an element region between both regions;
A plurality of unit circuits;
A first signal line to which correction data of each unit circuit is sequentially supplied;
A second signal line to which gradation data of each unit circuit is sequentially supplied;
First selection means arranged in the first region for sequentially selecting each of the plurality of unit circuits;
Second selection means arranged in the second region to sequentially select each of the plurality of unit circuits,
Each of the plurality of unit circuits is
An electro-optic element disposed in the element region and having a gradation corresponding to a driving current;
Correction data acquired from the first signal line when the first selection unit selects the unit circuit and gradation data acquired from the second signal line when the second selection unit selects the unit circuit. Control means for supplying a drive current according to the above to the electro-optic element. The control means of each unit circuit includes data acquisition means for acquiring gradation data from the second signal line when the second selection means selects the unit circuit,
The electro-optical device according to claim 1, wherein the data acquisition unit is disposed in the second region. The control means of each unit circuit includes correction means for generating a reference current according to correction data acquired from the first signal line when the first selection means selects the unit circuit, and includes gradation data and The electro-optical device according to claim 1, wherein the drive current is controlled according to the reference current generated by the correction unit. The electro-optical device according to claim 3, wherein the correction unit is disposed in one of the first region and the second region. The correction means includes a plurality of current generation units each generating a current according to correction data,
A reference current is generated by adding the currents generated by the current generators,
The first current generation unit among the plurality of current generation units is disposed in the first region, and a second current generation unit different from the first current generation unit is disposed in the second region. 4. The electro-optical device according to 3. Each of the plurality of current generators is
Holding means for holding a bit corresponding to the current generator in the correction data;
The electro-optical device according to claim 5, further comprising: a current source that generates a current corresponding to the bit held by the holding unit. The electro-optical device according to claim 1, further comprising: a sealing body that is disposed on the surface of the substrate and covers at least the electro-optical element of each unit circuit. An electronic apparatus comprising the electro-optical device according to claim 1.

Images