JP2007201518A - Manufacturing method for semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for semiconductor wafer capable of preventing loss of chamfers in a planarization process. <P>SOLUTION: Sliced wafers are obtained by cutting a semiconductor ingot. A primary planarization process is performed on the sliced wafers, and irregularities are removed. A chamfering process is performed on the peripheral part of the sliced wafers whose irregularities have been removed. Then, secondary planarization is performed. After that, the front surface of the processed wafer is etched. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a manufacturing method for obtaining a semiconductor wafer by subjecting a sliced wafer obtained by cutting a semiconductor ingot to processing such as polishing and etching, and in particular, its shape is highly flat and has an outer peripheral shape. The present invention relates to a method for manufacturing a semiconductor wafer with high precision.

The most basic method for manufacturing a semiconductor wafer that has been conventionally performed includes the following steps.
(1) The semiconductor ingot is cut to obtain a sliced wafer.
(2) Chamfer the outer periphery of the sliced wafer.
(3) The chamfered wafer is flattened by lapping or the like.
(4) The processing strain layer generated by the flattening process is removed by alkali or acid etching.
(5) At least one surface of the etched wafer is polished to obtain a mirror wafer.

  In flattening, lapping, which is a batch process, was preferred because of its high productivity. However, the demand for high flatness from the device process side becomes more stringent, so that the flatness is limited by lapping. There are cases where it is difficult to satisfy the demand. Furthermore, with the increase in the diameter of semiconductor wafers, it is difficult to wrap a wafer of 12 inches or more to achieve high flatness due to problems such as an increase in size of the apparatus in addition to flatness. Therefore, in increasing the diameter of this semiconductor wafer, various types of surface grinding have attracted attention by placing importance on higher quality than productivity by batch processing. In particular, double-sided simultaneous grinding (hereinafter referred to as “double-sided grinding”), in which both front and back surfaces are ground simultaneously with the upper and lower grinding wheels, has a high leveling performance and is simultaneous processing on both front and back sides. Its productivity is high.

As a prior art using various surface grinding, there is a “semiconductor wafer manufacturing method” disclosed in Japanese Patent Laid-Open No. 9-260314. In this method, the chamfered sliced wafer is flattened by different types of surface grinding including the above-described double-head grinding.
JP 09-270397 A JP 09-103944 A JP 09-260314 A JP 09-246216 A Japanese Patent Laid-Open No. 08-197397 JP 09-272049 A

However, the semiconductor wafer processed by the prior art capable of high planarization has a problem in the shape of the outer peripheral portion shown below.
(1) Single-sided surface grinding The cut sliced wafer 5a has irregularities 52a such as waviness and warpage. One side of the sliced wafer 5a, here, the back surface 51a is vacuum chucked for convenience, and the outer peripheral portion thereof is chamfered. [See Fig. 8 (a)]
By vacuum chucking, the back surface 51b of the wafer 5b is in a state following the vacuum chuck 50, and its shape is temporarily corrected. Therefore, the vacuum chuck 50 is chamfered with the suction surface as a reference surface. [See FIG. 8 (b)]
In the same way, in the chamfering process, one surface that is attracted for convenience is referred to as a “back surface”.

When this chamfered wafer 5b is subjected to surface grinding by, for example, single-sided suction and single-side grinding, the adsorbing equipment is different from the adsorbing equipment in the chamfering, and therefore the reference surface does not coincide with the reference surface in the chamfering. Therefore, the center of the chamfered portion does not coincide with the thickness center plane serving as a reference for surface grinding. For this reason, if both the front and back surfaces are ground by this one-side surface grinding, a part of the chamfered portion is ground, and the chamfered shape of the wafer 5c may be impaired. [Refer to FIG. 8 (c)]
In particular, according to the first grinding technique or the second grinding technique described in the above prior art, the center plane of the chamfered portion may further deviate from the thickness center plane.

(2) Double-head grinding In the same manner as the single-side surface grinding described above, chamfering before grinding is performed with the back surface 61a as a reference surface. [See Fig. 9 (a)]
However, in simultaneous surface grinding of the front and back surfaces of the sliced wafer 6a by double-headed grinding, since the grinding is started in a form sandwiched from the front and back surfaces, the reference surfaces are the reference surfaces 60a and 60b on both the front and back surfaces. These center planes do not coincide with the chamfering center plane 60c of chamfering. [See FIG. 9 (b)]
As a result, a part of the chamfered shape of the wafer 6c is lost. [See FIG. 9 (c)]

  Therefore, when a wafer in which a part of the chamfered shape is lost is processed in a subsequent process, the wafer may not originally serve as a chamfer for preventing chipping or chipping. Further, even if chipping or chipping does not occur, there is a possibility that it does not meet the chamfered shape standard required in recent device processes. The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor wafer that prevents a chamfered shape from being lost in a planarization step.

  For this reason, in the present invention, when a sliced wafer obtained by cutting a semiconductor ingot is processed to manufacture a semiconductor wafer, the cut sliced wafer is flattened and then the outer peripheral portion thereof is chamfered. It is a thing. As the flattening process, there is a method of performing double-headed grinding as finish flattening after double-headed grinding. Further, there are a method of performing a flattening process after chamfering the outer peripheral part, or a method of rough chamfering the outer peripheral part before performing the flattening process.

Since it comprised as mentioned above in this invention, there exists the outstanding effect shown next.
(1) The chamfered shape once formed is not lost in the subsequent process. Therefore, problems such as chipping and chipping due to incomplete chamfering shape are eliminated, and the yield in the device process is improved.
(2) Since the flattened thickness center plane coincides with the center plane of the chamfered shape, a high-quality semiconductor wafer having a balanced shape can be manufactured. In particular, since a large-diameter semiconductor wafer has a large distance between the end surfaces, the matching accuracy between the thickness center surface and the chamfered center surface is an important requirement in semiconductor wafer quality.

  In the present invention, the chamfering that has always been performed before the planarization process of the sliced wafer is conventionally performed after the planarization process of the sliced wafer.

  Conventionally, since lapping has been frequently used in the flattening process, chamfering has been indispensable for preventing chipping and chipping. However, with the recent improvement in surface grinding technology accompanying the increase in the diameter of semiconductor wafers, it is not always necessary to chamfer before planarization. In particular, in single-sided surface grinding with one side chucked and double-sided grinding performed simultaneously on the front and back surfaces, unlike the lapping that fits the lapping carrier, there is nothing that the outer periphery collides with, causing cracks and chipping. The load concentration on the outer peripheral portion becomes very small. Therefore, by chamfering the sliced wafer after cutting after adjusting the shape of the flat surface by surface grinding, the chamfered shape is not greatly lost in the subsequent steps.

Embodiments of the present invention will be described below with reference to the drawings.
Example 1
FIG. 1 is a process diagram showing an example of a combination of steps in a manufacturing method according to the present invention, FIG. 2 is a process diagram showing a manufacturing method of Example 1, and FIG. 3 shows a shape of a semiconductor wafer obtained by the manufacturing method of Example 1. It is side surface sectional drawing highlighted. As shown in FIG. 2, the manufacturing method of the present embodiment includes the following steps.
(1) The semiconductor ingot is cut to obtain a sliced wafer 1a. Concavities and convexities 12a such as waviness are present on the front and back surfaces of the cut sliced wafer 1a. [See Fig. 3 (a)]
(2) Both the front and back surfaces of the cut sliced wafer 1a are flattened by primary double-side grinding, and irregularities 12a such as waviness due to cutting are removed. The double-head grinding here is rough grinding whose main purpose is to adjust the shape after cutting. Therefore, some unevenness 13a remains on the front and back surfaces. [Refer to FIG. 3 (b)]
(3) Both the front and back surfaces of the sliced wafer 1a from which the irregularities 12a have been removed are further subjected to precise secondary double-head grinding as a finishing process. The double-head grinding here is aimed mainly at increasing the flatness and reducing the processing strain layer generated in the first double-head grinding, thereby reducing the load of subsequent surface processing and increasing the productivity. Has an effect. [Refer to FIG. 3 (c)]
(4) The rear surface of the flatly processed wafer 1b is sucked and the outer peripheral portion 11b is chamfered. The chamfering method is arbitrarily selected depending on the target finish such as conventional grinding and polishing. [Refer to FIG. 3 (d)]
(5) The surface of the chamfered wafer 1c is etched to remove the front and back processing strain layers remaining in the secondary planarization process, and the processing strain layer generated by the chamfering process is also removed.

Example 2
In this embodiment, rough chamfering is performed before the flattening process, and then a flat shape is established by various surface grinding and lapping, and then the main chamfering for forming the shape of the outer peripheral portion is performed. (See Figure 1)
FIG. 4 is a partially enlarged side sectional view showing the shape of the outer peripheral portion of the semiconductor wafer in the manufacturing method of the second embodiment. The difference between the rough chamfering shown in the present embodiment and the chamfering for forming the original shape is that, as shown in FIG. 4, when the sliced wafer 3a is processed to obtain the wafer 3c, the shape of the outer peripheral portion 31c is changed. For removing the edge portion 31a which does not affect the thickness, for example, the thickness is about 8 inches and the thickness is about 800 to 900 μm, the allowance t is preferably about 50 to 100 μm.

  The main purpose of this rough chamfering is to prevent this when there is a risk of chipping or chipping during handling of the sliced wafer until it moves to the main chamfering process after the flattening process. It is formed as a simple means.

Example 3
In each of the above embodiments, the chamfering process is performed between the flattening process and the etching or polishing process. However, in this example, the chamfering process is performed between the two stages of the flattening process. Is. FIG. 5 is a process diagram showing an example of a combination of steps in the manufacturing method of Example 3, and FIG. 6 is a side sectional view showing the shape of a semiconductor wafer obtained by the manufacturing method of Example 3. As shown in FIG. 6A, the first surface grinding is applied to the sliced wafer 4a obtained by cutting the semiconductor ingot (not shown) by double-head grinding. As a result, the rough irregularities 42a on both the front and back surfaces of the sliced wafer 4 are removed.

  As shown in FIG. 6B, the back surface of the sliced wafer 4a subjected to the primary surface grinding is sucked and its outer peripheral portion is chamfered. Since the rough irregularities 42a have already been removed, the thickness center plane and the chamfer center plane substantially coincide. Therefore, the chamfered shape is not impaired in the subsequent steps.

  As shown in FIG. 6C, since the rough unevenness has already been removed, the thickness center plane 40a of the sliced wafer 4a and the chamfered center plane 40b of the wafer 4b substantially coincide. Therefore, the chamfered shape is not impaired in the subsequent steps.

  Secondary chamfering is performed on the chamfered wafer 4b by double-head grinding. As shown in FIG. 6D, chamfering has already been performed, but rough irregularities have already been removed, so that the chamfering shape of the wafer 4c is not impaired by this secondary surface grinding. In addition, since it has already chamfered and can be loaded into the lapping carrier without any problem, batch lapping can also be applied as the secondary surface grinding.

Example 4
In this embodiment, as a means for flattening, dry plasma etching is performed. This plasma etching has recently attracted attention as an etching means to replace the conventional immersion type wet etching. The biggest difference from the immersion type wet etching is the control accuracy of the machining allowance. In addition, since etching is performed, no load stress is generated on the outer peripheral portion of the wafer during processing, so there is no concern of chipping or chipping, and it can be said that it is suitable for flattening a sliced wafer after cutting.

  FIG. 7 is a process diagram showing the manufacturing method of Example 4. Although it is possible to planarize the sliced wafer after cutting only by plasma etching, a weak point of plasma etching at present is that the processing time is long. (See Figure 1)

  Therefore, productivity can be improved by using it in combination with surface grinding or lapping. For example, as shown in FIG. 7, rough irregularities on the front and back surfaces of the sliced wafer cut as shown in FIG. 7 are removed by double-head grinding, and then chamfering is performed, and plasma etching is further performed. Since the flat shape of the wafer is generally prepared by double-head grinding, the chamfering center plane in the subsequent process and the etching reference (center) plane substantially coincide. By performing plasma etching on the chamfered wafer, the flatness can be further improved, and at the same time, the processing strain layer generated by double-head grinding can be removed, and the next polishing is performed without performing wet etching. It is also possible.

It is process drawing which shows the example of a combination of the process in the manufacturing method concerning this invention. FIG. 3 is a process diagram illustrating the manufacturing method of Example 1. It is side surface sectional drawing which emphasizes and shows the shape of the semiconductor wafer obtained by the manufacturing method of Example 1. FIG. FIG. 10 is a partial enlarged side cross-sectional view showing the shape of a semiconductor wafer outer peripheral portion in the manufacturing method of Example 2. 6 is a process diagram showing an example of a combination of processes in the manufacturing method of Example 3. FIG. 6 is a side sectional view showing the shape of a semiconductor wafer obtained by the manufacturing method of Example 3. FIG. FIG. 6 is a process diagram showing the manufacturing method of Example 4. It is side surface sectional drawing which emphasizes and shows the shape of the semiconductor wafer at the time of planarizing by single-sided surface grinding in the manufacturing method of a prior art. It is side surface sectional drawing which emphasizes and shows the shape of the semiconductor wafer at the time of planarizing by double-headed grinding in the manufacturing method of a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a ... Sliced wafer 12a ... Unevenness 13a ... Unevenness 1b ... Wafer 11b ... Outer peripheral part 1c ... Wafer 3a ... Sliced wafer 3c ... Wafer 31a ... Edge part 31c ... Outer part t ... Tolerance 4a ... Sliced wafer 42a ... Unevenness 4b ... Wafer 4c ... wafer 40a ... thickness center plane 40b ... chamfer center plane

Claims (2)

In manufacturing a semiconductor wafer by processing a sliced wafer obtained by cutting a semiconductor ingot, the sliced wafer that has been cut is flattened, and then the outer periphery is chamfered and the outer periphery is chamfered. Further, the sliced wafer is further flattened by a double-headed grinding machine. In manufacturing a semiconductor wafer by processing a sliced wafer obtained by cutting a semiconductor ingot, the sliced wafer that has been cut is flattened, and then the outer periphery is chamfered and the outer periphery is chamfered. A method of manufacturing a semiconductor wafer, comprising subjecting the sliced wafer to planarization and then subjecting the sliced wafer to etching.

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