JP2007189703A - Output circuit for gradation control and apparatus for inspection thereof, and method for inspecting the output circuit for gradation control - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an output circuit for gradation control which is used for a display device or an output device for achieving excellent gradation display, and to provide a means for inspecting the output circuit for gradation control for current driving. <P>SOLUTION: An output circuit for gradation control comprises a low-side current mirror 55, a low-side gradation control circuit 59, a high-side current mirror 56, a high-side gradation control circuit 60, a current volume-up control circuit 61, and a selective precharge control circuit 62. Since the gradation control circuit for outputting a gradation signal is divided into a high-side and a low-side, characteristics of an output current can be approximated to γ characteristics of a light-emitting element. Furthermore, by using a multi-stage type current mirror, the dispersion of a current for each output part can also be suppressed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a gradation control output circuit used for a display device and an output device, and more particularly, to a driver IC that performs gradation control by current or voltage, an inspection apparatus for the driver IC, and a driver IC inspection method.

  In general, in an active matrix image display apparatus, an image is displayed by arranging a large number of pixels in a matrix and controlling the intensity of light for each pixel in accordance with given luminance information. Therefore, for example, a rectangular display panel is arranged in a matrix, and TFTs (Thin-Film-Transistors) that control the state of liquid crystals or optical materials, and data line driving circuits provided along the upper and lower sides of the panel, And a gate line driving circuit provided at a side end portion of the panel.

  Conventionally, image display devices such as display panels have mainly used liquid crystal as an optical material. In these image display devices, a liquid crystal driving circuit (liquid crystal driver) supplies display information to each pixel in the form of voltage, and changes the transmittance of the pixel in accordance with this display information.

  In contrast, in recent years, there have been active proposals for image display devices using organic EL (Electro Luminescence) as light emitting elements. Unlike the liquid crystal, the organic EL itself emits light, so that a display panel using the organic EL has advantages of high visibility and no need for a backlight. An organic EL used for a display panel has a function of a diode, and emits light when supplied with a current. This organic EL panel has two driving methods.

  FIG. 24 is a diagram for explaining a driving method of the organic EL panel.

As shown in the figure, the first driving method of the organic EL panel is a voltage writing method. This is a method in which display data is supplied to a TFT (low poly pixel Tr) in the form of a voltage V ₀ from a voltage driving driver. The electric charge accumulated in the load such as a capacitor is charged or discharged according to the voltage V ₀ , and thereby the current I ₀ flows through the organic EL diode. This driving method has the advantage that the existing liquid crystal driver IC technology can be used. However, since the voltage supply is unstable, there is a problem that it is difficult to compensate for the characteristic unevenness of the TFT made of low-temperature polysilicon. is doing.

The second driving method of the organic EL panel is a current writing method. This method is a method of controlling gradation display by changing the amount of current drawn from the panel. The TFT made of low-temperature polysilicon on the panel forms a current mirror, and a current equal to the current I ₀ drawn from the panel to the signal line flows through the TFT. According to this method, variation in TFT characteristics can be compensated, and high image quality of the organic EL panel can be realized.

  In an organic EL panel capable of color display, pixels of three colors R (red), G (green), and B (blue) are arranged. In the case of the current writing method, the current from the driver for current driving is used. Accordingly, the brightness of the pixel is changed, so that gradation display of the brightness of the pixel is possible.

  25A and 25B are a circuit diagram showing the configuration of a conventional voltage driving driver for driving the display device, which realizes the above-described gradation display, and the power supply potential in the power supply voltage supply line. It is a figure which shows the relationship between the distance from a power supply voltage supply part.

As shown in FIG. 6A, a conventional voltage driver (grayscale control output circuit) is connected to a power supply voltage supply unit 1112 and a power supply voltage supply unit 1112, and has grayscale control having an output unit 1116. 1101a, 1101b... 1101 _N (N is a natural number), a current supply unit 1110 connected to the ground, a power supply voltage supply unit 1112 and a current supply unit 1110, and a drain and a gate electrode. The first MISFET 1111 which is a P-channel MISFET connected to each other, the first node 1118 provided between the first MISFET 1111 and the power supply voltage supply unit 1112, and the gate electrode of the first MISFET 1111 are connected. The gate bias supply line 1115 and the first node 1118 are connected to each other to supply power to each gradation control unit. A voltage supply line 1121 is provided on the power supply voltage supply line 1121, tone control unit 1101a, 1101b ..., the power voltage supply node 1117 connected respectively to 1101 _N, and between the power supply voltage of each power supply voltage supply node 1117 A resistor 1113 provided between the supply node 1117 and the first node 1118 is provided. Here, an example in which N gradation control units are provided is shown, but generally one gradation control output circuit is often provided with about 400 to 500 gradation control units.

Further, in the conventional gradation control output circuit, tone control unit 1101a, 1101b ..., a current mirror circuit is utilized to 1101 _N.

That is, as shown in FIG. 25A, the gradation control unit 1101a includes both the P-channel type second MISFET 1102a and the third MISFET 1103a, whose sources are connected to each other and to the power supply voltage supply node 1117. The voltage selection switch 1120a, the operational amplifier 1106a having the voltage selection switch 1120a connected to the (+) side of the input unit, the output unit 1116 connected to the (−) side, the source to ground, and the drain to the third MISFET 1103a. In addition, the output side transistor 1105a, which is an N-channel MISFET whose gate electrode is connected to the output portion of the operational amplifier 1106a, is interposed between the output side transistor 1105a and the third MISFET 1103a, and is connected to the output portion 1116. The first node 1114a and The output of the amplifier 1106a - and an oscillation preventing capacitor 1119a provided between the wiring for connecting the the gate electrode of the output side transistor output transistors 1105a- second node. The second MISFET 1102a and the operational amplifier 1106a constitute a differential circuit 1107a, and the third MISFET 1103a, the first node 1114, the oscillation prevention capacitor 1119a, and the output side transistor 1105a constitute an output buffer unit 1108a. Here, in the conventional gradation control unit 1101a, the second MISFET 1102a and the third MISFET 1103a have the same electrical characteristics, and both gate electrodes are connected to the gate bias supply line 1115. A current mirror circuit is configured. Then, in order to drive the load, towards the current _{I 2} flowing through the third MISFET1103a it is designed to be larger than the current _{I 1} flowing through the second MISFET1102a.

Further, in the conventional gradation control output circuit, N number of the tone control unit 1101a, 1101b ..., 1101 _N are respectively have the same circuit configuration as the above-described gradation control unit 1101a. The second MISFET1102a, 1102b ..., 1102 _N and a third MISFET1103a, 1103b ..., the gate electrode of 1103 _N are respectively connected to gate bias supply line 1115. As shown in FIG. 25B, equal voltages are applied from the gate bias supply line 1115 to the gate electrodes of these MISFETs so that the MISFETs are turned on.

  In the conventional gradation control output circuit, a multiplexer capable of selecting a plurality of reference voltages according to digital data is used as a voltage selection switch. The voltage selected here is current-amplified by an operational amplifier and output to a panel using liquid crystal or organic EL.

Note that the conventional current control gradation control output circuit used in the current writing type organic EL panel includes gradation control units 1101a, 1101b... 1101 _N of the gradation control output circuit shown in FIG. A structure replaced with a current addition type D / A converter is adopted. From this D / A converter, a current having a magnitude corresponding to the gradation data is supplied to the TFT and the pixel, thereby enabling gradation display on the organic EL panel.

  Note that such a current-driven gradation control output circuit can be used not only as a driver for an organic EL panel but also as a head of an output device such as a printer. In addition, it can be used not only as an organic EL, but also as a display driver or printer head using an inorganic EL or LED (Light Emitting Diode).

  Next, a conventional method for inspecting a current drive gradation control output circuit will be described.

  FIGS. 26A and 26B are a sectional view showing a conventional probe card for inspecting a current-driven gradation control output circuit, and a block circuit diagram showing a section of the conventional probe card, respectively. .

  As shown in FIG. 4A, the conventional gray scale control output circuit for current drive is inspected by connecting a probe 1155 made of a conductor on the lower surface of the semiconductor tester 1152 connected to the head 1153 on the upper surface side. The card 1156 is placed on a wafer 1151 to be inspected on which a large number of drivers for current drive are provided.

  Specifically, as shown in FIG. 26B, an inspection current is applied from the head 1153 of the semiconductor tester 1152 in a state where the inspection pads 1154 (or bumps) provided on the wafer are in contact with the probes 1156. The inspection is executed by detecting the current output from the inspection bump after that.

  Many of the organic EL diodes exhibit the maximum luminance when the supplied current is 1 μA or less. Therefore, when the organic EL panel has 6-bit gradation (64 gradations), the current per gradation is 10 to 20 nA. It will be about. Therefore, the semiconductor tester 1152 can detect a current of about 10 to 20 nA. The semiconductor tester, the probe card, the connection jig between the semiconductor tester and the probe card, etc. used here are the same as those used for general wafer inspection.

First, as can be seen from FIG. 25B, in the conventional voltage driver, since the same gradation control unit is connected to one power supply voltage supply wiring 1121, it is far from the power supply voltage supply unit 1112. At the power supply voltage supply node 1117 at the position, the supplied voltage has dropped due to the presence of the resistor 1113 and the like. On the other hand, since the potential of the gate bias supply line 1115 is constant regardless of the position, the voltage V _GS applied between the gate and the source of the second MISFET 1102 and the third MISFET 1103 is a distance from the power supply voltage supply unit 1112. Will vary.

On the other hand, the oscillation prevention capacitor of the output buffer unit is charged by the output current of the differential circuit (output from the operational amplifier). In general, since the current flowing through the differential circuit side is smaller than that at the output buffer side, the length of the charging time of the oscillation prevention capacitor depends on the current flowing through the differential circuit. Further, if the power supply voltage supplied to each differential circuit varies, the magnitude of the current I ₁ varies. For this reason, in the conventional voltage control gradation control output circuit, the power supply voltage supplied to each differential circuit varies, and the magnitude of the current distributed to the differential circuit also varies. Charging time varied. As a result, in the conventional voltage drive gradation control output circuit, the slew rate of the operational amplifier varies depending on the distance from the power supply voltage supply unit 1112, and the current output from the output unit also varies.

  For this reason, when a conventional voltage-driven gradation control output circuit is used for a liquid crystal or an organic EL panel, problems such as unevenness of screen display have occurred. Further, when a conventional voltage-driven gradation control output circuit is used as a printer head, uneven printing may occur.

  Such inconvenience due to the voltage drop of the power supply voltage supply wiring can also be seen in a conventional current drive gradation control output circuit having a configuration similar to that of the voltage drive gradation control output circuit.

  In a conventional current control gradation control output circuit, current is directly distributed to 176 output units from one current source using a current mirror. One of the output currents is input to the gradation control unit, but there is a problem that the output current also varies from output unit to output unit.

  On the other hand, in the conventional method for inspecting the output circuit for gradation control for current drive, since the detected current value is as small as 10 to 20 nA, the detection signal deteriorates between the wafer 1151 to be inspected and the semiconductor tester 1152. There was a problem that it would. This is because the detection signal propagates through the probe card 1151, the connection wiring 1158, the jig, and the like. For this reason, it is difficult to inspect the gradation control output circuit with sufficient accuracy.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a gradation control output circuit that is used in a display device or an output device and realizes good gradation display, and to inspect a current-driven gradation control output circuit. It is to provide means.

  The first gradation control output circuit according to the present invention includes a power supply voltage supply section, a first current supply section, a first power supply voltage supply wiring connected to the power supply voltage supply section, and the power supply voltage supply. A second power supply voltage supply line connected to the power supply section, a first electrode having a gate electrode interposed between the first current supply section and the power supply voltage supply section and connected to the power supply voltage supply section. MISFET, an output buffer unit including a first transistor connected to the first power supply voltage supply wiring, and a current mirror connected to the second power supply voltage supply wiring and together with the first transistor A plurality of gradation control units having a differential circuit including a second transistor and a gate electrode of the first MISFET are connected to control a current flowing through the first transistor and the second transistor. of And a bias supply line.

  With this configuration, wiring for supplying a power supply voltage to each of the differential circuit and the output buffer unit is individually provided, and thus occurs in the first power supply voltage supply wiring and the second power supply voltage supply wiring. The voltage drop can be reduced as compared with the case where the power supply voltage supply wiring is not divided. Therefore, variation in the gate-source voltage or the gate-drain voltage of the first transistor and the second transistor caused by the difference in distance from the power supply voltage supply unit can be suppressed. As a result, variation in current flowing through each output buffer unit is suppressed, and variation in current flowing through each differential circuit is also suppressed, so variation in current output from each output unit of the gradation control unit is also suppressed. Therefore, the display unevenness in the panel can be reduced by using the output circuit for gradation control of the present invention for the display device, and the printing unevenness of the printer can be suppressed by using it for the head of the printer.

  The first transistor and the second transistor may both be MISFETs having a gate electrode connected to the bias supply line and having the same conductivity type.

  Since the current flowing through the first transistor during driving is larger than the current flowing through the second transistor, it is possible to effectively drive a large load such as a panel of a display device.

  The gradation control unit further includes a voltage selection switch for supplying a voltage for gradation control to the output buffer unit, so that the output circuit for gradation control of the present invention includes a liquid crystal panel and the like. It is preferably used for a display device or an output device that employs a voltage driving method.

  The differential circuit includes an operational amplifier having an input unit connected to the voltage selection switch and an output unit connected to the output buffer unit, and amplifies the current of the voltage signal selected by the voltage selection switch. Can do.

  A gradient bias MISFET connected to the second current supply unit, the second current supply unit, and the first power supply voltage supply line, and having the same conductivity type as the first MISFET; The gate electrode of the MISFET for use is connected to the first power supply voltage supply line and the bias supply line, so that the potential gradient in the bias supply line is changed to the first power supply voltage supply line and the second power supply voltage supply. Since it becomes possible to match the voltage drop in the wiring, it is possible to more effectively suppress variations in the gate-source voltage or the gate-drain voltage in the first transistor and the second transistor. As a result, variation in current output from the gradation control unit can be greatly reduced.

  The power supply voltage supply unit further includes a second MISFET that forms a sender-side current mirror together with the first MISFET, and the second current supply unit is connected to the sender-side current mirror, By being a receiver-side current mirror composed of MISFETs of the same conductivity type, the receiver-side current mirror receives a current equal to the current flowing through the sender-side current mirror even when the receiver-side current mirror is located away from the power supply voltage supply unit. Can flow to the current mirror.

  The second gradation control output circuit of the present invention includes a power supply voltage supply unit, a first current supply unit, a power supply voltage supply line connected to the power supply voltage supply unit, and the first current supply unit. And a plurality of grayscale controls including a first MISFET having a gate electrode connected to the power supply voltage supply unit and a transistor connected to the power supply voltage supply line. Connected to the second current supply unit, the second current supply unit, and the power supply voltage supply wiring, and the gradient bias MISFET having the same conductivity type as the first MISFET, and the first MISFET A bias supply line for connecting a gate electrode and the gate electrode of the tilt bias MISFET, connected to the power supply voltage supply line, and for controlling a current flowing through the transistor; .

  This makes it possible to match the slope of the potential in the bias supply line to the voltage drop in the power supply voltage supply wiring, thereby suppressing variations in current flowing through the transistors in the gradation control unit without dividing the power supply voltage supply wiring. be able to. Further, since the power supply voltage supply wiring is integrated into one, the wiring area can be reduced as compared with the case where the power supply voltage supply wiring is divided.

  Since the transistor is a MISFET having a gate electrode connected to the bias supply line, variation in output current from the gradation control unit can be more accurately suppressed.

  The power supply voltage supply unit further includes a second MISFET that forms a sender-side current mirror together with the first MISFET, and the second current supply unit is connected to the sender-side current mirror, By being a receiver-side current mirror composed of MISFETs of the same conductivity type, the receiver-side current mirror receives a current equal to the current flowing through the sender-side current mirror even when the receiver-side current mirror is located away from the power supply voltage supply unit. Can flow to the current mirror. That is, it is possible to supply a constant current to the gradation control unit at a position away from the power supply voltage supply unit without being affected by the voltage drop. For this reason, the dispersion | variation by the output part of a gradation control part can further be reduced.

  Since the plurality of gradation control units are current addition type D / A converters, the gradation control output circuit of the present invention is for current drive of a display device using a light emitting element such as an organic EL panel. It can be used as a printer head of a driver or an output device such as a printer using a light emitting element.

  The plurality of gradation control units include a plurality of current mirror units connected in parallel to the power supply voltage supply node and the same number of selection switches connected to the current mirror unit for representing M gradations. And a current output unit connected to all the selection switches, and the current mirror unit is configured by a current mirror composed of the transistor, so that a current-driven display device or output device is provided. The output circuit for gradation control used in the above can be manufactured with a relatively simple configuration.

  In order to control the M gradation, the current mirror section is composed of 1, 2,..., M / 2 current mirrors having the same element configuration, thereby providing a highly accurate current addition type D. / A converter can be realized. In other words, a gradation control output circuit that realizes satisfactory gradation display can be realized.

  The transistors are MISFETs having the same element configuration, and in order to control the M gradation, the output current from each current mirror section is adjusted by the ratio of the gate width of the MISFET to the gate length. Good.

  The gradation control unit includes a plurality of gradation generation units having a current mirror unit and selection switches having the same number of transfer gates and inverters connected to the current mirror unit, and the current mirror unit In addition, since the selection switch is arranged for each of the gradation generation units, the area of the gradation control output circuit of the present invention that realizes good gradation display can be reduced.

  The transistors are a first transistor and a second transistor that have the same conductivity type and constitute a current mirror. The gradation control unit includes: an output buffer unit including the first transistor; And a differential circuit having two transistors. This configuration is preferably employed particularly when used as a voltage driving driver.

  It is preferable for driving a load such as a panel that the current flowing through the first transistor during driving is larger than the current flowing through the second transistor.

  The gradation control unit further includes a voltage selection switch for supplying a voltage for gradation control to the output buffer unit, so that a variation in output current is reduced. It is preferably used as a drive type printer head.

  The differential circuit realizes a two-stage amplifier type voltage driver by having an operational amplifier having an input connected to the voltage selection switch and an output connected to the output buffer. Can do.

  The third gradation control output circuit of the present invention comprises a plurality of current mirrors, and a plurality of multistage current mirrors in which a current equal to the current flowing through the first stage current mirror flows through each of the three or more stage current mirrors And a plurality of gradation control units for receiving reference voltages and gradation signals from each of the plurality of multi-stage current mirror units and outputting different gradation control currents.

  With this configuration, by using a multistage current mirror, variation in the value of the current input to the gradation control unit is reduced. In addition to this, by providing a plurality of gradation control sections for outputting different gradation control currents, the characteristics of the output current of the gradation control output circuit can be changed to organic EL, inorganic EL, LED It can be approximated to the γ characteristic of the light emitting element. As a result, the display characteristics are improved when the gradation control output circuit of the present invention is used in a display device, and the printing characteristics are improved when it is used in an output device.

An output control unit for receiving a gradation control current from the plurality of gradation control units and changing a combination of the gradation control currents output according to the gradation signal; Control can be performed so that the characteristics of the output current from the gradation control output circuit approximate to the γ characteristics of the light emitting element. As a result, good gradation display can be realized in a display panel or printer using the gradation control output circuit of the present invention.

  The plurality of gradation control units include a low-side gradation control unit capable of controlling a gradation in the lowest range among the plurality of gradation control units, and a gradation higher than the low-side gradation control unit. The plurality of multi-stage current mirror sections are divided into a controllable high-side gradation control section, and the plurality of multi-stage current mirror sections include a low-side multi-stage current mirror section connected to the low-side gradation control section and the high-side gradation control section. By separating the high-side multistage current mirror unit connected to, the output current characteristic of the gradation control output circuit can be satisfactorily approximated to the γ characteristic of the light emitting element.

  The output control unit outputs only the gradation control current from the low-side gradation control unit when the number of gradations is a predetermined value or less, and when the number of gradations exceeds the predetermined value, By controlling to output the gradation control current from the high-side gradation control unit in addition to the gradation control current from the low-side gradation control unit, the γ characteristic (current -Luminance characteristics) It becomes possible to change the characteristics of the output current of the output circuit for gradation control in accordance with the inclination of the graph.

  The low-side multi-stage current mirror section, the high-side multi-stage current mirror section, the low-side gradation control section, and the high-side gradation control section for at least three colors of red, green, and blue are integrated on the same chip. Thus, the gradation control output circuit of the present invention is used as a driver IC for color display. It is also used as a printer head for a color printer.

  The low-side multistage current mirror unit and the high-side multistage current mirror unit are arranged adjacent to each other one by one and arranged in a predetermined color order in the row direction, and the low-side gradation control unit, The low-side gradation control unit and the output control unit are arranged substantially in a matrix and connected to one set of the low-side multistage current mirror unit and the high-side multistage current mirror unit. The high-side gradation control unit and the output control unit are arranged firmly, so that the wiring area can be reduced, which leads to a reduction in the size of the display panel.

  The gradation control unit includes a plurality of gradation generation units having a current mirror unit and selection switches having the same number of transfer gates and inverters connected to the current mirror unit, and the current mirror unit In addition, the selection switch is arranged in a solid manner for each of the gradation generation units, so that redundant wiring between the current mirror unit and the inverter can be reduced as compared with a layout in which the selection switches are arranged for each element. And the wiring area can be effectively reduced. In addition, the output impedance of the gradation control circuit can be reduced by widening the output wiring of the gradation control circuit.

  In response to the raising control signal and the reference voltage supplied from the high-side multistage current mirror, the output current from the low-side gradation control unit and the current that raises the output current from the high-side gradation control unit are By further providing a current raising control circuit for outputting to the output control unit, for example, the display contrast in a panel using a light emitting element can be increased.

  By further providing a current raising control circuit for outputting a current for raising the output current of the low-side gradation control unit between the low-side multistage current mirror unit and the low-side gradation control unit. Therefore, it is possible to increase the output current from the gradation control unit while suppressing an increase in area.

  The current raising control circuit can also have a function of increasing or decreasing the output current in accordance with the gradation to be controlled.

  The output control circuit includes a selection precharge circuit for supplying a voltage for charging an external signal line by switching control, and a selection for turning on the selection precharge circuit for a predetermined period by timing control according to display data. By further including the precharge control circuit, for example, since the signal line of the display panel can be charged in advance by the selective precharge circuit, black display on the display panel can be quickly executed. . This is particularly effective when TFTs made of low-temperature polysilicon are arranged on the panel of the display device.

  A fourth gradation control output circuit according to the present invention is integrated on a semiconductor chip and has an internal circuit having an output unit for outputting a current signal, and is provided on the semiconductor chip and connected to the output unit. And a resistor provided on the semiconductor chip and connected to the output unit for converting a current signal into a voltage signal.

  With this configuration, since a minute current output from the internal circuit can be converted into a voltage signal by a resistor on the chip, the voltage signal can be hardly attenuated by a probe or a jig. As a result, an accurate inspection can be performed.

  The switch circuit further includes a switch circuit connected to the resistor, and the switch circuit is connected so that the resistor is connected to the external terminal in series with the external terminal during normal operation and power-off. At the time of inspection, the resistor is connected to the ground, and the resistor and the external terminal are connected so as to be connected in parallel to the output unit, thereby causing a high voltage current (surge) from the external terminal. Is input, the resistor can limit the amount of current input from the outside, so that the internal circuit can be protected. Further, at the time of inspection, the resistor can function as a resistor for current / voltage conversion.

  The internal circuit may include a multistage current mirror section and a gradation control section for receiving a reference voltage from the multistage current mirror section and outputting a gradation control current.

  The fifth gradation control output circuit of the present invention supplies a signal to a plurality of gradation control sections having a plurality of bit cells, a latch circuit for normal operation provided for each of the bit cells, and all the bit cells. Common latch circuit, and the common latch circuit and the normal operation latch circuit are provided between the bit cell, the signal from the normal operation latch circuit is transmitted to the bit cell during normal operation, and at the time of inspection, And a selection circuit for switching so that the signal output from the common latch circuit is transmitted to the bit cell.

  This eliminates the need for a signal applied at the time of inspection through a plurality of latch circuits, thereby reducing the inspection time.

  A multi-stage current mirror unit for supplying a reference voltage to the plurality of gradation control units may be further provided.

  An inspection apparatus for a gradation control output circuit according to the present invention has an upper surface provided on a wafer tester and a lower surface of the substrate for receiving a current signal from at least the wafer to be inspected. A probe made of a conductor, disposed on the substrate in proximity to the probe, connected to the probe to convert the current signal into a voltage signal, connected to the resistor, and And a wiring provided penetrating therethrough.

  With this configuration, when a minute current signal is output from the wafer to be inspected, the current signal can be converted into a voltage signal by the resistor, so that the current signal can reach the tester without being attenuated. Therefore, it is possible to execute inspection of a wafer having a gradation control output circuit that outputs a minute current signal.

  The distance between the probe and the resistor is preferably 10 cm or less.

  By providing an operational amplifier connected in parallel with the resistor to the probe and having an output connected to the negative input via the resistor, signals from the wafer to be inspected can be easily obtained by a tester. It will be possible to measure.

  By inputting the reference voltage output from the tester to the positive side input section of the operational amplifier, even when the output current value range from the wafer to be inspected is wide, the reference voltage is changed to change the reference voltage from the wafer. Can be easily detected.

  Since the resistors are integrated, the inspection apparatus of the present invention can be easily realized.

  Since the operational amplifier is integrated, the inspection apparatus of the present invention can be easily realized.

  According to the grayscale control output circuit inspection method of the present invention, the reference current source connected to the first resistors connected in parallel to each other and the grayscale control current connected to the reference current source are output. An inspection method of a gradation control output circuit including a gradation control unit for providing a gradation control output circuit, wherein the inspection circuit is provided in parallel with the first resistor and has a resistance value lower than that of the first resistor. The second resistor is connected to the reference current source, and the connection between the second resistor and the reference current source is turned off during normal operation.

  By this method, the current input to the reference current source at the time of inspection can be made larger than that at the time of normal operation, so that the inspection current can be increased and the inspection can be facilitated.

  According to the output circuit for gradation control of the present invention, the gradation control circuit and the multi-stage current mirror section are provided separately on the low side and the high side, so that it matches the γ characteristic of the light emitting element such as an organic EL. Gradation control is possible. Further, since the arrangement of the gradation control circuit and the multistage current mirror unit is optimized, the wiring area can be kept small.

(First embodiment)
As a first embodiment of the present invention, a gradation control output circuit (for voltage driving) in which a wiring for supplying a power supply voltage to a differential circuit and a wiring for supplying a power supply voltage to an output buffer section are separated Driver) will be described with reference to the drawings.

-Basic configuration of output circuit for gradation control for voltage drive-
FIG. 1 is a circuit diagram showing a configuration of a gradation control output circuit according to the first embodiment of the present invention.

As shown in the figure, the output circuit for gradation control according to this embodiment includes a power supply voltage supply unit 12, a current supply unit 10 connected to the power supply voltage supply unit 12 for supplying a constant current, and a current. A first MISFET 11 which is a P-channel MISFET having a drain and a gate electrode connected to each other between the supply unit 10 and the power supply voltage supply unit 12, and a first MISFET 11 and a power supply voltage supply unit 12; .., 1 _N having a first node 23 and a second node 24, and a differential circuit 7a, a voltage selection switch 20a, an output buffer unit 8a, and an output unit 16. (N is an integer), connected to the gate bias supplying line 15 connected to the gate electrode of the first MISFET, between the output buffer portion 8a of the first node 23 and a tone control unit 1 _N, each floor Regulation An output unit for the voltage supply line 23a for supplying a power supply voltage to the output buffer unit parts, provided at an output unit for the voltage supply line on 23a, tone control unit 1a, 1b ..., 1 N- 1 of the output buffer Among the first power supply voltage supply node 25 connected to the output section and the output section voltage supply line 23a, the first power supply voltage supply node 25 is connected between the first power supply voltage supply node 25 and the first node 23. The first resistor 21 interposed therebetween, the second node 24 and the differential circuit 7 _N of the gradation control unit 1 _N are connected, and the power supply voltage is connected to the differential circuit of each gradation control unit. a differential circuit voltage supply line 24a for supplying, first provided on the differential circuit voltage supply line 24a, the tone control unit 1a, 1b ..., are connected to the 1 _N-1 differential circuit Of the second power supply voltage supply node 26 and the differential circuit voltage supply line 24a. And a second resistor 22 that is interposed between the supply node 26-second node 24 and between the second power supply voltage supply node 26. In many cases, one gradation control output circuit includes about 400 to 500 gradation control units. Note that the gradation control output circuit of this embodiment is usually integrated in the same chip.

  Further, the first resistor 21 and the second resistor 22 are generated due to factors such as layout, and ideally do not exist.

-Configuration of gradation control unit-
The gradation control unit of the output circuit for gradation control according to this embodiment has a current mirror circuit using MISFETs as in the case of a conventional voltage driving driver.

  As shown in FIG. 1, the gradation control unit 1a includes a P-channel type third MISFET 3a whose source is connected to the first power supply voltage supply node 25, and a source connected to the second power supply voltage supply node 26. The P-channel type second MISFET 2a, the voltage selection switch 20a, the operational amplifier 6a in which the voltage selection switch 20a is connected to the (+) side of the input unit, and the output unit 16 is connected to the (−) side, An output side transistor 5a, which is an N-channel MISFET having a source connected to ground, a drain connected to the third MISFET 3a, and a gate electrode connected to the output of the operational amplifier 6a, and between the output side transistor 5a and the third MISFET 3a A third node 14 connected to the output unit 16, and an output unit of the operational amplifier 6a-a gate electrode of the output side transistor 5a And an output-side transistor 5a- third node oscillation preventing capacitor 19a provided between the wiring which connects between 14 and.

The second MISFET 2a and the operational amplifier 6a constitute a differential circuit 7a, and the third MISFET 3a, the third node 14, the oscillation prevention capacitor 19a, and the output side transistor 5a constitute an output buffer unit 8a. Here, in the gradation control unit 1a of the present embodiment, the second MISFET 2a and the third MISFET 3a have the same electrical characteristics, and their gate electrodes are connected to the gate bias supply line 15. And constitutes a current mirror circuit. Then, the tone control output circuit of the present embodiment, N pieces of the tone control unit 1a, 1b ..., 1 _N are each have the same circuit configuration as the tone control unit 1a described above. The second MISFET2a, 2b ..., _{2 N,} and third MISFET3a, 3b ..., a gate electrode of the _{3 N} is connected to a gate bias supply line 15, respectively. Gate bias from the supply line 15 of the ₂ MISFET2a, 2b ..., 2 _N, and third MISFET3a, 3b ..., ₃ voltage supplied to the gate electrode of the _N is substantially the same regardless of its position, these MISFET is Always on.

In the following herein, the tone control unit 1a, 1b ..., 1 _N of in representing not distinguish each referred to as "gray scale control unit 1", components of the tone control unit 1 N second MISFETs, third MISFETs, output side transistors, operational amplifiers, and voltage selection switches that are not distinguished from each other are expressed as “second MISFET 2”, “third MISFET 3”, “ They are expressed as “output-side transistor 5”, “operational amplifier 6”, and “voltage selection switch 20”.

-Function of gradation control unit-
The gradation control unit 1 is a two-stage amplifier including an output buffer unit 8 for supplying a driving current to TFTs and pixels (not shown) of a liquid crystal panel, and a differential circuit 7 for controlling the driving current to be output. It has a configuration.

First, when the output circuit for gray scale control is driven, power supply voltages having substantially equal values are supplied from the first power supply voltage supply node 25 and the second power supply voltage supply node 26 to the second MISFET 2 and the third MISFET 3, respectively. Is done. Then, the current mirror circuit functions and currents I ₁ and I ₂ flow through the second MISFET 2 and the third MISFET 3, respectively. Note that the current I ₂ is set to be larger than the current I ₁ in order to drive the load connected to the output unit 16. In this embodiment, the ratio of the value of the current I ₁ : current I ₂ is about 1: 5.

  On the other hand, the voltage selection switch 20 is a multiplexer, for example, and has a function of selecting a plurality of reference voltages according to digital data. The operational amplifier 6 of the differential circuit 7 amplifies the selection voltage selected by the voltage selection switch 20 by negative feedback. Next, the current-amplified voltage is output from the output unit 16 to the liquid crystal or the organic EL panel via the oscillation prevention capacitor 19. At this time, the oscillation prevention capacitor 19 changes the phase of the output signal of the operational amplifier 6 and stabilizes the output of the operational amplifier 6 that has been negatively fed back.

In the gradation control unit 1, the oscillation prevention capacitor 19 is charged by the output current (= current I ₁ ) of the operational amplifier 6 and the current flowing through the output buffer unit 8. However, since the current flowing through the differential circuit 7 side is smaller than the current flowing through the output buffer unit 8 side, the charging time of the oscillation preventing capacitor 19 varies depending on the magnitude of the output current of the operational amplifier 6. When the charging time of the oscillation prevention capacitor 19 changes, the slew rate of the operational amplifier 6 changes, and the charging time to the load connected to the output unit 16 also changes. Since the current flowing through the differential circuit 7 changes according to the gate-source voltage V _GS1 of the second MISFET 2, when the potential of the gate bias supply line 15 is constant regardless of the position, the current from the second power supply voltage supply node 26 By making the supplied power supply voltage constant, the output current can be made constant.

-Differences from conventional voltage driver-
The gradation control output circuit of the present embodiment is different from the conventional voltage driver in that wirings for supplying respective power supply voltages to the differential circuit and the output buffer unit are separated.

  As a result, the gradation control output circuit of the present embodiment can suppress the voltage drop due to the resistor as compared with the conventional voltage driving driver. Therefore, a voltage drop at the first power supply voltage supply node 25 and the second power supply voltage supply node 26 located far from the power supply voltage supply unit 12 is suppressed, and the first power supply voltage supply node 25 and the second power supply voltage are suppressed. The voltage difference due to the position of the supply node 26 can be reduced.

In the gradation control output circuit of this embodiment, since the potential of the gate bias supply line 15 is constant regardless of the position, variations in the gate-source voltage V _GS1 of the second MISFET 2 can be suppressed. For this reason, the current flowing through the differential circuit 7 becomes substantially constant regardless of the distance from the power supply voltage supply unit 12, and the slew rate of the operational amplifier 6 can be made substantially constant.

  Therefore, by using the output circuit for gradation control of this embodiment, the charging time to the load can be made constant, so that a liquid crystal panel without display unevenness or a voltage writing type organic EL panel can be realized. it can.

  In the gradation control output circuit of this embodiment, the voltage to be supplied to the display device or the like can be switched by the voltage selection switch 20, and gradation control is performed thereby.

  Note that the gradation control output circuit of this embodiment is used not only as a liquid crystal drive driver but also as a printer head or the like that displays gradation according to voltage.

In the present embodiment, the ratio of the current I ₁ : current I ₂ value is set to about 1: 5. However, the current value ratio is not particularly limited as long as I ₁ <I ₂ .

  In the gradation control output circuit of this embodiment, a P-channel type MISFET is used as the MISFET constituting the current mirror circuit, but an N-channel type MISFET may be used instead.

  In the gradation control output circuit according to the present embodiment, an npn bipolar transistor can be used instead of the MISFET included in the gradation control unit 1 to provide a current driving driver.

(Second Embodiment)
FIGS. 2A and 2B are circuit diagrams showing the configuration of a gradation control output circuit (voltage drive driver) according to the second embodiment of the present invention, respectively, and the power supply potential in the power supply voltage supply line. It is a figure which shows the relationship with the distance from a power supply voltage supply part.

The voltage-driven gradation control output circuit of the present embodiment provides the gate-source voltages V _GS1 and V _GS of each second MISFET 2 and each third MISFET 3 by providing a slope to the potential of the gate bias supply line 15. _GS2 is made substantially constant.

As shown in FIG. 2A, the gradation control output circuit according to the second embodiment of the present invention is connected to the power supply voltage supply unit 12 and the power supply voltage supply unit 12 and has an output unit 16. , 1 _N ( _N is an integer), a first current supply unit 10 a connected to the ground for supplying a constant current, a first current supply unit 10 a and a power supply voltage supply A first MISFET 11, which is a P-channel MISFET having a drain and a gate electrode connected to each other, and a first MISFET 11 provided between the first MISFET 11 and the power supply voltage supply unit 12. 1 node 18, a second current supply unit 31 for supplying a constant current, a drain connected to the second current supply unit 31, and a P-channel type in which a drain and a gate electrode are connected to each other MIS transistor The oblique bias MISFET 30, the gate bias supply line 15 that connects the gate electrode of the first MISFET 11 and the gate electrode of the gradient bias MISFET 30, and the first node 18 and the source of the gradient bias MISFET 30 are connected to each other. a power supply voltage supply line 4 for supplying a power supply voltage to each gradation control unit 1 is provided on the power supply voltage supply line 4, the tone control unit 1a, 1b ..., the power supply voltage supply which is connected to the 1 _N A node 17 and a resistor 13 interposed between the power supply voltage supply nodes 17 and between the power supply voltage supply node 17 and the first node 18 are provided. Note that the gradation control output circuit of this embodiment is normally integrated in the same chip as in the first embodiment. Further, the gradation control output circuits according to the following embodiments are similarly integrated.

  The gradient bias MISFET 30 may be either a P-channel type or an N-channel type as long as it has the same conductivity type as the first MISFET 11.

  In the present embodiment, the gradation control unit 1 has the same configuration as that of the first embodiment.

  That is, as shown in FIG. 2 (a), the gradation control unit 1 includes both the P-channel type second MISFET 2a and the third MISFET 3a whose sources are connected to each other and to the power supply voltage supply node 17. The voltage selection switch 20a is connected to the (+) side of the input section, the operational amplifier 6a is connected to the output section 16 on the (−) side, the source is grounded, and the drain is connected to the third MISFET 3a. The output side transistor 5a, which is an N-channel MISFET whose gate electrode is connected to the output part of the operational amplifier 6a, and the output side transistor 5a and the third MISFET 3a are connected to the output part 16 The second node 14, the output section of the operational amplifier 6a and the gate electrode of the output side transistor, the output side transistor 5a and the second node And a oscillation preventing capacitor 19a provided between the wiring connecting between. The second MISFET 2a and the operational amplifier 6a constitute a differential circuit 7a, and the third MISFET 3a, the second node 14, the oscillation preventing capacitor 19a, and the output side transistor 5a constitute an output buffer unit 8a.

A feature of the gradation control output circuit of the present embodiment is that a second current supply unit 31 and a tilt bias MISFET 30 are provided. As a result, as described below, the gate-source voltages (V _GS1 and V _GS2 ) of the second MISFET 2 and the third MISFET 3 are prevented from decreasing due to the voltage drop of the power supply voltage supply node 17. .

Further, the tilt bias MISFET 30 is always on during the operation of the present apparatus. Therefore, the potential on the drain side of the tilt bias MISFET 30 is a potential obtained by dropping the potential of the power supply voltage supply unit 12 by at least the resistor 13. Since the drain and gate electrode of the gradient bias MISFET 30 are connected to each other, the potential of the gate electrode of the gradient bias MISFET 30 is lower than the potential of the gate electrode of the first MISFET 11. Therefore, as shown in FIG. 2B, a potential gradient is formed in the gate bias supply line 15 such that the potential decreases as the distance from the power supply voltage supply unit 12 increases. In the gradation control output circuit according to the present embodiment, the potential gradient in the gate bias supply line 15 is set so as to be substantially proportional to the voltage drop rate in the power supply voltage supply line 4. The gate-source voltages (V _GS1 and V _GS2 ) of the MISFET 2 and the third MISFET 3 can be made substantially constant.

Thereby, the value of the current I ₁ flowing through the second MISFET 2 can be made substantially constant regardless of the distance from the power supply voltage supply unit 12, and the slew rate of the operational amplifier 6 can be made almost constant. As a result, according to the gradation control output circuit of the present embodiment, a voltage signal having a uniform current value can be supplied to the TFTs and the pixels from the output sections 16 of all the gradation control sections 1. .

  Further, in the gradation control output circuit of this embodiment, the wiring for supplying the power supply voltage to the differential circuit 7 and the wiring for supplying the power supply voltage to the output buffer unit 8 are not separated. Since the area of the tilt bias MISFET 30 is very small compared to the area of the voltage supply line, the gradation control output circuit of this embodiment has a smaller area than the gradation control output circuit of the first embodiment. It has become. When a drive driver is used for a liquid crystal panel, it has multiple outputs (400 to 500 outputs) and is arranged at the edge of the panel. Therefore, a small area of the drive driver is important for downsizing the panel.

  In the gradation control output circuit of the present embodiment, the power supply voltages of the differential circuit 7 and the output buffer unit 8 are both supplied from the power supply voltage supply wiring 4, so that the resistance value of the resistor 13 varies. Regardless, the power supply voltages of substantially equal values are supplied to the differential circuit 7 and the output buffer unit 8 in one gradation control unit 1. This is also advantageous for keeping the slew rate of the operational amplifier constant.

  As described above, the slew rate of the operational amplifier 6 can be made substantially constant and the charging time to the load can be made constant by using the gradation control output circuit of the present embodiment. Display unevenness in the organic EL panel can be suppressed.

  In addition, since the gradation control output circuit of this embodiment can have a smaller area than the gradation control output circuit of the first embodiment, it is advantageous for integration and has a small liquid crystal size. It is also preferably used for panels.

  In the gradation control output circuit of the present embodiment, the current mirror circuit in the gradation control unit 1 is configured by a P-channel MISFET, but an N-channel MISFET may be used instead. In this case, both the first MISFET 11 and the gradient bias MISFET 30 may be N-channel MISFETs. The same applies to the output circuit for gradation control according to the following embodiments.

Also in the gradation control unit 1 of the present embodiment, the ratio of the current I ₁ : current I ₂ value is set to about 1: 5, but if I ₁ <I ₂ , the current value ratio is particularly high. There is no limit.

  In the gradation control output circuit according to the present embodiment, the second current supply unit 31 and the gradient bias MISFET 30 are provided to form a potential gradient on the gate bias supply line 15. A current supply unit independent of the power supply voltage supply unit 12 and a low voltage supply unit having a potential lower than the potential of the gate electrode of the first MISFET 11 may be provided.

  Although the gradation control output circuit has been described above, a current addition type D / A converter having a plurality of current mirrors is used in place of the gradation control unit 1 to perform gradation control by current. An output circuit for gradation control can be realized. Even in this case, since the gate-source voltages of the MISFETs constituting each D / A converter are equal to each other, the output current can be made constant. Such a gradation control output circuit can be used as a driver for an organic EL panel and an inorganic EL panel or a head of an LED printer. The current drive gradation control output circuit will be described in detail later.

(Third embodiment)
The gradation control output circuit according to the third embodiment of the present invention is a combination of the gradation control output circuit according to the first embodiment and the second embodiment.

  FIG. 3 is a circuit diagram showing a configuration of a voltage-driven gradation control output circuit according to the third embodiment of the present invention. The same elements and circuits as those in the first and second embodiments are denoted by the same reference numerals as those in FIGS.

As shown in FIG. 3, the output circuit for gradation control of the present embodiment is connected to the power supply voltage supply unit 12 and the power supply voltage supply unit 12, and includes a differential circuit 7, a voltage selection switch 20, an output buffer unit 8, and N gradation control units 1 each having an output unit 16, a first current supply unit 10a connected to the ground for supplying a constant current, a first current supply unit 10a, and a power supply voltage supply unit 12 A first MISFET 11 which is a P-channel MISFET having a drain and a gate electrode connected to each other, and a first MISFET 11 provided between the first MISFET 11 and the power supply voltage supply unit 12. The node 23 and the second node 24, the second current supply unit 31 for supplying a constant current, the source is connected to the second current supply unit 31, and the drain and the gate electrode are connected to each other P channel type M A slope bias MISFET 30 that is an S transistor, a gate bias supply line 15 that connects the gate electrode of the first MISFET 11 and the gate electrode of the slope bias MISFET 30, a second node 24, and the source of the slope bias MISFET 30 are connected to each other. A differential circuit voltage supply line 24a connected to each other, a second power supply voltage supply node 26 provided on the differential circuit voltage supply line 24a and connected to each differential circuit 7, and a second node 24 When the resistor 22 provided between and between the second power supply voltage supply node and the second power supply voltage supply node 26, an output which connects the first node 23 and N-th third MISFET 3 _N Section voltage supply line 23a, and first power supply voltage supply node 2 provided on output section voltage supply line 23a and connected to each output buffer section 8. When, and a first node 23 and the first resistor 21 provided between and between the first power supply voltage supply node 25 of the power voltage supply node 25. The configuration of the gradation control unit 1 is the same as that in the first embodiment.

  In the gradation control output circuit according to the present embodiment, the wiring for supplying the power supply voltage to the differential circuit 7 and the wiring for supplying the power supply voltage to the output buffer unit 8 are separated from each other. A drop in power supply voltage at the first power supply voltage supply node 25 and the second power supply voltage supply node 26 provided at a position far from the supply unit 12 can be suppressed.

In addition to this, a potential gradient is formed on the gate bias supply line 15 in the output circuit for gradation control of this embodiment. As a result, variations due to the positions of the gate-source voltages V _GS1 and V _GS2 of the second MISFET 2 and the third MISFET are suppressed.

  Therefore, in the gradation control output circuit of the present embodiment, the slew rate of the operational amplifier 6 can be made more accurate and constant regardless of the position of the gradation control unit 1 due to the synergistic effect of the two configurations described above. . For this reason, according to the output circuit for gradation control of the present embodiment, the current output from the output units 16 of all the gradation control units 1 can be made constant, and the charging time to the load is made constant. be able to. As a result, by using the gradation control output circuit of this embodiment, display unevenness that occurs in a liquid crystal panel and a voltage writing type organic EL panel can be suppressed.

(Fourth embodiment)
In the output circuit for gradation control of the first to third embodiments, the power supply voltage from the power supply voltage supply unit 12 is distributed to the second MISFET 2 through a common voltage supply line (hereinafter referred to as “voltage”). Each gate-source voltage V _GS1 is set to be substantially constant.

  On the other hand, the output circuit for gradation control according to the present embodiment is provided with a receiver-side current mirror circuit 43 on the side of the tilt bias MISFET 30 provided at a position far from the power supply voltage supply unit 12, and the first current supply unit 10a. Is distributed to the MISFET 30 side for the tilt bias by current distribution between the current mirrors. This is hereinafter referred to as a “current delivery method”.

  FIG. 4 is a circuit diagram showing a configuration of the gradation control output circuit of the present embodiment. The same elements and circuits as those in the third embodiment are denoted by the same reference numerals as those in FIG.

As shown in the figure, the gradation control output circuit of this embodiment is connected to a power supply voltage supply unit 12 and a power supply voltage supply unit 12, and includes a differential circuit 7, a voltage selection switch 20, an output buffer unit 8, and The N gradation control units 1 having the output unit 16, the first current supply unit 10 a connected to the ground, and the first current supply unit 10 a and the power supply voltage supply unit 12 are sequentially interposed. The first MISFET 11 which is a P-channel MISFET in which the drain and the gate electrode are connected to each other, and the first node 23 and the second node 24 provided between the first MISFET 11 and the power supply voltage supply unit. And a receiver-side current mirror circuit 4 composed of a first mirror MISFET 43a and a second mirror MISFET 43b, both of which are N-channel MISFETs and whose gate electrodes are connected to each other. The drain is connected to the first mirror MISFET 43a, the gate electrode is connected to the gate electrode of the first MISFET 11, the source is connected to the power supply voltage supply unit 12, and the P-channel constituting the sender side current mirror together with the first MISFET 11 Type MISFET 41, a gradient bias MISFET 30 which is a P-channel MIS transistor having a source connected to the second N-channel MISFET 43b and a drain and a gate electrode connected to each other, and a gate of the first MISFET 11 A gate bias supply line 15 connecting the electrode and the gate electrode of the gradient bias MISFET 30, a voltage supply line 24a for the differential circuit connecting the second node 24 and the source of the gradient bias MISFET 30, and for the differential circuit Provided on the voltage supply line 24a Provided between the second power supply voltage supply node 26 connected to each differential circuit 7, between the second node 24 and the second power supply voltage supply node 26, and between each second power supply voltage supply node. a resistor 22, a first node 23 and N-th third output unit for the voltage supply line 23a for connecting the MISFET 3 _N, and provided at an output unit for the voltage supply line on 23a, to the output buffer section 8 The connected first power supply voltage supply node 25, and the resistor 21 provided between the first power supply voltage supply node 25 and between the first power supply voltage supply node 25 and the first power supply voltage supply node 25. I have. The configuration of the gradation control unit 1 is the same as that of the third embodiment.

  The gradation control output circuit of the present embodiment is supplied from the receiver side current mirror circuit 43 and the first current supply unit 10a as the second current supply unit 31 of the third gradation control output circuit. A fourth MISFET 41 for distributing current is provided.

  Here, the first MISFET 11 and the fourth MISFET 41 constituting the current mirror have the same element configuration and electrical characteristics, and the first mirror MISFET 43a and the second mirror MISFET 43b are also the same element. It has configuration and electrical characteristics. In addition, in the output circuit for gradation control according to the present embodiment, each of the first MISFET 11, the fourth MISFET 41, the first mirror MISFET 43a, and the second mirror MISFET 43b operates in the saturation region, and thus the first current. The current supplied from the supply unit 10a is equal to the current flowing through the second mirror MISFET 43b with high accuracy.

  In addition, since it is possible to supply a constant current to a circuit at a distance by one bias circuit, an increase in circuit area can be avoided.

  In addition, according to the current delivery method, the current can be distributed without being affected by the voltage drop due to the resistor, so that it is provided at a position far from the power supply voltage supply unit 12 (position several mm away). The power supply voltage supplied to the second MISFET 2 (or the differential circuit 7) and the power supply voltage supplied to the second MISFET provided close to the power supply voltage supply unit 12 can be accurately aligned. become.

As a result, in the gradation control output circuit of the present embodiment, the gate-source voltage V _GS1 of the second MISFET 2 is substantially constant regardless of the distance from the power supply voltage supply unit 12. The slew rate can also be made almost constant. That is, by using the gradation control output circuit of this embodiment, display unevenness that occurs in a liquid crystal panel and a voltage writing type organic EL panel can be suppressed.

  In the present embodiment, an example in which the voltage distribution method and the current transfer method are combined has been described. However, a current mirror circuit is provided between each gradation control unit 1 and current is distributed to all the second MISFETs 2 by the current transfer method. You can also In this case, since the area increases, the power supply voltage is actually distributed to the second MISFET 2 relatively close to the power supply voltage supply unit 12 by the voltage distribution method, and the second MISFET 2 relatively distant from the power supply voltage supply unit 12 It is preferable to distribute the current to the MISFET 2 by a current delivery method.

(Fifth embodiment)
As a fifth embodiment of the present invention, an example in which the configuration of the voltage driving gradation control output circuit described in the first to fourth embodiments is applied to a current driving gradation control output circuit will be described. .

  FIG. 5 is a diagram showing a configuration of a gradation control output circuit (current driving driver) according to the fifth embodiment of the present invention, and FIG. 6 is a detailed diagram of the gradation control circuit 51 shown in FIG. It is a figure which shows a structure.

  As shown in FIG. 5, the output circuit for gradation control of this embodiment is connected to the power supply voltage supply unit 12 and the power supply voltage supply unit 12 and has N levels that function as a current addition type D / A converter. The adjustment control circuit 51, the first current supply unit 10a connected to the ground, and the drain and gate electrode interposed between the first current supply unit 10a and the power supply voltage supply unit 12 are connected to each other. The first MISFET 11, which is a P-channel MISFET, and the first node 18 provided between the first MISFET 11 and the power supply voltage supply unit 12 are both N-channel MISFETs, and their gate electrodes are connected to each other. Receiver-side current mirror circuit 43 including the first mirror MISFET 43a and the second mirror MISFET 43b, and the drain of the first mirror MISFET 43a. A P-channel fourth MISFET 41 having a gate electrode connected to the gate electrode of the first MISFET 11 and a source connected to the power supply voltage supply unit 12 and constituting a sender-side current mirror together with the first MISFET 11; A gradient bias MISFET 30 which is a P-channel MIS transistor connected to the second N-channel MISFET 43b and having a drain and a gate electrode connected to each other; a gate electrode of the first MISFET 11; and a gate electrode of the gradient bias MISFET 30; Are connected to each of the gradation control circuits 51, the gate bias supply line 15 for connecting the power supply voltage, the power supply voltage supply wiring 4 for supplying the power supply voltage to each gradation control circuit 51, and the power supply voltage supply wiring 4. Power supply voltage supply node 17 and each power supply voltage supply node And between the power voltage supply node 17 of the 17 and and a resistor 13 which is interposed between the first node 18.

  As shown in FIG. 6, the gradation control circuit 51 includes a plurality of current mirror units 52 for current addition, the sources of which are connected to the power supply voltage supply node 17 and connected in parallel to each other, and each current addition unit. The selection switch 53 is provided on the drain side of the current mirror unit 52 and the output side is connected to each other, and the output unit 54 is connected to the output side of the selection switch 53 and supplies an output current. .

The current adding current mirror 52 is composed of P-channel MISFETs connected in parallel to each other, and in the case of 6-bit gradation (64 gradations), 1, 2, 4, 8, It is composed of 16,32 P-channel type MISFETs. The selection switch 53 includes a transfer gate unit 49 including an N channel MISFET and a P channel MISFET, and an inverter 50 whose output side is connected to the N channel MISFET. Each selection switch 53 is sequentially controlled to be turned on / off by digital data L ₀ , L ₁ ,..., L ₅ . Since the MISFETs constituting the current adding current mirror unit 52 have the same electrical characteristics, each P-channel MISFET of the current adding current mirror unit 52 is turned on when the selection switch 53 is on. Are equal to each other.

  With this configuration, in the gradation control output circuit according to the present embodiment, it is possible to supply 64 different currents from the output unit 54. In addition, as described in the fourth embodiment, the variation in the amount of current output from the output unit 54 is suppressed between the gradation control circuits 51 of the gradation control output circuit of the present embodiment. By using the output circuit for gradation control of the present embodiment, gradation control of a panel using current-driven light emitting elements such as organic EL, inorganic EL, and LED can be realized, and display unevenness can be suppressed. . In addition, by using the output circuit for gradation control of the present embodiment for a printer head using these light emitting elements, a printer with less printing unevenness can be realized.

  Further, in the gradation control output circuit of the present embodiment, it is not necessary to provide an operational amplifier that requires a relatively large area. Therefore, a current-driven gradation control output circuit using an operational amplifier or a voltage drive is used. The chip size can be reduced as compared with the grayscale control output circuit.

In the above description, an example of an output circuit for gradation control that realizes 64 gradations is shown. However, in order to realize gradation display of n bits (M gradations; M = 2 ⁿ ), 1 and A current adding current mirror unit 52 having 2,..., M / 2 MISFETs may be provided in one gradation control circuit 51. Here, M is a positive even number. For example, by providing a current addition unit 52 having 64 P-channel MISFETs in the gradation control circuit 51 of the present embodiment, 128 gradations can be obtained. Gray scale display is possible.

  In the present embodiment, gradation display is realized by the number of MISFETs of the current mirror unit 52 for current addition. However, one MISFET is provided per bit number, and their gate width (W) / gate length. The value of (L) may be 1, 2, 4,. However, the accuracy of the output current is higher when gradation control is performed according to the number of MISFETs.

  As described above, in the gradation control output circuit of this embodiment, a current addition type D / A converter is used instead of the gradation control unit 1 of the gradation control output circuit described in the first to fourth embodiments. By providing, an organic EL panel with little luminance unevenness can be realized.

  In the gradation control output circuit of this embodiment, an N-channel MISFET may be used as the MISFET constituting the current adding current mirror unit 52.

  Note that when the gradation control output circuit of this embodiment includes the gradation control unit 1 used in the second embodiment instead of the gradation control circuit 51, the voltage drive used for a liquid crystal panel or the like. It becomes a driver for.

(Sixth embodiment)
The gradation control output circuit according to the sixth embodiment of the present invention is a current drive driver having the following four characteristics.

  First, the first feature is that variation between output currents is reduced by providing a multi-stage current mirror section.

  Next, the second feature is that means for correcting the difference between the luminance control given to the display device and the luminance characteristic actually displayed is provided.

  A third feature is that a selection precharge circuit (not shown) and a selection precharge control circuit 62 for assisting charging of parasitic capacitance generated in the signal line on the display device are provided.

  Next, the fourth feature is that a current raising control circuit 61 for raising the output current is provided.

  FIG. 9 is a block circuit diagram showing a configuration of a current drive type display device using the gradation control output circuit according to the sixth embodiment of the present invention.

  As shown in the figure, the gradation control output circuit of the present embodiment has a low-side current output section, and controls the low-side gradation control for controlling 1 to 4, 8 and 16 gradations. A circuit 59, a low-side current mirror unit 55 for supplying a reference voltage Vst1 to the low-side gradation control circuit 59, and a high-side current output unit; A high-side gradation control circuit 60 for controlling, a current raising control circuit 61 connected to the output unit 64, and a reference voltage Vst2 for supplying the high-side gradation controlling circuit 60 and the current raising control circuit 61, respectively. A high-side current mirror unit 56 and a selective precharge control circuit 62 connected to a source signal line 58 on the display side are provided.

  Although shown in a simplified manner in FIG. 9, the low-side current mirror unit 55 and the high-side current mirror unit 56 both have a three-stage configuration and each have 176 outputs. The first stage of the low-side current mirror unit 55 and the first stage (parent current source) of the high-side current mirror unit 56 are connected to external resistors 63a and 63b, respectively.

  Further, the output unit 64 supplies a current obtained by adding the output current from the current raising control circuit 61 to the output current from the low-side current output unit and the low-side current output unit to the display panel side.

  The characteristics of the gradation control output circuit of this embodiment will be described below. However, the raising circuit will be described in a later embodiment.

-Multi-stage current mirror section-
In order to maintain the constant current characteristics of the current mirror circuit, it is necessary to limit the number of mirror transistors connected to the common voltage supply line (voltage distribution method). This is because as the number of mirror transistors increases, as described above, the influence of the voltage drop in the voltage supply line increases.

  On the other hand, the current drive gradation control output circuit has many outputs in the same manner as the voltage drive gradation control output circuit, and the number of outputs of the gradation control output circuit of this embodiment is as follows. , 176 outputs per color for R (red), G (green), and B (blue), for a total of 528 outputs. If the power supply voltage is supplied from the common voltage supply line to the current mirror corresponding to the 176 outputs, there is a possibility that variations between the output currents occur. Therefore, a current delivery method for connecting current mirrors is used. However, if the number of current distributions is increased, current consumption increases, so there is a trade-off with product performance. For this reason, the inventors of the present application employ a current mirror system in combination with a voltage distribution system and adopt a multi-stage structure of current mirror portions.

  FIG. 7 is a diagram showing a multi-stage current mirror unit when the current source is a three-stage type.

  As shown in the figure, the current value of the first stage current mirror (parent current source 55a) is copied to 16 second stage current mirrors (child current source 55b) by the current mirror circuit. Further, the current value of the child current source 55b is also copied to the eleven third stage current mirrors (grandchild current source 55c) by the current mirror circuit. In this way, currents of equal magnitude are distributed to the MISFETs constituting the current mirror at each stage. With the above configuration, the current value of the parent current source 55a is transmitted to 16 × 11 = 176 grandchild current sources 55c. According to the configuration of the current mirror unit, the variation in the output current value from the grand current source 55c can be made smaller than when the current value of the parent current source 55a is directly transmitted to the 176 grand current sources 55c. . Therefore, when the multistage current mirror unit is used for an organic EL display or the like, display unevenness can be reduced.

  The gradation control output circuit according to the present embodiment includes the above-described three-stage multi-stage current mirror unit. Therefore, variations in the reference voltages Vst1 and Vst2 input to the low-side gradation control circuits 59 are small. It has become. Therefore, variation in output current from each low-side current output unit and high-side current output is also reduced.

  Note that the number of stages of the current mirror unit may be three or more, and the number of outputs of the current mirror unit may be changed to an appropriate number.

-Efforts for gamma correction-
The luminance of the light emitting element used for the display does not increase in direct proportion to the applied current. The increase rate of current with respect to luminance is larger when the applied current is larger than when the applied current is small. This is called a γ characteristic and is a characteristic that can be seen even in the case of liquid crystals.

  FIG. 8 is a diagram showing the gradation level-output current characteristics of the current output from the current drive gradation control output circuit.

  In the output circuit for gradation control for current driving, since the gradation is controlled by a combination of unit current sources using a current mirror, when there is one current mirror unit for gradation control, gradation level versus output current The graph becomes a straight line. For this reason, the luminance of the light emitting element on the panel may deviate from the setting.

  In order to solve this problem, the inventors of the present application divide the current mirror portion and the gradation control circuit of the gradation control output circuit used in the display device into two, the low side and the high side, and output current When the output current is small, current is output only from the low-side current output unit, and when the output current is large, the current from the high-side current output unit is added to the current from the low-side current output.

  In the gradation control output circuit of the present embodiment, the output current from the low-side gradation control circuit 59 that can independently control 1 to 16 gradations is always output from the output unit 64, 4, 8, 16, The output current from the high-side gradation control circuit 60 capable of controlling 32 and 64 gradations is output from the output unit 64 only when gradation control exceeding 16 gradations is performed.

  As a result, the characteristics of the output current are approximated to the γ characteristics of the light emitting element as indicated by arrows in FIG. In the example of this embodiment, the gradient of the gradation level-output current characteristic graph is 10 nA / gradation at 16 gradations or less, and 40 nA / gradation from 16 to 64 gradations.

  Here, on / off of the switch circuits in the low-side gradation control circuit 59 and the high-side gradation control circuit 60 is performed by the data conversion circuit, the γ correction control signals G0 to G1 applied via the two-stage latch, and the image. It is controlled by data D0 to D5.

  Thereby, when the output circuit for gradation control of this embodiment is used for an organic EL panel or the like, gradation control as set can be performed.

  The gradation control output circuit of the present embodiment in which such a countermeasure for γ correction is taken is used in a display device using not only an organic EL but also a light emitting element such as an inorganic EL or LED. It can also be used in printer heads using these light emitting elements.

  Note that FIG. 9 shows an example of a gradation control output circuit for current driving of only one color. However, in a light emitting element such as an organic EL, an inorganic EL, and an LED, γ is used for each of R, G, and B colors. Since the characteristics are different, it is preferable to provide a multistage current mirror section having different output characteristics for the output of each color of R, G, and B.

  In the output circuit for gradation control according to the present embodiment, the gradation-output current characteristic is approximated to the γ characteristic by combining current mirror portions having different linear characteristics, but three or more sets of multistage current mirrors are used. By combining the unit and the gradation control circuit, a more accurate approximation is realized.

-Selective precharge control circuit-
As shown in FIG. 24, in the organic EL panel, a large number of P-channel TFTs made of, for example, low-temperature polysilicon are arranged. In this panel, if the current I ₀ drawn from the panel to the gradation control output circuit side is increased, a large current flows through the TFT and the organic EL element, so that the luminance of the organic EL element increases. At this time, white is displayed.

  Conversely, when the drain voltage of the TFT is increased, the current is reduced, so that black is displayed on the panel. At this time, in order to increase the drain voltage, it is necessary to raise the potential of the source signal line 58 to the vicinity of the potential of the panel.

  However, the signal lines of the panel have a large parasitic capacitance, and it is necessary to charge this parasitic capacitance when displaying black. However, the mobility of the low-temperature polysilicon is an order of magnitude lower than that of the silicon crystal, and the current capability is small, so that prompt black display is difficult.

  In order to improve current capability, the W / L ratio of the TFT may be increased. However, since the TFT in the pixel is arranged on the display pixel, if the W / L ratio is increased, the aperture ratio of the display is increased. The malfunction that it will fall arises.

  In order to solve this problem, the inventors of the present application have studied and precharged from the drive circuit side. That is, a selective precharge circuit and a selective precharge control circuit for charging the parasitic capacitance of the source signal line 58 for a certain period and supplementing the current capability of the low-temperature polysilicon are provided in the gradation control output circuit.

  FIG. 10 is a circuit diagram showing an example of the selective precharge circuit and the selective precharge control circuit in the gradation control output circuit of this embodiment.

  As shown in the figure, the selective precharge circuit 62a in this embodiment has a transfer gate 70 composed of an N-channel MISFET 70a and a P-channel MISFET 70b, and an output portion connected to the gate electrode of the N-channel MISFET 70a. , And an inverter 71 connected to the gate electrode of the P-channel type MISFET 70b. The source of the transfer gate 70 is connected to the power supply voltage supply unit for supplying the power supply voltage PV, and the drain is connected to the output unit of the gradation control circuit via the current output node 77.

  The selection precharge control circuit 62 includes, for example, a NOR circuit 74, an OR circuit 75, and a NAND circuit 76 that outputs a signal for controlling the selection precharge circuit 62a. The selective precharge circuit and the selective precharge control circuit are integrated on a chip as a part of the gradation control output circuit.

  The selection precharge circuit 62a in the present embodiment is timing-controlled, and outputs a voltage corresponding to the black level only for a fixed period at the beginning of one horizontal period when the image data is close to the black level, for example, 0-7. Then, the selection precharge control circuit 62 controls. Thereby, when the image data is close to the black level, the parasitic capacitance of the source signal line 58 is charged in advance, and the quality of black display can be improved.

  During other periods, the transfer gate 70 is controlled to be off, so that the parasitic capacitance is not charged.

  In addition, when the selective precharge control circuit 62 and the selective precharge circuit 62a are used, the precharge period can be selectively controlled when image data close to the black level is input, so that the parasitic capacitance is relatively relatively large. It is possible to suppress wasteful power consumption in a small panel.

  Note that the gradation control output circuit including the selective precharge control circuit 62 and the selective precharge circuit 62a is preferably used for controlling a panel having TFTs using amorphous silicon.

  The above functions of the selective precharge control circuit 62 and the selective precharge circuit 62a are exhibited regardless of the presence / absence of the low-side current mirror unit 55 and the high-side current mirror unit 56 and the presence / absence of γ correction means. . The selective precharge control circuit 62 and the selective precharge circuit 62a are also effective for a display device using light emitting elements other than the organic EL.

  Note that the gradation control output circuit of this embodiment does not include the current raising control circuit 61, the selective precharge control circuit 62, and the selective precharge circuit 62 a, but displays compared to the conventional gradation control output circuit. Although display unevenness of the apparatus can be suppressed, image display with higher accuracy can be achieved when these circuits are provided.

(Seventh embodiment)
As a seventh embodiment of the present invention, a gradation control output circuit (current drive driver) having the same circuit configuration as the gradation control output circuit according to the sixth embodiment and an improved layout is provided. explain.

  FIG. 11 is a diagram showing a reference example of the layout of the gradation control output circuit according to the sixth embodiment of the present invention, and FIG. 12 is a gradation control output according to the seventh embodiment of the present invention. It is a figure which shows the layout of a circuit. 11 and 12 show layouts using two-layer wiring.

  A drive driver for a display device usually has a width of several millimeters. However, in order to reduce the size of the edge of the panel and reduce the panel size, it is important to reduce the area of the circuit. Therefore, the inventors of the present application studied improvement in the layout of the gradation control output circuit of the sixth embodiment.

  In the gradation control output circuits shown in FIGS. 11 and 12, the child (second stage) current source LCCS of the low-side current mirror unit and the child current source HCCS of the high-side current mirror unit form one set, which is R (Red), G (Green), and B (Blue) are arranged in a horizontal row for 16 pieces in this order. Then, 11 wires each extend from the child current sources LCCS of the low-side current mirror section toward the low-side current output circuit LDRV, and 11 wires from the child current sources HCCS of the high-side current mirror portion respectively. The wiring extends toward the high-side current output circuit HDRV. Furthermore, wiring extends from both the low-side current output circuit LDRV and the high-side current output circuit HDRV toward the output control circuit OCTL.

  Here, the low-side current output circuit LDRV includes the grandchild current source of the low-side current mirror unit 55 shown in FIG. 9 and the low-side gradation control circuit 59. The high-side current output circuit HDRV includes The grand current source of the high-side current mirror unit 56 and the high-side gradation control circuit 60 are included. The output control circuit OCTL includes an output unit 64, a selective precharge control circuit 62, and the like.

  As shown in FIG. 11, in the reference example of the layout, the low-side current output circuit LDRV, the high-side current output circuit HDRV, and the output control circuit OCTL are R, G, B, R, G, B,. Are arranged in the order. According to this layout, there is a relatively short wiring, as shown by the thick line on the right side in FIG. Moreover, it turns out that the intersection of wiring increases and wiring is complicated.

  On the other hand, as shown in FIG. 12, in the layout of the present embodiment, the current connected to one set of the child current source LCCS of the R-side current mirror unit and the child current source HCCS of the high-side current mirror unit. The output circuit and the output control circuit are arranged together. The low-side current output circuit LDRV, the high-side current output circuit HDRV, and the output control circuit OCTL are arranged in a matrix, the first row is the low-side current output circuit LDRV, the second row is the high-side current output circuit HDRV, and The third row is the output control circuit OCTL.

  With such a layout, it is possible to eliminate extremely long wires as seen in the reference example shown in FIG. 11, and to reduce the intersection of the wires. For this reason, it is possible to reduce the wiring area from the current mirror unit to the output control unit.

  FIG. 12 shows only for R, but the arrangement in which only for G and only for B are sequentially arranged to the side of the region shown in FIG.

  FIG. 13 is a wiring diagram showing an output wiring region of the output circuit for gradation control of this embodiment.

  As shown in the figure, when the layout of this embodiment is applied, the wiring routing from the current mirror unit to the output control unit is reduced, whereas the output unit (IOUT1 to 11) of the output control circuit OCTL is used. The wiring route to the output terminal to the display panel is longer than that in the above-described reference example.

  However, in the output circuit for gradation control of this embodiment, the current mirror unit and the output control unit have a 2: 1 correspondence, whereas the output control unit and the output terminal to the display panel are 1: Therefore, simplification of the wiring from the current mirror unit to the output control unit is effective in reducing the area of the wiring region.

  Therefore, when three or more current output circuits are provided for γ correction, according to the layout of the gradation control output circuit of the present embodiment, the wiring region is more effectively compared with the layout of the reference example. The area can be reduced.

  In this embodiment, an example has been described in which 176 outputs per parent current source and 176 × 3 = 528 outputs including R, G, and B per chip are combined, but the layout of this embodiment is The present invention can also be applied to a gradation control output circuit having a different number of outputs.

  In addition, when the gradation control output circuit is used as a head of a color printer, there are cases where driven pixels become four or more colors. In this case as well, if the layout of this embodiment is used, the wiring area is reduced. A significant increase can be prevented.

(Eighth embodiment)
As an eighth embodiment of the present invention, an example in which the layout of the gradation control circuit 51 described in the fifth embodiment is improved will be described. This layout is also applied to the low-side gradation control circuit 59 and the high-side gradation control circuit in the sixth embodiment.

  FIGS. 14A and 14B are a circuit diagram showing the configuration of the gradation control circuit, and a diagram schematically showing a reference example of the layout of the gradation control circuit.

  As shown in FIG. 14 (a), the gradation control circuit 51 shown in FIG. 6 is connected to a plurality of current mirror units 52 composed of P-channel type MISFETs having the same element configuration, and to each current mirror unit 52. The current mirror unit 52 and the same number of selection switches 53 are configured. Each selection switch 53 includes a transfer gate 49 including a P-channel type MISFET and an N-channel type MISFET, and an inverter 50. The outputs from all the selection switches 53 are directed to the common output unit IOUT through the output wiring.

  Since the output current from all the selection switches 53 is collected in this output wiring, lowering the impedance of this output wiring is important for increasing the accuracy of the output current.

  Further, as shown in FIG. 14B, a reference example of the layout of the gradation control circuit 51 is gathered for each part of the current mirror unit 52 (CM), the transfer gate 49 (TG), and the inverter 50 (IN). Is to be placed. According to this layout, there is an advantage that a mask can be easily manufactured in an impurity diffusion process or an etching process of a semiconductor chip in which the gradation control circuit 51 is integrated.

  However, according to the layout of this reference example, as can be seen from FIG. 14 (b), the wirings are redundant in order to group elements at distant positions in the circuit diagram. Since the width of the current driving driver used in the panel is about several millimeters, the width of the output wiring becomes narrow due to the presence of redundant wiring in the opposite direction to the output wiring, and the output impedance of the gradation control circuit 51 becomes large. End up.

  Therefore, the inventors of the present application tried to improve the circuit arrangement.

  15A is a circuit diagram showing the configuration of the gradation control circuit (the same as FIG. 14A), and FIG. 15B is a diagram schematically showing a reference example of the layout of the gradation control circuit. (Same as FIG. 14B) and FIG. 14C are diagrams schematically showing a layout of the gradation control circuit according to the present embodiment.

  As shown in FIG. 15C, the layout of the gradation control circuit of the present embodiment is such that the current mirror unit 52, the transfer gate 49 and the inverter 50 connected to the current mirror unit 52 are arranged together, and this is arranged according to the circuit configuration. They are arranged in a row. That is, if a group of the current mirror unit 52 and the transfer gate 49 and the inverter 50 connected to the current mirror unit 52 is called a “gradation generation unit”, the number of bit generation units is arranged in a line. Yes.

  According to the layout of the gradation control circuit of the present embodiment, since the elements are arranged according to the circuit configuration, redundant wiring as shown in FIG. 15B does not occur. As a result, the width of the output wiring of the gradation control circuit can be widened to reduce the output impedance of the gradation control circuit.

  Further, since redundant wiring can be eliminated, the wiring area can be reduced, so that the area of the chip on which the gradation control circuit is integrated can be greatly reduced.

  The layout of the gradation control circuit according to the present embodiment can also be applied to a gradation control circuit that performs gradation control by changing the value of the gate width / gate length of the MISFET.

(Ninth embodiment)
-Current raising circuit-
As a method for improving display characteristics in a current-driven panel using a light emitting element, there is contrast adjustment for changing the entire luminance.

  A circuit for realizing the contrast adjustment is a current raising control circuit. This is a circuit for receiving the raising signals K0 to K1 and outputting a current for raising the output currents from the high-side gradation control circuit 60 and the low-side gradation control circuit 59.

  For example, in the gradation control output circuit according to the sixth embodiment, the raising current from the current raising control circuit is input to the output unit 64 of the gradation control circuit. In this case, when all gradations are controlled, the current output from the output unit 64 is raised.

  However, since it is necessary to raise the output current for all the outputs of the gradation control circuit, the current raising control circuit 61 shown in FIG. 9 is connected to the high-side current mirror unit 56 shared with the high-side gradation control circuit 60. It was either connected or connected to a separately provided current mirror portion 65 for raising circuit.

  FIGS. 16A and 16B are diagrams showing the current value-gradation level characteristics of the output circuit for gradation control shown in FIG. 16B, respectively, and the case where the current mirror unit 65 for raising circuit is provided. It is a block circuit diagram showing an example of an output circuit for gradation control.

  In the gradation control output circuits shown in FIGS. 9 and 16, the current raising control circuit 61 is effective, but the area of the wiring and the current mirror portion is increased.

-Output circuit for gradation control of this embodiment-
FIG. 17 is a diagram showing a current raising control circuit in the gradation control output circuit of the present embodiment.

  Note that the gradation control output circuit of this embodiment is used for a current driving driver of a display device, a printer head, and the like.

  The gradation control output circuit of the present embodiment includes a low-side gradation control circuit 59 connected to the output unit 64 and a low-side current mirror unit 55 for supplying the reference voltage Vst1 to the low-side gradation control circuit 59. A current raising control circuit 66 provided between the low-side current mirror unit 55 and the low-side gradation control circuit 59, a high-side gradation control circuit 60 connected to the low-side output unit 64, and a high side A high-side current mirror unit 56 for supplying a reference voltage Vst2 to the gradation control circuit 60 and a selection precharge control circuit 62 connected to a source signal line 58 on the display side are provided.

  As shown in FIG. 17, the current raising control circuit 66 includes a current mirror section having one and two current mirrors, and a switch circuit that determines on / off according to the raising signals K0 and K1. Yes.

  Since the current raising control circuit 66 has a configuration similar to that of the low-side gradation control circuit 59, it is easy to manufacture and it is not necessary to newly provide a current mirror section. For this reason, the area for the output circuit for gradation control according to the present embodiment can be greatly reduced as compared with the output circuit for gradation control shown in FIGS. 9 and 16B.

  Note that the current raising control circuit 66 in this embodiment only raises the output current of the low-side gradation control circuit 59. However, since the output current of the low-side gradation control circuit 59 is always output from the output unit 64, there is no problem due to this. In addition, it is more important to increase the current for controlling the lower gradation than the high gradation.

  As described above, according to the gradation control output circuit of this embodiment, it is possible to easily realize contrast adjustment by the current raising control circuit while suppressing an increase in area.

(Tenth embodiment)
As a tenth embodiment of the present invention, an inspection apparatus for the gradation control output circuit (current driving driver) described in the above embodiments will be described.

  The current per gradation of the gradation control output circuit used in the current driving method is 10 nA to 20 nA, and the current value to be detected at the time of inspection is the same. Therefore, it is necessary to transmit a minute inspection current output from the gradation control output circuit to the semiconductor tester 79 without being attenuated.

  In order to solve this problem, the inventors of the present application have considered converting a detection current, which is a minute current, into a voltage and transmitting it.

  FIGS. 18A and 18B are a cross-sectional view showing a probe card according to a tenth embodiment of the present invention for inspecting a current-driven gradation control output circuit, and a cross-section of the probe card, respectively. FIG.

  As shown in FIGS. 18A and 18B, the probe card of the present embodiment has a substrate 78 whose upper surface can be set on the semiconductor tester 79, and a probe 83 made of a conductor provided on the lower surface of the substrate 78. A high-precision resistor 88 disposed on the substrate 78 within about 10 cm from the root of the probe 83 and connected to the probe 83, and a wiring provided through the substrate 78 and connected to the resistor 88. It has.

  On the wafer 82 to be inspected, for example, inspection pads 87 (or bumps) and an internal circuit (not shown) connected to the pads 87 are provided.

  The semiconductor tester 79 has a comparator for comparing the inspection signal output from the wafer 82 to be inspected with a reference voltage.

  Next, an inspection procedure using the probe card of this embodiment will be briefly described.

  First, at the time of inspection, the probe card 78 is set on the semiconductor tester 79 and the probe 83 is brought into contact with the pad 87 of the wafer 82 to be inspected. In this state, a predetermined current is input from the probe 83 to the pad 87 on the wafer 82 to be inspected.

  Next, a current signal corresponding to the input current is transmitted from the pad 87 to the probe 83. At this time, as shown in FIG. 18B, the current signal from the wafer 82 to be inspected is converted into a voltage signal by the resistor 80 arranged in the immediate vicinity of the probe 83. This voltage signal is transmitted to the semiconductor tester 79 via the wiring 86 of the probe card 78, the connection wiring 85, a jig (not shown), and the like.

  Next, the voltage signal input to the semiconductor tester 79 is input to the negative input portion of the comparator and compared with a predetermined reference voltage. At this time, if the difference between the voltage signal and the reference voltage is within a certain range, the product is determined to be “pass”.

  In general, a voltage signal is less likely to attenuate in the transmission path than a current signal. Therefore, in the probe card of the present embodiment, the current signal from the wafer to be inspected 82 is converted into a voltage signal by the resistor 80, so that the signal from the wafer to be inspected can be reliably transmitted to the semiconductor tester 79. it can. However, in the probe card of this embodiment, since the signal path passing through the resistor 80 has a large impedance, it is desirable to take a shield measure so as not to be affected by disturbance noise.

  In the probe card of this embodiment, the distance between the probe 83 and the resistor 80 is preferably about 10 cm or less. This is because if the distance between the probe 83 and the resistor 80 becomes too large, the current signal may be attenuated before reaching the resistor 80.

  The probe card shown here is of a type that inspects the wafer for each chip, but even a wafer burn-in probe card is provided with a high-precision resistor in the immediate vicinity of the probe. It is possible to inspect a wafer having an output circuit for adjustment control.

  In addition, the wafer to be inspected is not limited to the one having the gradation control output circuit, and any wafer provided with a circuit having a function of outputting a minute current should be inspected by the same probe card of this embodiment. Can do.

  Note that an integrated resistor 88 may be used as the resistor 88 disposed in the probe card of the present embodiment.

(Eleventh embodiment)
In the inspection using the probe card according to the tenth embodiment, when the voltage range to be detected changes greatly, the voltage value of the voltage signal may be outside the detection range of the comparator of the semiconductor tester 79. In order to avoid this, the inventors of the present application studied to further improve the structure of the probe card.

  FIG. 19 is a block circuit diagram showing a cross section of a probe card according to the eleventh embodiment of the present invention.

  In the probe card of the present embodiment, the resistance value is set with high accuracy that is disposed in the immediate vicinity of the probe 83 among the substrate 78, the probe 83 provided on the lower surface of the substrate 78, and the lower surface of the substrate 78. A resistor 80 and a comparator 81 provided on the lower surface of the substrate 78, with one end of the resistor 80 connected to the output portion and the other end of the resistor 80 connected to the negative input portion, and the substrate 78 are passed through. And provided wiring (not shown). Further, a reference voltage signal is supplied from the semiconductor tester 79 to the positive side input portion of the comparator 81 at the time of inspection. Here, an operational amplifier having a high input impedance is preferably used.

  The probe card of the present embodiment includes an operational amplifier 81 that is negatively fed back by a resistor 80 and that has a reference voltage signal input to a positive input portion. Since the gain (output voltage) / (input voltage) of the voltage input to the positive side input portion of the operational amplifier 81 that has been negatively fed back is determined by the feedback factor of the resistor 80, it depends on the magnitude of the input signal voltage. By changing the reference voltage signal, the signal voltage range can be within the measurable range of the comparator of the semiconductor tester 79. Specifically, when the signal current from the wafer 82 to be inspected is small, a low-voltage reference voltage signal is input to the positive input portion of the operational amplifier 81, and when the signal current is large, the high-voltage reference voltage signal is input to the operational amplifier. 81 is input to the positive side input unit. As the operational amplifier 81, one having a sufficiently high input impedance is used.

  As described above, in the probe card of this embodiment, the range of the signal voltage to be detected can be controlled by changing the reference voltage signal according to the magnitude of the signal current from the wafer 82 to be inspected. This makes it possible to perform inspection more easily and accurately.

  Note that the operational amplifier 81 provided on the probe card of the present embodiment has a problem in size, and therefore, it is preferable to use one integrated on the chip.

(Twelfth embodiment)
A twelfth embodiment of the present invention will be described in which a resistor for converting a current signal into a voltage signal is provided on a chip on which a gradation control output circuit is mounted.

  20A and 20B are a circuit diagram showing the semiconductor chip of the present embodiment at the normal time and a circuit diagram showing the semiconductor chip of the present embodiment at the time of inspection, respectively. Here, the normal time indicates a time including normal operation and power-off.

  As shown in FIGS. 4A and 4B, the semiconductor chip of this embodiment includes an integrated gradation control output circuit, an output unit 107 of the gradation control output circuit, and a selective precharge circuit. 106, a resistor 100 having a resistance value set with high accuracy, diodes 102 and 103 for protecting the internal circuit from electrostatic discharge (ESD), switch circuits 104 and 105, and external terminals ( (Not shown).

  The semiconductor chip of this embodiment will be described for each operation mode.

  First, as shown in FIG. 20A, during normal times (when the power is turned off and during normal operation), the switch circuit 104 is turned off and the switch circuit 105 connects the resistor 100 to an external terminal. At this time, the external terminal, the resistor 100, and the gradation control output circuit are connected in series with each other.

  Thereby, when a high voltage such as static electricity is applied from the external terminal, the gradation control output circuit can be protected by the voltage drop action of the resistor 100.

  On the other hand, as shown in FIG. 20B, at the time of inspection, the switch circuit 104 is turned on and the switch circuit 105 connects the resistor 100 to the ground.

  Thus, the current signal for measurement is converted into a voltage signal by the resistor 100 before being output from the external terminal.

  As described above, according to the semiconductor chip of this embodiment, the resistor 100 is used as an ESD protection resistor during normal operation and used as a current / voltage conversion resistor during inspection, thereby achieving ESD protection and high accuracy. An inspection can be performed. Further, by providing the resistor 100 on the semiconductor chip, it is not necessary to provide a resistor on the probe card as in the eleventh embodiment. Therefore, in order to inspect the gradation control output circuit, the inspection can be performed even if a low-quality probe card is used.

  Also in the semiconductor chip of this embodiment, the integrated internal circuit may be a circuit that outputs a minute current other than the gradation control output circuit.

  In addition, the switch circuits 104 and 105 can be provided at a place different from the position described in the present embodiment, and it is sufficient that the connection of the resistor can be switched between the inspection time and the normal time.

(13th Embodiment)
The thirteenth embodiment of the present invention relates to a method for inspecting a gradation control output circuit (current drive driver).

  FIG. 21 is a circuit diagram for explaining the inspection method of the gradation control output circuit according to the thirteenth embodiment of the present invention. As an example of the gradation control output circuit, here, the gradation control output circuit according to the ninth embodiment shown in FIG. 17 is shown.

  In the gradation control circuit of the present invention, the magnitude of the output current from the gradation control circuit varies depending on the magnitude of the current supplied from the multistage current mirror. In the multistage current mirror used in this embodiment, a current having the same value as the current flowing through one parent current source is supplied to 176 gradation control circuits, so that the current input to the multistage current mirror section is If the number is increased, the current output from all the gradation control circuits connected to the multistage current mirror section also increases.

  Therefore, in the inspection method for the gradation control output circuit of the present embodiment, the resistor 69 having a lower resistance value than the external resistor 68 is used.

  At the time of inspection, the resistor 69 is connected in parallel with the external resistor 68 to the low-side current mirror unit 55.

  Normally, the connection of the resistor 69 is switched by a switch circuit or the like so as not to be connected to the low-side current mirror unit 55.

  With this method, during inspection, a larger current than that during normal operation temporarily flows, and the signal current output from the gradation control output circuit can be increased, for example, 10 times. As a result, it is possible to reduce the influence of insulation resistance leakage due to parasitic elements and wiring materials during inspection.

  Note that, according to the inspection method of the present embodiment, the example in which the external resistor 69 is connected to the low-side current mirror unit 55 is shown, but the resistor 69 may be connected to the high-side current mirror unit 56. .

(Fourteenth embodiment)
As a fourteenth embodiment of the present invention, an example in which a common latch circuit is provided to inspect the gradation control output circuit will be described.

  FIG. 22 is a block circuit diagram for showing a path of an external input signal in the gradation control output circuit.

  When the gradation control output circuit of the present invention is used as a current drive driver for a display device, display data is input from a data input terminal and is supplied to a plurality of latch circuits for each bit cell (cell circuit for one output). After being latched, it is supplied to each gradation control circuit. That is, display data input from the outside during normal operation is input to the gradation control circuit via a normal operation latch circuit 111a, 111b, etc., along a path such as the black line shown in FIG.

  However, when inputting a minute current for inspection, if the above path is followed, the inspection time becomes long. In particular, when an analog current is input and a change in gradation is inspected, the inspection time becomes enormous.

  In order to shorten the inspection time and improve the inspection efficiency, the inventors of the present application have integrated the grayscale control circuit with one common latch circuit 90 for all output units on the chip, which is used only during the inspection. It was decided to be provided on the chip.

  FIG. 23 is a circuit diagram showing a configuration of a selection circuit in the semiconductor chip of the present embodiment.

  As shown in the figure, the semiconductor chip of this embodiment includes a gradation control output circuit integrated on the semiconductor chip, and a normal operation latch circuit 111 provided for each bit cell of the gradation control output circuit. And one common latch circuit 90 provided on the semiconductor chip, and a selection circuit for connecting any one of the normal operation latch circuit 111 and the common latch circuit 90 to the bit cell of the output circuit for gradation control. I have.

  A wiring for connecting to all the bit cells extends from the common latch circuit 90.

  During normal operation, the switch circuit is off so that the common latch circuit 90 is not connected to the bit cell.

  At the time of inspection, the selection circuit can connect the common latch circuit 90 and all the bit cells. In the present embodiment, the output from the common latch circuit 90 is connected to all the 528 outputs of the gradation control output circuit.

  With this configuration, it is not necessary to latch data every bit cell at the time of inspection, so that the inspection time can be greatly shortened.

1 is a circuit diagram showing a configuration of a gradation control output circuit according to a first embodiment of the present invention. FIG. (A), (b) is the circuit diagram which shows the structure of the output circuit for gradation control which concerns on the 2nd Embodiment of this invention, respectively, and the distance from the power supply potential and power supply voltage supply part in a power supply voltage supply line, It is a figure which shows the relationship. It is a circuit diagram which shows the structure of the output circuit for gradation control which concerns on the 3rd Embodiment of this invention. It is a circuit diagram which shows the structure of the output circuit for gradation control which concerns on the 4th Embodiment of this invention. It is a figure which shows the structure of the output circuit for gradation control which concerns on the 5th Embodiment of this invention. FIG. 6 is a diagram showing a detailed configuration of a gradation control circuit shown in FIG. 5. It is a figure which shows a multistage type current mirror part at the time of making a current source into a three-stage type. It is a figure which shows the gradation level-output current characteristic of the electric current which the output circuit for gradation control for current drives outputs. It is a block circuit diagram which shows the structure of the display apparatus of the current drive system using the output circuit for gradation control concerning the 6th Embodiment of this invention. It is a circuit diagram which shows an example of the selection precharge circuit and the selection precharge control circuit in the output circuit for gradation control which concerns on 6th Embodiment. It is a figure which shows the reference example of the layout of the output circuit for gradation control which concerns on 6th Embodiment. It is a figure which shows the layout of the output circuit for gradation control which concerns on the 7th Embodiment of this invention. It is a wiring diagram which shows the output wiring area | region of the output circuit for gradation control which concerns on 7th Embodiment. (A), (b) is the circuit diagram which shows the structure of a gradation control circuit, respectively, and the figure which shows schematically the reference example of the layout of this gradation control circuit. (A) is a circuit diagram showing a configuration of a gradation control circuit, (b) is a diagram schematically showing a reference example of a layout of the gradation control circuit, and (c) is an eighth embodiment of the present invention. It is a figure which shows roughly the layout of the gradation control circuit which concerns on a form. (A), (b) is the figure which shows the electric current value-gradation level characteristic of the output circuit for gradation control shown in the figure (b), respectively, and the gradation control at the time of providing the current mirror part for raising circuits It is a block circuit diagram showing an example of the output circuit for use. It is a figure which shows a current raising control circuit among the output circuits for gradation control which concern on the 9th Embodiment of this invention. (A), (b) is sectional drawing which shows the probe card based on the 10th Embodiment of this invention, respectively, and a block circuit diagram which shows the cross section of this probe card. It is a block circuit diagram which shows the cross section of the probe card based on the 11th Embodiment of this invention. (A), (b) is a circuit diagram showing a semiconductor chip according to a twelfth embodiment of the present invention at a normal time, and a circuit diagram showing a semiconductor chip of the twelfth embodiment at the time of inspection, respectively. It is a circuit diagram for demonstrating the inspection method of the output circuit for gradation control which concerns on the 13th Embodiment of this invention. FIG. 3 is a block circuit diagram for showing a path of an input signal from the outside in a gradation control output circuit. It is a circuit diagram which shows the structure of the selection circuit in the semiconductor chip concerning the 14th Embodiment of this invention. It is a figure for demonstrating the drive system of an organic electroluminescent panel. (A), (b) is a circuit diagram which shows the structure of the conventional voltage drive driver, respectively, and is a figure which shows the relationship between the power supply potential in a power supply voltage supply line, and the distance from a power supply voltage supply part. (A), (b) is sectional drawing which shows the conventional probe card for test | inspecting the output circuit for gradation control for current drive, respectively, and a block circuit diagram which shows the cross section of the conventional probe card.

Explanation of symbols

1 Gradation controller 2 Second MISFET
3 Third MISFET
4 power supply voltage supply wiring 5 output side transistor 6 operational amplifier 7 differential circuit 8 output buffer unit 10, 10a current supply unit 11 first MISFET
DESCRIPTION OF SYMBOLS 12 Power supply voltage supply part 13 Resistor 14 3rd node 15 Gate bias supply line 16 Output part 19 Oscillation prevention capacitor 20 Voltage selection switch 21 1st resistor 22 2nd resistor 23 1st node 23a Output part Voltage supply line 24 second node 24a differential circuit voltage supply line 25 first power supply voltage supply node 26 second power supply voltage supply node 30 tilt bias MISFET
31 Second current supply unit 41 Fourth MISFET
43 Receiver-side current mirror 49, 70 Transfer gate 50, 71 Inverter 52 Current mirror unit 53 Selection switch 55 Low-side current mirror unit 56 High-side current mirror unit 59 Low-side gradation control circuit 60 High-side gradation control circuits 61, 66 Current raising control circuit 62, 106 Select precharge circuit 63a, 63b, 68, 69, 80, 88, 100 Resistor 64, 107 Output unit 65 Current mirror unit 74 for raising circuit NOR circuit 75 OR circuit 76 NAND circuit 77 Output node 78 Substrate 79 Semiconductor Tester 81 Comparator 82 Inspected Wafer 83 Probe 85 Connection Wiring 86 Wiring 87 Pad
90 Common latch circuit 102, 103 Diode 104, 105 Switch circuit 111a, 111b Latch circuit for normal operation

Claims (35)

A power supply voltage supply unit;
A first current supply unit;
A power supply voltage supply wiring connected to the power supply voltage supply unit;
A first MISFET having a gate electrode interposed between the first current supply unit and the power supply voltage supply unit and connected to the power supply voltage supply unit;
A plurality of gradation control units having transistors connected to the power supply voltage supply wiring;
A second current supply unit;
A tilt bias MISFET having the same conductivity type as that of the first MISFET, connected to the second current supply unit and the power supply voltage supply wiring;
A bias supply line that connects between the gate electrode of the first MISFET and the gate electrode of the gradient bias MISFET, is connected to the power supply voltage supply wiring, and controls a current flowing through the transistor; Output circuit for gradation control. The gradation control output circuit according to claim 1,
The gradation control output circuit, wherein the transistor is a MISFET having a gate electrode connected to the bias supply line. The gradation control output circuit according to claim 1 or 2,
A second MISFET which is connected to the power supply voltage supply unit and forms a sender-side current mirror together with the first MISFET;
The gradation control output circuit, wherein the second current supply unit is a receiver-side current mirror connected to the sender-side current mirror and composed of MISFETs of the same conductivity type. The gradation control output circuit according to any one of claims 1 to 3,
The gradation control output circuit, wherein the plurality of gradation control units are current addition type D / A converters. In the gradation control output circuit according to any one of claims 1 to 4,
The plurality of gradation control units are
A plurality of current mirror portions connected in parallel to the power supply voltage supply node to represent M gray scale;
The same number of selection switches connected to the current mirror section;
A current output connected to all the selection switches,
The gradation control output circuit, wherein the current mirror section is formed of a current mirror including the transistor. The output circuit for gradation control according to claim 5,
In order to control the M gradation, the current mirror section is composed of 1, 2,..., M / 2 current mirrors having the same element configuration, respectively. circuit. The output circuit for gradation control according to claim 5,
The transistors are MISFETs having the same element configuration,
An output circuit for gradation control, wherein an output current from each of the current mirror units is adjusted by a ratio of a gate width to a gate length of the MISFET in order to control M gradation. In the gradation control output circuit according to any one of claims 4 to 7,
The gradation control unit
A plurality of gradation generation units having a current mirror unit and a selection switch having the same number of transfer gates and inverters connected to the current mirror unit;
The output circuit for gradation control, wherein the current mirror section and the selection switch are arranged firmly for each gradation generation section. The gradation control output circuit according to any one of claims 1 to 3,
The transistors are a first transistor and a second transistor both having the same conductivity type and constituting a current mirror,
The gradation control output circuit, wherein the gradation control section includes an output buffer section having the first transistor and a differential circuit having the second transistor. The gradation control output circuit according to claim 9,
An output circuit for gradation control, wherein a current flowing through the first transistor during driving is larger than a current flowing through the second transistor. The gradation control output circuit according to claim 9 or 10,
The gradation control output circuit, wherein the gradation control unit further includes a voltage selection switch for supplying a voltage for gradation control to the output buffer unit. The output circuit for gradation control according to claim 11,
The differential circuit includes an operational amplifier having an input section connected to the voltage selection switch and an output section connected to the output buffer section. A plurality of multi-stage current mirror units, each of which is composed of a plurality of current mirrors, and in which a current equal to a current flowing through the first stage current mirror flows through each of the three or more stage current mirrors
A grayscale control output circuit comprising a plurality of grayscale control sections for receiving a reference voltage and a grayscale signal from each of the plurality of multi-stage current mirror sections and outputting different grayscale control currents . The gradation control output circuit according to claim 13,
A gray scale control including a gray scale control current from the plurality of gray scale control sections and an output control section for changing a combination of the gray scale control currents output according to the gray scale signal Output circuit. The gradation control output circuit according to claim 13 or 14,
The plurality of gradation control units include a low-side gradation control unit capable of controlling a gradation in the lowest range among the plurality of gradation control units, and a gradation higher than the low-side gradation control unit. It is divided into a controllable high-side gradation control unit,
The plurality of multi-stage current mirror sections include a low-side multi-stage current mirror section connected to the low-side gradation control section and a high-side multi-stage current mirror section connected to the high-side gradation control section. A gradation control output circuit characterized by being separated. The gradation control output circuit according to claim 15,
The output control unit outputs only the gradation control current from the low-side gradation control unit when the number of gradations is a predetermined value or less, and when the number of gradations exceeds the predetermined value, A gradation control output characterized by controlling to output the gradation control current from the high-side gradation control unit in addition to the gradation control current from the low-side gradation control unit circuit. The gradation control output circuit according to claim 15 or 16,
The low-side multi-stage current mirror section, the high-side multi-stage current mirror section, the low-side gradation control section, and the high-side gradation control section for at least three colors of red, green, and blue are integrated on the same chip. An output circuit for gradation control, characterized in that The gradation control output circuit according to claim 17,
The low-side multi-stage current mirror section and the high-side multi-stage current mirror section are arranged adjacent to each other one by one and arranged in a predetermined color order in the row direction.
The low-side gradation control unit, the high-side gradation control unit, and the output control unit are arranged substantially in a matrix, and constitute one set of the low-side multistage current mirror unit and the high-side multistage current mirror unit. A gradation control output circuit, wherein the low-side gradation control unit, the high-side gradation control unit, and the output control unit connected to each other are arranged together. The gradation control output circuit according to any one of claims 13 to 18,
The gradation control unit
A plurality of gradation generation units having a current mirror unit and a selection switch having the same number of transfer gates and inverters connected to the current mirror unit;
The output circuit for gradation control, wherein the current mirror section and the selection switch are arranged firmly for each gradation generation section. The gradation control output circuit according to any one of claims 15 to 19,
In response to the raising control signal and the reference voltage supplied from the high-side multistage current mirror, the output current from the low-side gradation control unit and the current that raises the output current from the high-side gradation control unit are An output circuit for gradation control, further comprising a current raising control circuit for outputting to the output control unit. The gradation control output circuit according to any one of claims 15 to 19,
A current raising control circuit for outputting a current for raising the output current of the low-side gradation control unit is further provided between the low-side multistage current mirror unit and the low-side gradation control unit. A characteristic gradation control output circuit. The gradation control output circuit according to claim 21,
The gray scale control output circuit, wherein the current raising control circuit has a function of increasing or decreasing a current to be output in accordance with a gray scale to be controlled. In the gradation control output circuit according to any one of claims 14 to 22,
The output control circuit is
A selection precharge circuit for supplying a voltage for charging an external signal line by switching control;
A gradation control output circuit, further comprising: a selection precharge control circuit for turning on the selection precharge circuit for a predetermined period by timing control according to display data. An internal circuit integrated on a semiconductor chip and having an output unit for outputting a current signal;
An external terminal provided on the semiconductor chip and connected to the output unit;
A gradation control output circuit comprising: a resistor provided on the semiconductor chip and connected to the output unit for converting a current signal into a voltage signal. The gradation control output circuit according to claim 24,
A switch circuit connected to the resistor;
The switch circuit is
At the time of normal operation and power off, the resistor is connected to the external terminal so as to be connected in series with the internal circuit,
A gradation control output circuit characterized in that, at the time of inspection, the resistor is connected to ground, and the resistor and the external terminal are switched to be connected in parallel to the output unit. The gradation control output circuit according to claim 24 or 25.
The internal circuit is
A multi-stage current mirror,
A gradation control output circuit comprising: a gradation control section for receiving a reference voltage from the multistage current mirror section and outputting a gradation control current. A plurality of gradation control units having a plurality of bit cells;
A latch circuit for normal operation provided for each bit cell;
A common latch circuit for supplying signals to all the bit cells;
Provided between the common latch circuit and the normal operation latch circuit and the bit cell, and transmits a signal from the normal operation latch circuit to the bit cell during normal operation, and is output from the common latch circuit during inspection. And a selection circuit for switching so as to transmit the received signal to the bit cell. The gradation control output circuit according to claim 27.
A gradation control output circuit, further comprising a multistage current mirror section for supplying a reference voltage to the plurality of gradation control sections. A substrate whose upper surface can be set on a tester for wafer inspection;
A probe made of a conductor provided on the lower surface of the substrate and receiving a current signal from at least a wafer to be inspected;
A resistor disposed on the substrate in proximity to the probe and connected to the probe for converting the current signal into a voltage signal;
An inspection apparatus for a gradation control output circuit, comprising: a wiring connected to the resistor and provided through the substrate. The inspection apparatus for an output circuit for gradation control according to claim 29,
An inspection apparatus for an output circuit for gradation control, wherein a distance between the probe and the resistor is 10 cm or less. The gradation control output circuit inspection apparatus according to claim 29 or 30,
An inspection of an output circuit for gradation control, further comprising an operational amplifier connected in parallel with the resistor to the probe and having an output unit connected to the negative side input unit through the resistor. apparatus. The inspection apparatus for an output circuit for gradation control according to claim 31,
An inspection apparatus for a gradation control output circuit, wherein a reference voltage output from the tester is input to a positive input portion of the operational amplifier. In the inspection apparatus for an output circuit for gradation control according to any one of claims 29 to 32,
An inspection apparatus for a gradation control output circuit, wherein the resistors are integrated. In the inspection apparatus for an output circuit for gradation control according to any one of claims 31 to 33,
An inspection apparatus for an output circuit for gradation control, wherein the operational amplifier is integrated. A reference current source connected to a first resistor connected in parallel to each other and a gradation control unit connected to the reference current source and outputting a gradation control current. An inspection method for an output circuit,
At the time of inspection, a second resistor that is provided in parallel with the first resistor and has a lower resistance value than the first resistor is connected to the reference current source,
A method for inspecting a gradation control output circuit, wherein the connection between the second resistor and the reference current source is turned off during normal operation.

Images