JP2007189654A - Afc circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable a digital processing section to perform frequency error detection and frequency correction processing when a receiver side receives a digital modulated signal and applies demodulation processing thereto. <P>SOLUTION: In a communication system using a digital modulation scheme in which a transition for each modulation cycle does not pass through a zero point, a receiver is equipped with an analog processing section for converting a received signal into an IF signal and a digital signal processing section 30 for applying frequency correction processing to the IF signal. The digital signal processing section 30 converts a digital signal (IF signal) converted by an A/D converter 19 into an in-phase signal (I) and a quadrature signal (Q) by using a quadrature demodulation processing part 31, detects a frequency error of the IF signal by using a frequency error detection part 34 and inputs it to a complex frequency conversion processing part 32. The complex frequency conversion processing part 32 applies frequency correction based on the frequency error detected by the frequency error detection part 34 to the in-phase signal (I) and the quadrature signal (Q) from the quadrature demodulation processing part 31 and at the same time applies complex frequency conversion to the in-phase signal (I) and the quadrature signal (Q) and outputs the signals to a demodulation processing part 33. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an AFC circuit used in a receiver or the like in wireless communication, and more particularly to an AFC circuit in a demodulation process of a digital modulation system in which a transition for each modulation period does not pass through a zero point.

  In wireless communication using a digital modulation method, a transmitter and a receiver use a local oscillator to perform frequency conversion processing. However, if a local error of the receiver causes a frequency error due to, for example, a temperature change or the like, remarkably occurs. Reception characteristics deteriorate. In order to compensate for this frequency error, an AFC (Auto Frequency Control) circuit is generally used (see, for example, Patent Documents 1, 2, and 3).

  FIG. 4 shows a configuration example of a receiver including a conventional AFC circuit. The receiver is a digital modulation system such as π / 4 QPSK (Quadrature Phase Shift Keying), π / 2 BPSK (Binary Phase Shift Keying), GMSK (Gaussian filtered Minimum Shift Keying), etc. The signal modulated by is received and demodulated.

  In FIG. 4, reference numeral 11 denotes an input terminal of a receiver to which a signal received by an antenna (not shown) is input. The signal input to the input terminal 11 is subjected to band filtering processing by a band pass filter (BPF) 12, amplified by a low noise amplifier 13 with a predetermined amplification degree, and input to the mixer 14. Further, a local oscillation signal output from the local oscillator 15 is input to the mixer 14. The local oscillator 15 is configured using a voltage-controlled oscillator, and the oscillation frequency is controlled by a control signal sent from a digital signal processing unit 20 described later.

  The mixer 14 mixes the signal amplified by the low noise amplifier 13 with the local oscillation signal from the local oscillator 15 and converts it into an intermediate frequency signal (IF signal). This intermediate frequency signal is sent to an amplifier 17 through a band pass filter (BPF) 16. The bandpass filter 16 has an action of attenuating an image signal and an unnecessary leak signal from the local oscillator 15. The intermediate frequency signal from which unnecessary signals have been removed by the band pass filter 16 is amplified by an amplifier 17 and then input to an A / D converter 19 through a low pass filter (LPF) 18 to be converted into a digital signal. It is sent to the digital signal processing unit 20. The low-pass filter (LPF) 18 has an action of attenuating the aliasing signal generated when the A / D converter 19 converts the analog signal into the digital signal to a predetermined level.

  The digital signal processing unit 20 includes a demodulation processing unit 21, a frequency error detection unit 22, and a loop filter 23, and the digital signal converted by the A / D converter 19 is sent to the demodulation processing unit 21 and the frequency error detection unit 22. Entered. The frequency error detector 22 detects the frequency error of the intermediate frequency signal converted by the mixer 14 and inputs it to the loop filter 23.

  The loop filter 23 is a filter having a predetermined time constant, converts the frequency error detected by the frequency error detector 22 into a voltage, and controls the local oscillator 15 formed of a voltage controlled oscillator to control the frequency deviation of the local oscillation frequency. Correct.

  In the above configuration, the signal received by the antenna is input from the input terminal 11 to the bandpass filter 12 to select a predetermined band, amplified by the low noise amplifier 13 and input to the mixer 14. The mixer 14 mixes the signal amplified by the low noise amplifier 13 with the local oscillation signal from the local oscillator 15 and converts it into an intermediate frequency signal. This intermediate frequency signal is taken out through a band pass filter 16 and attenuates an image signal and an unnecessary leakage signal from the local oscillator 15. The intermediate frequency signal from which unnecessary signals have been removed by the band pass filter 16 is amplified by the amplifier 17 and then input to the A / D converter 19 via the low pass filter 18 to be converted into a digital signal for digital signal processing. Sent to the unit 20.

  The digital signal processing unit 20 detects the frequency error of the input digital signal (intermediate frequency signal) by the frequency error detection unit 22 and inputs the detected frequency error to the loop filter 23. The loop filter 23 converts the frequency error detected by the frequency error detector 22 into a voltage and controls the voltage controlled oscillator of the local oscillator 15 to correct the local oscillation frequency, that is, the frequency deviation of the reception reference signal. The demodulation processing unit 21 demodulates the digital signal converted by the A / D converter 19.

In addition to the above, as a technique related to the present invention, in a low IF receiver, the center frequency of a desired signal is set to 0 Hz by complex frequency conversion, so that an image can be removed without using a complex coefficient filter having a large calculation amount. A receiver is known (see, for example, Patent Document 4).
Japanese Patent Laid-Open No. 9-186731 JP-A-9-199997 Japanese Patent Laid-Open No. 9-232927 JP 2004-266416 A

  In the receiver using the conventional digital modulation method, in the automatic frequency correction process (AFC process) at the time of demodulation, the frequency error is detected by the frequency error detection unit 22 of the digital signal processing unit 20, and the local oscillator 15 which is an analog circuit is used. Controls a voltage controlled oscillator.

  As described above, the method of controlling the local oscillator 15 that is an analog circuit based on the frequency error detected by the digital signal processing unit 20 has a problem that the frequency correction control is complicated and the response is slow. Further, since analog processing and digital processing cannot be performed independently, for example, when an analog circuit is changed, the digital processing must be changed accordingly, and there is a problem that versatility is lacking.

  Further, in the frequency deviation detection method described above, it is possible to calculate the frequency deviation if the modulation method does not allow the transition for each modulation period to pass through the zero point. However, even in a time division multiple access method, etc., even if the modulation of the data part is a modulation system in which the transition for each modulation period does not pass through the zero point, the transition for each modulation period is not performed in the preamble other than the data modulation part or the modulation part of the unique word. When passing through the zero point, there is a problem that an error occurs in the detection of the frequency deviation due to the presence of a portion where the transition passes through the zero point.

  The present invention has been made to solve the above-described problems. In wireless communication using a digital modulation method in which transitions at each modulation period do not pass through a zero point, a digitally modulated signal is received and demodulated at the receiver side. When processing, the digital processing unit can detect frequency error and correct the frequency, and the frequency correction can be controlled easily and quickly, and analog processing and digital processing can be performed independently. An object is to provide a circuit.

  The present invention detects a switching between positive and negative of an input digital signal in an AFC circuit that receives a signal by a digital modulation method in which a transition every modulation period does not pass through a zero point and corrects a frequency deviation of the received signal. A frequency error detection unit that counts for a certain time and detects a frequency error by comparing with a preset reference value, an orthogonal demodulation processing unit that performs orthogonal demodulation processing on the digital signal, and an output signal of the orthogonal demodulation processing unit And a complex frequency conversion processing unit that performs complex frequency conversion processing based on the frequency error signal detected by the frequency error detection unit to correct the frequency error.

  According to the present invention, for example, an AFC that receives a signal by a digital modulation method in which a transition of each modulation period such as π / 4QPSK, π / 2BPSK, GMSK, etc. does not pass a zero point and corrects a frequency deviation of the received signal. In the circuit, frequency error detection and frequency correction processing can be performed by the digital signal processing unit, so that frequency correction control can be performed easily and quickly, and analog processing and digital processing can be separated. Therefore, the AFC circuit can be configured without using an analog element such as a voltage-controlled oscillator that is complicated to adjust in the frequency correction process.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a block diagram showing a configuration of a receiver including an AFC circuit according to the first embodiment of the present invention, and FIG. 2 is a block diagram showing a detailed configuration of a digital signal processing unit in FIG.
In the wireless communication using a digital modulation method in which the transition for each modulation period such as π / 4 QPSK, π / 2 BPSK, GMSK, etc. does not pass through the zero point, for example, the receiver receives a digitally modulated signal and performs demodulation processing The frequency error detection and frequency correction processing can be performed by digital processing. In addition, the same code | symbol is attached | subjected and demonstrated about the part similar to FIG.

  In FIG. 1, reference numeral 11 denotes an input terminal of a receiver to which a signal received by an antenna (not shown) is input. The signal input to the input terminal 11 is subjected to band filtering processing by a band pass filter (BPF) 12, amplified by a low noise amplifier 13 with a predetermined amplification degree, and input to the mixer 14. In addition, a local oscillation signal output from the local oscillator 25 is input to the mixer 14. The local oscillator 25 is, for example, a numerically controlled oscillator whose transmission frequency is discrete and semi-fixed.

  The mixer 14 mixes the signal amplified by the low noise amplifier 13 with the local oscillation signal from the local oscillator 25 and converts it into an intermediate frequency signal (IF signal). This intermediate frequency signal is sent to the amplifier 17 via the BPF 16. The BPF 16 has a channel selection function of attenuating an image signal and an unnecessary leakage signal from the local oscillator 25 and passing only a desired frequency channel. The intermediate frequency signal from which unnecessary signals are removed by the BPF 16 is amplified by the amplifier 17 and then input to the A / D converter 19 via the LPF 18 to be converted into a digital signal. The LPF 18 may not be provided when the A / D converter 19 performs undersampling, or may be configured as a BPF similar to 16.

  The signal processed by the analog processing unit including the BPF 12 to the A / D converter 19 as described above is converted into a digital signal by the A / D converter 19 and input to the digital signal processing unit 30.

  The digital signal processing unit 30 includes an orthogonal demodulation processing unit 31, a complex frequency conversion processing unit 32, a demodulation processing unit 33, and a frequency error detection unit 34. The intermediate frequency signal converted into a digital signal by the A / D converter 19 is used. Is input to the orthogonal demodulation processing unit 31 and the frequency error detection unit 34. The quadrature demodulation processing unit 31 converts the digital signal (intermediate frequency signal) into an in-phase signal (I) and a quadrature signal (Q) and outputs the converted signal to the complex frequency conversion processing unit 32. This output signal corresponds to an in-phase signal (I) corresponding to a real number and a quadrature signal (Q) corresponding to an imaginary number, and is hereinafter referred to as a quadrature detection signal.

On the other hand, the frequency error detector 34 detects the frequency error of the intermediate frequency signal sent from the A / D converter 19 and inputs it to the complex frequency conversion processor 32. The complex frequency conversion processing unit 32 performs frequency correction processing by complex calculation on the quadrature detection signal output from the quadrature demodulation processing unit 31 based on the frequency error detected by the frequency error detection unit 34, and the demodulation processing unit 33. Output to. The demodulation processing unit 33 demodulates the signal frequency-corrected by the complex frequency conversion processing unit 32 and outputs the demodulated signal to a subsequent processing unit (not shown).
As an example, the quadrature demodulation processing unit 31 converts the quadrature detection signal into a complex signal having a center frequency of about 0 Hz, and the complex frequency conversion processing unit 32 converts the signal into a baseband analysis signal. In that case, an LPF for individually low-pass filtering the in-phase signal (I) and the quadrature signal (Q) may be provided between the quadrature demodulation processing unit 31 and the complex frequency conversion processing unit 32.

Next, a detailed configuration of the digital signal processing unit 30 will be described with reference to FIG.
For example, the orthogonal demodulation processing unit 31 includes multipliers 311 and 312, a cos table 313, and a sin table 314, and a digital signal from the A / D converter 19 is input to the multipliers 311 and 312. The multiplier 311 multiplies the input signal and the value of the cos table 313 to output the in-phase signal (I), and the multiplier 312 multiplies the input signal and the value of the sin table 314 to obtain the quadrature signal (Q). Output. The frequency of the local signal read from the cos table 313 or the sin table 314 can be normally selected to be fixed or discontinuous.

The complex frequency conversion processing unit 32 is provided with a sin table 321 and a cos table 322 for simultaneously performing complex frequency conversion and frequency error correction on the quadrature detection signal output from the quadrature demodulation processing unit 31. The increment amount of the address for reading the sin table 321 and the cos table 322 is corrected by the frequency error signal detected by the frequency error detection unit 34 with the center frequency of the desired frequency channel included in the analysis signal as a reference. Further, the increment amount is AFCed as described later, so that the center frequency of the channel is converted to 0 Hz with sufficient accuracy.
Further, the complex frequency conversion processing unit 32 multiplies the in-phase signal (I) output from the multiplier 311 of the quadrature demodulation processing unit 31 by the value of the sin table 321 and the value of the cos table 322. A multiplier 324; a multiplier 325 that multiplies the value of the sin table 321 by the quadrature signal (Q) output from the multiplier 312 of the quadrature demodulation processing unit 31; a multiplier 326 that multiplies the value of the cos table 322; A subtracter 327 for subtracting the output of the multiplier 326 from the output of the multiplier 323 and an adder 328 for adding the output of the multiplier 324 and the output of the multiplier 325 are provided. The in-phase signal (I) output from the subtractor 327 and the quadrature signal (Q) output from the adder 328 are sent to the demodulation processing unit 33.

The frequency error detection unit 34 includes a limiter 341, a rising edge detection unit 342, a frequency counter 343, and an error detection unit 344. A digital signal (intermediate frequency signal) sent from the A / D converter 19 in the previous stage is received. Input to the limiter 341.
The limiter (base clipper) 341 detects a signal having a certain amplitude or more and outputs the signal to the edge detection unit 342.
The edge detection unit 342 detects a switching between positive and negative of the signal in the carrier band only when the input signal changes to positive and negative, and outputs a pulse signal whose waveform has been shaped to the frequency counter 343. .
The frequency counter 343 counts the input pulses for a predetermined time, and outputs the count value to the error detection unit 344.

The error detection unit 344 detects the frequency error of the intermediate frequency signal by comparing the count value of the frequency counter 343 with a preset reference value, and the error signal is converted into a sin table 321 and cos in the complex frequency conversion processing unit 32. Output to table 322. The reference value used in the error detector 344 is set in advance so that the error signal becomes zero when the frequency of the intermediate frequency signal input from the A / D converter 19 to the frequency error detector 34 is a specified value. Is done. The complex frequency conversion processing unit 32 corrects the frequencies of the sin and cos signals to be multiplied based on the error signal sent from the error detection unit 344, and corrects the frequency error of the intermediate frequency signal.

Next, the overall operation in the first embodiment will be described with reference to FIGS.
A signal received by the antenna is input from the input terminal 11 to the BPF 12, a predetermined band is selected, amplified by the low noise amplifier 13, and input to the mixer 14. The mixer 14 mixes the signal amplified by the low noise amplifier 13 with the local oscillation signal of the local oscillator 25 formed of a fixed frequency oscillator or the like and converts it into an intermediate frequency signal. This intermediate frequency signal is input to the BPF 16 and an image signal and an unnecessary leakage signal from the local oscillator 15 are attenuated. The intermediate frequency signal from which unnecessary signals are removed by the BPF 16 is amplified by the amplifier 17, and then input to the A / D converter 19 through the low-pass filter 18, converted into a digital signal, and sent to the digital signal processing unit 30. Sent.

  The digital signal sent from the A / D converter 19 to the digital signal processing unit 30 is input to the orthogonal demodulation processing unit 31 and the frequency error detection unit 34. The signal input to the quadrature demodulation processing unit 31 is multiplied by the value of the cos table 313 by the multiplier 311 and converted into the in-phase signal (I), and is also multiplied by the value of the sin table 314 by the multiplier 312. It is converted into an orthogonal signal (Q) and sent to the complex frequency conversion processing unit 32.

  On the other hand, the signal input to the frequency error detection unit 34 is detected by the limiter 341 when the amplitude is equal to or greater than a certain level, and is sent to the edge detection unit 342. The edge detection unit 342 detects a rising portion when changing between positive and negative, and outputs the detection pulse signal to the frequency counter 343. The frequency counter 343 counts the pulse signal detected by the edge detection unit 342 for a predetermined time, and outputs the count value to the error detection unit 344. The error detection unit 344 detects the error of the intermediate frequency signal by comparing the value counted by the frequency counter 343 with a preset reference value, and outputs the error signal to the complex frequency conversion processing unit 32.

  The complex frequency conversion processing unit 32 is a sum table 321 while incrementing an address with the sum of a value obtained by multiplying an error signal transmitted from the error detection unit 344 of the frequency error detection unit 34 by an appropriate constant and a reference increment amount. And the cos table is read.

  The analysis signals input from the quadrature demodulation processing unit 31 to the complex frequency conversion processing unit 32 are multiplied by the values of the sin table 321 by the multipliers 323 and 325, respectively, and the cos table by the multipliers 324 and 326, respectively. Multiply by the value of 322. Then, the output values of the multipliers 323 and 326 are subtracted by the subtractor 327 and sent to the demodulation processing unit 33 as the in-phase signal (I). Further, the output values of the multipliers 324 and 325 are added by the adder 328 and sent to the demodulation processing unit 33 as an orthogonal signal (Q).

  That is, the in-phase signal (I) and the quadrature signal (Q) demodulated by the quadrature demodulation processing unit 31 have a deviation based on the frequency error detected by the frequency error detection unit 34 in the complex frequency conversion processing unit 32. It is corrected. Then, the in-phase signal (I) and the quadrature signal (Q) corrected by the complex frequency conversion processing unit 32 are sent to the demodulation processing unit 33 and demodulated.

  In this example, each of the limiter 341 and the edge detection unit 342 may be configured by an analog circuit using a diode such as an anti-parallel diode or a slicer. Further, the quadrature demodulation processing unit 31 may be configured by an analog circuit, and the output thereof may be A / D converted. However, the local transmission signal of the quadrature modulator at that time uses a signal having no frequency error (for example, a signal interlocked with a digital clock).

  According to the first embodiment, for example, a signal modulated by a digital modulation method in which transition for each modulation period does not pass through a zero point, such as π / 4 QPSK, π / 2 BPSK, GMSK, etc., is received by (quasi) synchronous detection. When demodulating, the digital signal processing unit 30 simultaneously performs complex frequency conversion and frequency correction processing by one complex multiplication, so that analog processing can be made unnecessary with almost no increase in digital processing.

  Further, when the analog signal is converted into an intermediate frequency signal by the mixer 14 and the local oscillator 25 in the analog processing unit, even if a fixed frequency oscillator is used as the local oscillator 25, the frequency counter 343 of the digital signal processing unit 30 temporarily If the frequency is measured, although there is a delay due to the counting time, the frequency error is accurately corrected at one time. Therefore, there is no problem as long as the fluctuation speed of the normal frequency error is obtained. Therefore, it is not necessary to use an analog element such as a voltage-controlled oscillator that is complicated to adjust in the frequency correction process, and the frequency correction control can be performed quickly and easily.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.
FIG. 3 is a block diagram showing a configuration of a receiver including an AFC circuit according to the second embodiment of the present invention. FIG. 3 shows the configuration of the digital signal processing unit 30A. The analog processing unit provided in the preceding stage is omitted because it has the same configuration as that of the first embodiment shown in FIG. This example differs from the first embodiment in that AFC is feedback controlled.

  The digital signal processing unit 30A includes an orthogonal demodulation processing unit 31, a complex frequency conversion processing unit 32, an orthogonal modulation processing unit 41, a frequency error detection unit 34, and a loop filter 42. As in the first embodiment, the quadrature demodulation processing unit 31 performs quadrature detection of the digital signal sent from the A / D converter 19 into the in-phase signal (I) and the quadrature signal (Q), and a complex frequency conversion processing unit. To 32. The complex frequency conversion processing unit 32 performs frequency correction processing on the analysis signal output from the orthogonal demodulation processing unit 31 based on the frequency error transmitted from the frequency error detection unit 34 via the loop filter 42.

  The quadrature modulation processing unit 41 performs quadrature modulation on the in-phase signal (I) and the quadrature signal (Q) corrected by the complex frequency conversion processing unit 32 at an arbitrary frequency, and outputs a real signal having an intermediate frequency. The intermediate frequency signal output from the quadrature modulation processing unit 41 is input to the frequency error detection unit 34 and sent to a quadrature demodulation processing unit (not shown) provided in the next stage intermediate frequency processing unit. If it is input only to the frequency error detection 34, the frequency and accuracy of quadrature modulation are not particularly required. Therefore, a carrier wave having the same frequency as that of the demodulation processing unit 31 (that is, a carrier wave generated by a cos table and a sin table, not shown). ) Is convenient.

  The frequency error detection unit 34 detects the frequency error of the intermediate frequency signal output from the quadrature modulation processing unit 41, smoothes it by the loop filter 42, and outputs the result to the complex frequency conversion processing unit 32. The signal sent from the loop filter 42 to the complex frequency conversion processing unit 32 is input as a correction signal to the sin table 321 and the cos table 322 as shown in detail in FIG. The complex frequency conversion processing unit 32 converts the in-phase signal (I) and the quadrature signal (Q) converted by the quadrature demodulation processing unit 31 into a frequency error input from the frequency error detection unit 34 via the loop filter 42. Based on this, frequency correction processing is performed.

  The quadrature demodulation processing unit 31, the complex frequency conversion processing unit 32, and the frequency error detection unit 34 in the digital signal processing unit 30A have the same configuration as that of the first embodiment shown in FIG. .

  As shown in the second embodiment, the output signal of the complex frequency conversion processing unit 32 is orthogonally modulated by the orthogonal modulation processing unit 41 and converted into an intermediate frequency signal, and the converted intermediate frequency signal is converted into a frequency error detection unit 34. With this configuration, it is possible to detect a frequency error simply by counting the frequency without securing symbol synchronization. Then, the output signal of the quadrature modulation processing unit 41 is fed back to the complex frequency conversion processing unit 32 so that the frequency correction processing of the intermediate frequency signal can be performed with high accuracy. Thereby, the same effect as the first embodiment can be obtained.

  In the second embodiment, the case where the intermediate frequency signal output from the quadrature modulation processing unit 41 is output to the quadrature demodulation processing unit provided in the next stage intermediate frequency processing unit has been described. Similarly to the case, the output signal of the complex frequency conversion processing unit 32 may be demodulated by the demodulation processing unit, and the demodulated signal may be output to the processing unit of the next stage. The means for obtaining the analysis signal is completely arbitrary, and a radio frequency signal may be directly subjected to analog quadrature detection and A / D converted.

(Third embodiment)
Next, a third embodiment of the present invention will be described.
FIG. 5 is a block diagram showing a configuration of a receiver including an AFC circuit according to the third embodiment of the present invention. FIG. 3 shows the configuration of the digital signal processing unit 30A. Components that are the same as those in the first embodiment are given the same reference numerals, and illustration and description thereof are omitted. This example is different from the first embodiment in that a time division multiple access (TDMA) system is premised and a frequency counting period is controlled. It is assumed that appropriate band limitation or the like is performed in order to ensure a signal-to-noise ratio before the frequency error detection unit 34 so that frequency error detection processing can be performed.
The frame synchronization processing unit 351 performs frame synchronization processing by extracting frame timing, and outputs a frame timing signal for controlling demodulation processing.
Based on the frame timing signal, the counter window signal generation unit 352 outputs a window signal that becomes 1 during the frequency counting period (data portion of the frame) and becomes 0 during the frequency non-counting period.
The AND unit 345 calculates and outputs a logical product of the output of the rising edge detection unit 342 and the window signal.

The frequency counter 343 counts the output frequency of the AND unit 357. Since the signal of the part other than the window is masked in the output signal of the AND unit 357, the frequency of only the data part in the frame is counted.
The error detection unit 344 outputs an error signal detected based on the output of the frequency counter 343 to the averaging unit 351.
The averaging unit 353 averages the error signal in units of frames (moving average processing), and outputs it to the memory 354. The timing at which the averaging is performed is after the frequency counting period ends and the error signal is output, and is given from the frequency correction control unit. However, when a substitute value is input from the substitute processing unit during the frame period, the substitute value is taken in the frame instead of the error signal and averaged. That is, an averaging process is performed on the error signal of a frame before the frame.
The memory 354 stores the latest output from the averaging unit 353 and outputs it to the sin table 321 and the cos table. Reading and writing of the memory 354 is controlled by the frequency correction control unit 355 and may be read for the averaging process in the next frame.
The frequency correction control unit 355 controls the averaging unit 353 and the memory 354 so that the averaging unit 353 performs averaging.

The RSSI threshold determination unit 356 receives a received signal strength indicator (RSSI) such as the received intermediate frequency signal, determines whether or not the threshold is exceeded, and outputs the result. The RSSI is obtained, for example, by detecting and logarithmically converting the intermediate frequency signal before A / D conversion. The threshold value is set with a margin at the lowest level at which the frequency error detection unit can accurately detect the error.
The alternative processing unit 357 outputs nothing while the frame RSSI exceeds the threshold value, and outputs the initial value to the averaging unit 353 when the frame RSSI does not exceed the threshold value. The initial value may be a predetermined fixed value (for example, a frequency count value corresponding to the nominal center frequency of the carrier wave, 0, etc.), or may be set according to a value stored in the memory 354.
In this way, the moving average process is performed in units of frames, and the output of the averaging process is output to the complex frequency conversion process 32 as the frequency correction deviation signal of the next frame at the end of the frame, thereby correcting the deviation. Frequency correction processing is performed.

FIG. 6 is an operation timing chart of AFC processing in the third embodiment. The upper band in FIG. 6 shows a frame in the TDMA system, and the lower band shows a frequency deviation detection section and a frequency correction section in this embodiment. The frame is provided with a guard section (G) for ensuring a margin of timing with the preceding and succeeding frames, and a symbol (preamble) for AGC, AFC, symbol synchronization, etc., and a ramp for ensuring the time required for following them. It consists of a section (R), a unique word section (UW) used for frame detection, symbol synchronization and identification, and a data section (DATA). In this example, a ramp section is also provided at the end of the frame. Further, the “frequency deviation detection section” of the AFC process corresponds to a frame data section, and the “frequency deviation detection section” corresponds to a ramp section (or a guard section).
The window signal generated by the counter window signal generation unit 352 corresponds to a “frequency deviation detection section”. Further, the detection of the frequency deviation by the error detection unit 344 and the averaging process with the error signal of the previous frame by the averaging unit 353 are performed within the “frequency correction section”, and before the ramp period of the next frame starts. By the time, it is read from the memory 354 and the complex frequency conversion process is performed.
Even in a communication system in which the data section, the ramp section, and the unique word section are separated in time, the same processing is performed as long as the “frequency deviation detection section” is set to an appropriate section (data section). be able to.

Here, the operation of the AFC of this embodiment in consideration of the RSSI input will be described.
AFC processing operates in units of frames. Then, when the RSSI input value is compared with the set value and the threshold is always exceeded during the “frequency deviation detection section”, AFC is enabled (ON), and when the threshold is sometimes exceeded, the AFC is Disable (OFF).
After the received input signal is cut off and AFC is turned off, when the signal is recovered and AFC is turned on, the initial value of the preset frequency detection amount is used in the averaging unit 353. Even in the averaging process, the convergence time of AFC can be reduced.
Even when error correction coding is performed on the data and the data is not sufficiently randomized and an error occurs in the detection of the frequency deviation, an error occurs in the detection of the frequency deviation by averaging for a long time in units of frames. There is nothing. If the data randomization is not sufficient, the transmission (modulation) side performs data scrambling processing before or after error correction coding, and the reception (demodulation) side performs corresponding descrambling processing. It is possible to reduce the number of times of averaging processing for each frame.

Finally, in each of the above embodiments, the digital signal processing units 30 and 30A can be realized by using any hardware such as FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor) or software for performing numerical operations. Is possible.
Further, the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage.

It is a block diagram which shows the structure of the receiver provided with the AFC circuit which concerns on 1st Embodiment of this invention. It is a block diagram which shows the detailed structure of the digital signal processing part in the embodiment. It is a block diagram which shows the structure of the digital signal processing part of the receiver provided with the AFC circuit which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the structure of the receiver provided with the conventional AFC circuit. It is a block diagram which shows the structure of the receiver provided with the AFC circuit which concerns on 3rd Embodiment of this invention. It is an operation | movement timing diagram of the AFC process in 3rd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Input terminal, 12 ... Band pass filter (BPF), 13 ... Low noise amplifier, 14 ... Mixer, 15 ... Local oscillator, 16 ... Band pass filter (BPF), 17 ... Amplifier, 18 ... Low pass filter (LPF), 19 ... A / D converter,
DESCRIPTION OF SYMBOLS 20 ... Digital signal processing part, 21 ... Demodulation processing part, 22 ... Frequency error detection part, 23 ... Loop filter, 25 ... Local oscillator,
30, 30A: Digital signal processing unit, 31: Quadrature demodulation processing unit, 311, 312 ... Multiplier, 313, 314 ... sin table, 32 ... Complex frequency conversion processing unit, 321 ... sin table, 322 ... cos table, 323 326 ... Multiplier, 327 ... Subtractor, 328 ... Adder, 33 ... Demodulation processing section, 34 ... Frequency error detection section, 341 ... Limiter, 342 ... Edge detection section, 343 ... Frequency counter, 344 ... Error detection section, 345 ... AND part,
351: Frame synchronization processing, 352: Counter window signal generation unit, 353 ... Averaging unit, 354 ... Memory, 355 ... Frequency correction control unit, 356 ... RSSI threshold determination unit, 357 ... Substitution processing unit,
41: Quadrature modulation processing unit, 42: Loop filter.

Claims (1)

In an AFC circuit that receives a signal by a digital modulation method in which a transition every modulation period does not pass through a zero point, and corrects a frequency deviation of the received signal,
A frequency error detector that detects a positive and negative switching of the input digital signal, counts for a certain period of time, and detects a frequency error in comparison with a preset reference value;
An orthogonal demodulation processing unit for performing orthogonal demodulation processing on the digital signal;
A complex frequency conversion processing unit that performs complex frequency conversion processing on the output signal of the orthogonal demodulation processing unit based on the frequency error signal detected by the frequency error detection unit to correct the frequency error. AFC circuit.

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