JP4479460B2 - Demodulator and demodulation method - Google Patents

Description

  The present invention relates to a demodulation device and a demodulation method, and more particularly to a demodulation method for demodulating a multilevel orthogonal modulation signal in a digital wireless communication system.

  An example of this type of conventional demodulator is shown in FIG. Referring to FIG. 10, the quadrature detector 1, the local oscillator 2, the A / D (analog / digital) converter 3, the phase rotator 4, the signal determiner 5, and the phase detector (PD) 6 , LPF 10 and numerically controlled oscillator 11.

  In FIG. 10, IF IN that is an input signal in the intermediate frequency band subjected to quadrature modulation is input to the quadrature detector 1, and the output of the local oscillator 2 having substantially the same frequency as the carrier wave is used to obtain an Ich 103 that is a quadrature component. , Qch104. The analog signals Ich103 and Qch104 are converted into digital signals Ich105 and Qch106 by the A / D converter 3 for subsequent digital processing. At this time, the phase rotation caused by the frequency difference between the local frequency output from the local oscillator 2 and the IF frequency (frequency of IF IN) remains in the Ich 105 and the Qch 106.

  In the phase rotator 4, the Ich 105 and Qch 106 are subjected to complex multiplication by phase control signals (phase rotation information) cos 119 and sin 120 output from the numerically controlled oscillator 11, thereby performing phase correction to converge the phase rotation. It is like that.

  The signal determiner 5 performs symbol determination of Ich107 and Qch108, which are outputs of the phase rotator 4, and outputs signal determination values Ich109 and Qch110. An error signal 112 defined by a value obtained by subtracting the signal determination values Ich 109 and Qch 110 from Qch 108 is calculated and sent to the phase detector (PD) 6.

  The phase detector 6 calculates a phase difference signal 113 from the polarity signal 111 and the error signal 112, and the LPF 10 smoothes the phase difference signal 113 and outputs it to the numerically controlled oscillator 11 as an APC (automatic phase control) signal 118. . The numerically controlled oscillator 11 integrates the APC signal 118 to generate the phase control signals (phase rotation information) cos 119 and sin 120 described above.

Such a demodulator is disclosed in, for example, Patent Documents 1 and 2 as a quasi-synchronous detection circuit, and is a well-known technique.
JP 2000-216839 A Japanese Patent Laid-Open No. 2000-244592

  Assuming a multi-level QAM (Quadrature Amplitude Modulation) modulation signal, the signal far from the origin on the Ich and Qch phase planes fluctuates greatly even with a slight deviation, so that the signal is erroneously detected. The possibility of being judged increases. As a result, on the phase plane, the phase difference signal 113 obtained from a signal point located far from the origin is used uniformly regardless of the distance from the origin, although the reliability is low. ing. Also, since it follows an instantaneous phase change such as a so-called phase jump, the carrier wave is de-synchronized when an irregular phase change occurs that reverses the direction of phase rotation. As a result, control will be applied in the direction, causing a loss of synchronization.

  An object of the present invention is to provide a demodulating apparatus and method capable of improving the reliability of a phase difference signal and capable of appropriate phase control without being affected by an irregular phase change such as so-called phase jump. That is.

  The demodulator according to the present invention receives a quadrature modulation signal and detects a quadrature component, a phase correction unit that performs phase correction of the detection output, and performs signal determination of each component after the phase correction to perform quadrature component And a means for detecting a phase shift of the output of the signal determination means to generate a phase difference signal for the phase correction means, wherein the signal determination means Weighting means for weighting the phase difference signal according to the magnitude of the output.

  The demodulation method according to the present invention includes a step of detecting a quadrature component by receiving a quadrature modulation signal, a phase correction step of correcting the phase of the detection output, and performing signal determination of each component after the phase correction to perform a quadrature component And a step of detecting a phase shift of the output by the signal determination step and generating a phase difference signal for the phase correction step, wherein the signal determination step And a weighting step for weighting the phase difference signal in accordance with the magnitude of the output.

  According to the present invention, weighting is performed according to the absolute value of the signal determination value of the received signal even in an environment where the phase noise characteristic observed in the demodulator is degraded due to poor performance of the local oscillator in the analog system. By using the phase difference signal, the reliability of the phase difference signal can be improved, thereby improving the detection characteristics of the phase difference and ignoring instantaneous phase fluctuations that do not need to be tracked. There is an effect that loss of carrier synchronization can be suppressed. In addition, since deterioration of analog characteristics can be compensated for by digital processing, there is an effect that the total cost can be reduced by integrating the functions in the LSI.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention, and the same parts as those in FIG. 10 are denoted by the same reference numerals. In this example, a weighting selection circuit 7, an averaging circuit 8, a PD (phase detector) output control circuit 9, and a multiplier 18 are added to the conventional example of FIG.

  The weighting selection circuit 7 determines (selects) and outputs the weighting coefficient 115 according to the absolute values of the signal determination values Ich109 and Qch110. This weighting coefficient 115 is set to be inversely proportional to the magnitude (absolute value) of the signal determination value, and is stored in advance in a ROM table (not shown) provided in the weighting selection circuit 7. The weighting coefficient 115 corresponding to the magnitude of the signal determination value is read from the ROM table and output.

  The averaging circuit 8 calculates the average phase difference signal 114 based on the total number and total value of the phase difference signals 113 input from the PD (phase detector) 6 so far, and outputs the average phase difference signal 114 to the PD output control circuit 9. . Note that the phase difference signal 113 is a signal whose polarity represents the phase advance / delay and whose absolute value represents the degree (magnitude) of the phase advance / delay.

  The PD output control circuit 9 has a function of controlling whether or not to output the phase difference signal 113 according to the average phase difference signal 114, and calculates a difference between the phase difference signal 113 and the average phase difference signal 114. If the difference value is larger than a preset threshold value, it is determined that a phase jump has occurred, and the output of the phase difference signal 113 is stopped. In other cases, the phase difference signal 113 is left as it is. Output.

  The phase difference signal 114 whose output is controlled by the PD output control circuit 9 is input to a weighting multiplier 18 and is weighted by being multiplied by a weighting coefficient 115. The weighted phase difference signal 117 is input to the LPF 10. The other configuration is the same as that of FIG.

  Hereinafter, the operation of the present embodiment will be described. Here, the phase difference signal 113, which is a feature of the present invention, will be described. First, in the signal determination unit 5, the polarity signal (D) 111 and the error signal (E) 112 are calculated as shown in FIG. It is done. Then, the PD 6 generates a phase difference signal 113 from the polarity signal (D) and the error signal (E). The polarity of the phase difference signal 113 represents the phase advance / delay, and its absolute value represents the degree of phase advance / delay.

  Here, referring to FIG. 3, the phase difference signal control direction with respect to the phase shift of the received signal when the modulation method is 32QAM is shown. FIG. When the value deviates counterclockwise with respect to the value, control for giving the phase rotation in the clockwise direction is shown. However, as shown in FIG. 3B, when the phase shift of the received signal is further increased, it can be seen that an appropriate phase difference signal is not obtained as the signal is farther from the origin on the IQ phase plane. .

  Therefore, in the present invention, the larger the absolute value of the signal determination value of the received signal from which the phase difference signal is obtained, the more the phase difference signal is decreased, and conversely, the smaller the absolute value of the signal determination value is. The reliability of the phase difference signal is increased by weighting so as to increase the phase difference signal. In the case of 32QAM, since there are five absolute values of the signal determination values, the weight selection circuit 7 generates five weighting coefficients 115 according to the absolute values of these signal determination values.

  The weight selection circuit 7 reads and outputs five preset weighting factors from the ROM table according to the signal determination values Ich109 and Qch110. The output weighting coefficient 115 is multiplied by the multiplier 18 with respect to the phase difference signal 116 from the PD output control circuit 10 and is weighted.

  FIG. 4 shows changes in the phase difference signal with respect to the phase shift (degree) between when this weighting is performed (the proposed method) and when it is not performed (the conventional method). By the weighting according to the present invention, an appropriate phase difference signal is obtained with respect to an input phase difference larger than the conventional one.

  The PD output control circuit 9 detects the phase jump and limits the output of the phase difference signal 113, and has a function of preventing the phase jump from being followed. The method for detecting this phase jump is as follows. First, in the averaging circuit 8 in FIG. 1, the absolute value of the average value of the phase difference signal 113 input in the past is output. Therefore, the PD output control circuit 9 calculates the difference between the average phase difference signal 114 that is an average value from the averaging circuit 8 and the absolute value of the phase difference signal 113 at the present time, and this difference value is determined in advance. When the threshold value is exceeded, it is determined that a phase jump has occurred, and the output of the phase difference signal 113 at that time is stopped.

  FIG. 5 shows a phase change when a phase jump occurs suddenly from a state where the frequency synchronization is established. FIG. 5A shows the conventional method, and FIG. 5B shows the present proposal (the present invention). It is of the method. In the conventional system shown in (A), the phase information 119 and 120 from the numerically controlled oscillator 11 is the same in the opposite direction with respect to the amount of phase change caused by the difference between the local frequency of the oscillator 2 and the frequency of the carrier wave. It has increased. When a phase jump occurs in the form shown in the figure, it initially follows, but it cannot follow when the phase control direction is reversed in the middle, and the carrier is out of synchronization. Control is applied in the direction, resulting in loss of synchronization.

  On the other hand, in the system of the present invention shown in (B), when a phase jump occurs, control that does not follow the change in phase is applied. Therefore, although the phase difference is enlarged, an appropriate phase difference signal can be output even for a certain large phase difference by the above-described weighting. As a result, it becomes difficult to control in the direction of releasing the synchronization of the carrier wave, and the loss of synchronization of the carrier wave can be controlled.

  FIG. 6 is a block diagram of the second embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. In this example, a frame synchronization circuit 12 is added to the block of FIG. 1, and output control of the PD output control circuit 9 is performed by a frame synchronization signal 121 that is an output thereof. More specifically, in this example, the PD output control circuit 9 determines whether or not the frequency synchronization is established based on the frame synchronization signal 121 output from the frame synchronization circuit 12, and the synchronization is not achieved. The output of the phase difference signal 113 is output without limitation. As a result, it is not necessary to reduce the gain of the phase difference signal 113 at the time of carrier pull-in, so that better pull-in characteristics can be obtained. On the other hand, when the synchronization is established, the same control as the PD output control circuit 9 in FIG.

  FIG. 7 shows a third embodiment of the present invention. In this example, the weighting selection circuit 7 and the weighting multiplier 18 in the block of FIG. 1 are eliminated, and the phase difference signal 113 of the phase detector (PD) 6 is directly input to the LPF 10, and the PD of FIG. Instead of the output control circuit 9, a phase skip detection circuit 13 is provided. The characteristics of the LPF 10 are controlled by the phase jump detection result 122 from the phase jump detection circuit 13. Other configurations are the same as those in FIG.

  In this example, the LPF 10 is controlled based on the phase jump detection result 122 detected by the phase jump detection circuit 13. That is, when a phase jump occurs, the loop bandwidth of the LPF 10 is increased to facilitate pull-in, and conversely, when a phase jump does not occur, the loop bandwidth is reduced, thereby improving the follow-up property when the phase jump occurs and the steady state. It is possible to achieve both suppression of noise in the PLL loop.

  As described above, the phase skip detection method in the phase skip detection circuit 13 calculates the difference between the average phase difference signal 114 from the averaging circuit 8 and the absolute value of the current phase difference signal 113, and this difference value. According to the method, it is determined that the phase jump has occurred when the value exceeds a predetermined threshold value, and the phase jump does not occur otherwise.

  FIG. 8 is a diagram showing a fourth embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. In this example, as another example of the phase detector (PD) 6 in the first to third embodiments, the phase difference signal 113 is output according to the magnitude of the absolute value of the signal determination value of the received signal. The example which has the function to select whether or not is shown.

  In FIG. 8, the weight selection circuit 7 and the multiplier 18 of FIG. 1 are eliminated, and a PD output selection circuit 14 that receives the Ich 109 and Qch 110 outputs of the signal determination unit 5 is provided. The PD output selection signal 123 for selecting whether or not to output the signal 113 is obtained and sent to the phase detector (PD) 6 and the averaging circuit 8.

  The PD output selection circuit 14 generates the PD output selection signal 123 according to the magnitude of the absolute value of the signal determination value of the received signal. For example, the outermost signal points on the IQ phase plane By stopping the output of the phase difference signal 113 only at, control by phase information with lower reliability obtained from a signal point far from the origin on the phase plane is not performed.

  Therefore, the PD output selection circuit 14 generates a PD output selection signal 123 for selecting whether or not to output the phase difference signal from the reception signals Ich 109 and Qch 110, and sends it to the phase detector (PD) 6 and the averaging circuit 8. The phase detector (PD) 6 controls whether or not to output the phase difference signal 113 in accordance with the PD output selection signal 123. The averaging circuit 8 does not perform the averaging process if the PD output selection signal 123 is a signal for stopping the output of the phase difference signal. The other structure is the same as that of FIG.

  FIG. 9 is a diagram showing a fifth embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. In this example, a flip-flop (D) 15 that is a delay element and a selector 20 are added to the configuration of FIG. In this example, the follow-up to the phase jump is eliminated by an approach different from the first, second, and fourth embodiments.

  That is, the PD output control circuit 9 always stores the previous phase difference signal 113 from the phase detector (PD) 6, and when the phase skip is not detected, the current phase difference signal 113 is used as it is. (117) When the output is detected and the phase skip is detected, the previous phase difference signal is output as 117, thereby preventing the phase skip. The weighting coefficient 115 is similarly controlled. That is, when a phase skip is detected, the selector 20 selects a weighting factor for the previous phase difference signal that is the output of the flip-flop 15. The method for detecting the phase jump is the same as the previous example.

  In each of the above embodiments, a quasi-synchronous detection method is used as the detection method of the demodulator, and the input modulation signal is a quadrature modulation signal such as QPSK or QAM, but the error signal after correcting the frequency and phase offset and If the phase rotation signal at the time of correcting the frequency and the phase offset is obtained, it is not always necessary to perform the quasi-synchronous detection, and the modulation method may be other than QPSK and QAM, for example, PSK and APSK other than QPSK. It is. Moreover, it can be realized by appropriately combining the above embodiments.

  Of course, in each of the embodiments described above, these can be appropriately combined.

It is a block diagram of a first embodiment of the present invention. It is a figure explaining the error signal E and the polarity signal D which are the outputs of the signal determination device 5 in FIG. It is a figure which shows the example of control of the phase difference signal in the case of 32QAM, (A) is a conventional system, (B) is a thing in the case of the system by this invention. It is a figure which shows the example of a characteristic of phase shift (degree) vs phase difference signal in comparison with the conventional system. It is a figure which shows the example of the variation | change_quantity of the phase accompanying a time change, (A) is a conventional system, (B) is a thing in the case of the system by this invention. It is a block diagram of 2nd embodiment of this invention. It is a block diagram of 3rd embodiment of this invention. It is a block diagram of 4th embodiment of this invention. It is a block diagram of a fifth embodiment of the present invention. It is a block diagram of the demodulator which shows a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Quadrature demodulator 2 Local oscillator 3 A / D converter 4 Phase rotator 5 Signal determination device 6 Phase detector (PD)
7 Weighting selection circuit 8 Averaging circuit 9 PD output control circuit 10 LPF
DESCRIPTION OF SYMBOLS 11 Numerically controlled oscillator 12 Frame synchronous circuit 13 Phase skip detection circuit 15 Flip-flop 18 Multiplier 20 Selector

Claims (16)

A means for detecting a quadrature component by receiving a quadrature modulation signal, a phase correction means for performing phase correction of the detection output, and a signal determination means for performing signal determination of each component after the phase correction to demodulate the quadrature component And a means for detecting a phase shift of the output of the signal determination means and generating a phase difference signal for the phase correction means,
And a weighting means for weighting the phase difference signal in accordance with the magnitude of the output of the signal determination means.   The weighting unit sets the error signal to a smaller value as the output level of the signal determination unit increases, and sets the error signal to a higher level as the output level of the signal determination unit decreases. The demodulator according to claim 1.   3. The demodulator according to claim 1, further comprising phase difference signal suppression means for detecting an instantaneous phase shift and suppressing output of the phase difference signal.   3. The apparatus according to claim 1, further comprising means for detecting an instantaneous phase shift and outputting a phase difference signal immediately before the phase difference signal, wherein the weighting means weights the phase difference signal immediately before. Demodulator.   The loop filter having the phase difference signal as an input and means for detecting an instantaneous phase shift and controlling the expansion of the frequency band of the loop filter according to claim 1 or 2. Demodulator.   6. The instantaneous phase shift is detected when the average value of the error signal and the current error signal are compared and the difference exceeds a predetermined threshold value. The demodulator described.   7. The method according to claim 1, further comprising means for determining a frequency synchronization state of the output of the signal determination means and stopping the inhibition operation of the phase difference signal inhibition means in the synchronization state. Demodulator.   8. The demodulator according to claim 1, further comprising means for suppressing the output of the phase difference signal in accordance with the output level of the signal determination means. A step of detecting a quadrature component by receiving a quadrature modulation signal, a phase correction step of performing phase correction of the detection output, and a signal determination step of performing signal determination of each component after the phase correction to demodulate the quadrature component And a step of detecting a phase shift of the output by the signal determination step and generating a phase difference signal for the phase correction step,
And a weighting step for weighting the phase difference signal in accordance with the magnitude of the output in the signal determination step.   In the weighting step, the error signal is set to be smaller as the output magnitude in the signal determination step is larger, and the error signal is set to be larger as the output magnitude in the signal determination step is smaller. The demodulation method according to claim 9.   The demodulation method according to claim 9 or 10, further comprising a phase difference signal suppression step of detecting an instantaneous phase shift and suppressing output of the phase difference signal.   11. The method according to claim 9, further comprising a step of detecting an instantaneous phase shift and outputting a phase difference signal immediately before the phase difference signal, wherein the weighting step weights the phase difference signal immediately before. Demodulation method.   The loop filter having the phase difference signal as an input, and the step of detecting an instantaneous phase shift and controlling the expansion of the frequency band of the loop filter, further comprising: Demodulation method.   14. The instantaneous phase shift is detected when the average value of the error signal and a current error signal are compared and the difference exceeds a predetermined threshold value. The demodulation apparatus method as described.   15. The method according to claim 9, further comprising: determining a frequency synchronization state of the output in the signal determination step, and stopping the suppression operation of the phase difference signal suppression step in the case of the synchronization state. Demodulation method. The demodulation method according to any one of claims 9 to 15, further comprising a step of suppressing the output of the phase difference signal in accordance with the magnitude of the output in the signal determination step.

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