JPH10200591A - Automatic frequency control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance performance and to improve code error ratio characteristic by writing the frequency error of each reception slot in a frequency error memory and using a value of the frequency error memory of each reception slot as an automatic frequency control initial value at burst leading of each reception slot. SOLUTION: A frequency error detecting part 1 takes out a frequency error from an input signal. The frequency error is balanced, when it is passed through an LPF 2, and noise that affects an operation of the frequency error is reduced. An output of the LPF 2 is written in a frequency error memory 4 in the latter half of a reception slot, where the frequency error is stable. An initial lead-in of the LPF 2 becomes easy by inputting a value, that is written in the memory 4 as an initial value of the LPF 2 at the time of the start of the next slot. Also, a memory write controlling part 5 detects various reception states and controls so that a value of the frequency error which is optimum to the states is written in the memory 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic frequency control circuit for a transmission signal whose amplitude or angle is modulated by a digital signal, mainly for wirelessly transmitting digital data.

[0002]

2. Description of the Related Art In recent years, digitalization of wireless communication has been progressing in the mobile communication field represented by a car telephone from the viewpoint of improving confidentiality, affinity with an ISDN network or a computer, and effective use of frequency resources. doing. In digital mobile radio communication, for example, as specified in the Radio System Development Center Standards RCRSTD-27 or RCRSTD-28, which are the standards for digital cellular telephones or digital cordless telephones in Japan, the modulation scheme is different. Dynamic encoding phase shift keying (hereinafter referred to as differential P
The π / 4 shift QPSK, which is one type of SK, is divided into units called time slots of a fixed time width on one carrier frequency (hereinafter, referred to as a carrier) as a multiple access system, and two or more Time-division multiple access (hereinafter referred to as TDMA) in which communication is performed by allocating the wireless channels in a time-division manner is often used. In a receiving section of a digital radio apparatus using differential PSK, delay detection or synchronous detection is used as a demodulation method. The demodulated received signal is subjected to various frequency conversions on the transmission side and the reception side and then becomes a demodulator input. Therefore, the sum of the frequency errors corresponding to the respective frequency stability appears as the received signal frequency error. Also, when the tank limiter method is used as the carrier recovery circuit, even if the tank uses a single-tuned filter with a small phase rotation, the phase of the output reproduction carrier wave corresponds to the input burst signal frequency deviation from the tank center frequency. An error occurred, resulting in a deterioration in the code disapproval rate.

However, a method of controlling the frequency so that the average value of each input burst frequency becomes the center frequency of the carrier wave or controlling a local oscillation circuit for frequency conversion of the demodulator input is often used today.

Hereinafter, a conventional automatic frequency control circuit will be described with reference to the drawings. FIG. 13 is a block diagram of a conventional automatic frequency control circuit, and FIG. 14 is a block diagram of the same low-pass filter. In FIG. 13, reference numeral 1 denotes a frequency error detection unit that detects a frequency error from an input signal such as a received modulation signal, and 2 denotes a low-pass filter (hereinafter, LPF) for reducing noise of the frequency error output from the frequency error detection unit 1. ), For example, as shown in FIG. In the figure, 201 is a subtractor, 202 is a constant multiplier for multiplying an input signal by α, 203 is an adder, and 204 is a delayer for delaying one symbol. Note that α is set in the range of 0 ≦ α <1, and at 0, the filter action is stopped, and as the value approaches 1, the band becomes narrower. Reference numeral 3 denotes a frequency correction unit that performs frequency correction from a frequency error in which noise output from the LPF 2 has been reduced.

[0005]

However, in the above-described conventional automatic frequency control circuit, it takes time until the average value of the frequency error converges due to the transient response of the LPF 2, and the reception frequency is sufficiently high so that the noise can be ignored. If so, a symbol determination error occurs. For a received wave that has undergone high-speed fading, the LPF
If the band of 2 is narrow, it cannot follow. Therefore, the band of the LPF 2 must be widened to some extent in order to accelerate the convergence and follow-up of the phase error. As a result, the carrier power-to-noise power ratio (C / N) of the reproduced baseband carrier is reduced, and the code error rate characteristic is reduced. There was a problem that the characteristics deteriorated from the theoretical characteristics.

Accordingly, the present invention provides a performance of an automatic frequency control circuit of a receiver by narrowing a band of a filter for reducing noise of a frequency error signal and quickly converging the frequency error signal immediately after the start of the filter operation. It is an object of the present invention to provide an automatic frequency control circuit which can improve the bit error rate characteristics by improving the error rate.

[0007]

According to the present invention, there is provided an automatic frequency control circuit for a receiver in time division multiple access communication, comprising: a frequency error memory for storing a frequency error; A memory write control unit for performing a write control of a memory, the frequency error of each reception slot is written in the frequency error memory, and the frequency error memory of each reception slot is used as an initial value of automatic frequency control at a burst head of each reception slot. Is used.

According to a second aspect of the present invention, in the first aspect of the present invention, the memory write control unit includes a frequency error change polarity determination unit that detects a polarity of a change in frequency error. And controls writing to the frequency error memory according to the polarity of the change in the frequency error.

According to a third aspect of the present invention, in the first or second aspect of the invention, the memory write control unit includes a reception intensity detection unit that detects a reception intensity and a state determination of the reception intensity. The receiving strength state determining unit controls writing to the frequency error memory based on the receiving strength.

According to a fourth aspect of the present invention, in the first aspect of the present invention, the memory write control section generates a reproduced symbol clock from a phase- or frequency-modulated received signal. The symbol clock reproduction state determination unit determines the state of the symbol clock reproduction unit, and controls writing to the frequency error memory based on the symbol clock reproduction state determined by the symbol clock reproduction state determination unit.

According to a fifth aspect of the present invention, in the first aspect of the present invention, the memory write control unit is configured to determine the phase of the determined symbol by using a determination phase signal and a detector. A phase error detection unit for obtaining a difference from the output detection phase, and a phase error state determination unit for determining a state of the phase error, wherein writing to the frequency error memory is controlled by an output value of the phase error unit. I do.

According to a sixth aspect of the present invention, in the first aspect of the present invention, the memory write control unit includes a demodulated signal bit error detection unit and a bit error detection state determination unit. And controls writing to the frequency error memory according to the bit error detection state.

According to a seventh aspect of the present invention, in the first aspect of the present invention, the memory write control unit is configured to determine the frequency error of the previous reception slot and the current reception slot in each reception slot. An error change amount detection unit that detects a frequency change amount that is a change amount with respect to the frequency error, and an error change amount state determination unit that performs a state determination of the change amount of the frequency error. Controls writing to the frequency error memory.

According to an eighth aspect of the present invention, in the first aspect of the present invention, the receiver is a diversity receiver having a plurality of antennas, and the memory write control unit detects the reception intensity. A detection unit, a reception intensity relative value calculation unit that calculates a relative value of the reception intensity for each antenna, and a reception intensity relative value state determination unit,
The writing to the frequency error memory in each reception slot is controlled by the relative value of the reception intensity.

According to a ninth aspect of the present invention, in the first or the eighth aspect of the present invention, the receiver is a diversity receiver having a plurality of antennas, and the memory write control unit determines A phase error detector for calculating a difference between a determination phase signal, which is a symbol phase, and a detection phase output from the detector, a phase error relative value calculator for calculating a relative value of a phase error for each antenna, and a phase error A relative value state determination unit controls the writing to the frequency error memory in each reception slot based on the relative value of the phase error.

According to a tenth aspect of the present invention, in an automatic frequency control circuit in a diversity receiver having a plurality of antennas for time division multiple access communication, an antenna common frequency error memory for storing a common antenna frequency error, A frequency error selector for selecting a frequency error related to one antenna from a frequency error of the antenna, and a frequency selector control unit for controlling the frequency error selector, wherein an output from the frequency error selector of each reception slot is output to the antenna common frequency. Write to error memory,
At the beginning of the burst of each reception slot, the value of the antenna common frequency error memory of each reception slot is used as an automatic frequency control initial value.

According to an eleventh aspect of the present invention, in the invention according to the tenth aspect, the frequency selector control section calculates a relative value of the reception intensity with a reception intensity detection section for detecting the reception intensity of each antenna. A reception intensity relative value calculation unit, and a reception intensity maximum antenna determination unit that determines the antenna with the highest reception intensity, and the frequency error of the antenna with the maximum reception intensity as the output of the frequency error selector and the frequency This is the value written to the error memory.

According to a twelfth aspect of the present invention, in the tenth or eleventh aspect, the frequency selector control unit calculates a relative value of a phase error for each antenna. And a phase error minimum antenna determination unit that determines the antenna with the smallest phase error, and the frequency error of the antenna with the smallest phase error as the output of the frequency error selector and the value written to the frequency error memory. I do.

[0019]

According to a first aspect of the present invention, a symbol having a stable frequency error in each reception slot, for example, a frequency error at that time is written in a frequency error memory in the latter half of each reception slot, and the next slot start is started. The value written in the frequency memory is input to the LPF as the initial value.
Transient response is suppressed even in a narrow band filter operation.

According to the second aspect of the present invention, the polarity of the change in the frequency error of the reception slot is monitored by the frequency error change polarity determination unit, and the frequency error between the transmission side and the reception side is usually constant. If the polarity determination unit determines that the frequency error is in the same direction, it is considered that there is a frequency error between the transmitting side and the receiving side, and writing to the frequency error memory is performed. By writing 0 to the frequency error memory
This has the effect of suppressing the effect of the output data error of the frequency error detector due to noise.

According to a third aspect of the present invention, when the reception intensity of the reception slot is high, it is considered that the operation of the demodulation unit is stable, the frequency error memory is written, and when the reception intensity of the reception slot is low, C / N The detection output data of the demodulation unit is deemed to have an error due to deterioration, and 0 is written to the frequency error memory, or the frequency error memory is not updated. Has the effect of suppressing the effect of

According to a fourth aspect of the present invention, when the symbol clock reproduction state is stable, for example, when the digital PLL incorporated in the symbol clock reproduction unit is locked, the operation of the demodulation unit is considered to be stable, and the frequency error When writing to the memory is performed and the symbol clock reproduction state is unstable, for example, when the digital PLL incorporated in the symbol clock reproduction unit is not locked, the accuracy of the reproduction symbol clock is deteriorated. The output data is regarded as having an error, and 0 is written to the frequency error memory or the frequency error memory is not updated, thereby suppressing the influence of the output data error of the frequency error detection unit due to the deterioration of the accuracy of the reproduced symbol clock. It has the effect of doing.

According to a fifth aspect of the present invention, when the phase error is small, it is considered that the operation of the demodulation unit is stable, and the frequency error memory is written. When the phase error is large, C / N
It is assumed that an error has occurred in the detection output data of the demodulation unit due to deterioration of the frequency error memory, and 0 is written to the frequency error memory or the frequency error memory is not updated, so that the output data of the frequency error detection unit due to the deterioration of the phase error is written. It has the effect of suppressing the effects of errors.

According to a sixth aspect of the present invention, when a bit error does not occur, for example, the time division multiple access apparatus detects a unique word or determines that no bit error has occurred by checking an error detection code. If the operation of the demodulation unit is considered to be stable, the frequency error memory is written, and if a bit error occurs, for example, the time division multiple access device cannot detect the unique word, or checks the error detection code. If it is considered that a bit error has occurred, the detection output data of the demodulation unit is regarded as having an error, and 0 is written to the frequency error memory, or the frequency error memory is not updated, so that the frequency error This has the effect of suppressing the effect of the output data error of the detection unit.

According to a seventh aspect of the present invention, when the amount of change in frequency is small, it is considered that the operation of the demodulation unit is stable, and writing to the frequency error memory is performed.
By assuming that extremely strong external noise has arrived, writing 0 to the frequency error memory or not updating the frequency error memory has the effect of suppressing the effect of the output data error of the frequency error detection unit.

According to the eighth aspect of the present invention, when the relative reception intensity of a certain antenna is large for each antenna, the operation of the demodulation unit input from that antenna is considered to be stable, and the frequency error memory of the antenna is regarded as stable. When writing is performed and the relative value of the reception intensity of a certain antenna is small, it is considered that the C / N of the antenna deteriorates and the detection output data of the demodulation unit has an error, and 0 is stored in the frequency error memory of the antenna. By not writing or updating the frequency error memory, it has the effect of suppressing the effect of the output data error of the frequency error detector due to the deterioration of the reception intensity.

According to a ninth aspect of the present invention, when the phase error relative value of a certain antenna is small for each antenna, the operation of the demodulation unit input from that antenna is considered to be stable, and the frequency error memory of that antenna is regarded as stable. When writing is performed and the relative value of the phase error of a certain antenna is large, it is considered that the C / N of the antenna deteriorates and the detection output data of the demodulation unit has an error, and 0 is stored in the frequency error memory of the antenna. By not writing or updating the frequency error memory, it has the effect of suppressing the influence of the output data error of the frequency error detection unit due to the deterioration of the phase error.

According to a tenth aspect of the present invention, in the diversity system, the frequency error for the most reliable output data of the frequency error detection unit is corrected by writing the frequency error relating to the antenna having the best reception state into the frequency error memory. It has the effect of being able to do it.

According to an eleventh aspect of the present invention, in the diversity system, the frequency error correction for the most reliable output data of the frequency error detection unit is performed by writing the frequency error relating to the antenna having the best reception strength into the frequency error memory. It has the effect of being able to do it.

According to a twelfth aspect of the present invention, in a diversity system, a frequency error relating to an antenna having the best phase error is written in a frequency error memory, whereby a frequency error correction for the most reliable output data of the frequency error detector can be performed. It has the effect of being able to do it.

(Embodiment 1) FIG. 1 is a block diagram of an automatic frequency control circuit according to Embodiment 1 of the present invention. In FIG. 1, 1 is a frequency error detection unit, and 2 is an LP
F and 3 are frequency correction units, which are the same as those in the conventional example of FIG. Reference numeral 4 denotes a frequency error memory, which is provided with a memory for each reception slot and has a structure suitable for digital signal processing and circuit integration by a latch circuit driven by a symbol clock or a memory updated by the clock. It is preferable that
Reference numeral 5 denotes a memory write control unit. The configuration of the low-pass filter is the same as the conventional example shown in FIG.

The operation of the automatic frequency control circuit configured as described above will be described below. Modulation input signal,
Alternatively, a frequency error component is extracted by the frequency error detection unit 1 from an input signal such as a reproduction baseband signal. L
By passing through the PF2, the frequency error is averaged, and noise affecting the frequency error calculation is reduced. Symbols for which the initial pull-in of the demodulation operation has been completed and the frequency error has stabilized, for example, L
The stable output of PF2 is written to frequency error memory 4. At the start of the next slot, the frequency error memory 4
Is input as the initial value of LPF2, the LPF2 operates with the value of the previous slot as the initial value, so that the initial pull-in of LPF2 is facilitated.
Further, the memory write control unit 5 detects various reception states, and performs write control so as to write an optimal frequency error value to the frequency error memory 4 for the state. This operation is performed for each reception slot.

(Embodiment 2) In Embodiment 2, the memory write control section 5 in Embodiment 1 is constituted by a frequency error change polarity determination section. FIG.
FIG. 10 is a block diagram of a frequency error change polarity determination unit of the automatic frequency control circuit according to Embodiment 2 of the present invention.

In FIG. 2, reference numeral 11 denotes a lead / lag determining unit which determines the polarity of the detected change in the frequency error. 12
Is an up / down counter that controls the counter based on the result of the advance / delay determining unit 11. Reference numeral 13 denotes a symbol number threshold value setting memory for setting a threshold value of the counter value. 1
4 is a symbol number threshold judging unit, and an up / down counter 1
The value of 2 is compared with the value of the symbol number threshold value setting memory 13. Reference numeral 15 denotes a memory write timing control unit.
Control the timing of writing to the frequency error memory 4;
Whether or not to write is determined based on the result of the symbol number threshold determination unit 14.

The operation of the frequency error change polarity determining section configured as described above will be described below. When the advance / delay determining section 11 determines that it is advanced, the up / down counter 12 is incremented by +1. When it is determined that it is delayed, the up / down counter 12 is decremented by −1. When the advance / delay determining unit 11 determines that there is neither advance nor delay, the up / down counter 12 may have a function of holding the value of the counter.

Whether the absolute value of the value of the up / down counter 12 exceeds the value of the symbol number threshold value setting memory 13 is determined by a symbol number threshold determination 14. If the threshold is exceeded, it is considered that there is a frequency error, and the memory write timing control unit 15 performs writing to the frequency error memory 4. If the threshold is not exceeded, it is considered that there is no frequency error, and the memory write timing control unit 15 does not write to the frequency error memory 4. Alternatively, 0 may be written in the frequency error memory 4.

(Embodiment 3) In Embodiment 3, the memory write control unit 5 in Embodiment 1 is constituted by a reception intensity detection unit and a reception intensity state determination unit. FIG. 3 is a block diagram of a reception intensity detection unit and a reception intensity state determination unit of the automatic frequency control circuit according to Embodiment 3 of the present invention.

In FIG. 3, reference numeral 21 denotes a reception intensity detection unit.
A reception strength, for example, an RSSI value is derived from the reception signal.
A reception intensity threshold setting memory 22 sets a threshold value of the reception intensity. Reference numeral 23 denotes a reception intensity threshold determination unit which stores a value of the reception intensity detection unit 21 and a reception intensity threshold setting memory 22.
Is compared with the value of Reference numeral 15 denotes a memory write timing control unit which controls the timing of writing to the frequency error memory 4 and determines whether or not to perform writing based on the result of the reception intensity threshold determination unit 23.

The operation of the reception strength detection section and the reception strength state determination section configured as described above will be described below. The reception intensity detection unit 21 derives the reception intensity, and the reception intensity threshold determination unit 23 determines whether the reception intensity exceeds the value of the reception intensity threshold setting memory 22. If the threshold has been exceeded, the frequency error detector 1 considers that the frequency error has been calculated with high accuracy, and the memory write timing controller 15
Write to. If you have not crossed the threshold,
The output of the frequency error detection unit 1 is considered to include many uncertain elements, and the memory write timing control unit 15 does not perform writing to the frequency error memory 4. Or
0 may be written to the frequency error memory 4.

(Embodiment 4) In Embodiment 4, the memory write control unit 5 in Embodiment 1 is constituted by a symbol clock reproduction state determination unit. FIG. 4 is a block diagram of a symbol clock reproduction state determination unit of the automatic frequency control circuit according to Embodiment 4 of the present invention.

In FIG. 4, reference numeral 31 denotes a symbol clock recovery unit which performs clock recovery using a received signal or a baseband signal as input. Reference numeral 32 denotes a reproduced symbol clock phase shift determining unit, which determines whether the phase pull-in operation has been completed. Reference numeral 15 denotes a memory write timing control unit which controls the write timing to the frequency error memory 4 and determines whether or not to perform writing based on the result of the reproduced symbol clock phase shift determining unit 32.

The operation of the symbol clock reproduction state determination section configured as described above will be described below. The symbol clock recovery unit 31 performs clock recovery using a received signal or a baseband signal as input. The symbol clock generated by the symbol clock reproducing unit 31 is input to the reproduced symbol clock phase shift determining unit 32, and the pull-in operation of the symbol clock reproducing unit 31 is completed to determine whether there is a phase shift. For example, when the received symbol clock is not good and the reproduced symbol clock has much jitter and the pull-in operation is not completed, the reproduced symbol clock phase shift determining unit 32 determines that there is a phase shift.

Here, when the reproduced symbol clock phase shift judging section 32 judges that there is a phase shift, the frequency error detecting section 1 considers that the calculation of the frequency error with high accuracy has been performed, and the memory write timing control section 15 Writing to the frequency error memory 4 is performed. If the threshold is not exceeded, the output of the frequency error detection unit 1 is considered to include many uncertainties, and the memory write timing control unit 15 does not write to the frequency error memory 4. Alternatively, 0 may be written in the frequency error memory 4.

(Embodiment 5) In Embodiment 5, the memory write control section 5 in Embodiment 1 is constituted by a phase error detection section and a phase error state determination section. FIG. 5 is a block diagram of a phase error detection unit and a phase error state determination unit of the automatic frequency control circuit according to the fifth embodiment of the present invention.

In FIG. 5, reference numeral 41 denotes a phase error detecting unit.
The difference between the detected phase signal and a determination phase signal which is a determination result of the phase signal is calculated. Reference numeral 42 denotes a phase error threshold value setting memory for setting a threshold value of the phase error. Reference numeral 43 denotes a phase error threshold determination unit which compares the value of the phase error detection unit 41 with the value of the phase error threshold value setting memory 42. Fifteen
Is a memory write timing control unit that controls the write timing to the frequency error memory 4 and determines whether or not to write based on the result of the phase error threshold determination unit 43.

The operation of the phase error detecting section and the phase error state judging section configured as described above will be described below. The difference between the phase signal detected by the phase error detection unit 41 and the judgment phase signal which is the judgment result of the phase signal is derived to derive a phase error, and the phase error exceeds the value of the phase error threshold value setting memory 42. The determination is made by the phase error threshold determination unit 43.

If the threshold has been exceeded, the frequency error detector 1 assumes that the frequency error has been calculated with high accuracy, and the memory write timing controller 15 performs writing to the frequency error memory 4. If the threshold has not been exceeded, the output of the frequency error detector 1 is considered to contain many uncertainties, and the memory write timing controller 1
5 does not write to the frequency error memory 4.
Alternatively, 0 may be written in the frequency error memory 4.

(Embodiment 6) In Embodiment 6, the memory write control section 5 in Embodiment 1 is constituted by a bit error detection section and a bit error detection state determination section.

FIG. 6 is a block diagram of a bit error detection section and a bit error detection state determination section of the automatic frequency control circuit according to the sixth embodiment of the present invention.

In FIG. 6, reference numeral 51 denotes a time-division multiple access device for sending out a demodulated signal, which is an output of the demodulation unit, only in a specific allocated time zone. Reference numeral 52 denotes a unique word detection unit which uses a unique word in TDMA communication to synchronize with the transmitting and receiving sides, and detects the unique word, and is constituted by a digital correlator.

Reference numeral 53 denotes an error detection code check unit for checking an error detection code, such as an error detection CRC code check. Reference numeral 54 denotes a bit error detection state determination unit which determines a bit error occurrence state.
Reference numeral 15 denotes a memory write timing control unit which controls the write timing to the frequency error memory 4 and determines whether or not to write based on the result of the bit error detection state determination unit 54.

The operation of the bit error detecting section and the bit error detecting state judging section configured as described above will be described below. A time-division frame is created by the time-division multiple access device 51, and the unique word detection unit 52 attempts to detect a unique word in the frame.
The unique word detection unit 52 outputs an HI level signal to the bit error detection state determination unit 54 when a unique word cannot be detected, and outputs a LOW level signal when a unique word can be detected. In addition, the error detection code check unit 53 checks an error of the frame. The error detection code checking unit 53 outputs an HI level signal to the bit error detection state determination unit 54 when there is an error in the error detection code, and outputs a LOW level signal when there is no error in the error detection code.

The bit error detection state determination section 54 determines the error state of the frame. As a determination method, the OR of the output of the unique word detection section 52 and the output of the error detection code check section 53 or AND is used. ,
If the output result is HI, the frequency error detection unit 1 considers that the calculation of the frequency error with high accuracy has been performed, and the memory write timing control unit 15 performs writing to the frequency error memory 4. If the output result is LOW, the frequency error detection unit 1 considers that many uncertainties are included, and the memory write timing control unit 15 does not perform writing to the frequency error memory 4. Alternatively, 0 may be written in the frequency error memory 4.

(Embodiment 7) In Embodiment 7, the memory write control section 5 in Embodiment 1 is constituted by an error change amount detection section and an error change amount state determination section. FIG. 7 is a block diagram of an error change amount detection unit and an error change amount state determination unit of the automatic frequency control circuit according to the seventh embodiment of the present invention.

In FIG. 7, reference numeral 61 denotes an error change amount detection unit which calculates the difference between the frequency error signal output from the frequency error detection unit 1 and the output of the frequency error memory 4, and calculates the frequency error of the previous slot and the frequency of the current slot. The amount of change in the error is detected. Reference numeral 62 denotes an error change amount threshold value setting memory for setting a threshold value of the change amount of the frequency error. Reference numeral 63 denotes an error change amount threshold determination unit which compares the value of the error change amount detection unit 61 with the value of the error change amount threshold value setting memory 62. Reference numeral 15 denotes a memory write timing control unit,
The write timing is controlled, and whether or not to write is determined based on the result of the error change threshold determining unit 63.

The operation of the error change amount detector and the error change amount state determiner configured as described above will be described below. The difference between the frequency error signal output from the frequency error detector 1 and the output of the frequency error memory 4 is calculated by the error change detector 61 to derive a change between the frequency error of the previous slot and the frequency error of the current slot. The error change amount threshold determination unit 63 determines whether the change amount of the frequency error exceeds the value of the error change amount threshold value setting memory 62.

If the threshold has been exceeded, the frequency error detection unit 1 assumes that the calculation of the frequency error has been performed with high accuracy, and the memory write timing control unit 15 performs writing to the frequency error memory 4. If the threshold is not exceeded, the frequency error detection unit 1 considers that many uncertain factors such as the sudden arrival of large noises are included, and the memory write timing control unit 15 does not perform writing to the frequency error memory 4. . Alternatively, 0 may be written in the frequency error memory 4.

(Eighth Embodiment) In the eighth embodiment, in the diversity receiver having a plurality of antennas in the first embodiment, the memory write control unit 5 is replaced by the reception intensity detection unit, the reception intensity relative operation unit, and the reception intensity relative operation unit. It is configured by a value state determination unit. FIG. 8 is a block diagram of a reception intensity detection unit, a reception intensity relative operation unit, and a reception intensity relative value state determination unit of the automatic frequency control circuit according to Embodiment 8 of the present invention. Here, description will be made on the assumption that the number of antennas is four.

In FIG. 8, reference numeral 71 denotes a first reception intensity detector, which derives a reception intensity, for example, an RSSI value from a reception signal of the first antenna. 72 is a second reception strength detection unit,
Reference numeral 73 denotes a third reception intensity detection unit, and 74 denotes a fourth reception intensity detection unit, which derives reception intensity for the second, third, and fourth antennas, respectively. Reference numeral 75 denotes a reception intensity relative value calculation unit that calculates a relative value of the reception intensity for each of the first, second, third, and fourth antennas.

Reference numeral 76 denotes a reception intensity relative value threshold value setting memory for setting a threshold value of the relative value of the reception intensity. Reference numeral 77 denotes a first reception intensity relative value threshold determination unit which compares the relative value of the first antenna output from the reception intensity relative value calculation unit 75 with the value of the reception intensity relative value threshold value setting memory 76. I do. Reference numeral 78 denotes a second reception intensity relative value threshold determination unit, 79 denotes a third reception intensity relative value threshold determination unit, and 80 denotes a fourth reception intensity relative value threshold determination unit.
The relative value of the reception intensity for the second, third, and fourth antennas is compared with the value of the reception intensity relative value threshold value setting memory 76.

Reference numeral 81 denotes a first memory write timing control unit which controls the write timing of the first antenna to the frequency error memory 4 for the first antenna and the first reception intensity relative value threshold determination unit 77 Whether or not to write is determined according to the result. Reference numeral 82 denotes a second memory write timing control unit, 83 denotes a third memory write timing control unit, and 84 denotes a fourth memory write timing control unit, and frequency errors related to the second, third, and fourth antennas, respectively. The timing of writing to the memory 4 is controlled.

The operation of the reception intensity detection unit, reception intensity relative calculation unit, and reception intensity relative value state determination unit configured as described above will be described below. First reception intensity detection unit 7
1 to derive the reception intensity of the first antenna, and the second reception intensity detection unit 72, the third reception intensity detection unit 73, and the fourth reception intensity detection unit 74 respectively
The reception intensity for the second, third, and fourth antennas is derived. The relative value of the reception intensity for each antenna is calculated by the reception intensity relative value calculation unit 75. As an example of the calculation of the relative value, a processing method of calculating a ratio with the reception intensity of each antenna based on the reception intensity of the antenna having the highest reception intensity is given as an example. In this case, it is assumed that the reception intensity relative value outputs a large value for an antenna having a high reception intensity and a small value for an antenna having a high reception intensity.

The first reception intensity relative value threshold determination unit 77 determines whether the reception intensity relative value derived for each antenna exceeds the value of the reception intensity relative value threshold value setting memory 76,
A determination is made for each antenna by a second reception intensity relative value threshold determination unit 78, a third reception intensity relative value threshold determination unit 79, and a fourth reception intensity relative value threshold determination unit 80. First
If the threshold is exceeded for the antenna of the first antenna, the frequency error detection unit 1 for the first antenna considers that an accurate calculation of the frequency error has been performed, and the first memory write timing control unit 81 Is written to the frequency error memory 4.

If the threshold is not exceeded, the output of the frequency error detector 1 for the first antenna is regarded as containing many uncertainties, and the memory write timing controller 15 writes the data to the frequency error memory 4. No. Alternatively, 0 may be written in the frequency error memory 4. This performs the same operation for the first, second, and third antennas.

(Embodiment 9) The ninth embodiment is different from the first embodiment in a diversity receiver having a plurality of antennas in that the memory write control unit 5 includes a phase error detection unit, a phase error relative value calculation unit, It is configured by an error relative value state determination unit. FIG. 9 is a block diagram of a phase error detector, a phase error relative value calculator, and a phase error relative value state determiner of the automatic frequency control circuit according to the ninth embodiment of the present invention. Here, the description will be made simply assuming that there are four antennas.

In FIG. 9, reference numeral 91 denotes a first phase error detector, which calculates a difference between a detected phase signal related to the first antenna and a determination phase signal which is a determination result of the phase signal, and calculates a phase error. To detect. Reference numeral 92 denotes a second phase error detection unit, 93 denotes a third phase error detection unit, and 94 denotes a fourth phase error detection unit, which respectively detect phase errors for the second, third, and fourth antennas. To detect.

Reference numeral 95 denotes a phase error relative value calculator which calculates the relative value of the phase error for each of the first, second, third and fourth antennas. Reference numeral 96 denotes a phase error relative value threshold value setting memory for setting a relative threshold value of the phase error. 97 is a first phase error relative value threshold determination unit,
The relative value of the first antenna from the phase error relative value calculation unit 95 is compared with the value of the phase error relative value threshold value setting memory 96. Reference numeral 98 denotes a second phase error relative value threshold determination unit, 99 denotes a third phase error relative value threshold determination unit, and 100 denotes a fourth phase error relative value threshold determination unit. , And the values of the phase error relative value threshold value setting memory 96 are compared. A first memory write timing control unit 81 controls the write timing of the first antenna to the frequency error memory 4 for the first antenna, and writes the result based on the result of the first reception intensity relative value threshold determination unit 77. It is determined whether or not to do so. Reference numeral 82 denotes a second memory write timing control unit, 83 denotes a third memory write timing control unit, and 84 denotes a fourth memory write timing control unit, and frequency errors related to the second, third, and fourth antennas, respectively. The timing of writing to the memory 4 is controlled.

The operation of the phase error detecting section, the phase error relative value calculating section, and the phase error relative value state judging section configured as described above will be described below. The first phase error detector 91 derives a phase error for the first antenna, and the second phase error detector 92, the third phase error detector 93, and the fourth phase error detector 94 , Respectively, to derive phase errors for the second, third and fourth antennas. The relative value of the phase error for each antenna is calculated by the phase error relative value calculator 95. As an example of the calculation of the relative value, a processing method of calculating a ratio with the phase error of each antenna based on the phase error of the antenna having the least phase error is given as an example. In this case, it is assumed that the phase error relative value outputs a large value for an antenna with a small phase error and a small value for an antenna with a large phase error.

The first reception intensity relative value threshold determination unit 97 determines whether the phase error relative value derived for each antenna exceeds the value of the reception intensity relative value threshold value setting memory 96,
A second phase error relative value threshold determination unit 98, a third phase error relative value threshold determination unit 99, and a fourth phase error relative value threshold determination unit 100 make a determination for each antenna. If the threshold has been exceeded for the first antenna, the first
The frequency error detection unit 1 regarding the antenna with regard to this antenna considers that the calculation of the frequency error with high accuracy has been performed, and the first memory write timing control unit 81 writes the frequency error into the frequency error memory 4 with respect to the antenna.

If the threshold has not been exceeded, the output of the frequency error detector 1 for the first antenna is considered to contain many uncertainties, and the memory write timing controller 15 writes the data to the frequency error memory 4. No. Alternatively, 0 may be written in the frequency error memory 4. This performs the same operation for the second, third, and fourth antennas.

(Embodiment 10) FIG. 10 is a block diagram of an automatic frequency control circuit according to Embodiment 10 of the present invention. Here, the description will be made simply assuming that there are four antennas. In FIG. 10, reference numeral 111 denotes a first frequency error detection unit, 112 denotes a second frequency error detection unit, 113 denotes a third frequency error detection unit, and 114 denotes a fourth frequency error detection unit. A frequency error for the second, third, and fourth antennas is detected. 115 is the first LPF
Where 116 is the second LPF, 117 is the third LPF, 1
Reference numeral 18 denotes a fourth LPF which is a first LPF, a second LPF, and a fourth LPF, respectively.
10 is an LPF for a frequency error of the fourth antenna. The configuration of the low-pass filter is the same as the conventional example shown in FIG.

Reference numeral 119 denotes a first frequency correction unit, 120 denotes a second frequency correction unit, 121 denotes a third frequency correction unit, and 12 denotes a third frequency correction unit.
Reference numeral 2 denotes a fourth frequency correction unit, which performs a frequency correction from a frequency error of the first, second, third, and fourth antennas in which noise is reduced. 1
Reference numeral 23 denotes a frequency error selector, which includes a first LPF 115 and a second
LPF 116, third LPF 117, fourth LPF 1
A selector for selecting any one of the 18 outputs.

Numeral 124 denotes an antenna common frequency error memory for storing the output of the frequency error selector 123. Each memory has a memory for each receiving slot, and a latch circuit driven by a symbol clock or the same clock. It is preferable to adopt a configuration suitable for digital signal processing and circuit integration by using an updated memory or the like. Reference numeral 125 denotes a frequency error selector control unit which writes the optimum antenna frequency error value into the antenna common frequency error memory 124.
Control.

The operation of the automatic frequency control circuit configured as described above will be described below. A first frequency error detection unit 111 extracts a frequency error component related to the first antenna from an input signal such as a modulation input signal from the first antenna or a reproduction baseband signal, and a second frequency error detection unit. 112, the third frequency error detection unit 113, and the fourth frequency error detection unit 114 detect frequency errors of the second, third, and fourth antennas, respectively. The frequency error for each antenna is the first LPF 115, the second LPF 116,
Are passed through the LPF 117 and the fourth LPF 118, the frequency error is averaged, and noise affecting the calculation of the frequency error is reduced.

The frequency error selector control section 125 detects various reception states, determines an optimum antenna for the state, and controls the frequency error selector 123 to reduce the noise error of the optimum antenna with reduced noise. And write control is performed so that the data is written to the antenna common frequency error memory 124. The symbol whose frequency error is stabilized after the initial pull-in of the demodulation operation is completed, for example, the stable output of the frequency error selector 123 in the latter half of the reception slot is written to the antenna common frequency error memory 124. At the start of the next slot, the value written in the antenna common frequency error memory 124 is input as an initial value of the first LPF 115, the second LPF 116, the third LPF 117, and the fourth LPF 118.

The first LPF 115 and the second LPF 11
6, the third LPF 117 and the fourth LPF 118 operate using the value of the previous slot as the initial value, and therefore the first LPF 11
5, the initial pull-in of the second LPF 116, the third LPF 117, and the fourth LPF 118 is facilitated. First LPF 115, second LPF 116, third LPF 11
7. The outputs of the fourth and fourth LPFs 118 are respectively frequency-corrected by the first frequency corrector 119, the second frequency corrector 120, the third frequency corrector 121, and the fourth frequency corrector 122 for each antenna. I do. This operation is performed for each reception slot.

(Embodiment 11) This embodiment 11
In the tenth embodiment, the frequency error selector control unit 12
5 is composed of a reception intensity detection unit and a reception intensity maximum antenna determination unit. FIG. 11 is a block diagram of a reception strength detection unit and a reception strength maximum antenna determination unit of the automatic frequency control circuit according to Embodiment 11 of the present invention.

Here, the description will be made on the assumption that the number of antennas is four. In FIG. 11, reference numeral 71 denotes a first reception intensity detection unit, 72 denotes a second reception intensity detection unit, 73 denotes a third reception intensity detection unit, and 74 denotes a fourth reception intensity detection unit. It is similar to that of the eighth embodiment. Reference numeral 131 denotes a maximum reception intensity antenna determination unit that determines an antenna having the maximum reception intensity and notifies the frequency error selector 123 of the maximum reception intensity antenna.

The operation of the reception strength detection section and the reception strength maximum antenna determination section configured as described above will be described below. The first reception intensity detection unit 71 derives the reception intensity of the first antenna, and the second reception intensity detection unit 72, the third reception intensity detection unit 73, and the fourth reception intensity detection unit 74 The reception intensities for the second, third, and fourth antennas are derived, respectively. Among the four antennas, the antenna with the maximum reception intensity is determined by the maximum reception intensity antenna determination unit 131, and the maximum error antenna is notified to the frequency error selector 123.

The frequency error selector 123 inputs the noise-reduced frequency error of the informed antenna to the antenna common frequency error memory 124 and writes the same, whereby the most reliable frequency error correction for the frequency error data is performed. It has the effect of being able to do it. Alternatively, when the reception strength of the antenna determined by the maximum reception strength antenna determination unit 131 is lower than a certain set value, the frequency error selector 123 may output 0.

(Embodiment 12) Embodiment 12
In the tenth embodiment, the frequency error selector control unit 12
5 is constituted by a phase error detecting section and a phase error minimum antenna judging section. FIG. 12 is a block diagram of a phase error detection unit and a phase error minimum antenna determination unit of the automatic frequency control circuit according to Embodiment 12 of the present invention.

Here, the description will be made on the assumption that the number of antennas is four. In FIG. 12, reference numeral 91 denotes a first phase error detector, 92 denotes a second phase error detector, 93 denotes a third phase error detector, and 94 denotes a fourth phase error detector.
Is similar to that of the ninth embodiment.

A minimum phase error antenna determination section 141 determines an antenna having the minimum phase error, and notifies the frequency error selector 123 of the minimum phase error antenna. The frequency error selector 123 inputs the notified frequency error of the reduced noise relating to the antenna to the antenna common frequency error memory 124 and writes the same, thereby performing the frequency error correction for the most reliable frequency error data. Having. Alternatively, when the reception strength of the antenna determined by the maximum reception strength antenna determination unit 131 is lower than a certain set value, the frequency error selector 123 may output 0.

[0084]

According to the present invention, by using the frequency error memory in the automatic frequency control circuit, since the transient response of the low-pass filter does not occur, even if the band of the filter is narrowed, an error caused by the transient response is reduced. Since this does not occur, the band of the filter can be narrowed, and the value of the frequency error with reduced noise can be quickly converged, so that an excellent automatic frequency control circuit of the receiver can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of an automatic frequency control circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a frequency error change polarity determination unit of an automatic frequency control circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a reception intensity detection unit and a reception intensity state determination unit of an automatic frequency control circuit according to a third embodiment of the present invention.

FIG. 4 is a block diagram of a symbol clock reproduction state determination unit of an automatic frequency control circuit according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram of a phase error detection unit and a phase error state determination unit of an automatic frequency control circuit according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram of a bit error detection unit and a bit error detection state determination unit of an automatic frequency control circuit according to a sixth embodiment of the present invention.

FIG. 7 is a block diagram of an error change amount detection unit and an error change amount state determination unit of an automatic frequency control circuit according to a seventh embodiment of the present invention.

FIG. 8 is a block diagram of a reception intensity detection unit, a reception intensity relative operation unit, and a reception intensity relative value state determination unit of the automatic frequency control circuit according to the eighth embodiment of the present invention.

FIG. 9 is a block diagram of a phase error detector, a phase error relative value calculator, and a phase error relative value state determiner of the automatic frequency control circuit according to the ninth embodiment of the present invention;

FIG. 10 is a block diagram of an automatic frequency control circuit according to a tenth embodiment of the present invention.

FIG. 11 is a block diagram of a reception intensity detection unit and a reception intensity maximum antenna determination unit of an automatic frequency control circuit according to Embodiment 11 of the present invention.

FIG. 12 is a block diagram of a phase error detection unit and a phase error minimum antenna determination unit of an automatic frequency control circuit according to a twelfth embodiment of the present invention.

FIG. 13 is a block diagram of a conventional automatic frequency control circuit.

FIG. 14 is a block diagram of a low-pass filter of the automatic frequency control circuit according to the related art and the first and tenth embodiments of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Frequency error detection part 2 LPF (Low-pass filter) 3 Frequency correction part 4 Frequency error memory 5 Memory writing control part 15 Memory writing timing control part 123 Frequency error selector 124 Antenna common frequency error memory 125 Frequency error selector control part

Claims (12)

[Claims] An automatic frequency control circuit for a receiver in time division multiple access communication, comprising: a frequency error memory for storing a frequency error; and a memory write control unit for performing a write control of the frequency error memory. An automatic frequency control circuit, wherein the frequency error of a reception slot is written into the frequency error memory, and the value of the frequency error memory of each reception slot is used as an automatic frequency control initial value at the beginning of a burst of each reception slot. 2. The memory write control unit includes a frequency error change polarity determination unit that detects a polarity of a change in a frequency error, and controls writing to the frequency error memory based on the polarity of the change in the frequency error. The automatic frequency control circuit according to claim 1, wherein: 3. The memory writing control unit includes a reception intensity detection unit that detects reception intensity, and a reception intensity state determination unit that determines a state of the reception intensity. 3. The automatic frequency control circuit according to claim 1, wherein writing is controlled. 4. The symbol clock reproduction state determining section for determining a state of a symbol clock reproduction section for generating a reproduction symbol clock from a phase- or frequency-modulated received signal, and wherein the symbol clock reproduction state is determined. 4. The automatic frequency control circuit according to claim 1, wherein writing to the frequency error memory is controlled based on a symbol clock reproduction state determined by a state determination unit. 5. A memory write control unit, comprising: a phase error detection unit that calculates a difference between a determination phase signal, which is a phase of a determined symbol, and a detection phase output from a detector, and determines a state of a phase error. 5. The automatic frequency control circuit according to claim 1, wherein the automatic frequency control circuit is configured by a phase error state determination unit, and controls writing to the frequency error memory based on an output value of the phase error detection unit. 6. The memory write control section comprises a demodulated signal bit error detection section and a bit error detection state determination section, and controls writing to the frequency error memory according to the bit error detection state. The automatic frequency control circuit according to claim 1. 7. An error change amount detection unit for detecting a frequency change amount, which is a change amount between the frequency error of a previous reception slot and the frequency error of a current reception slot in each reception slot, 7. An apparatus according to claim 1, further comprising an error change amount state determination unit that determines a state of a change amount of the frequency error, wherein writing to the frequency error memory is controlled by the peripheral frequency change amount.
The automatic frequency control circuit according to any one of the above. 8. The diversity receiver having a plurality of antennas, wherein the memory write control unit calculates a reception intensity detection unit for detecting reception intensity and a relative value of reception intensity for each antenna. 2. The automatic receiving apparatus according to claim 1, further comprising a receiving intensity relative value calculating unit and a receiving intensity relative value state determining unit, wherein writing to the frequency error memory in each receiving slot is controlled by the relative value of the receiving intensity. Frequency control circuit. 9. The diversity receiver having a plurality of antennas, wherein the memory write control unit determines a difference between a determination phase signal, which is a phase of a determined symbol, and a detection phase output from a detector. , A phase error relative value calculator for calculating the relative value of the phase error for each antenna, and a phase error relative value state determiner, and the phase error relative value in each reception slot is determined by the relative value of the phase error. 9. The automatic frequency control circuit according to claim 1, wherein writing to the frequency error memory is controlled. 10. An automatic frequency control circuit in a diversity receiver having a plurality of antennas for time division multiple access communication, comprising: an antenna common frequency error memory for storing a common antenna frequency error; A frequency error selector for selecting a frequency error for one antenna, and a frequency selector control unit for controlling this frequency error selector, writing the output from the frequency error selector of each reception slot to the antenna common frequency error memory, An automatic frequency control circuit characterized in that a value of the antenna common frequency error memory of each reception slot is used as an automatic frequency control initial value at the beginning of a burst of each reception slot. 11. A frequency selector control unit comprising: a reception intensity detection unit for detecting reception intensity of each antenna; a reception intensity relative value calculation unit for calculating a relative value of reception intensity; 11. A reception intensity maximum antenna determination unit, wherein the frequency error of the antenna having the maximum reception intensity is set as an output of the frequency error selector and a value written to the frequency error memory. Automatic frequency control circuit as described. 12. The frequency selector control section comprises a phase error relative value calculation section for calculating a relative value of a phase error for each antenna, and a phase error minimum antenna determination section for determining an antenna having the smallest phase error. 12. The frequency error selector according to claim 10, wherein the frequency error of the antenna having the minimum phase error is used as an output of the frequency error selector and a value written to the frequency error memory.
Automatic frequency control circuit as described.