JP2007188137A - Microprocessor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a microprocessor for performing prefetch control which is optimal to the configurations of a memory or input/output device unique to a system. <P>SOLUTION: This microprocessor is provided with a wait number setting register 17 and an address decoder 15 for generating a wait number 16 necessary for a CPU 11 to read data or an instruction code, a wait upper limit value setting register 19 for storing a wait upper limit value 18 showing the upper limit of the wait number 16 permitting the prefetch of the CPU 11 and a determination circuit 20 for comparing and determining the wait number 16 from the wait number setting register 17 and the wait upper limit value 18 from the wait upper limit value setting register 19, and for outputting a prefetch inhibition signal 13 for stopping the prefetch function of the CPU 11 based on the determination result. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a microprocessor having an instruction code or data prefetching function.

  In recent years, the speed of microprocessors has been remarkably increased, and the difference in operating frequency between an external memory used as a main storage device and the microprocessor tends to widen. Therefore, a microprocessor having a mechanism for incorporating or adding a cache memory so that access to the external memory does not greatly affect the performance of the microprocessor, and having a function of prefetching instruction codes and data into the cache memory. Has become mainstream. However, in such a microprocessor, when an instruction or data that has not been prefetched to the cache memory (cache miss hit) occurs, the cache memory needs to be rewritten (reloaded). To drop. Such a cache miss hit has a high probability of occurring in a jump instruction, a subroutine call instruction, or the like. For this reason, a method of detecting these instructions in advance and controlling prefetch to the cache memory (for example, “Patent Document 1”). And “Patent Document 2”) have been developed.

  On the other hand, since microprocessors can flexibly cope with function additions by software upgrades, they have been adopted as controllers for all devices ranging from game machines and home appliances to communication devices and information processing devices. Therefore, in such an application, it is very difficult to assume in advance a memory configuration including a main storage device and a configuration of an input / output device allocated to a memory space in a system in which a microprocessor is mounted. There was a problem that there was. For example, when a low-speed external memory having a large number of wait cycles, such as an EEPROM, is allocated in the memory space in addition to the main memory, control such as selectively stopping the prefetch function only when accessing the EEPROM is desirable. However, such a configuration is unique to the system based on a specific user specification, and the address to which the EEPROM is allocated is not always fixed in advance. Therefore, in order to cope with the conventional microprocessor, it is necessary to prepare a special control mechanism for each system.

That is, the conventional microprocessor having the function of pre-reading the instruction code or data has a problem that prefetch control that is optimum for the system-specific memory configuration and input / output device configuration in which it is mounted cannot be performed.
JP 2001-273137 A JP-A-5-27972

  The present invention provides a microprocessor capable of performing prefetch control optimal for a system-specific memory configuration and input / output device configuration.

  According to one aspect of the present invention, wait number generation means for generating the number of wait cycles necessary for the CPU to read data or instruction code, and a weight upper limit value indicating the upper limit of the number of wait cycles that allow the CPU to prefetch A prefetch prohibition signal for comparing and determining the number of wait cycles from the wait number generation unit and the upper limit value of the wait from the holding unit, and stopping the prefetch function of the CPU based on the determination result There is provided a microprocessor characterized by having a judging means for outputting.

  According to the present invention, the prefetch function can be controlled flexibly corresponding to various memory configurations and input / output device configurations unique to the system.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit block diagram showing a microprocessor according to Embodiment 1 of the present invention. Here, the part mainly related to the control of the function of prefetching the instruction code and data into the cache memory (hereinafter referred to as “prefetch function”) is shown.

  The microprocessor according to the first embodiment of the present invention outputs from the CPU 11 a central processing unit 11 (hereinafter referred to as “CPU 11”) that performs processing based on an instruction code, and an instruction code or data address to be read next. An address bus 12 and a prefetch control unit 14 that generates a prefetch inhibition signal 13 for controlling the prefetch function of the CPU 11 based on the address on the address bus 12 are provided.

  A prefetch prohibiting signal 13 from the prefetch control unit 14 is input to the input of the CPU 11, an address output of the CPU 11 is connected to the address bus 12, and an address bus 12 is connected to the input of the prefetch control unit 14.

  The CPU 11 interprets the instruction code read from the external memory (not shown), and based on the result, the address of the data necessary for executing the instruction code or the address of the instruction code to be executed next is sent to the address bus. 12 is output.

  These addresses are the addresses of instruction codes or data to be read next by the CPU 11, and when the addresses deviate from the prefetched address range (generally referred to as “cache miss hit”), the prefetch control unit. Except for the case where 14 outputs the prefetch prohibition signal 13, the CPU 11 suspends continuation of program execution and sends a series of instruction codes or data to which the address belongs via a data bus (not shown). And prefetch (read ahead) to the cache memory.

  On the other hand, when the prefetch prohibition signal 13 is output, the CPU 11 performs the sequential operation without performing the above-described prefetch operation. That is, the CPU 11 waits (waits) until the instruction code or data from the external memory can be read via the data bus.

  As shown in FIG. 1, the prefetch control unit 14 includes an address decoder 15 that decodes addresses, a wait number setting register 17 that holds 16 wait cycles for each memory space (hereinafter referred to as “wait number 16”), A weight upper limit value setting register 19 that holds an upper limit value of the number of waits 16 (hereinafter referred to as “weight upper limit value 18”) and a determination circuit 20 that compares and determines the number of waits 16 and the weight upper limit value 18 are provided.

  The address bus 12 is connected to the input of the address decoder 15, and the output of the address decoder 15 is supplied to the input of the wait number setting register 17. The output of the wait number setting register 17 is supplied to the first input of the determination circuit 20 as the number of waits 16, and the output of the weight upper limit value setting register 19 is supplied to the second input of the determination circuit 20 as the weight upper limit value 18. The output of the determination circuit 20 is supplied to the input of the CPU 11 as a prefetch prohibiting signal 13.

  The address decoder 15 is composed of an FPGA, and associates the address on the address bus 12 with the wait number setting register 17. That is, the address decoder 15 outputs a selection signal corresponding to the address to the wait number setting register 17 in accordance with the association set in advance.

  An example of specific association will be described later with reference to FIG. 2. These are set when the CPU 11 initializes the FPGA according to the system program when the power is turned on or the system is reset.

  The number of waits 16 is defined by the performance of the external memory or input / output device mounted in the memory space, and is set for each divided memory space, as will be described later with reference to FIG.

  The wait number setting register 17 is composed of a plurality of registers that hold the wait number 16, and selectively outputs the wait number 16 corresponding to the address on the address bus 12 to the determination circuit in response to a selection signal from the address decoder 15.

  Each wait number 16 held by the wait number setting register 17 is set by the CPU 11 according to the system program at power-on or system reset.

  The weight upper limit value 18 is a reference value for determining the stop of the prefetch operation of the CPU 11, and the determination circuit 20 determines the number of waits 16 from the wait number setting register 17 based on the performance of the external memory or the input / output device based on this value. Determine.

  The wait upper limit value setting register 19 is a register that holds a wait upper limit value, and this value is set by the CPU 11 according to the system program at power-on or system reset.

  The determination circuit 20 compares the number of waits 16 from the wait number setting register 17 with the weight upper limit value 18 from the weight upper limit value setting register 19, and when the number of waits 16 exceeds the weight upper limit value 18, the prefetch prohibition signal 13 is generated and output to the CPU 11.

FIG. 2 is a table showing an example of setting information in the microprocessor according to the first embodiment of the present invention.
The setting information in the microprocessor according to the first embodiment of the present invention includes a memory space number for identifying the divided memory space, an address range corresponding to the memory space number, a weight number 16 corresponding to the memory space number, and a weight upper limit value. 18 is provided.

  The memory space of the CPU 11 is divided according to the type and performance of the external memory and input / output device allocated to the memory space, and a memory space number is assigned to identify each.

  In the address range, a series of addresses are assigned to each external memory or input / output device. For example, as illustrated in FIG. 2, the memory space number “1” corresponds to the address range “0 to 0FFFF”, the memory space number “2” corresponds to the address range “10000 to 1FFFF”, The memory space number “3” corresponds to the address range “addresses 1FFFF to 2FFFF”.

  The number of waits 16 is defined by the performance of the external memory or input / output device assigned to each address range. Specifically, after the CPU 11 outputs a read signal to read data, the data is actually transferred to the data. The waiting time until the data can be read from the bus is indicated by the number of system clocks.

  For example, as shown in FIG. 2, when the memory space number is “1”, the number of waits is “0”, and when the memory space number is “2”, the number of waits is 16 and the memory space number is “3”. The number of waits 16 is “20”.

  These are the number of waits 16 set assuming high-speed main memory such as SRAM, low-speed main memory such as DRAM, and secondary storage such as EEPROM.

  The weight upper limit value 18 is set to “8” in FIG. This permits the prefetch operation of the CPU 11 for the main storage of the memory space numbers “1” and “2”, and stops the prefetch operation of the CPU 11 for the secondary storage of the memory space number “3”. It means to let you.

Next, the operation of the microprocessor having the above configuration will be described.
FIG. 3 is a table showing an example of the operation in the microprocessor according to the first embodiment of the present invention. Here, the operation of the microprocessor will be described assuming that the setting information of FIG. 2 is set in advance in the address decoder 15, the wait number setting register 17, and the wait upper limit value setting register 19.

  The first column of the table shown in FIG. 3 shows the address that the CPU 11 outputs to the address bus 12, the second column shows the instruction code at that address, and the third column shows the memory space number to which the address belongs. Yes.

  First, the CPU 11 executes a “jump 1” instruction at “address 02000”. The memory space number at this time is “1”. The execution of the CPU 11 jumps to “20000 address” by the “jump 1” instruction.

  Next, the CPU 11 executes an “arithmetic 1” instruction at “address 20000”. The memory space number at this time is “3”. Then, the process proceeds and the execution of the CPU 11 reaches “20100”. At “20100”, the CPU 11 executes a “jump 2” instruction and jumps to “10000”.

  The memory space number of “10000 addresses” is “2”. That is, in the operation shown in FIG. 3, the memory space number changes from “1” → “3” → “2”. Note that the address output by the CPU 11 to the address bus 12 is the address of the next instruction code.

  Therefore, when the CPU 11 interprets and executes the “jump 1” instruction at “02000”, the next “20000” is output to the address bus 12, and the address decoder 15 selects the selection signal corresponding to the memory space number “3”. Is output to the wait number setting register 17.

  FIG. 4 is a waveform diagram showing an example of the prefetch inhibition signal 13 in the microprocessor according to the first embodiment of the present invention. Here, the prefetch prohibition signal 13 generated in accordance with the operation shown in FIG. 3 is shown on the time axis.

  The prefetch inhibition signal 13 is “H” and stops the prefetch operation of the CPU 11. That is, as shown in FIG. 4, in the memory space numbers “1” and “2”, the prefetch prohibition signal 13 is “L”, and the prefetch operation of the CPU 11 is permitted. In the memory space number “3”, the prefetch prohibition signal 13 is “H”, and the prefetch operation of the CPU 11 is stopped.

  FIG. 5 is an image diagram showing an example of detailed operation in the microprocessor according to the first embodiment of the present invention. Here, the operation related to the transition from the memory space number “1” to “3” in FIG. 3 is shown.

  5 shows the waveform of the system clock (CLK), the second stage shows the prefetch inhibition signal 13, the third stage shows the instruction code read timing, and the fourth stage shows the internal operation of the CPU 11. The timing shows the timing, and the bottom row shows the waveform of the read signal that the CPU 11 outputs to the external memory.

  As shown in FIG. 5, when the address transitions to the memory space number “3”, the operation of the CPU 11 is a sequential process, and no unnecessary read operation occurs during a long standby period. Thereby, even if there is a branch instruction, the bus cycle is started after the branch determination, so that a useless bus cycle does not occur, and the load on the address bus 12 and the data bus is reduced.

  Importantly, since the setting information can be set in advance by a program, the user can set the values in the number-of-waits setting register 17 and the weight upper limit value setting register 19 in accordance with the configuration unique to the system. This means that optimal prefetch control can be performed.

  According to the first embodiment, since the prefetch function of the microprocessor is controlled for each memory space, it is possible to flexibly cope with various memory configurations and input / output device configurations unique to the system.

  Further, according to the first embodiment, the number of waits 16 for each memory space and the correspondence between the address and the wait number setting register 17 are set by the system program at the time of power-on or system reset. Accordingly, the prefetch control of the CPU 11 can be easily changed.

  Furthermore, according to the first embodiment, for the external memory or input / output device having a large number of waits 16, the CPU 11 is in a standby state without performing a prefetch operation even at the time of a cache miss, so a useless bus cycle occurs. Instead, the load on the address bus 12 and the data bus is reduced. At the same time, the load on the CPU 11 necessary for the brifetch operation is also reduced.

  In the first embodiment described above, the address decoder 15 is configured with an FPGA in consideration of the flexibility of the configuration. However, the present invention is not limited to this. For example, the memory space number and the address range are fixed in advance. These correspondences can also be configured by logic circuits.

  In the first embodiment, the memory space is divided into three and the external memory is assigned to each of them for the sake of explanation. However, the present invention is not limited to this, and in principle, the memory space is assigned to the memory space of the CPU 11. A configuration corresponding to an arbitrary number of external memories and input / output devices can be adopted.

  FIG. 6 is a circuit block diagram showing a microprocessor according to Embodiment 2 of the present invention. Here, the part mainly related to the control of the prefetch function is shown.

  The microprocessor according to the second embodiment of the present invention includes a CPU 61 that performs processing based on an instruction code, and a prefetch control unit 64 that generates a prefetch inhibition signal 63 for controlling the prefetch function of the CPU 61 based on an external wait signal 62. It has.

  A prefetch inhibition signal 63 from the prefetch control unit 64 is input to the input of the CPU 61, and an output of the CPU 61 is supplied to a first input of the prefetch control unit 64. An external wait signal 62 is input to the second input of the prefetch control unit 64.

  Since the functions and operations of the CPU 61 are the same as those in the first embodiment except for the output of the reset signal 65, detailed description thereof is omitted.

  As shown in FIG. 6, the prefetch control unit 64 counts a system clock (hereinafter referred to as “CLK”) in synchronization with the external wait signal 62, thereby generating a wait number counter 67 that generates a wait number 66. A weight upper limit setting register 69 that holds a weight upper limit 68 that is an upper limit of the number of waits 66 and a determination circuit 70 that compares and determines the number of waits 66 and the weight upper limit 68 are provided.

  A reset signal 65 from the CPU 61 is input to the first input of the wait number counter 67, and an external wait signal 62 is input to the second input of the wait number counter 67. The output of the wait number counter 67 is supplied as a wait number 66 to the first input of the determination circuit 70, and the output of the weight upper limit value setting register 69 is supplied as the weight upper limit value 68 to the second input of the determination circuit 70 for determination. The output of the circuit 70 is supplied to the CPU 61 as a prefetch prohibiting signal 63.

  The wait number counter 67 starts counting up the CLK by the external wait signal 62 and outputs the count number to the determination circuit 70 as the wait number 66. The wait number counter 67 is stopped from being counted up by a reset signal 65 from the CPU 61 and reset to an initial state.

  After the prefetch operation is stopped by the prefetch inhibition signal 63, the CPU 61 outputs a reset signal 65 when the next instruction code or data is read from the data bus.

  Since the functions and operations of the wait upper limit setting register 69 and the determination circuit 70 are the same as those in the first embodiment, the description thereof is omitted.

  In the second embodiment, unlike the first embodiment, the CPU 61 can be in a standby state while the external wait signal 62 is being input. Therefore, it is possible to cope with the case where the number of waits 66 of the external memory or the input / output device is not fixed in advance.

  According to the second embodiment, since the prefetch function of the microprocessor is controlled for each external memory or input / output device, it is possible to flexibly cope with various configurations unique to the system.

  Further, according to the second embodiment, the wait upper limit value 68 is set by the system program when the power is turned on or when the system is reset, so that the prefetch control of the CPU 61 can be easily changed as needed even after the system is operated.

  Further, according to the second embodiment, since the number of waits 66 is generated regardless of the address of the external memory or the input / output device, the allocation of the external memory and the input / output device to the memory space is easily changed after the system is operated. be able to.

  Further, according to the second embodiment, for the external memory or input / output device having a variable number of waits 66, the CPU 61 is in a standby state without performing a prefetch operation even when a cache miss hits. No load occurs on the address bus and data bus. At the same time, the load on the CPU 61 necessary for the brifetch operation is also reduced.

  In the first and second embodiments described above, the configuration using the wait number setting register 17 and the configuration using the wait number counter 67 are described separately for ease of explanation. However, the present invention is not limited to this. A configuration using both the wait number setting register 17 and the wait number counter 67 may be adopted.

1 is a circuit block diagram showing a microprocessor according to Embodiment 1 of the present invention. 4 is a table showing an example of setting information in the microprocessor according to the first embodiment of the present invention. 4 is a table showing an example of an operation in the microprocessor according to the first embodiment of the present invention. FIG. 3 is a waveform diagram showing an example of a prefetch inhibition signal 13 in the microprocessor according to Embodiment 1 of the present invention. FIG. 3 is an image diagram showing an example of detailed operation in the microprocessor according to the first embodiment of the present invention. FIG. 6 is a circuit block diagram showing a microprocessor according to Embodiment 2 of the present invention.

Explanation of symbols

11, 61 CPU
12 Address bus 13, 63 Prefetch prohibition signal 14, 64 Prefetch control unit 15 Address decoder 16, 66 Wait number 17 Wait number setting register 18, 68 Wait upper limit value 19, 69 Wait upper limit value setting register 20, 70 Judgment circuit 62 External wait Signal 65 Reset signal 67 Wait number counter

Claims (5)

Wait number generation means for generating the number of wait cycles necessary for the CPU to read data or instruction code;
Holding means for holding a weight upper limit value indicating an upper limit of the number of wait cycles allowing the CPU to prefetch;
A determination unit that compares and determines the number of wait cycles from the wait number generation unit and the upper limit value of the wait from the holding unit, and outputs a prefetch prohibition signal that stops the prefetch function of the CPU based on the determination result; A microprocessor characterized by that.   The wait number generation means includes a setting register for holding the predetermined number of wait cycles, and when the address of the data or instruction code is within a predetermined range, the wait number held in the setting register 2. The microprocessor according to claim 1, wherein the number of cycles is selected and output.   The wait number generating means includes a plurality of registers for holding the number of wait cycles corresponding to the memory space of the CPU divided into a plurality, and from the plurality of registers based on the address of the data or instruction code 2. The microprocessor according to claim 1, wherein the number of wait cycles corresponding to data or an instruction code is selected and output.   2. The microprocessor according to claim 1, wherein the wait number generating means generates the wait cycle number corresponding to the data or instruction code by counting up a clock signal based on an external wait signal.   2. The microprocessor according to claim 1, wherein the wait upper limit value is stored in the holding unit at power-on or system reset.

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