JP2006048258A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To flexibly respond to a request for low power consumption and the high-speed implementation of a program. <P>SOLUTION: The invention comprises an instruction fetch control part (5), an instruction buffer (15) that holds an instruction fetched by the fetch control part, and an execution part (6) that executes the instruction held by the instruction buffer in a pipeline in a predetermined order. The fetch control part obtains prediction information showing the predicted direction of conditional branching and its accuracy using the instruction address of the branch instruction. The fetch control part is capable of carrying out the fetching of instructions on the branching predicting side and the fetching of instructions on the non-branching prediction side in the conditional branching instructions, and restricts selectively the fetching of instructions on the non-branching prediction side according to the prediction information. The fetch control part restricts fetching of instructions on the non-prediction side when the accuracy of branching prediction by the prediction information is relatively high. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to instruction fetch control by branch prediction of a conditional branch instruction in a data processor (pipeline processor) capable of executing instructions by a pipeline.

  Branch prediction of a conditional branch instruction is a technique for predicting a branching direction in advance and filling an instruction with an address based on the prediction into the pipeline to eliminate the waste of the pipeline. Further, in order to increase the efficiency of instruction execution by the branch prediction, instruction execution in the predicted branch direction is allowed before branch prediction is confirmed, and instruction execution contradictions are resolved when the prediction is lost. A technique called speculative execution can be employed.

  In Patent Literature 1, in a pipeline processor having a branch prediction and speculative execution function, in order to prevent deterioration of power consumption efficiency due to failure of branch prediction, a conditional branch instruction that is difficult to hit branch prediction is determined, and branch prediction is performed. For a conditional branch instruction that is difficult to hit, the speculative execution of the subsequent instruction is not performed, and the execution of the subsequent instruction is waited until the branch condition is determined. After receiving the branch condition verification result, it is determined whether or not the branch condition is satisfied. If the branch condition is satisfied, the process is executed from the instruction at the address next to the conditional branch instruction. If the branch condition is not satisfied, the branch jump is performed. Execute from the instruction at the destination address.

JP 2000-322257 A

  The present inventor has studied a reduction in power consumption of an instruction fetch unit in a microprocessor that achieves low power consumption and high-speed operation. In a processor for an embedded field such as a portable information device, it is necessary to increase the speed as the application becomes complicated. Moreover, since it is a portable application, low power consumption is also necessary. However, as described in Patent Document 1, when a conditional branch instruction that is difficult to predict branch detection is detected, if execution of an instruction sequence after the branch instruction is always stopped, the high-speed execution performance of the program may be degraded. It was found by the person.

  An object of the present invention is to provide a data processor that can flexibly cope with demands for low power consumption and high-speed program execution.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] The data processor pipes the instruction fetch control unit (5), the instruction buffer (15) holding the instruction fetched by the fetch control unit, and the instructions held in the instruction buffer in a predetermined order. And an execution unit (6) that executes on the line. The fetch control unit obtains prediction information (33) indicating the prediction direction and the accuracy of the conditional branch using the instruction address of the branch instruction, fetches the instruction on the branch prediction side in the conditional branch instruction, and the branch non-prediction side It is possible to fetch an instruction, and selectively inhibit fetching of an instruction on the branch non-prediction side according to the prediction information. For example, the fetch control unit suppresses fetching of the instruction on the non-prediction side when the accuracy of branch prediction based on the prediction information is relatively high.

  By fetching both the branch prediction side instruction and the branch non-prediction side instruction in the conditional branch instruction, even if the conditional branch prediction misses, the non-prediction side instruction fetch is performed. The number of stall cycles in the pipeline at the time of branch misprediction is reduced, which can contribute to high-speed program execution. On the other hand, when it is determined by the prediction information that the conditional branch prediction is hit with a high probability, instruction fetch on the non-prediction side can be suppressed. Therefore, the number of instruction fetches that are not actually required in program execution is The number of memory reads for instruction fetch can be reduced, and the power required for memory read can be reduced. Since suppression of fetch for the non-prediction side instruction can be selectively performed in accordance with the prediction information, it is possible to flexibly cope with demands for low power consumption and high-speed program execution.

  [2] A data processor according to another aspect of the present invention includes an instruction fetch control unit, an instruction buffer that holds an instruction fetched by the fetch control unit, and instructions held in the instruction buffer in a predetermined order. An execution unit that executes in a pipeline, and the fetch control unit obtains prediction information indicating a prediction direction and accuracy of a conditional branch using an instruction address of the branch instruction, and an instruction on a branch prediction side in the conditional branch instruction The first fetch mode for fetching both of the instruction and the branch non-prediction side instruction, fetching the branch prediction side instruction, and selectively fetching the branch non-prediction side instruction according to the prediction information Selection of the second fetch mode to be suppressed is made possible. The fetch control unit suppresses fetching of the instruction on the non-prediction side when the accuracy of branch prediction based on the prediction information is relatively high in the second fetch mode.

  In the conditional branch instruction, in the first fetch mode, a prediction instruction fetch and a non-prediction instruction fetch are performed in the conditional branch instruction. For example, if the number of executions of conditional branch instructions is 2,000, and there is one non-predicted instruction fetch per almost conditional branch, 2,000 non-predicted instruction fetches for the entire program Will occur. If the conditional branch prediction hit rate is 90%, the number of instruction fetches for an instruction not executed on the non-prediction side is 2,000 × 0.9 = 1,800. In the second fetch mode, when it is predicted that the conditional branch prediction will be hit with a high probability, the instruction fetch on the non-prediction side can be suppressed to reduce the number of memory reads. Also, if the conditional branch prediction is predicted to hit with a low probability, the instruction fetch on the non-prediction side is also performed, so even if the prediction actually deviates, the instruction fetch on the non-prediction side has already been performed. The number of pipeline installation cycles imposed on the execution of the actual instruction sequence in the branch direction is reduced, and the program can be executed at high speed. In a pipeline processor having a branch prediction mechanism, the power consumption in the instruction fetch unit and the memory unit during program execution may occupy 10 to 30% of the total power consumption. The number of instruction fetches in the second fetch mode Reduction is effective in reducing the overall power consumption.

  A specific form of the present invention includes a control register for designating the first fetch mode or the second fetch mode according to a set value. The set value of the control register is variable by instruction execution by the execution unit.

  In another specific form of the present invention, the prediction information has a plurality of bits, and represents different branch predictions and their accuracy depending on the difference in the values. The fetch control unit includes a prediction information table unit that is indexed using a part of an instruction address of a conditional branch instruction and stores a plurality of pieces of the prediction information. When the branch of the conditional branch instruction is confirmed, if the prediction information indexed using the conditional branch instruction is a hit, the fetch control unit sets the prediction information to the maximum accuracy of the prediction. If the prediction information indexed using the conditional branch instruction is a miss, the prediction information is updated in the direction in which the prediction accuracy decreases. This enables dynamic branch prediction.

  At this time, the maximum value of the branch prediction information means the maximum accuracy of branch prediction due to the establishment of the branch condition in the conditional branch instruction, and the minimum value means the maximum accuracy of branch prediction due to the failure of the branch condition in the conditional branch instruction.

  [3] A data processor according to still another aspect of the present invention includes an instruction fetch control unit, an instruction buffer that holds an instruction fetched by the fetch control unit, and instructions stored in the instruction buffer in a predetermined order. An execution unit that executes in a pipeline, and the fetch control unit is indexed using a part of the instruction address of a conditional branch instruction, and stores a prediction information table unit (32A) that stores a plurality of branch prediction information; A shift register unit (21) which shift-inputs the branch result of hit or miss for the prediction and holds a plurality of branch results as branch history information from the latest. The branch prediction information (33A) indicates the prediction direction of the conditional branch according to the value. The fetch control unit is capable of fetching a branch prediction side instruction and a branch non-prediction side instruction in a conditional branch instruction and branching from branch history information (22) held in the shift register unit. The accuracy is judged, and when the branch accuracy is high, fetching of instructions on the branch non-prediction side is suppressed. For example, the fetch control unit determines that the accuracy of branch prediction is high when a branch result of more than half of the branch history information held by the shift register unit indicates a prediction hit. Prediction information can be composed of a minimum of 1 bit, and fetching of non-predicted instructions can be selectively suppressed by a global branch history.

  [4] A data processor according to still another aspect of the present invention includes an instruction fetch control unit, an instruction buffer that holds an instruction fetched by the fetch control unit, and instructions held in the instruction buffer in a predetermined order. The fetch control unit is indexed using a part of the instruction address of the conditional branch instruction and stores a plurality of branch prediction information, and a hit for branch prediction. Alternatively, a shift register unit that shift-inputs a miss branch result and holds a plurality of branch results from the latest as branch history information, and the branch prediction information indicates a prediction direction of a conditional branch according to the value. The fetch control unit obtains prediction information indicating a prediction direction of a conditional branch using an instruction address of a branch instruction, and fetches both a branch prediction side instruction fetch and a branch non-prediction side instruction fetch in the conditional branch instruction. A first fetch mode to be performed, and fetching an instruction on the branch prediction side, and when branch history information acquired from the shift register unit indicates a high branch accuracy, fetching an instruction on the branch non-prediction side is inhibited. Selection with the 2-fetch mode is made possible.

  A specific form of the present invention includes a control register for designating the first fetch mode or the second fetch mode according to a set value. The set value of the control register is variable by instruction execution by the execution unit.

  [5] A data processor according to still another aspect of the present invention includes an instruction fetch control unit, an instruction buffer that holds an instruction fetched by the fetch control unit, and instructions stored in the instruction buffer in a predetermined order. And an execution unit that executes in a pipeline, wherein the fetch control unit fetches N1 branch prediction side instructions and N2 branch non-prediction side instructions in a conditional branch instruction, and a condition When the information indicating the prediction accuracy for the branch instruction indicates a high prediction accuracy, it has a second fetch function for fetching N3 instructions on the prediction side, and N3 <N1, N2.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, it is possible to flexibly meet the demands for low power consumption and high-speed program execution.

  FIG. 1 shows an example of a data processor. The data processor 7 is not particularly limited, but is formed on one semiconductor substrate such as single crystal silicon by a complementary MOS integrated circuit manufacturing technique. The data processor 7 has a processor core unit (PCOR) 1. The processor core unit 1 is fetched by a control register (CREG) 16, a fetch control unit (FCNT) 5 that performs fetch control of instructions, and the fetch control unit 5. A central processing unit (CPU) comprising an instruction buffer (IBUF) 15 for holding the received instructions and a pipeline execution unit (PEXEC) 6 for executing the instructions held in the instruction buffer 15 in a predetermined order in the pipeline. Have. The fetch control unit 5, the control register 16 and the pipeline execution unit 6 are connected to the internal bus 4. A cache memory (CACH) 2 and a work RAM (WRAM) 3 are connected to the internal bus 4 as built-in memories. The cache memory 2 and work RAM 3 can be interfaced with an external bus 8, a DMAC (direct memory access controller) 14, and a peripheral bus 5 via a bus state controller (BSC) 13. A representative external memory (EXMEM) 9 is connected to the external bus 8. The peripheral bus 5 is connected to a representatively shown interrupt controller (INTC) 10, CPG (clock pulse generator) 11, and TMU (timer unit) 12.

  The fetch control unit 5 fetches an instruction sequence from the cache memory 2 via the internal bus 4. When the cache memory 2 has a cache miss, the instruction sequence to be fetched is supplied from the external memory 9 to the cache memory 2. The instruction fetched by the fetch control unit 5 is stored in the instruction buffer 15, and the instruction stored in the instruction buffer 15 is input to the pipeline execution unit 6 and executed by the pipeline. A predetermined result of the instruction execution results by the pipeline execution unit 6 is reflected on the instruction fetch control unit 5 by a signal 18. For example, information for determining whether the branch condition is satisfied or not is supplied to the instruction fetch control unit 5 by the signal 18.

  The fetch control unit 5 performs branch prediction of a conditional branch instruction and packs an instruction at an address based on the prediction into the pipeline to eliminate the waste of the pipeline. The pipeline execution unit 6 controls speculative execution so as to permit instruction execution in the branch direction predicted before the branch prediction is finalized and to resolve inconsistencies in instruction execution when the prediction is lost.

  Here, the pipeline stage in the data processor will be described. FIG. 2 illustrates the pipeline stage of the data processor 7. There are seven pipeline stages, and the processing contents of each stage are as follows. Stage I1 and stage I2 are instruction fetch stages for fetching instructions via the internal bus 4, and a fetch command is issued to the cache memory 2 at stage I1. At stage I2, the fetched instruction is stored in the instruction buffer 15, and a branch instruction is detected. In the example of FIG. 2, a maximum of four instructions can be fetched in one instruction fetch cycle, and instructions A, B, C, and D are fetched at stage I1 and stored in the instruction buffer at stage I2. The stage ID is an instruction decode stage and decodes the instruction supplied from the instruction buffer 15. When the fetched instruction is decoded in the next cycle, the process proceeds from the I2 stage to the ID stage. If the fetched instruction cannot be immediately advanced to the ID stage due to pipeline installation or the like, the fetched instruction remains in the instruction buffer 15 and continues to detect the branch instruction. This period is called a predecode stage PD. Stages E1, E2, and E3 are execution stages, and perform operations according to instruction decode results. The stage WB is a write back stage, and writes the operation result to a register or a memory. The stages ID, E1, E2, E3, and WB are processed by the pipeline execution unit 6.

  The fetch control unit 5 fetches an instruction sequence from the cache memory 2 via the internal bus 4. The instruction fetched by the fetch control unit 5 is stored in the instruction buffer 15. The fetch control unit 5 searches for branch instructions at the I2 and PD stages. When a conditional branch instruction is detected, the conditional branch direction is predicted based on prediction information corresponding to the instruction address. The fetch control unit 5 performs a first fetch mode in which both a branch prediction side instruction fetch and a branch non-prediction side instruction fetch are performed in a conditional branch instruction, the branch prediction side instruction is fetched, and the prediction information Accordingly, selection with the second fetch mode that selectively suppresses fetching of instructions on the branch non-prediction side is enabled. Whether the first fetch mode or the second fetch mode is selected is determined by the value of the fetch mode switching bit 17 of the control register 16. The set value of the control register 16 is made variable by instruction execution by the pipeline execution unit 6.

  In FIG. 2, when the first fetch mode is selected, an instruction fetch in the predicted branch direction and an instruction fetch on the non-prediction side are issued, and the instruction fetched via the internal bus is stored in the instruction buffer 15. It is shown. That is, when the conditional branch instruction C is detected in the I2 stage of cycle C2, the conditional branch direction is predicted in the PD stage of cycle C3. If the branch prediction of the conditional branch instruction C is a branch establishment prediction (Taken) prediction, the instruction stream on the branch establishment side (Taken side) is fetched in cycle C4. Further, in this fetch mode, an instruction stream on the branch failure (NotTaken side) on the non-prediction side is also fetched in cycle C5 and stored in the instruction buffer. The non-predicted instruction fetch before cycle C3 is based on the prediction for an instruction fetched before cycle C1 (not shown).

  FIG. 3 shows an example in which the fetch of the instruction stream on the non-prediction side is suppressed when the second fetch mode is selected and the branch prediction accuracy is high. In this case, the instruction stream on the non-prediction side is the branch failure (Not Taken) side, and fetching of the instruction stream on the Not Taken side is suppressed. In short, with respect to the prediction result in the conditional branch direction in the PD stage of cycle C3, the instruction sequence on the prediction side is fetched in cycles C4 and C5, and fetching for the instruction sequence on the non-prediction side is suppressed.

  FIG. 4 illustrates a configuration for instruction fetch control according to the fetch mode. The instruction address to be fetched here is generated by a fetch address generation circuit 20 that generates a prefetch address preceding a plurality of instructions with respect to the execution instruction address executed by the pipeline execution unit 6. The generated fetch address is held in the fetch address buffer (FABUF) 38, the fetch address FADR is output to the internal bus 4, and the instruction INST is fetched from the cache memory 2. Instruction fetch is performed using an empty cycle of the internal bus 4. The fetch address generation circuit 20 searches for a conditional branch instruction from the instructions fetched to the instruction buffer 15. When the conditional branch instruction is searched, the instruction address of the conditional branch instruction is held in the conditional branch instruction address buffer 31. The conditional branch instruction address held in the conditional branch instruction address buffer 31 is used for associative access to the branch prediction table (branch prediction information table section) 32. The branch prediction table 32 has a plurality of table entries indexed by index addresses of a plurality of lower bits of an instruction address, and the indexed table entry is a plurality of branches that can be selected by an offset address of the lower bits of the instruction address. Predictive information 33 is held. The branch prediction information held in the branch prediction table 32 has a correlation with the instruction address. Here, the branch prediction information 33 has a plurality of bits, and the value represents the prediction direction and the accuracy of the prediction. The branch prediction information is updated in a direction reflecting the actual branch state with respect to the branch prediction of the corresponding conditional branch instruction. Details of the branch prediction information update will be described later. The branch prediction information 33 read from the branch prediction table 32 is supplied to the fetch direction determination unit 34 and the fetch suppression unit 36. The fetch direction determination unit 34 generates a predicted fetch signal 35 indicating the predicted direction of instruction fetch according to the branch prediction information. For example, the prediction fetch signal 35 is at a high level when the prediction direction is on the branch taken (taken) side, and is at a low level when the prediction direction is on the not taken branch side. The fetch suppression unit 36 inputs the value of the fetch mode switching bit 17 and the branch prediction information 33. In the first fetch mode, the non-prediction side fetch suppression signal 37 is negated (deactivated level), and the non-prediction side instruction Allow fetching. In the second fetch mode, the accuracy of the prediction direction is determined from the branch prediction information 33. When it is determined that the accuracy is high, the non-prediction side fetch suppression signal is asserted (set to the activation level), and the non-prediction side instruction fetch. Instructs suppression. When it is determined that the accuracy of the prediction direction determined from the branch prediction information 33 in the second fetch mode is low, the non-prediction side fetch suppression signal is negated to instruct permission of the non-prediction side instruction fetch. The fetch address generation circuit 20 to which the prediction fetch signal 35 and the non-prediction side fetch suppression signal 37 are given is not instructed to suppress the non-prediction side instruction fetch, and the fetch side buffer 38 has the prediction side address of the conditional branch instruction. And the non-prediction side address are set, and both the prediction side instruction and the non-prediction side instruction are fetched using an empty cycle of the internal bus. On the other hand, when it is instructed to inhibit fetching of the non-predictive instruction, the fetch address generation circuit 20 sets the predictive address of the conditional branch instruction in the fetch address buffer 38 and uses an empty cycle of the internal bus. Thus, the prediction side instruction is fetched, and the non-prediction side instruction is not fetched. The decision information of the conditional branch direction of the conditional branch instruction is returned from the pipeline execution unit to the fetch control unit 4 by a signal 18, and the fetch control unit 4 updates the accuracy or the prediction direction of the corresponding prediction information 33 according to the prediction success / failure. To do. The signal 18 is generated at the E3 stage of the conditional branch instruction. With this information, the preliminary information of the branch prediction table corresponding to the address of the confirmed conditional branch instruction is updated.

  FIG. 5 illustrates an instruction fetch flow utilizing the branch prediction information. The flow in the pipeline stage I2 and PD stages is composed of steps S1, S2, S3, and S4, and the pipeline stage I1 stage is composed of steps S5, S6, and S7. In step S1, the instruction buffer 15 is searched to detect a conditional branch instruction. In S2, the branch prediction table 32 is subtracted from the address of the detected branch instruction, and the branch prediction direction and the prediction accuracy of the conditional branch instruction are acquired. In S3, it is determined whether or not the second fetch mode is instructed by the fetch mode switching bit 17. When the second fetch mode is instructed, it is determined in S4 whether the prediction accuracy of the conditional branch is high. If it is determined in S4 that the prediction accuracy of the conditional branch prediction is high, in S6, the instruction on the prediction side is fetched, and the instruction fetch on the non-prediction side in the subsequent empty cycle is suppressed. If it is determined in S4 that the prediction accuracy of the conditional branch prediction is low, or if the fetch mode is determined to be the first fetch mode in S3, the instruction on the prediction side is fetched in S5, and the subsequent empty cycle Do not suppress instruction fetch on the non-prediction side. In the flow of FIG. 5, the flow in the I2 stage of the pipeline stage is composed of steps S1, S2, S3, and S4. When a conditional branch instruction is detected in the stage, the branch destination of the conditional branch instruction or The I1 stage of the non-branch destination instruction is composed of steps S5, S6, and S7.

  Here, when the fetch control unit 4 fetches N1 branch prediction side instructions and N2 branch non-prediction side instructions in the conditional branch instruction in the first fetch mode, the fetch control unit 4 predicts the conditional branch instruction in the second fetch mode. When the information indicating the accuracy indicates a high prediction accuracy, N3 instructions on the prediction side are fetched. At this time, it is desirable to satisfy the relationship of N3 <N1, N2. From the point of view of low power consumption by eliminating unnecessary instruction fetches, even if the accuracy is high, fetching more predictor instructions than when fetching non-predictor instructions together This is because the low power consumption effect may not be sufficiently exhibited.

  FIG. 6 shows the significance of the branch prediction information and the calculation method of the prediction accuracy. The branch prediction information 33 stored in the branch prediction table is composed of two prediction bits. For example, the number of entries in the branch prediction information 33 is 256. The state of the branch prediction information 33 holds a value reflecting the history of prediction for the past branch establishment (Taken) and branch failure (Not Taken) of the corresponding conditional branch instruction. There are four prediction states for each branch prediction information. The state 0 is branch failure failure (NotTaken) strong prediction, and indicates the state in which the accuracy of the NotTaken direction is high as the direction of the conditional branch. State 1 is a weak prediction of branch failure (NotTaken), and the conditional branch direction is prediction of the NotTaken direction, but the accuracy is low. State 2 is weak prediction of branch establishment (Taken), and the direction of conditional branch is prediction of Taken direction, but the accuracy is low. State 3 is branch prediction (Taken) strong prediction, and the condition branch direction indicates a state in which the accuracy in the Taken direction is high. The transition of the 2-bit prediction information 33 is incremented by 1 if the determined branch direction of the conditional branch instruction is Taken, and saturated to the maximum value when the bit maximum value is reached. If the determined branch direction of the conditional branch instruction is NotTaken, 1 is subtracted, and when the bit minimum value is reached, it is saturated to the minimum value. The update timing of the prediction information 33 is a point in time when the direction of the currently predicted conditional branch instruction is fixed, and this conditional branch direction determination information is reflected by the signal 18 from the pipeline execution unit. This information is generated at the E3 stage of the conditional branch instruction.

  FIG. 7 illustrates the fetch mode switching bit 17 of the control register 16. The fetch mode switching bit 17 is defined in a predetermined bit field in the control register 16 of the CPU, and when this bit is a logical value 0, it designates the first fetch mode that does not inhibit the instruction fetch on the non-prediction side, and this bit is logical When the value is 1, the second fetch mode for selectively inhibiting instruction fetching on the non-prediction side is designated. Depending on the value of the fetch mode switching bit 17 of the control register 16, the instruction fetch control unit 4 can change the fetch operation of the branch destination of the conditional branch instruction and the non-branch destination instruction.

  FIG. 8 illustrates an instruction sequence for controlling the instruction fetch mode. The instruction fetch mode can be switched from the program by the CPU instructions shown in the instruction sequence 81 and the instruction sequence 82. In the first fetch mode setting instruction sequence 82, the address of the control register 16 holding the fetch mode switching bit 17 is loaded, the value of the control register is loaded, and the mode value is set to the value of the first fetch mode (logical value 0). The first fetch mode is set by writing the changed value to the control bit 17. In the second fetch mode setting instruction sequence 81, the address of the control register 16 holding the fetch mode switching bit 17 is loaded, the value of the control register is loaded, and the mode value is set to the value of the second fetch mode (logical value 1). The second fetch mode is set by writing the changed value to the control bit 17. In short, the instruction fetch mode can be dynamically switched by rewriting the control bit 17 of the control register 16 with an instruction.

  FIG. 9 shows a method for generating a control code in the instruction fetch mode as shown in FIG. Here, the second fetch mode can be selected in accordance with the execution of the program to be operated with low power consumption. In step T1, the target program is compiled. At T2, the program generated at T1 is executed by the simulator, and an execution profile such as the number of elapsed cycles in function units on the source code is acquired. At T3, the execution profile is analyzed and a function having a large number of execution cycles is selected. At T4, it is determined whether the branch prediction hit rate of the function is high. If the branch prediction hit rate of the function is high, the source file is rewritten at T5. This is realized by inserting a pragma directive that instructs insertion of an instruction code for setting the instruction fetch mode in the function into the second fetch mode for low power consumption at the start point of the function. If the branch prediction hit rate of the function is low at T4, the code of the first fetch mode is inserted. However, if the first fetch mode is set to the default setting in operation, the source code of the function does not need to be rewritten. . At T6, recompiling the program completes compiling the program for low power consumption. With this method, it is possible for a software programmer to incorporate an instruction sequence for controlling fetch mode switching into the software.

  FIG. 10 shows an example of an instruction fetch mode setting pragma directive on the source code. A pragma is a compiler directive that is used to pass specific information to the compiler, which allows detailed control of the compilation. In the code 100 of FIG. 10, when the function “func0 ()” is compiled in the second fetch mode of the instruction, the pragma directive “#pragma fetch_mode_2 (func0)” is described in the source code. A compiler that recognizes the pragma directive generates an instruction sequence indicated by code 101.

  According to the fetch control unit 5 using the branch prediction described above, the conditional branch prediction is missed in the first fetch mode in which the instruction fetch on the prediction side and the instruction fetch on the non-prediction side are performed in the execution of the conditional branch instruction. However, since the instruction fetch on the non-prediction side is performed, the number of stall cycles in the pipeline at the time of a conditional branch prediction error is reduced, which contributes to high-speed program execution. In execution of a conditional branch instruction, in the second fetch mode in which the instruction fetch operation can be performed by determining whether or not to fetch an instruction on the non-prediction side according to the state of the prediction bit indicating the conditional branch direction, the conditional branch direction is set to Fetch instructions that are not actually needed in program execution in order to suppress non-predicted instruction fetches when it is determined that the conditional branch prediction will hit with a high probability according to the state of the prediction bit indicated The number of times of memory reading is reduced and the number of times of memory reading is reduced, and the power required for memory reading is reduced. In the second fetch mode, when it is predicted that the conditional branch prediction will be hit with a high probability, the instruction fetch on the non-prediction side can be suppressed to reduce the number of memory reads, which is effective in reducing power consumption. In addition, if the conditional branch prediction is predicted to hit with a low probability, the instruction fetch on the non-prediction side is also performed. Therefore, even if the prediction actually deviates, the instruction fetch on the non-prediction side has already been performed. The number of pipeline installation cycles imposed on the execution of the instruction sequence in the branch direction is reduced, and high-speed execution is possible. The fetch mode can be changed by the switching bit 17, and in the second fetch mode, it is possible to selectively suppress fetch for the non-prediction side instruction in accordance with the prediction information 33. It is possible to respond flexibly to requests for high-speed execution.

  FIG. 11 shows another configuration of the fetch control unit 4. The difference from FIG. 4 is that the number of bits of the prediction information 33A is set to 1 bit, the size of the branch prediction table 32A is reduced or the number of entries is increased, and the branch prediction is used to index the accuracy for branch prediction. The shift register unit 21 that shift-inputs the hit result or the miss result and holds a plurality of branch results as the branch history information 22 from the latest is adopted. The branch prediction information 33A indicates the prediction direction of the conditional branch according to the value. A logical value of 0 means branch not taken (not taken) prediction, and a logical value of 1 means branch taken (taken) prediction. In the pipeline stage I2, the fetch address generation circuit 20 searches for a conditional branch instruction. The address of the conditional branch instruction is stored in the buffer 31, and the Taken side address and NotTaken side address of the conditional branch instruction are stored in the fetch address buffer 38 in association with the address of the conditional branch instruction. The branch prediction table 32A is accessed using a part of the instruction fetch address of the conditional branch instruction. The branch prediction table 32A is an associative memory that retains prediction information in correlation with the instruction address as described above. The fetch direction determination unit 34A receives the prediction information 33A output from the branch prediction table 32A, and generates a prediction fetch signal 45 according to the logical value. Further, the fetch suppression unit 36A receives the branch history information 22 representing the global history of branch hits from the shift register unit 21, determines the branch prediction accuracy from the past branch history, and determines the instruction fetch suppression signal on the non-prediction side. 37 is generated. The decision information of the conditional branch direction is reflected by the signal 18 from the pipeline execution unit. This information is generated at the E3 stage of the conditional branch instruction. With this information, the branch prediction information table 32A corresponding to the address of the confirmed conditional branch instruction is updated. Further, the branch history information 22 of the shift register unit 21 is shifted by 1 bit and updated by the information of the signal 18.

  FIG. 12 shows branch history information 22 held by the shift register unit 21 and a branch prediction accuracy determination operation based on the branch history information 22. For example, the branch history information is composed of 4 bits, and holds four bits representing a past prediction success with a logical value 1 and a prediction failure with a logical value 0 from the current conditional branch instruction. In the pipeline stage in which past information is shown from the right side of the figure to the left side bit and the direction of each conditional branch instruction is decided, the bit indicating the confirmed prediction success / failure is shifted in to the left side. The conditional branch prediction accuracy is determined based on the state of the branch history information 22 held by the shift register unit 21. For example, if the prediction has been successful three times in the past four predictions, that is, if there are three or more bits of logical value 1, it is determined that the accuracy of the current conditional branch prediction is high. The update timing of the shift register 22 is the time when the direction of the currently predicted conditional branch instruction is determined, and is generated at the E3 stage of the conditional branch instruction. If the prediction success is less than 3 times among the 4 predictions in the past, that is, if the number of bits with one logical value 1 is less than 3, it is determined that the accuracy of the current conditional branch prediction is low. In general, the number of bits of the shift register 22 is N bits, and the threshold value for accuracy determination is M bits as the number of bits with a logical value of 1; This can be realized by determining that the accuracy is low. In the second fetch mode, as described above, when the prediction accuracy is high, instruction fetch in the non-prediction direction is suppressed and instruction fetch in the prediction direction is performed. When the prediction angle is low, instruction fetch in both the prediction direction and the non-prediction direction is performed.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the number of bits of the branch prediction information is not limited to the above 1 bit or 2 bits. The branch history information is not limited to 4 bits. The number of pipeline stages and the number of instructions that can be fetched by one instruction fetch can be changed as appropriate. Further, the circuit modules possessed by the data processor are not limited to those shown in FIG. 1, and various modifications such as including a floating-point arithmetic unit in the processor core, no peripheral circuit bus, and other peripheral modules are possible. It is. The data processor may be not only a general-purpose microprocessor but also a semiconductor integrated circuit specialized for system-on-chip specific control.

It is a block diagram which shows an example of a data processor. When the first fetch mode is selected, a pipeline stage for issuing an instruction fetch in the predicted branch direction and an instruction fetch on the non-prediction side and storing the instruction fetched via the internal bus in the instruction buffer 15 It is operation | movement explanatory drawing which illustrates these. When the second fetch mode is selected, when the accuracy of branch prediction is high, it is an operation explanatory diagram illustrating the pipeline stage when the fetch of the instruction stream on the non-prediction side is suppressed. It is a block diagram which illustrates the structure for the instruction fetch control according to fetch mode. It is a flowchart which illustrates the instruction fetch flow using branch prediction information. It is explanatory drawing which illustrates the calculation method of the significance of branch prediction information, and prediction accuracy. It is a format diagram of a control register having a fetch mode switching bit. It is explanatory drawing which illustrates the instruction sequence which controls instruction fetch mode. It is a flowchart which shows the production | generation method of the control code of instruction fetch mode. It is explanatory drawing which illustrates the instruction fetch mode setting pragma directive in a source code. It is a block diagram which illustrates another composition of a fetch control part. It is explanatory drawing which shows the branch history information which a shift register part holds, and the determination operation | movement of the branch prediction accuracy by it.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Processor core 2 Cache memory 4 Internal bus 5 Fetch control part 6 Pipeline execution part 7 Data processor 13 Bus state controller 15 Instruction buffer 16 Control register 17 Fetch mode switching bit 20 Fetch address generation circuit 31 Condition branch instruction address buffer 32, 32A Branch prediction table (prediction information table)
33, 33A Branch prediction information 34, 34A Fetch direction determination unit 35 Predictive fetch signal 36, 36A Fetch suppression unit 37 Non-prediction side fetch suppression signal 38 Fetch address buffer

Claims (14)

An instruction fetch control unit, an instruction buffer that holds an instruction fetched by the fetch control unit, and an execution unit that executes the instructions held in the instruction buffer in a predetermined order in a pipeline,
The fetch control unit obtains prediction information indicating a prediction direction and accuracy of a conditional branch using an instruction address of the branch instruction, fetches a branch prediction side instruction and a branch non-prediction side instruction in the conditional branch instruction. And a data processor that selectively inhibits fetching of instructions on the branch non-prediction side according to the prediction information. The data processor according to claim 1, wherein the fetch control unit suppresses fetching of the non-prediction side instruction when the accuracy of branch prediction based on the prediction information is relatively high. An instruction fetch control unit, an instruction buffer that holds an instruction fetched by the fetch control unit, and an execution unit that executes the instructions held in the instruction buffer in a predetermined order in a pipeline,
The fetch control unit obtains prediction information indicating a prediction direction and accuracy of a conditional branch using an instruction address of the branch instruction, fetches a branch prediction side instruction and a branch non-prediction side instruction in the conditional branch instruction. The first fetch mode that performs both of the above and the second fetch mode that fetches the instruction on the branch prediction side and selectively suppresses fetching of the instruction on the branch non-prediction side according to the prediction information can be selected. Data processor. 4. The data processor according to claim 3, wherein the fetch control unit suppresses fetching of the instruction on the non-prediction side when the accuracy of branch prediction based on the prediction information is relatively high in the second fetch mode. 5. The data processor according to claim 4, further comprising a control register for designating the first fetch mode or the second fetch mode according to a set value. 6. The data processor according to claim 5, wherein the set value of the control register is variable by instruction execution by the execution unit. The prediction information has a plurality of bits, each representing a different branch prediction and its accuracy according to the difference in value,
The fetch control unit includes a prediction information table unit that is indexed using a part of an instruction address of a conditional branch instruction and stores a plurality of the prediction information,
When the branch of the conditional branch instruction is confirmed, the fetch control unit, when the prediction information indexed using the conditional branch instruction is a hit, the prediction information is limited to the maximum accuracy of the prediction. The data processor according to claim 6, wherein the prediction information is updated in a direction in which the prediction accuracy decreases when the prediction information indexed using the conditional branch instruction is a miss. . 8. The data processor according to claim 7, wherein the maximum value of the branch prediction information means the maximum accuracy of branch prediction due to the condition establishment in the conditional branch instruction, and the minimum value means the maximum accuracy of branch prediction due to the failure of the condition in the conditional branch instruction. An instruction fetch control unit, an instruction buffer that holds an instruction fetched by the fetch control unit, and an execution unit that executes the instructions held in the instruction buffer in a predetermined order in a pipeline,
The fetch control unit is indexed by using a part of the instruction address of the conditional branch instruction, and a prediction information table unit for storing a plurality of branch prediction information, and a shift result of a branch result of hit or miss for branch prediction is input from the latest A shift register unit that holds a plurality of branch results as branch history information;
The branch prediction information indicates the prediction direction of the conditional branch according to the value,
The fetch control unit can fetch a branch prediction side instruction and a branch non-prediction side instruction in a conditional branch instruction, and determine branch accuracy from branch history information held by the shift register unit. A data processor that suppresses fetching of instructions on the branch non-prediction side when the branch accuracy is high. The data processor according to claim 9, wherein the fetch control unit determines that the accuracy of branch prediction is high when a branch result of more than half of the branch history information held by the shift register unit indicates a prediction hit. An instruction fetch control unit, an instruction buffer that holds an instruction fetched by the fetch control unit, and an execution unit that executes the instructions held in the instruction buffer in a predetermined order in a pipeline,
The fetch control unit is indexed by using a part of the instruction address of the conditional branch instruction, and a prediction information table unit for storing a plurality of branch prediction information, and a shift result of a branch result of hit or miss for branch prediction is input from the latest A shift register unit that holds a plurality of branch results as branch history information;
The branch prediction information indicates the prediction direction of the conditional branch according to the value,
The fetch control unit obtains prediction information indicating the prediction direction of the conditional branch using the instruction address of the branch instruction, and fetches both the branch prediction side instruction fetch and the branch non-prediction side instruction fetch in the conditional branch instruction. A first fetch mode to be performed, and fetching an instruction on the branch prediction side, and when branch history information acquired from the shift register unit indicates a high branch accuracy, fetching an instruction on the branch non-prediction side is suppressed. A data processor that enables selection between two fetch modes. 12. The data processor according to claim 11, further comprising a control register for designating the first fetch mode or the second fetch mode according to a set value. 13. The data processor according to claim 12, wherein the set value of the control register is variable by instruction execution by the execution unit. An instruction fetch control unit, an instruction buffer that holds an instruction fetched by the fetch control unit, and an execution unit that executes the instructions held in the instruction buffer in a predetermined order in a pipeline,
The fetch control unit includes a first fetch function for fetching N1 branch prediction side instructions and N2 branch non-prediction side instructions in a conditional branch instruction, and information indicating a prediction accuracy for a conditional branch instruction with high prediction accuracy. , A data processor having a second fetch function for fetching N3 instructions on the prediction side and N3 <N1, N2.

Images