JP2007128336A - Parallel register access device and system lsi - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a parallel register access device capable of speeding up access to a plurality of peripheral registers as the whole. <P>SOLUTION: The device includes: a plurality of register access modules accessing the peripheral registers according to an instruction previously stored in a memory; and an arbitration part arbitrating access from the plurality of register access modules. The parallel register access device has a parallel access function to the plurality of peripheral functioning independently of a CPU. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a parallel register access device and a system LSI.

  Japanese Patent Laid-Open No. 11-353153 discloses a register setting circuit that can easily change the setting of the initial value of a register in the system at low cost. The register setting circuit disclosed in the publication includes a program code storage area for storing a program code for changing an initial value of a register and a non-volatile memory having a register setting area for storing a setting value for changing the initial value of the register And a setting control circuit for directly changing and setting the initial value of the register according to the setting value read from the register setting area based on the program code in the program code storage area, and instructed by the CPU. It is possible to change the initial value of the register simply by reading the set value in the register setting area.

JP 11-353153 A

  By the way, it can be seen that a cellular phone or the like takes time from when the power is turned on until a picture is displayed on the liquid crystal screen. One of the factors that slows down the start-up of the system is that it takes time to initialize the system LSI, and it is even faster to have a good feeling not only for the model but also for the manufacturer. Is required.

  FIGS. 16, 19, and 20 are diagrams showing a flow when the CPU initializes a plurality of peripherals (peripherals, peripheral devices). As shown in the figure, in the conventional method, after the power is turned on and reset is released, the CPU initializes peripheral A (see FIG. 17), and then initializes peripheral B (see FIG. 18). ), The CPU processes n peripherals in series.

  The first problem is that in the initialization of a certain peripheral, after setting a certain register (Register), for example, (Registers B and C), there is a case where a certain amount of “wait” is necessary, and the subsequent The delay is propagated to the process. This waiting time may reach several tens of ms, which is one factor in prolonging the entire initialization process as shown in FIG.

  The second problem is that, as shown in FIG. 20, the restriction that registers A, B, and C must be set only after a certain period of time has passed since power is turned on. The processing start time of peripheral initialization and subsequent processing is delayed. The above constraints are imposed to wait for the power supply and clock to stabilize, but in reality, at the time when the peripheral is initialized, a time longer than the above constraint time has often passed. There is a lot of waste.

  Further, in the system in which the peripherals are initialized in series by the CPU, the first and second problems can be solved only by giving complicated instructions to the CPU or rationalizing compilation. Another problem is that it puts a heavy burden on software designers.

  According to the register setting circuit described in Patent Document 1, there is a possibility that the load on the CPU and the burden on the software designer related to the above may be reduced. However, in terms of performing serial access to the register, The same is true, and there is no change in that a waiting time loss occurs.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an apparatus capable of speeding up the overall read / write processing to a plurality of registers represented by the initialization. There is.

  According to a first aspect of the present invention, there is provided a parallel register access device that is connected to a plurality of peripherals via a bus and operates independently of a CPU, and each of the peripherals according to instructions stored in a memory in advance. A parallel register comprising a plurality of register access modules for accessing a plurality of registers, and an arbitration unit for arbitrating accesses from the plurality of register access modules, and providing a parallel access function to a plurality of peripherals An access device is provided.

  According to the present invention, a mechanism for minimizing the waiting time and efficiently accessing a plurality of registers is provided. More specifically, this advantage is exhibited in the initialization of a system that requires access to a plurality of registers, and the time required for initialization can be greatly reduced.

  Next, the best mode for carrying out the present invention will be described in detail with reference to the drawings. FIG. 1 shows a configuration of a first embodiment of a system LSI including a parallel register access apparatus according to the first embodiment of the present invention embodied as an LSI initialization apparatus (DRSC: Direct Register Set Controller, hereinafter referred to as DRSC). It is a block diagram showing.

  Referring to FIG. 1, a CPU 2a, a DRSC 2b, a DMAC (Direct Memory Access Controller) 2c, a DSP (Digital Signal Processor) 2d, an internal bus 2e, an external memory I / F 2f, an internal memory 2l, an interrupt controller 2k, and peripherals 2g to 2j A configuration is shown in which the system LSI 1a provided is connected to an external storage device 1b such as a nonvolatile memory, a volatile memory, or a hard disk.

  FIG. 2 is a block diagram showing the detailed configuration of the DRSC 2b. Referring to FIG. 2, the DRSC 2b includes a register group (Registers) 4a, a DRSM (Direct Register Set Module) group 4b that operates as a register access module and can independently initialize each peripheral, and from each DRSM. An arbitration unit (Arbiter) 4c that arbitrates access and an error status manager (Error Status Manager) 4d that holds error state information and generates an interrupt to the interrupt controller 2k are configured.

  Each DRSM (DRSMa to DRSMn) included in the DRSM group 4b operates independently, and executes initialization processing in accordance with an instruction read from an area in which initialization data of the external storage device 1b is written.

  The arbitrating unit (Arbiter) 4c arbitrates access from each DRSM (DRSMa to DRSMn). Therefore, when a plurality of access requests are issued at the same time, only the access that has won the arbitration can initialize the peripheral to be initialized.

  Accordingly, for example, the DRSC 2b is schematically illustrated in FIG. 3 by giving instructions to initialize the peripherals A2g and B2h to at least two DRSMs (for example, DRSMa and DRSMb), respectively, and arbitrating access from each DRSM. As shown in FIG. 2, the registers 3a and 3b of the two peripherals A and B can be accessed directly and in parallel. Meanwhile, the CPU 2a is in a free state and can access other resources.

  4 to 9 are diagrams for explaining a detailed configuration of the register group (Registers) 4a. As shown in FIG. 4, DRSC_START_ADDRn is a 32-bit register, and the start address on the external storage device storing the instruction (see FIG. 10) to be given to the nth (n; the number of DRSM) DRSM is stored. Stored.

  As shown in FIG. 5, DRSC_INTERRUPT_STATUSn stores various statuses of the nth (n; the number of DRSM) DRSM, and is used to monitor the interrupt generation status.

  As shown in FIG. 6, DRSC_INTERRUPT_ENABLEn stores n (n: the number of DRSM) -th DRSM interrupt enable / disable settings.

  As shown in FIG. 7, DRSC_POLL_TIMEOUTn is used when setting the number of clocks up to Timeout when [Polling TimeoutEn] Field of DRSC_INTERRUPT_ENABLEn is set to Enable'1 '.

  As shown in FIG. 8, DRSC_CHANEL_GO indicates an operation instruction given to each DRSM, and a Start / Stop bit representing the operation instruction is written in each DRSM position (GOOnField). FIG. 8 shows an example in which the DRSC 2b includes 15 DRSMs, and these DRSMs can be managed using 15 bits out of 32 bits.

  For example, when performing initialization, the CPU writes a Start bit “1” in a corresponding location of DRSC_CHANEL_GO in order to activate a required DRSM of the DRSM group 4b. The DRSM in which the Start bit is written reads an instruction from the address specified in the DRSC_START_ADDRn and starts operation.

  As shown in FIG. 9, DRSC_CHANEL_STATUS indicates the operation status of each DRSM, and the status (operating / stopped) bit is written at the position of each DRSM.

  FIG. 10 is a diagram showing how instructions are stored in the external storage device 1b, and FIG. 11 is a diagram showing a detailed configuration of the instruction field shown in FIG. As shown in FIG. 10, instruction field data in 128-bit units is prepared in advance in a predetermined area of the external storage device 1b according to the execution order. In the instruction field data, an address (data to be initialized), data, verify data, an instruction operand, and an end bit are stored.

  Therefore, a series of instructions to be given to the DRSM is constituted by the contents from the instruction field stored at the address specified by DRSC_START_ADDRn to the instruction field in which the [End] bit '1' is set.

  Next, some examples of instructions that can be executed in DRSM will be described.

  When [ReWr] Field is “0”, it is interpreted as a Write instruction, and the contents of [Data] Field are written into the register having the address specified in [Address] Field. Further, when [Verify] Field is “1”, it is interpreted as “Verify” required, and the contents of the written address are read, and the Verify operation is performed to collate with [Data] Field. Furthermore, when [ReVerifyWr] Field is “1”, it is interpreted as a Read Verify Write instruction, and the contents of the address specified in [Address] Field are read first, and the result is read in [Verify Data] Field. The operation of storing and writing the result of ORing with the value of [Data] Field is performed at the address of [Address] Field.

  On the other hand, when [ReWr] Field is “1”, it is interpreted as a Read instruction, and the contents of the register having the address specified in [Address] Field are read and stored in [Data] Field. Again, if [Verify] Field is “1”, it is interpreted as Verify required, and a Verify operation is performed to collate the read contents with the contents of [Verify Data] Field. Furthermore, when [Polling] Field is “1”, the [Address] Field is polled until the read data matches [Verify Data] Field. Furthermore, when [Polling] Field is “1”, [Timeout] Field can also be set to “1”, and the Timeout function can be validated.

  When a value is set in [Repeat] Field, the instruction written in the instruction Field is repeated by the number of times written in [Repeat] Field.

  Also, when [Wait] Field is “1”, it is interpreted as a Wait instruction, and a wait for the value specified by [Data] Field × clock is performed. [NOP] If Field is '1', the instruction written in the instruction Field is skipped.

  Further, when [Comp] Field is “1”, it is interpreted as a Compare instruction for performing a conditional branch according to the read content. FIG. 12 is a diagram for explaining the operation of the Compare instruction defined to execute three instructions according to the read contents. As shown in FIG. 12, when the Compare instruction at the address 0x ***** 0020 is read, the DRSM first reads the contents of the address specified in [Address] Field, and [Data] Field, [Verify] Field. Compare with the contents of.

  As a result of the comparison, if the read data matches the contents of [Data] Field, DRSM executes the immediately following commands Field 4 to 6 (addresses 0x *** 0030 to 0x ******* 0050). Then, after executing the instruction Field6, the program jumps to the address 0x ****** 0090 and executes the instruction Fieldda.

  On the other hand, if the read data matches the contents of [Verify] Field, DRSM executes instructions Fields 7 to 9 (addresses 0x *** 0060 to 0x ****** 0080), and directly executes the instruction Fieldda. Execute.

  The specific example of the Compare instruction has been described above, but the number of instruction executions based on the comparison result is not limited to three instructions, and can be designed flexibly according to the application.

  Subsequently, the operation of the DRSC 2b of the present embodiment will be described by giving an example in which the system LSI 1a is initialized. First, the DRSM in which the Gon bit = 1 of the DRSC_CHANEL_GO is read by the CPU 2a, the instruction Field data at the address stored in the [StartAddress] Field of the DRSC_START_ADDRn.

  DRSM decodes the contents of instruction Field and executes the instruction. When the execution of the instruction is completed, the DRSM reads and executes the next instruction Field data. The DRSM operates according to the content set in [Repeat] Field or the content set in [Wait] Field as appropriate, and repeats the execution of the instruction until the instruction Field in which “1” is set in [End] Field.

  [END] After executing the instruction in which “1” is set in Field, DRSC writes Stop bit “0” in the DRSM position (GOn) of DRSC_START_ADDRn, and DRSM stops.

  In the above process, for example, when the execution of the instruction field whose [End] Field is “1” is finished, the DRSM changes the [EndST] Field of its own DRSC_INTERRUPT_STATUSn to “1”.

  Similarly, when Read Verify is executed, if the read value does not match the value of [Verify Data] Field, DRSM changes [ReadErr] Field of its own DRSC_INTERRUPT_STATUSn to “1”.

  Similarly, when the value of [Data] Field of the instruction field and the actually written value do not match when the Write Verify is executed, the DRSM sets [WriteErr] Field of its own DRSC_INTERRUPT_STATUSn to “1”. Change to

  Similarly, when executing the polling with the timeout function enabled, the polling data (the data specified by the [address] field) is the [Verify Data] of the instruction field even when the [PollTimeout] Field clock of DRSC_POLL_TIMEOUTn has elapsed. If it does not match the Field, the DRSM changes [PollingTimeout] Field of its own DRSC_INTERRUPT_STATUSn to “1”.

  Similarly, if the read data does not match the contents of [Data] Field and [Verify] Field when the Compare instruction is executed, DRSM sets [CompareErr] Field of its own DRSC_INTERRUPT_STATUSn to ' Change to 1 '.

  In this way, the interrupt of each DRSM is cleared by setting “1” to each bit of DRSC_INTERRUPT_STATUSn.

  FIG. 13 is a diagram illustrating a situation when register settings of four Peripheral A to D are performed by three DRSMs through the arbitration unit 4c of the DRSC 2b. First, the arbitration unit 4c permits access from DRSMa to PeripheralA having the highest priority, but when DRSMa reads the wait instruction, switching from DRSMc to PeripheralC is performed.

  Subsequently, even if DRSMc completes the setting of PeripheralC, since the register setting process of PeripheralD is described in the subsequent instruction Field, Access to PeripheralD is performed. Then, when DRSMc reads the wait command, the access is switched from DRSMb to PeripheralB.

  Subsequently, when DRSMb completes the setting of PeripheralB and “1” is set in [EndST] Field of DRSC_INTERRUPT_STATUSb, this time, switching from DRSMc to PeripheralD is performed.

  When the DRSMa executes one instruction, the DRSMa waiting time has ended, so this time the DSMMa is switched to the access to Peripheral A. Then, when DRSMa completes the setting of Peripheral A and “1” is set in [EndST] Field of DRSC_INTERRUPT_STATUSa, it is switched again to access to Peripheral D from DRSMc, and all the Peripherals are initialized.

  As described above, when a plurality of DRSMs process initialization of each peripheral in parallel, other peripherals can be initialized during the waiting time for initialization of a certain peripheral. It can be shortened.

  Also, as described above, since the operation instruction (Start / Stop) to the DRSM can be set freely, an initialization routine can be configured flexibly and the load on each DRSM can be leveled. .

  In addition, the burden on the software designer is greatly reduced. For example, it is possible to reduce the total time required for initialization by determining whether or not each DRSM is operating and rearranging the instruction order.

  Next, a description will be given of a second embodiment of the present invention in which the initialization operation is performed at the time of reset in the configuration of the first embodiment. FIG. 14 is a diagram showing values (ResetValue) to be written to DRSC_CHANEL_GO when an instruction is given to operate the required DRSM simultaneously with the reset operation.

  Referring to FIG. 14, in Reset value, three GOn bits from DRSMa to DRSMc are set to “1”, and DRSMa to DRSMc start to move along with the reset release.

  Similarly, a Reset value of [StartAddress] Field of DRSC_START_ADDRa to DRSC_START_ADDRc is prepared, and a predetermined reset operation command can be read from a predetermined address of the external storage device 1b. More specifically, when starting up the CPU, add functions such as leaving indispensable peripheral settings or setting peripherals that can be set even before the PLL is initialized. Can do.

  Although the first and second embodiments of the present invention have been described above, the technical scope of the present invention is limited to the above-described embodiments, as is clear from the fact that instruction contents can be determined flexibly. It goes without saying that various modifications and replacements can be made without departing from the spirit of the present invention that allows direct and parallel access to a plurality of registers of the system LSI. Absent. For example, various known logics that realize parallel processing can be applied to the arbitration logic of the arbitration unit (Arbiter).

  For example, if instruction data is set in the external storage device 1b in advance, the system LSI equipped with the parallel register access device according to the present invention can be used as a randomly accessible host device. For example, it is possible to set other peripherals without degrading the performance of the CPU even when the CPU is moving in a closed state in the cache or accessing the built-in memory frequently.

  Also, as shown in FIG. 15, a DRSC_IO_INT_STARTn register having [IO_INT_Enable] Field for determining whether or not to accept a general-purpose IO interrupt for each DRSM and [IONNumber] Field for specifying a general-purpose IO number is added, and a predetermined general-purpose I / O is added. When an input interrupt from / O is received, the corresponding DRSM can start operating. In this case, the system LSI can change the register setting of the peripheral even when the CPU is off.

1 is a block diagram illustrating a configuration of a system LSI according to a first embodiment of the present invention. 1 is a block diagram showing a configuration of a DRSC included in a system LSI according to a first embodiment of the present invention. It is a figure showing schematic operation | movement of DRSC contained in the system LSI which concerns on the 1st Embodiment of this invention. FIG. 5 is a diagram for explaining the contents of a DRSC register group included in the system LSI according to the first embodiment of the present invention. FIG. 5 is a diagram for explaining the contents of a DRSC register group included in the system LSI according to the first embodiment of the present invention. FIG. 5 is a diagram for explaining the contents of a DRSC register group included in the system LSI according to the first embodiment of the present invention. FIG. 5 is a diagram for explaining the contents of a DRSC register group included in the system LSI according to the first embodiment of the present invention. FIG. 5 is a diagram for explaining the contents of a DRSC register group included in the system LSI according to the first embodiment of the present invention. FIG. 5 is a diagram for explaining the contents of a DRSC register group included in the system LSI according to the first embodiment of the present invention. It is a figure for demonstrating the command data prepared for the external storage device in the 1st Embodiment of this invention. It is a figure for demonstrating the command data prepared for the external storage device in the 1st Embodiment of this invention. It is a figure for demonstrating the operation | movement by the DRSC Compare instruction contained in the system LSI which concerns on the 1st Embodiment of this invention. It is a figure showing the flow of initialization of the some peripheral by DRSC contained in the system LSI which concerns on the 1st Embodiment of this invention. It is a figure for demonstrating the content of the register group of DRSC contained in the system LSI which concerns on the 2nd Embodiment of this invention. It is a figure for demonstrating the content of the register added in the 3rd Embodiment of this invention. It is a figure showing the flow of initialization of several peripherals by CPU. It is a figure for demonstrating initialization of the peripheral by CPU. It is a figure for demonstrating initialization of the peripheral by CPU. It is a figure showing the flow of initialization of several peripherals by CPU. It is a figure showing the flow of initialization of several peripherals by CPU.

Explanation of symbols

1a System LSI
1b External storage device 2a CPU
2b DRSC (Direct Register Set Controller)
2c DMAC (Direct Memory Access Controller)
2d DSP (Digital Signal Processor)
2e Internal bus 2f External memory I / F
2l Internal memory 2k Interrupt controller 2g to 2j Peripheral
3a, 3b Register (Register)
4a Registers (Registers)
4b DRSM (Direct Register Set Module) group 4c Arbiter
4d Error Status Manager (Error Status Manager)

Claims (5)

A parallel register access device connected to a plurality of peripherals via a bus and operating independently of the CPU,
A plurality of register access modules for accessing the registers of each peripheral in accordance with instructions stored in memory in advance;
An arbitration unit that arbitrates access from the plurality of register access modules, and provides a parallel access function to the plurality of peripherals;
A parallel register access device. Reads initialization data defining the register initialization procedure including the operation waiting time of the register access module from a predetermined memory, and initializes the peripherals in parallel to the register access modules. Running
The parallel register access apparatus according to claim 1. A register for setting whether or not an interrupt is permitted for each register access module;
A register for holding the operation status of each of the register access modules,
The arbitration unit performs arbitration using the register values;
The parallel register access apparatus according to claim 1, wherein: Each register access module has a register for setting whether or not an input interrupt from the outside of the system is possible,
The parallel access to the registers of multiple peripherals can be executed by a command from outside the system.
The parallel register access apparatus according to claim 1, wherein:
Providing   5. A system LSI comprising the parallel register access device according to claim 1 and the plurality of peripherals.

Images