JP2007317102A - Simulation device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a simulation device analyzing a timing to instruct the circuit change of software controlling a system by calculating a time required for changing the circuit of dynamically reconfigurable hardware included in the system. <P>SOLUTION: The simulation device includes; a simulation circuit storage device 50 storing data of a simulation circuit including a hardware model having a plurality of hardware operation models corresponding to a plurality of circuits respectively and a memory model having a plurality of pieces of data defining the plurality of circuits respectively; and an analysis module 10 which operates the simulation circuit by software to analyze the switching operation of the plurality of hardware operation models and calculates the time required for the switching operation, including a transfer time of a plurality of pieces of data from the memory model to the hardware model. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a simulation apparatus used for software analysis, and more particularly to a simulation apparatus used for software analysis for controlling a system including hardware that dynamically reconfigures a circuit.

  In recent years, hardware that dynamically reconfigures a circuit by switching a plurality of circuits (hereinafter referred to as “dynamically reconfigurable hardware”) has been used. The dynamically reconfigurable hardware dynamically changes its circuit configuration according to data defining the circuit configuration (hereinafter referred to as “hardware specification data”). By configuring a circuit suitable for the processing content, the dynamically reconfigurable hardware can achieve high-speed processing. Also, by adopting dynamically reconfigurable hardware, the hardware development period can be shortened compared to the case where dedicated hardware is newly produced.

  In order to develop software for controlling the system, circuit simulation using a simulation model is used (see, for example, Patent Document 1). When designing software that controls a system that includes dynamically reconfigurable hardware, it is necessary to predict the time required to change the circuit of the dynamically reconfigurable hardware during system operation. The time required for changing the circuit of the dynamically reconfigurable hardware depends on (1) the time for transferring the hardware specification data from the memory to the dynamically reconfigurable hardware, and (2) depending on the transferred hardware specification data. And the time required for completing the change of the circuit of the dynamically reconfigurable hardware. The software developer estimates the time required for the circuit change of the dynamically reconfigurable hardware, and describes an instruction (hereinafter referred to as “driver command”) instructing the circuit change to the dynamically reconfigurable hardware in the software. To do.

  However, even if the dynamically reconfigurable hardware is instructed to change the circuit, if the dynamically reconfigurable hardware is in operation, the circuit cannot be changed and can be dynamically reconfigured after the processing in operation is completed. The hardware circuit is changed. For this reason, if the timing at which the driver command is executed is not appropriate, a waiting time for changing the circuit of the dynamically reconfigurable hardware occurs, and the throughput of the entire system decreases.

  In general, a plurality of bus masters that can directly access the memory are connected to a bus that connects dynamically reconfigurable hardware and a memory that stores hardware specification data. The time required to transfer the hardware specification data from the memory to the dynamically reconfigurable hardware varies depending on the data transfer status on the bus, that is, the access status of each bus master to the memory. Therefore, it is difficult to estimate the time for transferring the hardware specification data from the memory to the dynamically reconfigurable hardware.

In the related art, the timing for instructing the circuit change of the dynamically reconfigurable hardware cannot be accurately analyzed in the software that controls the system including the dynamically reconfigurable hardware. For this reason, it is difficult to detect a malfunction due to the execution of the operation instruction for the dynamically reconfigurable hardware before the transfer of the hardware specification data to the dynamically reconfigurable hardware is completed. Furthermore, there has been a problem that the effort of adjusting the execution timing of the driver command by the manual operation of the software developer increases.
Japanese Patent Application Laid-Open No. 11-149489

  The present invention provides a simulation apparatus capable of analyzing the timing for instructing a circuit change of software for controlling the system by calculating the time required for the circuit change of the dynamically reconfigurable hardware included in the system.

  According to one aspect of the present invention, (a) a hardware model having a plurality of hardware operation models respectively corresponding to a plurality of circuits, and a memory model storing a plurality of data respectively defining the plurality of circuits are included. (B) The simulation circuit is operated by software to analyze the switching operation of a plurality of hardware operation models, and the transfer time of the plurality of data from the memory model to the hardware model And a simulation device for analyzing software, and an analysis module for calculating a time required for the switching operation including.

  According to the present invention, it is possible to provide a simulation device capable of analyzing the timing for instructing the circuit change of the software for controlling the system by calculating the time required for the circuit change of the dynamically reconfigurable hardware included in the system. it can.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. Further, the following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention. The technical idea of the present invention describes the structure, arrangement, etc. of components as follows. It is not something specific. The technical idea of the present invention can be variously modified within the scope of the claims.

As shown in FIG. 1, the simulation apparatus according to the embodiment of the present invention includes a hardware model having a plurality of hardware operation models respectively corresponding to a plurality of circuits, and a plurality of data defining each of the plurality of circuits. A simulation circuit storage device 50 that stores data of a simulation circuit including a memory model to be stored and a simulation circuit that is operated by software to analyze a switching operation of a plurality of hardware operation models, and a plurality of memory models to hardware models are analyzed. And an analysis module 10 for calculating the time required for the switching operation including the data transfer time, and analyze the software.

  The simulation apparatus shown in FIG. 1 further includes a memory 20, an input device 30, and an output device 40. The memory 20 includes a software storage area 21, a hardware configuration information storage area 22, and a log information storage area 23. The software storage area 21 stores analysis target software (hereinafter referred to as “target software”). The hardware configuration information storage area 22 stores hardware configuration information described later. The log information storage area 23 stores simulation results.

  The input device 30 includes a keyboard, a mouse, a light pen, a flexible disk device, or the like. A simulation executor can specify the target software or modify the simulation circuit from the input device 30. As the output device 40, a display or a printer for displaying the analysis result, a recording device for storing in a computer-readable recording medium, or the like can be used. Here, the “computer-readable recording medium” refers to a medium capable of recording electronic data such as an external memory device of a computer, a semiconductor memory, a magnetic disk, an optical disk, a magneto-optical disk, and a magnetic tape. means. Specifically, a “flexible disk, CD-ROM, MO disk, etc.” are included in the “computer-readable recording medium”.

  Hereinafter, an example in which software for controlling the system shown in FIG. 2 is analyzed using the simulation apparatus shown in FIG. 1 will be described. The system shown in FIG. 2 includes a processor 101 connected to a bus 105, dynamically reconfigurable hardware 102, a memory controller 103, and a memory 104. First, the system shown in FIG. 2 will be described.

  The processor 101 executes target software for controlling the system shown in FIG. 2 in units of instructions. The target software is stored in the memory 104. The processor 101 decodes the instruction fetched from the memory 104 and executes the decoded instruction to instruct a circuit change or the like in the dynamically reconfigurable hardware 102.

  When the dynamically reconfigurable hardware 102 receives a circuit configuration change command (hereinafter referred to as a “switching command”) transmitted by the processor 101 in accordance with a circuit change command included in the target software, the dynamically reconfigurable hardware 102 is designated by the switching command. The hardware specification data of the circuit is transferred from the memory 104, and the circuit configuration of the dynamically reconfigurable hardware 102 is changed. As the dynamically reconfigurable hardware 102, for example, a field programmable gate array (FPGA) can be employed.

  The memory controller 103 is a bus master that can directly access the memory 104, and is, for example, a direct memory access (DMA) controller. The memory controller 103 is controlled by the processor 101.

  The memory 104 stores target software for controlling the system shown in FIG. 2 and a plurality of hardware specification data. The transfer of hardware specification data from the memory 104 to the dynamically reconfigurable hardware 102 is controlled by the memory controller 103.

  The bus 105 is connected to the processor 101, dynamically reconfigurable hardware 102, the memory controller 103, and the memory 104. Data transfer among the processor 101, the dynamically reconfigurable hardware 102, the memory controller 103, and the memory 104 is performed via the bus 105.

  The configuration of FIG. 2 is an example, and a bus master other than the processor 101 and the memory controller 103 may be connected to the bus 105. For example, memories for storing the target software and hardware specification data may be separately connected to the bus 105. As described above, when a plurality of bus masters are connected to the bus 105, the number of clock cycles required to transfer hardware specification data from the memory 104 to the dynamically reconfigurable hardware 102 is transferred to the memory 104 of each bus master. Fluctuates depending on the access situation.

  The analysis module 10 shown in FIG. 1 operates the target software in a simulation circuit corresponding to the system shown in FIG. 2 in order to analyze the operation of the software that controls the system shown in FIG. FIG. 3 shows a simulation circuit for simulating the operation of the system shown in FIG. The processor model 201, hardware model 202, memory controller model 203, memory model 204, and bus model 205 shown in FIG. 3 are the same as the processor 101, dynamically reconfigurable hardware 102, memory controller 103, This is a circuit operation model that simulates the operations of the memory 104 and the bus 105, respectively. Each circuit operation model shown in FIG. 3 can be configured by a software module group that operates on a host processor such as a personal computer (PC) or a workstation (WS). The data of each circuit operation model is stored in the simulation circuit storage device 50 shown in FIG.

  In the simulation circuit shown in FIG. 3, the processor model 201 and the memory controller model 203 are connected to the bus model 205 as a bus master. A bus master circuit operation model such as another processor or a peripheral circuit may be connected to the bus model 205 in accordance with an actual use situation.

  The processor model 201 has a function of simulating the operation of the processor 101 and executing target software in units of instructions. The processor model 201 controls the hardware model 202, the memory controller model 203, and the memory model 204, respectively.

  The hardware model 202 simulates the operation of the dynamically reconfigurable hardware 102 that changes its own circuit configuration during system operation. As shown in FIG. 3, the hardware model 202 includes a plurality of hardware operation models 211 to 21n, an access control unit 220, a management unit 230, and a switching unit 240 (n: an integer of 2 or more).

  The hardware operation models 211 to 21n simulate the operations of a plurality of circuits that can be configured by the dynamically reconfigurable hardware 102, respectively. That is, the hardware model 202 includes hardware operation models 211 to 21n respectively corresponding to a plurality of hardware specification data transferred from the memory 104 to the dynamically reconfigurable hardware 102. In response to the switching command transferred from the processor model 201, the hardware model 202 changes the circuit to be simulated by switching the hardware operation models 211 to 21n. When the hardware model 202 switches the hardware operation models 211 to 21n, the circuit changing operation of the dynamically reconfigurable hardware 102 is simulated.

  The access control means 220 receives a request command to the hardware model 202 transferred from the processor model 201. The access control unit 220 controls access of the processor model 201 to the hardware model 202 according to the state of the hardware model 202. For example, the access control means 220 accesses the hardware model 202 of the processor model 201 during the period when the hardware model 202 switches the hardware operation models 211 to 21n or during the period when the hardware model 202 is operating. Is prohibited. When access to the hardware model 202 is prohibited, it is said that “the hardware model 202 is in an access prohibited state”.

  Based on the hardware configuration information set in the dynamically reconfigurable hardware 102, the management unit 230 indicates the relationship between the hardware operation models 211 to 21n and the circuit specified by the switching command included in the target software. Create a management table. The management table is stored in a management table storage area 231 included in the management unit 230. “Hardware configuration information” includes hardware operation models 211 to 21n corresponding to circuits that can be configured by the dynamically reconfigurable hardware 102 (hereinafter simply referred to as “configurable circuits”), and each configurable circuit. The corresponding indicator and information on the number of changed clock cycles necessary for changing the circuit formed by the dynamically reconfigurable hardware 102 to each configurable circuit are included. The “number of changed clock cycles” is the number of clock cycles required from completion of hardware specification data transfer to the dynamically reconfigurable hardware 102 to completion of the circuit change of the dynamically reconfigurable hardware 102.

  The circuit after the circuit change of the dynamically reconfigurable hardware 102 is determined by an indicator designated by a circuit change instruction included in the target software. FIG. 4 shows an example of a part including a circuit change instruction of the target software. FIG. 4 shows an example of changing the dynamically reconfigurable hardware 102 to a configurable circuit corresponding to the indicator “hweX”.

  FIG. 5 shows an example of hardware configuration information when the configurable circuits of the dynamically reconfigurable hardware 102 are the configurable circuit A and the configurable circuit B. As shown in FIG. 5, the hardware operation models of the configurable circuit A and the configurable circuit B are the operation model MA and the operation model MB, respectively. The indicator that designates the configurable circuit A by the instruction to change the circuit of the target software is the indicator “hweA”, which is necessary for changing the circuit that the dynamically reconfigurable hardware 102 configures to the configurable circuit A. The number of changed clock cycles is 20. The indicator that designates the configurable circuit B by the instruction to change the circuit of the target software is the indicator “hweB”, which is necessary for changing the circuit configured by the dynamically reconfigurable hardware 102 to the configurable circuit B. The number of changed clock cycles is 30.

  FIG. 6 shows an example of a management table created by the management unit 230 based on the hardware configuration information shown in FIG. As shown in FIG. 6, the management table includes a reference of an object in which a behavior description is described, a state in simulation, a change address indicating a timing for instructing a circuit change in the target software, and Contains information on the number of clock cycles required to change the circuit. When the program counter matches one of the changed addresses, the processor model 201 instructs the hardware model 202 to switch to the hardware operation model corresponding to the changed address. In other words, the management table indicates the relationship between the hardware operation model and the configurable circuit specified by the instruction for instructing the circuit change included in the target software. Information on the change address assigned to the indicator corresponding to each configurable circuit is included in the symbol information of the target software. The management unit 230 creates a management table with reference to software symbol information and hardware configuration information.

  The states that the hardware operation models 211 to 21n can take during simulation execution are any one of “execution state”, “executable state”, and “standby state”. The “execution state” indicates that the hardware model 202 is simulating the operation of the hardware operation model. The “executable state” indicates that the hardware model 202 can simulate the operation of the hardware operation model without switching the hardware operation model. The “standby state” indicates that the hardware model 202 cannot simulate the operation of the hardware operation model unless the hardware operation model is switched. The initial state of the hardware operation model in the management table is “standby state”.

  The switching unit 240 switches the hardware operation models 211 to 21n with reference to the management table in order to simulate the circuit changing operation of the dynamically reconfigurable hardware 102 instructed by the target software during the simulation. By switching the hardware operation models 211 to 21n, the hardware model 202 simulates the configurable circuit instructed by the target software.

The memory model 204 simulates the operation of the memory 104 such as reading of target software and hardware specification data. Transfer of hardware specification data from the memory model 204 to the hardware model 202 is controlled by the memory controller model 203. Specifically, the memory controller model 203 simulates the operation of transferring the data length L of data to be transferred from the memory 104 to the dynamically reconfigurable hardware 102 and the occupation request to the bus 105. The bus model 205 calculates the shortest clock cycle number C required for data transfer from the memory model 204 to the hardware model 202 from the data length L and the data width W of the bus 105 using the following equation (1). To:

C = α + L / W (1)

Here, the constant α is a value representing the number of clock cycles necessary for initial operation of each circuit in addition to data transfer, and is a constant value determined based on the architecture specifications adopted by the system. The data length L is also a value determined based on the architecture specification. For example, the data length L information is notified to the bus model 205 from the memory controller model 203 created based on the architecture specification.

  The bus model 205 detects requests from the processor model 201, the memory controller model 203, and other bus masters connected to the bus model 205, and grants data transfer permission to each bus master by an algorithm such as round robin. Then, the bus model 205 gives the data transfer permission to the end of the data transfer after counting the number of cycle clocks (hereinafter referred to as “the number of transfer clock cycles”) necessary for transferring the data requested by each bus master. Notify the bus master. The number of cycle clocks necessary for data transfer varies depending on the data transfer status in the bus model 205, that is, the access status of each bus master to the memory model 204. Therefore, the bus model 205 adjusts the data transfer request from each bus master, and the cycle clock obtained by adding the number of clock cycles calculated by the equation (1) to the number of clock cycles required for data transfer to the bus master in which data transfer is prioritized. The number is notified to each bus master as the number of transfer clock cycles.

  For example, if the bus master that has given the data transfer permission is the memory controller model 203, the hardware model 202 is notified that the transfer of the hardware specification data from the memory model 204 has been completed. As described above, the bus model 205 determines the time required to transfer hardware specification data from the memory 104 to the dynamically reconfigurable hardware 102, which varies depending on the data transfer status on the bus 105. Calculate as a number.

  Hereinafter, an example in which the target software that controls the system shown in FIG. 2 is analyzed by the simulation apparatus shown in FIG. 1 will be described. First, an example of analyzing the circuit changing operation of the dynamically reconfigurable hardware 102 will be described with reference to the flowchart shown in FIG. Hereinafter, an example in which the circuit of the dynamically reconfigurable hardware 102 is switched to the configurable circuit A illustrated in FIG. 5 will be described. That is, in the following analysis, the circuit simulated by the hardware model 202 is switched to the operation model MA. As described above, when the program counter of the processor model 201 matches the change address of the operation model MA, the operation of switching the circuit to be simulated by the hardware model 202 to the operation model MA is started.

  (A) In step S100, the target software and the hardware configuration information of the dynamically reconfigurable hardware 102 shown in FIG. 2 are input to the memory 20 via the input device 30 shown in FIG. Here, it is assumed that the hardware configuration information of the dynamically reconfigurable hardware 102 is the hardware configuration information illustrated in FIG. The target software and hardware configuration information are stored in the software storage area 21 and the hardware configuration information storage area 22, respectively.

  (B) In step S200, the analysis module 10 reads the target software and hardware configuration information from the software storage area 21 and the hardware configuration information storage area 22, respectively. Furthermore, the analysis module 10 reads the simulation circuit shown in FIG. 3 from the simulation circuit storage device 50 and starts the simulation.

  (C) In step S300, the management means 230 of the hardware model 202 shown in FIG. 3 creates the management table shown in FIG. 6 based on the hardware configuration information. The created management table is stored in the management table storage area 231 inside the management means 230.

  (D) In step S400, the analysis module 10 operates the target software in the simulation circuit shown in FIG. 3, and starts analyzing the target software. That is, the processor model 201 executes the target software in units of instructions.

  (E) In step S500, when the program counter of the processor model 201 matches the change address of the operation model MA, an operation of switching the hardware operation model of the hardware model 202 to the operation model MA is started. First, in step S510, the switching unit 240 determines whether or not the hardware model 202 is in an access prohibited state. If the hardware model 202 is not in the access prohibited state, the process proceeds to step S511. If the hardware model 202 is in an access prohibited state, the process proceeds to step S515.

  (F) In step S511, the hardware model 202 is set to an access prohibited state. Specifically, the switching unit 240 transfers to the access control unit 220 an access prohibition request that prohibits access to the hardware model 202. The access control unit 220 that has received the access prohibition request sets the hardware model 202 to the access prohibited state. In addition, the switching unit 240 transfers a request to transfer the hardware specification data of the operation model MA from the memory model 204 to the hardware model 202 to the memory controller model 203. Further, the switching unit 240 changes the state of the configurable circuit A in the management table from “standby state” to “executable state”.

  (G) In step S512, the transfer operation of the hardware specification data from the memory model 204 to the hardware model 202 is simulated. Specifically, a request to transfer the hardware specification data of the operation model MA from the memory model 204 to the hardware model 202 is transferred from the memory controller model 203 to the bus model 205. The bus model 205 calculates the number of transfer clock cycles necessary to transfer the hardware specification data of the operation model MA from the memory model 204 to the hardware model 202 using the equation (1) as described above. The bus model 205 notifies the hardware model 202 that the transfer of the hardware specification data from the memory model 204 is completed after counting the number of cycle clocks necessary for the transfer of the hardware specification data of the operation model MA. To do.

  (H) After the hardware model 202 is notified that the transfer of the hardware specification data has been completed, the analysis module 10 simulates the circuit changing operation of the dynamically reconfigurable hardware 102 in step S513. Specifically, the switching unit 240 refers to the management table stored in the management table storage area 231 and sets 20 as the number of changed clock cycles required until the circuit of the hardware model 202 is changed to the operation model MA. Countdown is performed as the initial value of the count value. The switching unit 240 decrements the count value by 1 every clock cycle and counts down until the count value becomes zero.

  (Re) After the count value reaches 0, the access prohibition state of the hardware model 202 is canceled in step S514. Specifically, the switching unit 240 transfers an access prohibition release request for canceling access prohibition to the hardware model 202 to the access control unit 220. The access control means 220 that has received the access prohibition release request releases the hardware model 202 from the access prohibited state, and the operation of switching the dynamically reconfigurable hardware 102 to the configurable circuit A is completed.

  (N) In step S515, the access control means 220 stops the access operation from the processor model 201 to the hardware model 202. In step S516, the access control unit 220 records log information such as a request command transferred from the processor model 201 to the hardware model 202 until the access prohibition state of the hardware model 202 is released. The log information is stored in the log information storage area 23 shown in FIG. Further, the access control means 220 counts the number of clock cycles until the access prohibition state of the hardware model 202 is released. After the access prohibition state of the hardware model 202 is released, the process proceeds to step S511.

  The access control unit 220 also records log information for a period during which the hardware specification data transfer operation and the dynamically reconfigurable hardware 102 circuit change operation are simulated. Further, the number of clock cycles during the period in which the access operation from the processor model 201 to the hardware model 202 is prohibited, including the changed clock cycle number and the transfer clock cycle number, is stored in the log information storage area 23 as a part of the log information. Is done.

  As described above, the analysis module 10 operates the target software in the simulation circuit and analyzes the change operation of the configurable circuit, thereby performing hardware specification data from the memory 104 to the dynamically reconfigurable hardware 102. The time required for reconfiguring the circuit of the dynamically reconfigurable hardware 102 including the transfer time is calculated as the number of clock cycles, and log information is created. The case where the configurable circuit is changed once has been described above. If there are multiple changes to the configurable circuit, log information is created at each change.

  Next, referring to the flowchart shown in FIG. 8, an example of analyzing the target software when access from the processor 101 is prohibited because the dynamically reconfigurable hardware 102 shown in FIG. 2 is operating. Will be explained. Hereinafter, the case where the circuit of the dynamically reconfigurable hardware 102 is the configurable circuit A illustrated in FIG. 5 will be described. That is, an example of analyzing the target software when the operation model MA is operating in the hardware model 202 will be described.

  (A) In steps S100 to S400 shown in FIG. 8, the management means 230 of the hardware model 202 shown in FIG. 3 creates a management table in the same manner as described with reference to the flowchart shown in FIG. Then, the analysis module 10 starts analyzing the target software.

  (B) In step S600, the behavior model MA operates in the hardware model 202 in response to a request command from the processor model 201.

  (C) In step S611, the hardware model 202 is set to an access prohibited state. Specifically, the switching unit 240 transfers to the access control unit 220 an access prohibition request that prohibits access to the hardware model 202. The access control unit 220 that has received the access prohibition request sets the hardware model 202 to the access prohibited state. The switching unit 240 changes the state of the configurable circuit A in the management table from “executable state” to “execution state”.

  (D) In step S612, the access control means 220 stops the access operation from the processor model 201 to the hardware model 202. In step S613, the access control unit 220 records log information such as a request command transferred from the processor model 201 to the hardware model 202 until the access prohibition state of the hardware model 202 is canceled. The log information is stored in the log information storage area 23 shown in FIG. Further, the access control means 220 counts the number of clock cycles until the access prohibition state of the hardware model 202 is released.

  (E) When the operation of the operation model MA according to the request command from the processor model 201 is completed, the access prohibition state of the hardware model 202 is canceled in step S614. Specifically, the switching unit 240 transfers an access prohibition release request for canceling access prohibition to the hardware model 202 to the access control unit 220. Receiving the access prohibition release request, the access control means 220 releases the hardware model 202 from the access prohibited state. In addition, after the access prohibition state of the hardware model 202 is released, the number of clock cycles in the period in which the access operation from the processor model 201 to the hardware model 202 is prohibited is the log information storage area 23 as part of the log information. Stored in

  As described above, according to the simulation apparatus shown in FIG. 1, log information is recorded during a period in which the hardware model 202 is in an access prohibited state and access to the hardware model 202 of the processor model 201 is stopped. Is done. During the period in which the hardware model 202 is in the access prohibited state, the circuit change operation of the dynamically reconfigurable hardware 102 after the program counter of the processor model 201 matches one of the change addresses of the hardware operation models 211 to 21n Is a period until one of the hardware operation models 211 to 21n is operating in the hardware model 202. The log information includes a request command transferred from the processor model 201 to the hardware model 202 and the number of clock cycles.

  FIG. 9 shows an example of log information stored in the log information storage area 23. Access to the hardware model 202 of the processor model 201 during the period in which the hardware model 202 is in an access-prohibited state is regarded as an error, and the column “error contents” shown in FIG. This indicates whether the operation model was “switching” or any one of the hardware operation models 211 to 21n in the hardware model 202 was “operating”. The column “time” indicates a clock cycle value when the processor model 201 accesses the hardware model 202 when the clock cycle value when the system starts operation is “0”. A column “pc” indicates a program counter value when the processor model 201 accesses the hardware model 202. The “count” column indicates the number of clock cycles in a period in which access to the hardware model 202 of the processor model 201 is stopped.

  As described above, the value in the “count” column when the access to the processor model 201 is performed during the switching of the hardware operation model is the hardware specification data transfer operation and the dynamically reconfigurable hardware 102. This includes the number of clock cycles during which the circuit change operation is simulated. That is, the value in the “Count” column includes the number of clock cycles required to transfer the hardware specification data from the memory 104 to the dynamically reconfigurable hardware 102 that varies depending on the data transfer status on the bus 105. The number of clock cycles required for transferring the hardware specification data is calculated based on the state of access to the memory 104 of each bus master. Therefore, according to the simulation apparatus shown in FIG. 1, the number of clock cycles required for changing the circuit of the dynamically reconfigurable hardware 102 can be easily estimated. As a result, it is easy to detect a malfunction due to execution of an operation instruction for the dynamically reconfigurable hardware 102 before the transfer of the hardware specification data to the dynamically reconfigurable hardware 102 is completed.

  The developer of the target software refers to the log information stored in the log information storage area 23 via the output device 40 shown in FIG. 1, so that the processor model 201 during the period when the hardware model 202 is in the access prohibited state. The occurrence of access to the hardware model 202 (hereinafter referred to as “error access”) can be detected. Therefore, the developer of the target software can modify the target software so as to reduce error access based on the log information. Specifically, the developer of the target software changes the timing at which the processor model 201 transfers the switching command to the hardware model 202 by correcting the change address of the indicator included in the symbol information of the target software. The developer of the target software sets the timing for executing the driver command in the target software based on the changed address corrected so that there is no waiting time of the processor 101. According to the above method, it is easier to correct the target software than the method of reducing error access while correcting the driver command setting itself of the target software, and the risk of bugs being mixed into the target software is also reduced. As a result, an increase in labor for adjusting the execution timing of the driver command by the manual work of the developer of the target software is suppressed.

  As described above, according to the simulation apparatus according to the embodiment of the present invention, it is possible to calculate the time required for the circuit change of the dynamically reconfigurable hardware according to the instruction of the target software that controls the system. Then, the developer of the target software can set the driver command so that the instruction for instructing the circuit change is executed at an optimal timing without the waiting time of the processor 101 by correcting the target software until there is no error access. . That is, the software developer can analyze the optimum timing for instructing the circuit change of the target software by the simulation apparatus shown in FIG. As a result, a decrease in the throughput of the entire system due to the circuit change waiting time is prevented.

(Other embodiments)
As described above, the present invention has been described according to the embodiment. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the description of the above-described embodiment, a system having only one dynamically reconfigurable hardware has been described. However, a simulation circuit is also configured for a system including a plurality of dynamically reconfigurable hardware. The target software can be analyzed.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

It is a schematic diagram which shows the structure of the simulation apparatus which concerns on embodiment of this invention. It is a schematic diagram which shows the example of the system which the software analyzed using the simulation apparatus which concerns on embodiment of this invention controls. It is a schematic diagram which shows the simulation circuit which simulates operation | movement of the system shown in FIG. It is a part of software analyzed using the simulation apparatus which concerns on embodiment of this invention. It is a table | surface which shows the example of the hardware configuration information which the simulation apparatus which concerns on embodiment of this invention uses. It is a table | surface which shows the example of the management table produced by the simulation apparatus which concerns on embodiment of this invention. It is a flowchart for demonstrating the example of the simulation method which concerns on embodiment of this invention. It is a flowchart for demonstrating the other example of the simulation method which concerns on embodiment of this invention. It is a table | surface which shows the example of the log information produced by the simulation apparatus which concerns on embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Analysis module 20 ... Memory 30 ... Input device 40 ... Output device 50 ... Simulation circuit memory | storage device 201 ... Processor model 202 ... Hardware model 203 ... Memory controller model 204 ... Memory model 205 ... Bus model 211-21n ... Hardware operation | movement Model 220 ... Access control means 230 ... Management means 231 ... Management table storage area 240 ... Switching means

Claims (5)

A simulation circuit storage device for storing data of a simulation circuit including a hardware model having a plurality of hardware operation models respectively corresponding to a plurality of circuits, and a memory model for storing a plurality of data defining the plurality of circuits. When,
The simulation circuit is operated by software to analyze the switching operation of the plurality of hardware operation models, and the time required for the switching operation including the transfer time of the plurality of data from the memory model to the hardware model is calculated. An analysis module for analyzing the software.   The simulation apparatus according to claim 1, wherein the hardware model further includes an access control unit that controls access to the hardware model according to an operation state of the hardware model.   The simulation apparatus according to claim 2, wherein the access control unit records information on access to the hardware model during a period in which access to the hardware model is prohibited. The hardware model is
A management unit having a management table indicating a relationship between the plurality of hardware operation models and the plurality of circuits;
4. The apparatus according to claim 1, further comprising a switching unit that refers to the management table and switches the plurality of hardware operation models in the hardware model according to a circuit change instruction included in the software. The simulation apparatus according to claim 1. The simulation circuit further includes a bus model that connects the hardware model and the memory model to each other, and the analysis module calculates the transfer time that varies depending on a data transfer situation in the bus model. The simulation apparatus according to any one of claims 1 to 4.

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