JP2007184981A - High-frequency switching system and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase an electric power which can be dealt with as compared with a conventional example. <P>SOLUTION: A voltage impressed to the gate terminal of FETs 101-116 to which the first terminal of resistance elements 217-219, 221-223 was connected to the intermediate connection point of the FETs 101-116, and a voltage of opposite phase to a voltage applied to the gate terminal of the FETs 101-116 to which the primary terminal of resistance elements 217-219 is applied to the second terminal of the resistance elements 217-219, 221-223. Consequently, falling can be suppressed in the voltage potential of the intermediate connection point of the FETs 101-116. As a result, an electric power which can be dealt with can be increased as compared with a conventional example. Moreover, since the fall of the voltage potential can be suppressed in the intermediate connection point of the FETs 101-116; degradation of distortion property and isolation characteristics is suppressed as resulting from the fall of the voltage potential of the intermediate connection point of the FETs 101-116, and an outstanding radio frequency characteristic is acquired. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a high-frequency switch device that amplifies and switches a high-frequency signal in a mobile communication device or the like, and a semiconductor device in which the high-frequency switch device is integrated on a semiconductor substrate.

  As shown in FIG. 15, an SPDT (Single-Pole Double-Throw) switch device, which is one of the conventional high-frequency switch devices, has a resistance element connected in parallel between the drain and source of each FET constituting the high-frequency switch circuit section. (For example, refer to Patent Document 1). In FIG. 15, 130 to 137 are depletion type FETs, 250 to 257 are resistance elements (resistance R1), 260 to 267 are resistance elements (resistance R2), 270 and 271 are resistance elements (resistance R3), and 510 to 512 are High frequency signal input / output terminals 610 and 611 are control terminals. I1 to I4 are currents.

In this configuration, for example, when a voltage of 3 V is applied to the control terminal 610 and a voltage of 0 V is applied to the control terminal 611, the FETs 130 to 133 are turned on and the FETs 134 to 137 are turned off. The path of the high frequency input / output terminal 511 can be turned on, and the path from the high frequency input / output terminal 510 to the high frequency input / output terminal 512 can be turned off.
JP 2002-232278 (page 13, FIG. 7)

However, in the conventional configuration, in the ON path, a gate forward current flows from the control terminal 610 through the resistance elements 250 to 253, the FETs 130 to 133, and the resistance element 270 to the control terminal 611. Since the resistance elements 250 to 253, 260 to 263, and 270 do not affect the high frequency characteristics, it is necessary to set the resistance value to 50 kΩ or more. The DC potential VB at the point B in the figure is the FET built-in voltage (in order). Assuming that the directional voltage is 0.4V,
Since 3V−0.4V = (R1 / 4 + R3) × I1, I1 = 2.6V / (R1 + 4R3),
Since VB = R3 × 4I1, VB = 10.4 × R3 / (R1 + 4R3) (1)
It is represented by For example, assuming that the resistance elements 250 to 253, 260 to 263, and 270 are all 50 kΩ, assuming that the potential of the control terminal 610 is 3V and the potential of the control terminal 611 is 0V, the DC potential VB at the point B is about 2 .1V. Since the on resistance values of the FETs 130 to 133 are negligibly small, about several Ω, the potentials at the points B, A, and C are almost equal. As a result, the reverse bias voltage of the FET 134 in the off path is almost the same as the point B. It becomes about 2.1 V, and the current 4I1 flowing through R3 is 40 μA.

The maximum power Pmax that can be handled by a switch circuit configured by cascading n FETs is Pmax = 2 {n (VH−VL + VT)} ² / Z ₀ (2)
It is represented by Here, VH represents a high level voltage applied to the FET, VL represents a low level voltage, and VT represents a threshold voltage of the FET. Z ₀ represents the characteristic impedance of the circuit and is generally 50Ω, and 50Ω is also assumed in this case. From the above results, substituting VH = 2.1V and VL = 0V and calculating for the case of VT = −0.6V, Pmax is 1.40 W, and resistance elements 260 to 263 and resistance elements 264 to 267 are added. Most of the effects are not obtained.

  In order to increase the DC potential VB at the point B and simultaneously reduce the current consumption, a method of increasing the value of the resistor R3 is conceivable. However, when the resistor R3 is increased, the potential VD at the point D decreases. There is a point.

That is, in the off path, a gate reverse current flows from the control terminal 610 through the resistance element 271, the FETs 134 to 137, and the resistance elements 254 to 257. In the figure, the potential VD at point D is VD = 3.0− (4 × R3 + 6 × R2) I2 (3)
It is represented by The value of the resistance element needs to be the same as the above-mentioned on-path condition because this path may be used as the on-path. For example, from the formula (1), in order to make the potential VB be 2.4 V or more, it is necessary to set the value of the resistor R3 to 300 kΩ. In this case, the potential VD at the point D is usually in the reverse direction of the gate. Assuming that a current of about 1 μA flows as the current (I2), it becomes 1.5 V, and Pmax further decreases.

  As described above, the conventional example has a problem that the handling power is easily lowered due to the drop of the drain-source potential of the FET, and the resistance R3 cannot be reduced, so that the current consumption increases.

  In order to avoid this problem, Japanese Patent Laid-Open No. 2002-232278 proposes a method in which a capacitor is inserted between the high-frequency input / output terminal and the switch circuit unit and both are separated in a DC manner. . However, when a capacitor formed by a semiconductor process is directly connected to a high-frequency input / output terminal, the ESD withstand voltage (electrostatic withstand voltage) is remarkably deteriorated and the area of the semiconductor chip is increased.

  An object of the present invention is to provide a high-frequency switch device and a semiconductor device that can handle higher power than in the conventional example.

  Another object of the present invention is to provide a high frequency switching device and a semiconductor device that can reduce current consumption.

  The present invention solves the above-described problems of the conventional configuration, and has a configuration in which a resistance element is individually connected to the connection point of the FET and a predetermined voltage is applied to the other terminal. As a result, higher power can be handled than in the conventional example. In addition, current consumption can be reduced.

  A high-frequency switch device according to a first aspect of the present invention includes a plurality of high-frequency input / output terminals that input and output a high-frequency signal, and a plurality of high-frequency switch circuit portions arranged between the high-frequency input / output terminals. The high-frequency switch circuit unit is configured by connecting a plurality of field effect transistors in series, and applies either a high-level voltage or a low-level voltage to the gate terminal of the field-effect transistor to switch between the on state and the off state. Realize.

  Further, in the plurality of high-frequency switch circuits, of the first and second high-frequency switch circuit portions that operate in reverse to each other, the intermediate connection point of the plurality of field effect transistors constituting the first high-frequency switch circuit portion. The first terminal of the first resistance element is connected, the first terminal of the second resistance element is connected to the intermediate connection point of the plurality of field effect transistors constituting the second high-frequency switch circuit unit, The first terminals of the third resistance elements are connected to the gate terminals of the plurality of field effect transistors constituting one high frequency switch circuit section, and the plurality of field effect transistors constituting the second high frequency switch circuit section The first terminal of the fourth resistor element is connected to the gate terminal, the second terminal of the fourth resistor element is connected to the second terminal of the first resistor element, and the second terminal of the second resistor element is connected. The third terminal Is connected to the second terminal of the resistive element, a high-frequency input and output terminals are connected directly to the respective source / drain terminal of the field effect transistors constituting the first and second high-frequency switch circuit section.

  According to this configuration, it is possible to suppress a decrease in the potential at the intermediate connection point of the plurality of field effect transistors. As a result, the power that can be handled can be increased compared to the conventional example, and the current consumption can also be reduced compared to the conventional example.

  A high-frequency switch device according to a second aspect of the present invention includes a plurality of high-frequency input / output terminals that input and output a high-frequency signal, a series high-frequency switch circuit portion disposed between the high-frequency input / output terminals, and a high-frequency input / output terminal and a ground terminal And a parallel high-frequency switch circuit unit. Each of the series high-frequency switch circuit section and the parallel high-frequency switch circuit section is configured by connecting a plurality of field effect transistors in series, and applies either a high level voltage or a low level voltage to the gate terminal of the field effect transistor. By doing so, an on state and an off state are realized.

  Further, in each of the series high-frequency switch circuit unit and the parallel high-frequency switch circuit unit, a plurality of first and second high-frequency switch circuit units that constitute the first high-frequency switch circuit unit among the first and second high-frequency switch circuit units that operate in reverse to each other The first terminal of the first resistance element is connected to the intermediate connection point of the field effect transistor, and the second resistance element of the second resistance element is connected to the intermediate connection point of the plurality of field effect transistors constituting the second high-frequency switch circuit unit. 1 terminal is connected, and the first terminal of the third resistance element is connected to the gate terminals of a plurality of field effect transistors constituting the first high-frequency switch circuit section, thereby forming the second high-frequency switch circuit section. The first terminal of the fourth resistance element is connected to the gate terminals of the plurality of field effect transistors, and the second terminal of the fourth resistance element is connected to the second terminal of the first resistance element. The second terminal of the third resistor element is connected to the second terminal of the second resistor element, and the high-frequency input / output terminals are field effect transistors constituting first to fourth high-frequency switch circuit sections, respectively. Directly connected to the source / drain terminals of

  According to this configuration, it is possible to suppress a decrease in the potential at the intermediate connection point of the plurality of field effect transistors. As a result, the power that can be handled can be increased compared to the conventional example, and the current consumption can also be reduced compared to the conventional example. In addition, since it is possible to suppress a decrease in potential at the intermediate connection point of a plurality of field effect transistors, deterioration of distortion characteristics and isolation characteristics due to a decrease in potential at the intermediate connection point of a plurality of field effect transistors can be suppressed, Excellent high frequency characteristics can be obtained.

  In the configurations of the first and second inventions, the second terminals of the first resistance elements are all connected in common, the second terminals of the second resistance elements are all connected in common, and the third terminal It is preferable that the second terminals of the resistance elements are all connected in common, and the second terminals of the fourth resistance elements are all connected in common.

  The semiconductor device of the present invention is obtained by integrating the high-frequency switch device according to any one of the first to second inventions on a semiconductor substrate.

  According to this structure, there exists an effect similar to the high frequency switch apparatus of the 1st to 2nd invention.

  As described above, according to the present invention, it is possible to suppress a decrease in the potential of the intermediate connection point of the intermediate connection points of a plurality of field effect transistors, so that the power that can be handled is increased compared to the conventional example. Can be made. In addition, deterioration of distortion characteristics and isolation characteristics due to a decrease in potential at the intermediate connection point of a plurality of field effect transistors can be suppressed, and excellent high frequency characteristics can be obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a circuit diagram showing a configuration of an SPDT switch device as a first embodiment of a high frequency switch device of the present invention. In FIG. 1, 101-108 are depletion type FETs, 201-208 are resistance elements (resistance R1), 217-219, 221-223 are resistance elements (resistance R2), 501 is a first high-frequency signal input / output terminal, Reference numeral 502 denotes a second high-frequency signal input / output terminal, 503 denotes a third high-frequency signal input / output terminal, 601 denotes a first control terminal, and 602 denotes a second control terminal. I1 to I6 are currents.

  The operation of the switch device configured as shown in FIG. 1 will be described below.

  When a signal input from the first high frequency signal input / output terminal 501 is output to the second high frequency signal input / output terminal 502, a high level voltage is applied to the control terminal 601 and a low level voltage is applied to the control terminal 602. To do.

  In FIG. 1, since depletion type FETs having a threshold value of about −0.6 V are used for the FETs 101 to 108, the FETs 101 to 104 to which a high level voltage is applied are turned on under the above voltage conditions. Thus, the FETs 105 to 108 to which a low level voltage is applied are turned off.

In the figure, the potential VB at point B and the potential VD at point D are
VB = 10.4 × R2 / (3 × R1 + 4 × R2) (4)
VD = 3.0−R2 × I5 (5)
I3 = 3 × VB / R2
I5 = I4 × 4/3
Respectively.

  When high level voltage = 3.0V, low level voltage = 0V, FET gate forward voltage = 0.4V, FET reverse leakage current I4 = 1 μA, R1 = 50 kΩ, R2 = 450 kΩ, VB = VA = VC = VD = 2.4V is obtained. However, VA is the potential at point A, and VC is the potential at point C. On the other hand, the current consumption is 16 μA for I3 under the above conditions, and the power consumption can be significantly reduced compared to 40 μA of the conventional example.

  Assuming that the threshold value of the FET is −0.6 V as in the conventional example, Pmax at this time is 2.07 W from the equation (2), and can handle up to about 1.5 times the power compared to the conventional example. .

  According to this embodiment, the first terminals of the resistance elements 217 to 219 and 221 to 223 are connected to the intermediate connection points of the FETs 101 to 108, and the second terminals of the resistance elements 217 to 219 and 221 to 223 are connected to each other. Since a voltage opposite in phase to the voltage applied to the gate terminals of the FETs 101 to 108 to which the first terminals of the resistance elements 217 to 222 are connected is applied, the potential drop at the intermediate connection point of the FETs 101 to 108 is suppressed. Can do. As a result, the power that can be handled can be increased compared to the conventional example.

(Embodiment 2)
FIG. 2 is a circuit diagram showing the configuration of an SPDT switch device as a second embodiment of the high frequency switch device of the present invention, and FIG. 3 is a characteristic diagram showing the high frequency characteristics of the SPDT switch device of FIG. 2, 101 to 116 are depletion type FETs, 201 to 219, 221 to 223, 225 to 228, 230 to 233 are resistance elements, 501 is a first high frequency signal input / output terminal, and 502 is a second high frequency signal. Input / output terminals, 503 is a third high-frequency signal input / output terminal, 601 is a first control terminal, 602 is a second control terminal, 301 and 302 are capacitors, and 701 and 702 are ground terminals.

  The operation of the SPDT switch device configured as shown in FIG. 1 will be described below.

  The path from the first high-frequency signal input / output terminal 501 to the second high-frequency signal input / output terminal 502 is turned on, and the path from the first high-frequency signal input / output terminal 501 to the third high-frequency signal input / output terminal 503 is turned off. For this purpose, a voltage of 3 V is applied to the control terminal 601 and a voltage of 0 V is applied to the control terminal 602.

  As a result, the FETs 101 to 104 and the FETs 113 to 116 are turned on, and the FETs 105 to 108 and the FETs 109 to 112 are turned off.

  As a result, the high-frequency signal leaking from the high-frequency signal input / output terminal 501 to the high-frequency signal input / output terminal 503 is released to the ground terminal 702 via the FETs 113 to 116 and is excellent between the high-frequency signal input / output terminals 501 and 503. Isolation is ensured.

  In addition, the SPDT switch device is required not to turn on the FETs 105 to 112 even when a high power signal is input. However, by setting the resistance value to the same value as that of the first embodiment of the present invention, it is possible to reduce the power to 2.0 W. Can withstand input power.

  FIG. 3 shows the input power dependence of the third harmonic and the isolation characteristics of the SPDT switch device having the conventional configuration and the SPDT switch device according to the second embodiment of the present invention. The broken line indicates the characteristic of the configuration of the conventional example, and the solid line indicates the characteristic of the second embodiment. In the characteristic diagram of FIG. 3, the third harmonic characteristic starts increasing when the input power exceeds a certain level, and the isolation characteristic starts decreasing when the input power exceeds a certain power. 6, 11, and 14 are the same as those in FIG. 3.

  The harmonic characteristic and the isolation characteristic are proportional to the maximum power that can be handled. In the conventional configuration, when the input power exceeds 31.5 dBm, the third harmonic characteristic and the isolation characteristic begin to deteriorate. In the second embodiment, the input power shows excellent characteristics up to 33 dBm, and it can be seen that the input power can be increased by 1.5 dBm compared to the conventional configuration. In addition, the current consumption is 32 μA, which can be significantly reduced as compared with 80 μA when a similar circuit is configured with the conventional configuration.

  According to this embodiment, the first terminals of the resistance elements 217 to 219 and 221 to 223 are connected to the intermediate connection points of the FETs 101 to 116, and the second terminals of the resistance elements 217 to 219 and 221 to 223 are connected to each other. Since a voltage opposite in phase to the voltage applied to the gate terminals of the FETs 101 to 116 to which the first terminals of the resistance elements 217 to 219 and 221 to 223 are connected is applied, the potential at the intermediate connection point of the FETs 101 to 116 is decreased. Can be suppressed. As a result, the power that can be handled can be increased compared to the conventional example. In addition, since a decrease in potential at the intermediate connection point of the FETs 101 to 116 can be suppressed, deterioration of distortion characteristics and isolation characteristics due to a decrease in potential at the intermediate connection point of the FETs 101 to 116 can be suppressed, and excellent high frequency characteristics can be obtained. It is done.

  Needless to say, the configuration of the present invention can be similarly applied to a high-frequency switch device other than the SPDT switch device.

(Embodiment 3)
FIG. 4 is a circuit diagram showing a configuration of an SPDT switch device as Embodiment 3 of the high-frequency switch device of the present invention. In FIG. 4, 101-108 are depletion type FETs, 201-208 are resistance elements (resistance R1), 217-219 are resistance elements (resistance R2), 221-223 are resistance elements (resistance R2), 235, 236 are Resistor element (resistor R4), 239 and 240 are resistor elements (resistor R3), 401 and 402 are diodes, 501 is a first high-frequency signal input / output terminal, 502 is a second high-frequency signal input / output terminal, and 503 is a third element. , 601 is a first control terminal, and 602 is a second control terminal. I1, I2, I4, and I5 are currents.

  The operation of the switch device configured as shown in FIG. 4 will be described below.

  The basic operation is the same as that of the first embodiment, but the difference from the first embodiment is that a diode 401 is inserted between the resistance elements 217 to 219 connected to the intermediate point of the FET and the control terminal 602, and The diode 402 is inserted between the resistance elements 221 to 223 and the control terminal 601.

  By providing the diode 401, the forward current I2 in the on state from the FET 101 to the FET 104 can be limited. The resistor 239 is for controlling the value of the forward current I2, and the resistor 235 is for preventing destruction of the diode 401 due to ESD (electrostatic discharge) from the control terminal 602. The same applies to the diode 402. Note that the resistors 235 and 239 can be omitted.

In FIG. 4, assuming that 3 V is applied to the control terminal 601 and 0 V is applied to the control terminal 602, the FETs 101 to 104 are turned on when the forward current I 1 of the FET flows. At this time, the potential VB at point B is
VB = (3-ΦB) {1-R1 / (3 × R1 + 4 × R2 + 12 × R3)} (6)
It is represented by Where ΦB is the built-in voltage of the gate. As is clear from the equation (6), the potential VB at the point B is dominated by the resistor R1 and the resistor R3, and the potential VB at the point B can be increased by increasing the value of the resistor R3. As described above, it is not preferable to reduce the resistance R1 because the insertion loss is deteriorated.

By setting R1 = R2 = 50 kΩ and R3 = 500 kΩ, the value of the current I4 can be set to a sufficiently small value of 1 μA or less, and the built-in voltage ΦB in this case is reduced to about 0.2V. Accordingly, the potential VB at the point B is 2.78V. On the other hand, regarding the off path, the potential VD at the point D is
VD = 3-ΦB-R2 × I5 (7)
I5 = (4/3) × I4
Similarly, when ΦB = 0.2V, I4 = 1 μA, and R2 = 50 kΩ are substituted into the equation (7), VD = 2.73V is obtained. When the above result is calculated by substituting into the equation (2), the Pmax of the circuit of the third embodiment is 2.90 W, and the power higher by 0.9 W than the circuit configuration of the first embodiment can be handled.

  According to this embodiment, the same effects as those of the first embodiment can be obtained. In addition, by providing the diodes 401 and 402, when the FET to which the cathodes of the diodes 401 and 402 are connected via a resistor is turned on, the forward current of the FET can be suppressed and the current consumption can be reduced. Can do.

  Further, the current consumption of the circuit of the third embodiment is about 1 μA, and the current consumption can be significantly reduced as compared with the conventional 40 μA.

(Embodiment 4)
FIG. 5 is a circuit diagram showing a configuration of an SPDT switch device as Embodiment 4 of the high-frequency switch device of the present invention, and FIG. 6 is a characteristic diagram showing high-frequency characteristics of the SPDT switch device of FIG.

  In FIG. 5, 101 to 116 are depletion type FETs, 201 to 219, 221 to 223, 225 to 228, 230 to 233, 235 to 242 are resistance elements, 403 to 406 are diodes, and 501 is a first high frequency signal input. Output terminal 502, second high frequency signal input / output terminal 503, third high frequency signal input / output terminal 601, first control terminal 602, second control terminal 301, 302 capacitors, 701, 702 Is a ground terminal.

  The operation of the switch device configured as shown in FIG. 5 will be described below.

  The circuit of FIG. 5 is an example in which the circuit of Embodiment 3 shown in FIG. 4 is applied to an SPDT circuit. The basic operation is the same as that of the SPDT circuit of the second embodiment. A difference from the second embodiment is that a circuit including a diode 403 and resistance elements 235 and 239 is inserted between the resistance elements 217 to 219 connected to the intermediate point of the FET and the control terminal 602, and the resistance elements 221 to 223 are controlled. A circuit composed of the diode 404 and the resistance elements 236 and 240 is inserted between the terminals 601, and a circuit composed of the diode 405 and the resistance elements 237 and 241 is inserted between the resistance elements 225 to 228 and the control terminal 601. This is that a circuit including a diode 406 and resistance elements 238 and 242 is inserted between 230 to 233 and the control terminal 602.

  A circuit comprising a diode 403 and resistance elements 235 and 239, a circuit comprising a diode 404 and resistance elements 236 and 240, a circuit comprising a diode 405 and resistance elements 237 and 241 and a circuit comprising a diode 406 and resistance elements 238 and 242 are provided. The operational effects of are the same as in the third embodiment.

  FIG. 6 shows the input power dependence of the third harmonic and the isolation characteristics by the SPDT circuit having the conventional configuration and the SPDT circuit according to the fourth embodiment of the present invention. The harmonic characteristic and the isolation characteristic are proportional to the maximum power that can be handled. In the conventional configuration, when the input power exceeds 31.5 dBm, the third harmonic characteristic and the isolation characteristic begin to deteriorate. The SPDT circuit of the fourth embodiment shows excellent characteristics with input power up to 34.5 dBm, and it can be seen that it can cope with input power that is 3.0 dBm larger than the conventional configuration. Further, the current consumption of the entire circuit is 5 μA or less, so that excellent characteristics and low current consumption can be realized simultaneously.

  According to this embodiment, the same effects as those of the first embodiment can be obtained. In addition, by providing the diodes 401 to 404, when the FET to which the cathodes of the diodes 401 to 404 are connected via a resistor is on, the forward current of the FET can be suppressed, and the current consumption can be reduced. Can do.

  Further, the current consumption of the circuit of the third embodiment is about several μA, and the current consumption can be significantly reduced as compared with 80 μA when the same circuit is configured in the conventional example.

  Needless to say, the configuration of the present invention can be similarly applied to a high-frequency switch device other than the SPDT switch device.

(Embodiment 5)
FIG. 7 is a circuit diagram showing a configuration of an SPDT switch device as a fifth embodiment of the high frequency switch device of the present invention. 7, 101 to 108 are depletion type FETs, 201 to 208 are resistance elements (resistance R1), 217 to 219, 221 to 223 are resistance elements (resistance R2), 501 is a first high-frequency signal input / output terminal, Reference numeral 502 denotes a second high-frequency signal input / output terminal, 503 denotes a third high-frequency signal input / output terminal, 601 denotes a first control terminal, and 602 denotes a second control terminal. I1 to I3 are currents.

  The operation of the switch device configured as shown in FIG. 7 will be described below.

Although the basic operation is the same as that of the first embodiment, the difference from the first embodiment is that the other end of the resistance elements 217 to 219 having one end connected to the middle point of the FETs 101 to 104 and the middle of the FETs 105 to 108. This is a point where the other ends of the resistance elements 220 to 222 having one end connected to the point are directly connected. Assuming that 3V is applied to the control terminal 601 and 0V is applied to the control terminal 602, the potential VB at the point B and the potential VD at the point D are:
VB = 3-R1 × I1-ΦB (8)
VD = VB-2 × R2 × I2 (9)
It is expressed as Substituting R1 = 50 kΩ, I1 = 1 μA, and ΦB = 0.2 V into the equations (8) and (9), the values of VB = 2.75 V and VD = 2.62 V are obtained. = 2.61 W, which is approximately 1.8 times the value of the conventional example.

  Thus, according to the present embodiment, among the first and second switch circuit units (FETs 101 to 104, FETs 105 to 108) that operate in opposite directions, the FETs 101 to 101 that constitute the first switch circuit unit. The first terminals of the resistance elements 217 to 219 are connected to the intermediate connection point 104, and the first terminals of the resistance elements 221 to 223 are connected to the intermediate connection points of the FETs 105 to 108 constituting the second switch circuit unit. A simple configuration in which the second terminals of the resistor elements 221 to 223 connected to the second switch circuit unit are connected to the second terminals of the resistor elements 217 to 219 connected to the first switch circuit unit. As a result, a decrease in potential at the intermediate connection point of the FETs 101 to 108 can be suppressed. As a result, the power that can be handled can be increased compared to the conventional example.

  Further, the current consumption of the circuit of the fifth embodiment is 16 μA, and the current consumption can be significantly reduced as compared with the conventional 40 μA.

  Needless to say, the configuration of the present invention can be similarly applied to a high-frequency switch device other than the SPDT switch device.

(Embodiment 6)
FIG. 8 is a circuit diagram showing a configuration of an SPDT switch device as a sixth embodiment of the high-frequency switch device of the present invention.

  8, 101 to 116 are depletion type FETs, 201 to 219, 221 to 223, 225 to 228 and 230 to 233 are resistance elements, 501 is a first high frequency signal input / output terminal, and 502 is a second high frequency signal. Input / output terminals, 503 is a third high-frequency signal input / output terminal, 601 is a first control terminal, 602 is a second control terminal, 301 and 302 are capacitors, and 701 and 702 are ground terminals.

  The operation of the switch device configured as shown in FIG. 8 will be described below.

  The circuit of FIG. 8 is an example in which the circuit of the fifth embodiment shown in FIG. 7 is applied to an SPDT circuit. The basic operation is the same as that of the SPDT circuit of the second embodiment. The difference from the second embodiment is that the other ends of the resistance elements 217 to 219 whose one ends are connected to the intermediate points of the FETs 101 to 104 and the FETs 105 to 108. Is connected to the other end of the resistive elements 225 to 228 having one end connected to the intermediate point of the FETs 109 to 112 and one end to the intermediate point of the FETs 113 to 116. This is that the other ends of the resistance elements 230 to 233 connected to each other are connected.

  With the configuration shown in FIG. 8, a stable bias potential is ensured by always flowing a current from an on-state FET to an off-state FET. As a result, high Pmax and excellent high-frequency characteristics can be obtained. The FETs 101 to 108 have the same size with a gate width of 4 mm, and the FETs 109 to 116 have the same size with a gate width of 1 mm. By pairing FETs of the same size or close sizes in this way, the current value becomes constant and stable characteristics can be obtained.

  As described above, according to the present embodiment, the same effect as that of the fifth embodiment can be obtained, and the decrease in the potential at the intermediate connection point of the plurality of field effect transistors can be suppressed. Deterioration of distortion characteristics and isolation characteristics due to a decrease in potential at the intermediate connection point of the effect transistor can be suppressed, and excellent high frequency characteristics can be obtained.

  Further, the current consumption of the circuit of the sixth embodiment is 32 μA, and the current consumption can be significantly reduced as compared with 80 μA when a similar circuit is configured in the conventional example.

  Needless to say, the configuration of the present invention can be similarly applied to a high-frequency switch device other than the SPDT switch device.

(Embodiment 7)
FIG. 9 is a circuit diagram showing a configuration of an SPDT switch device as a high frequency switch device according to a seventh embodiment of the present invention.

  9, 101 to 116 are depletion type FETs, 201 to 219, 221 to 223, 225 to 228 and 230 to 233 are resistance elements, 501 is a first high frequency signal input / output terminal, and 502 is a second high frequency signal. Input / output terminals, 503 is a third high-frequency signal input / output terminal, 601 is a first control terminal, 602 is a second control terminal, 301 and 302 are capacitors, and 701 and 702 are ground terminals.

  The operation of the switch device configured as shown in FIG. 9 will be described below.

  The basic operation of the circuit of FIG. 9 is the same as that of the SPDT circuit of the sixth embodiment. The difference from the sixth embodiment is that the other ends of the resistance elements 217 to 219 having one end connected to the intermediate point of the FETs 101 to 104. And the other end of the resistance elements 225 to 228 whose one ends are connected to the intermediate points of the FETs 109 to 112, and the other ends of the FETs 113 to The connection point with the other end of the resistance elements 230 to 233 having one end connected to the intermediate point 116 is commonly connected.

  With the configuration of FIG. 9, the current from the on-state FET to the off-state FET is averaged, so that a stable bias voltage is applied even when the FET is complicated and there is no FET that always operates in reverse. can do.

  As described above, according to the present embodiment, the first terminals of the resistance elements 217 to 219, 221 to 223, 225 to 228, and 230 to 233 are connected to the connection points of the FETs 101 to 116 constituting the plurality of switch circuit units. , And the second terminals of the resistance elements 217 to 219, 221 to 223, 225 to 228, and 230 to 233 are commonly connected to each other, thereby suppressing a decrease in potential at the intermediate connection point of the FETs 101 to 116. it can. As a result, the power that can be handled can be increased compared to the conventional example. In addition, since a decrease in potential at the intermediate connection point of the FETs 101 to 116 can be suppressed, deterioration of distortion characteristics and isolation characteristics due to a decrease in potential at the intermediate connection point of the FETs 101 to 108 can be suppressed, and excellent high frequency characteristics can be obtained. It is done.

  In addition, since the current from the on-state FET to the off-state FET is averaged, a stable bias voltage can be applied even when the circuit is complicated and there is no FET that always operates in reverse. .

  Further, the current consumption of the circuit of the seventh embodiment is several μA, and the current consumption can be significantly reduced as compared with 80 μA in the case where a similar circuit is configured in the conventional example.

  Needless to say, the configuration of the present invention can be similarly applied to a high-frequency switch device other than the SPDT switch device.

(Embodiment 8)
FIG. 10 is a circuit diagram showing the configuration of an SPDT switch device as an eighth embodiment of the high frequency switch device of the present invention, and FIG. 11 is a characteristic diagram showing the high frequency characteristics of the SPDT switch device of FIG.

  10, 101 to 116 are depletion type FETs, 201 to 223, 243 and 244 are resistance elements, 407 and 408 are diodes, 501 is a first high frequency signal input / output terminal, and 502 is a second high frequency signal input / output. 503 is a third high-frequency signal input / output terminal, 601 is a first control terminal, 602 is a second control terminal, 301 and 302 are capacitors, and 701, 702 and 703 are ground terminals.

  The operation of the switch device configured as shown in FIG. 10 will be described below.

  The basic operation of the circuit of FIG. 10 is the same as that of the SPDT circuit of the second embodiment. The difference from the sixth embodiment is that the anode of the diode 407 is connected to the first control terminal 601 via the resistance element 243. The anode of the diode 408 is connected to the second control terminal 602 via the resistance element 244, the cathodes of the diodes 407 and 408 are connected to one end of the resistance element 245, the other end of the resistance element 245 is grounded, and the diode 407, The connection point between 408 and the resistance element 245 is commonly connected to the other terminals of the resistance elements 217 to 233 connected to the intermediate points of the FETs 101 to 116.

  With the configuration of FIG. 10, when the control terminal 601 is at a high level, a current flows from the control terminal 601 through the resistance element 243, the diode 407, and the resistance element 245 to the ground terminal 703. When the control terminal 602 is at a high level, current flows from the control terminal 602 through the resistance element 244, the diode 408, and the resistance element 245 to the ground terminal. As a result, the potential at the point P is kept constant. Further, by changing the value of the resistance element 245, the potential at the point P can be arbitrarily set. The resistance elements 243 and 244 are inserted for the purpose of ESD protection. Now, by setting the values of the resistance elements 243 and 244 to 1 kΩ and the value of the resistance element 245 to 500 kΩ, the potential at the point P can be set to 2.8 V, and the maximum power Pmax that can be handled by the switch device of FIG. 3.10 W, which is 2.2 times that of the conventional configuration.

  FIG. 11 shows the input power dependence of the third harmonic and the isolation characteristics by the SPDT circuit having the conventional configuration and the SPDT circuit according to the eighth embodiment of the present invention. The harmonic characteristic and the isolation characteristic are proportional to the maximum power that can be handled. In the conventional configuration, when the input power exceeds 31.5 dBm, the third harmonic characteristic and the isolation characteristic begin to deteriorate. The SPDT circuit of the fourth embodiment shows excellent characteristics with input power up to 34.5 dBm, and it can be seen that it can cope with input power that is 3.0 dBm larger than the conventional configuration.

  As described above, according to the present embodiment, the first terminals of the resistance elements are connected to the intermediate connection points of the FETs 101 to 116 constituting the plurality of switch circuit units, and the resistance elements 217 to 219, 221 to 223, and 225 are connected. To 228 and 230 to 233 are connected to each other, the anode of the first diode 407 is connected to the first control terminal 601, and the anode of the second diode 408 is connected to the second control terminal 602. The first terminal of the resistance element 245 is connected to the cathodes of the first and second diodes 407 and 408, the second terminal of the resistance element 245 is grounded, and the first and second diodes 407 and 408 Resistance elements 217 to 219, 221 to 223, 225 to 228, and 230 to 2 connected to the intermediate points of the FETs 101 to 116 are connected to the first terminal of the resistance element 245. By connecting to the second terminal of the 3, it is possible to suppress the reduction in the potential of the intermediate connection points of the FETs 101 through 116. As a result, the power that can be handled can be increased compared to the conventional example. In addition, since a decrease in potential at the intermediate connection point of the FETs 101 to 116 can be suppressed, deterioration of distortion characteristics and isolation characteristics due to a decrease in potential at the intermediate connection point of the FETs 101 to 108 can be suppressed, and excellent high frequency characteristics can be obtained. It is done.

  In addition, a constant bias voltage can always be applied to the FETs 101 to 116 by a voltage OR circuit including the diodes 407 and 408.

  Further, the current consumption of the circuit of the fifth embodiment is about 40 μA, and the current consumption can be significantly reduced as compared with 80 μA in the case where a similar circuit is configured in the conventional example.

  Needless to say, the configuration of the present invention can be similarly applied to a high-frequency switch device other than the SPDT switch device.

  Further, in the configuration of FIG. 10, the circuit portions of the shunt FETs 109 to 116 can be omitted.

(Embodiment 9)
FIG. 12 is a circuit diagram showing a configuration of an SPDT switch device as a ninth embodiment of the high frequency switch device of the present invention.

  12, 101 to 116 are depletion type FETs, 201 to 219, 221 to 223, 225 to 228, 230 to 233, 246 to 249 are resistance elements, 409 and 410 are diodes, and 501 is a first high frequency signal input. Output terminal 502, second high frequency signal input / output terminal 503, third high frequency signal input / output terminal 601, first control terminal 602, second control terminal 301, 302 capacitors, 701, 702 Is a ground terminal.

  The operation of the switch device configured as shown in FIG. 12 will be described below.

  The basic operation of the circuit of FIG. 12 is the same as that of the SPDT circuit of the sixth embodiment. The difference from the sixth embodiment is that the anode of the diode 409 is connected to the first control terminal 601 through the resistance element 246. One end of the resistance element 248 is connected to the cathode of the diode 409, the control terminal 602 is connected to the other end of the resistance element 248, and the anode of the diode 410 is connected to the second control terminal 602 via the resistance element 247. One end of the resistance element 249 is connected to the cathode of the diode 410, the control terminal 601 is connected to the other end of the resistance element 249, the cathode of the diode 409 is connected to the resistance elements 217 to 219 and 230 to 233, The cathode is connected to the resistance elements 221 to 223 and 225 to 228.

  12, when the control terminal 601 is at a high level, a current flows to the control terminal 602 via the resistance element 246, the diode 409, and the resistance element 248, and when the control terminal 602 is at a high level, the resistance element 247, When the current flows to the control terminal 601 through the diode 410 and the resistance element 249, the potentials at the Q point and the R point are fixed. By changing the values of the resistance elements 248 and 249, the potentials at the Q point and the R point are made independent. Can be set to any value. The resistance elements 246 and 247 are inserted for the purpose of ESD protection.

  Now, by setting the values of the resistance elements 246 and 247 to 1 kΩ, and the values of 248 and 249 to 100 kΩ, the potential at the Q point can be set to 2.5 V and the potential at the R point can be set to 2.9 V. As a result, the forward bias of the on-state FET can be increased, and at the same time, the reverse bias voltage of the off-state FET can be increased. Under the above conditions, the maximum power Pmax that can be handled by the switch device of FIG. 12 is 3.4 W, which is 2.4 times that of the conventional configuration. On the other hand, the insertion loss is reduced by increasing the forward bias voltage of the FET in the on state. .1 dB can be reduced.

  Thus, according to the present embodiment, the first resistance elements 217 to 219, 221 to 223, and 225 to the intermediate connection points of the FETs 101 to 116 constituting the series high frequency switch circuit unit and the parallel high frequency switch circuit unit, respectively. 228, 230 to 233 are connected, the first control terminal 601 is connected to the anode of the first diode 409, and the first diode 409 is connected to the cathode of the first resistor 248. A second terminal of the second resistance element 248 is connected to the second control terminal 602, an anode of the second diode 410 is connected to the second control terminal 602, and the second diode 410 is connected. The first terminal of the third resistance element 247 is connected to the cathode of the second resistor, the second terminal of the third resistance element 247 is connected to the first control terminal 601, and the first diode 409 The sword is connected to the second terminals of the first resistance elements 217 to 219 and 230 to 233 connected to the field effect transistors FET 101 to 104 and 113 to 116 having the first control terminal 601 connected to the gate, and the second Since the second control terminal 602 is connected to the second terminals of the first resistance elements 221 to 223 and 225 to 228 connected to the FETs 105 to 108 and 109 to 112, the second control terminal 602 is connected to the gate. A decrease in potential at the intermediate connection point of the FETs 101 to 116 can be suppressed. As a result, the power that can be handled can be increased compared to the conventional example. Further, since the potential drop at the intermediate connection point of the FETs 101 to 108 can be suppressed, the deterioration of the distortion characteristic and the isolation characteristic due to the decrease in the potential at the intermediate connection point of the FETs 101 to 108 can be suppressed, and excellent high frequency characteristics can be obtained. It is done.

  Further, the combination of the diodes 409 and 410 and the resistors 246 to 249 enables a low bias voltage to be applied to the on-state FET and a high bias voltage to be applied to the off-state FET.

  Needless to say, the configuration of the present invention can be similarly applied to a high-frequency switch device other than the SPDT switch device.

  In addition, in the configuration of FIG. 12, it is possible to omit the circuit portions of the shunt FETs 109 to 116.

(Embodiment 10)
FIG. 13 is a circuit diagram showing a configuration of an SPDT switch device as Embodiment 10 of the high frequency switch device of the present invention, and FIG. 14 is a characteristic diagram showing high frequency characteristics of the SPDT switch device of FIG.

  13, 101 to 116 are depletion type FETs, 120 is an enhancement type FET, 201 to 216 are gate bias resistors, and resistance values are 50 kΩ, 217 to 219, 221 to 223, 225 to 228, and 230 to 233 are FETs. A voltage fixing resistor, resistance value 100 kΩ, 280 is a gate resistance of the voltage inverting FET, resistance value 100 kΩ, 281 is a load resistance of the voltage inverting circuit, resistance value 100 kΩ, 301 and 302 are capacitors, and capacitance values 10 pF, 501 Is a first high frequency signal input / output terminal, 502 is a second high frequency signal input / output terminal, 503 is a third high frequency signal input / output terminal, 607 is a control terminal, 701, 702 and 704 are ground terminals, and 801 is a power supply terminal. It is. Reference numeral 901 denotes an SPDT circuit, and reference numeral 902 denotes a voltage inverting circuit.

  The operation of the SPDT circuit 901 and the voltage inverting circuit 902 configured as shown in FIG. 13 will be described below.

  The basic operation of the SPDT circuit 901 is the same as that of the second embodiment. A difference from the second embodiment is that an input signal and an output signal of the voltage inverting circuit 902 are simultaneously used as control signals for the SPDT circuit 901. In this embodiment, the control terminal 607 is applied with a voltage of 3V as a high level voltage and 0V as a low level voltage. The voltage applied to the control terminal 607 is applied to the gate terminal of the enhancement FET 120 via the gate resistor 280, and is taken out as a signal having a reverse phase from the drain terminal. That is, when the input voltage of the voltage inverting circuit 902 is at a low level, the output voltage is at a high level, and when the input voltage is at a high level, the output power is at a low level and have a potential relationship that is opposite to each other. Therefore, the SPDT circuit 901 can be operated by using the input voltage and output voltage of the voltage inverting circuit 902.

  FIG. 14 shows the characteristics when the SPDT circuit 901 of this embodiment is used in comparison with the case where a conventional SPDT circuit and a voltage inverting circuit are combined. In general, in the voltage inverting circuit 902 using the enhancement type FET, when the output voltage is high level (input voltage is low level), the output voltage is lower than the power supply voltage due to the load resistance. In many cases, when the SPDT circuit 901 is operated at 607, a sufficient voltage cannot be obtained. However, by using the configuration of the present invention, excellent high frequency characteristics can be obtained even with a single control voltage.

  Needless to say, the configuration of the present invention can be similarly applied to a high-frequency switch device other than the SPDT switch device.

  Further, the voltage inverting circuit 902 can be applied to the SPDT switch devices of FIGS. 1, 4, 5, 7, 8, 9, 10, and 12 similarly to FIG. .

  Further, the semiconductor device of the present invention is obtained by integrating the SPDT switch device of each of the above embodiments on a semiconductor substrate.

  The high-frequency switch device according to the present invention can suppress a decrease in the potential of the intermediate connection point of the intermediate connection points of a plurality of field effect transistors, so that the power that can be handled is increased as compared with the conventional example. In addition, it has the effect of suppressing the deterioration of distortion characteristics and isolation characteristics due to a decrease in potential at the intermediate connection point of a plurality of field effect transistors, and obtaining excellent high frequency characteristics. This is useful for a high-frequency switch device for amplifying and switching high-frequency signals in a machine.

It is a circuit diagram which shows the equivalent circuit of the SPDT switch apparatus of Embodiment 1 of this invention. It is a circuit diagram which shows the equivalent circuit of the SPDT switch apparatus of Embodiment 2 of this invention. It is a characteristic view which shows the high frequency characteristic of the SPDT switch apparatus of Embodiment 2 of this invention. It is a circuit diagram which shows the equivalent circuit of the SPDT switch apparatus of Embodiment 3 of this invention. It is a circuit diagram which shows the equivalent circuit of the SPDT switch apparatus of Embodiment 4 of this invention. It is a characteristic view which shows the high frequency characteristic of the SPDT switch apparatus of Embodiment 4 of this invention. It is a circuit diagram which shows the equivalent circuit of the SPDT switch apparatus of Embodiment 5 of this invention. It is a circuit diagram which shows the equivalent circuit of the SPDT switch apparatus of Embodiment 6 of this invention. It is a circuit diagram which shows the equivalent circuit of the SPDT switch apparatus of Embodiment 7 of this invention. It is a circuit diagram which shows the equivalent circuit of the SPDT switch apparatus of Embodiment 8 of this invention. It is a characteristic view which shows the high frequency characteristic of the SPDT switch apparatus of Embodiment 8 of this invention. It is a circuit diagram which shows the equivalent circuit of the SPDT switch apparatus of Embodiment 9 of this invention. It is a circuit diagram which shows the equivalent circuit of the SPDT switch apparatus of Embodiment 10 of this invention. It is a characteristic view which shows the high frequency characteristic of the SPDT switch apparatus of Embodiment 10 of this invention. It is a circuit diagram which shows the equivalent circuit of the conventional SPDT switch apparatus.

Explanation of symbols

101-116 Depletion type FET
120 enhancement type FET
201-267, 280, 281 Resistive elements 301, 302 Capacitors 401-410 Diodes 501-503 High-frequency signal input / output terminals 601, 602, 607, 610, 611 Control terminals 701-704 Ground terminals 801 Power terminals 901 SPDT circuit 902 Voltage inversion circuit

Claims (6)

A plurality of high-frequency input / output terminals for inputting and outputting a high-frequency signal; and a plurality of high-frequency switch circuit portions arranged between the high-frequency input / output terminals,
The high-frequency switch circuit unit is configured by connecting a plurality of field effect transistors in series, and applies either a high level voltage or a low level voltage to the gate terminal of the field effect transistor to turn on and off A plurality of electric field effects constituting the first high-frequency switch circuit section among the first and second high-frequency switch circuit sections that realize the state and that operate reversely in the plurality of high-frequency switch circuit sections. The first terminal of the first resistance element is connected to the intermediate connection point of the transistor, and the first resistance element of the second resistance element is connected to the intermediate connection point of the plurality of field effect transistors constituting the second high-frequency switch circuit unit. Are connected to the gate terminals of a plurality of field-effect transistors constituting the first high-frequency switch circuit section. The first terminal of the fourth resistance element is connected to the gate terminals of the plurality of field effect transistors that are connected and constitute the second high-frequency switch circuit unit, and the second terminal of the first resistance element A second terminal of the fourth resistance element is connected; a second terminal of the third resistance element is connected to a second terminal of the second resistance element;
The high-frequency switch device, wherein the high-frequency input / output terminals are directly connected to source / drain terminals of field-effect transistors constituting the first and second high-frequency switch circuit sections, respectively. A plurality of high-frequency input / output terminals for inputting and outputting a high-frequency signal; a series high-frequency switch circuit section disposed between the high-frequency input / output terminals; and a parallel high-frequency switch circuit section disposed between the high-frequency input / output terminals and a ground terminal. With
Each of the series high-frequency switch circuit unit and the parallel high-frequency switch circuit unit is configured by connecting a plurality of field effect transistors in series, and either a high level voltage or a low level voltage is applied to the gate terminal of the field effect transistor. First and second high-frequency switch circuit units that realize an on-state and an off-state by applying a voltage, and that operate reversely in each of the series high-frequency switch circuit unit and the parallel high-frequency switch circuit unit The first terminal of the first resistance element is connected to the intermediate connection point of the plurality of field effect transistors constituting the first high-frequency switch circuit section, and the second high-frequency switch circuit section is constructed. A first terminal of a second resistance element is connected to an intermediate connection point of each of the field effect transistors, and the first high-frequency switch circuit The first terminals of the third resistance elements are connected to the gate terminals of the plurality of field effect transistors constituting the part, and the first terminals of the plurality of field effect transistors constituting the second high-frequency switch circuit part are connected to the first terminal. A first terminal of the fourth resistive element is connected, a second terminal of the fourth resistive element is connected to a second terminal of the first resistive element, and a second terminal of the second resistive element A second terminal of the third resistance element is connected to the terminal;
The high frequency input / output terminal is directly connected to a source / drain terminal of a field effect transistor constituting each of the first to fourth high frequency switch circuit sections.   All the second terminals of the first resistance elements are connected in common, all the second terminals of the second resistance elements are connected in common, and all the second terminals of the third resistance elements are common. 3. The high-frequency switch device according to claim 1, wherein all of the second terminals of the fourth resistance elements are connected in common. A semiconductor device in which a high-frequency switch device including a plurality of high-frequency input / output terminals for inputting / outputting a high-frequency signal and a plurality of high-frequency switch circuit portions arranged between the high-frequency input / output terminals is integrated on a semiconductor substrate. And
The high-frequency switch circuit unit is configured by connecting a plurality of field effect transistors in series, and applies either a high level voltage or a low level voltage to the gate terminal of the field effect transistor to turn on and off A plurality of electric field effects constituting the first high-frequency switch circuit section among the first and second high-frequency switch circuit sections that realize the state and that operate reversely in the plurality of high-frequency switch circuit sections. The first terminal of the first resistance element is connected to the intermediate connection point of the transistor, and the first resistance element of the second resistance element is connected to the intermediate connection point of the plurality of field effect transistors constituting the second high-frequency switch circuit unit. Are connected to the gate terminals of a plurality of field-effect transistors constituting the first high-frequency switch circuit section. The first terminal of the fourth resistance element is connected to the gate terminals of the plurality of field effect transistors that are connected and constitute the second high-frequency switch circuit unit, and the second terminal of the first resistance element A second terminal of the fourth resistance element is connected; a second terminal of the third resistance element is connected to a second terminal of the second resistance element;
The high frequency input / output terminal is directly connected to a source / drain terminal of a field effect transistor constituting the first and second high frequency switch circuit sections, respectively. A plurality of high-frequency input / output terminals for inputting and outputting a high-frequency signal; a series high-frequency switch circuit section disposed between the high-frequency input / output terminals; and a parallel high-frequency switch circuit section disposed between the high-frequency input / output terminals and a ground terminal. A semiconductor device in which a high-frequency switch device comprising:
Each of the series high-frequency switch circuit unit and the parallel high-frequency switch circuit unit is configured by connecting a plurality of field effect transistors in series, and either a high level voltage or a low level voltage is applied to the gate terminal of the field effect transistor. First and second high-frequency switch circuit units that realize an on-state and an off-state by applying a voltage, and that operate reversely in each of the series high-frequency switch circuit unit and the parallel high-frequency switch circuit unit The first terminal of the first resistance element is connected to the intermediate connection point of the plurality of field effect transistors constituting the first high-frequency switch circuit section, and the second high-frequency switch circuit section is constructed. A first terminal of a second resistance element is connected to an intermediate connection point of each of the field effect transistors, and the first high-frequency switch circuit The first terminals of the third resistance elements are connected to the gate terminals of the plurality of field effect transistors constituting the part, and the first terminals of the plurality of field effect transistors constituting the second high-frequency switch circuit part are connected to the first terminal. A first terminal of the fourth resistive element is connected, a second terminal of the fourth resistive element is connected to a second terminal of the first resistive element, and a second terminal of the second resistive element A second terminal of the third resistance element is connected to the terminal;
The high-frequency input / output terminal is directly connected to a source / drain terminal of a field effect transistor constituting each of the first to fourth high-frequency switch circuit units.   All the second terminals of the first resistance elements are connected in common, all the second terminals of the second resistance elements are connected in common, and all the second terminals of the third resistance elements are common. 6. The semiconductor device according to claim 4, wherein all of the second terminals of the fourth resistance elements are connected in common.

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