JP2007184571A - Silicon cardide semiconductor device, method of manufacturing same, junction between transition metal silicide and metal film therein, and method of manufacturing junction between transition metal silicide and metal film therein - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device which does not cause peeling of an upper conductor film that coats a silicide electrode, to provide a method of manufacturing the silicon carbide semiconductor device, to provide a junction between a transition metal silicide and a metal film in the silicon carbide semiconductor device, and to provide a method of manufacturing the junction between the transition metal silicide and the metal film in the silicon carbide semiconductor device. <P>SOLUTION: The low-carbon silicide electrode is formed by coating an n-type SiC substrate 1 with a contact parent material such as Ni, forming a silicide electrode 52 by making the contact parent material and the n-type SiC substrate 1 react in solid phase, drawing off at least a part of the carbon formed inside the silicide electrode 52 to the outside of the electrode, and removing it. Accordingly, an upper conductor film 3 of the silicon carbide semiconductor device is coated on a low-carbon silicide electrode 52 in which the carbon content is lower than the silicon content in comparing the mol numbers. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a silicon carbide semiconductor device, a method for manufacturing a silicon carbide semiconductor device, a joined body of a transition metal silicide and a metal film in the silicon carbide semiconductor device, and a joined body of a transition metal silicide and a metal film in the silicon carbide semiconductor device. It relates to a manufacturing method.

  Semiconductor silicon carbide (SiC) has excellent physical properties such as a high breakdown electric field, a high saturation electron velocity, high thermal conductivity, high heat resistance, high chemical stability, tough mechanical strength, and a pn junction. It can be formed and a thermally oxidized silicon film can be grown. For this reason, it has long been expected as a semiconductor material that realizes an ultra-low loss power device, a high-frequency power amplification element, a high-temperature operation switching element, and the like that cannot be achieved with Si, and basic research has been continuously performed. Recently, the development of each of these SiC electronic devices and their manufacturing technology has been vigorously promoted in the semiconductor industry, as a large-diameter, relatively high-quality single crystal substrate has become commercially available. (See, for example, Patent Document 1 below).

  In the manufacturing process of the SiC electronic device, it is necessary to form at least one ohmic contact. As a conventional technique for forming such an ohmic contact, for example, a method of forming an ohmic contact by forming a silicide electrode at an ohmic contact portion and forming an upper conductor film thereon is performed.

A method for forming the ohmic contact will be described in order. A contact base material made of, for example, Ni is formed on the silicon carbide substrate by EB vapor deposition or the like. Next, this silicon carbide substrate is subjected to high-temperature heat treatment at 1000 ° C. for 2 minutes, for example, in an inert atmosphere. As a result, the silicon carbide substrate and the contact matrix film react to produce a silicide electrode. By this reaction, ohmic properties can be obtained. If a transition metal such as Ni is used as the contact base material, a transition metal silicide is formed.

Thereafter, a mounting electrode is formed thereon. The mounting electrode is provided to improve solder wettability when soldering a semiconductor to a circuit board, for example, or to improve wire bonding connectivity. For example, a Ti / Ni / Ag laminated film is used. In this case, if a transition metal such as Ni is used as the contact base material, a composite of a transition metal silicide and a metal film is formed.
JP 2003-318398 A

  However, the above prior art has a problem that the upper conductor film is suddenly peeled off after the contact structure is formed, thereby reducing the yield of the device or causing a failure after the device is completed. Furthermore, this problem also occurs when the contact is not ohmic.

As a cause of this, the following reaction due to the heat treatment at the time of forming the ohmic contact is regarded as a problem.
Ni + 2SiC → NiSi ₂ + 2C (when the contact base material is Ni)
Ni reacts with Si of silicon carbide to produce Ni silicide, and at the same time, carbon, which is a constituent element of SiC, is produced as a byproduct. The generated carbon is considered to deteriorate the adhesion of the upper conductor film because the adhesion to the metal is poor. In order to investigate the carbon distribution, AES analysis is performed on the surface of the silicide electrode (Ni is deposited on a silicon carbide substrate with a thickness of 100 nm as a contact base material) after the rapid heat treatment, and the element distribution in the depth direction is examined. It was. The result is shown in FIG. The horizontal axis represents the distance converted from sputtering time to depth using the SiO ₂ sputtering rate, and the vertical axis represents the presence ratio of each element. Initially, the contact base material (Ni) existing only on the surface diffuses to the substrate side while reducing the existence ratio to a depth of about 500 nm. Si is distributed while gradually decreasing the existence ratio from the depth of about 500 nm toward the surface. Carbon gradually decreases from a depth of about 250 nm toward the surface, and once increases at a depth of about 100 nm (101 part in FIG. 14), then the abundance is decreased to a depth of about 40 nm. The surface is almost covered with carbon. Thus, it has been found that there is a portion (carbon enriched portion) where carbon is concentrated on the surface and inside of the silicide electrode. FIG. 13 shows the structure when the upper conductor film is attached in this state. When the upper electrode film was formed, the graphite deposited on the silicide surface was poor in adhesion, so that peeling occurred immediately. Further, the carbon in the carbon enriched portion in the silicide has been agglomerated and precipitated due to the long-term use of the semiconductor element, and has been in a state where it is more likely to be peeled off.

For example, in the method disclosed in Japanese Patent Application Laid-Open No. 2003-243323, Ni as a contact base material is vapor-deposited on a silicon carbide substrate and subjected to high-temperature heat treatment. Thereafter, Ni oxide generated on the silicide surface is removed with buffered hydrofluoric acid. Further, graphite and Ni carbide generated during the high temperature treatment are removed by O ₂ plasma etching or argon ion milling. When O ₂ plasma etching is performed, a metal oxide film is formed on the very surface. In order to remove the metal oxide, the metal oxide is removed by exposure to an inert gas plasma, ion milling, wet etching using diluted hydrofluoric acid, or the like. An upper electrode film made of a Ti film and an Au film is formed on this and completed.

However, this method can remove graphite and Ni carbide on the silicide surface, but cannot remove the carbon-enriched portion in the silicide electrode. This is because carbon does not diffuse at the temperature of the silicon carbide substrate during the O ₂ plasma etching, so that carbon in the silicide electrode remains in the silicide electrode as it is. For this reason, the upper electrode film does not peel off immediately after it is attached, but the remaining carbon agglomerates and precipitates during long-term use of the semiconductor element, resulting in peeling.

  Further, for example, in the method according to Japanese Patent Laid-Open No. 2006-24880, the process up to the step of depositing Ni as a contact base material on a silicon carbide substrate and performing a high temperature heat treatment is the same as that in Patent Document 2. Thereafter, a part of the silicide electrode is removed using chemical etching (for example, hydrogen peroxide). An upper electrode film made of a Ni film and an Au film is formed on this and completed.

  However, in this method, a graphite film is formed on the surface after silicide formation by high-temperature heat treatment, so even if chemical etching is performed after that, this graphite film prevents the etchant from entering the silicide. Therefore, etching becomes difficult.

  Further, since the silicide electrode after the high-temperature heat treatment is silicided to the surface, it is difficult to remove the carbon-enriched portion in the silicide itself because the silicide itself is difficult to etch with an acid. .

  Even if the carbon on the surface of the silicide electrode is removed by etching, the carbon-enriched portion inside the silicide causes agglomeration / precipitation of carbon in a long-term use of the semiconductor element, and produces a precipitate 44 that is seen as graphite. The upper electrode film peels off.

  The present invention has been made in view of the above problems, and the problem to be solved by the present invention is that of a silicon carbide semiconductor device and a silicon carbide semiconductor device that do not cause peeling of an upper conductor film deposited on a silicide electrode. An object of the present invention is to provide a manufacturing method, a bonded body of a transition metal silicide and a metal film in a silicon carbide semiconductor device, and a manufacturing method of a bonded body of a transition metal silicide and a metal film in a silicon carbide semiconductor device.

  In order to solve the above-mentioned problems, in the present invention, a silicon carbide semiconductor device is characterized in that the carbon content of the silicide electrode is smaller than the silicon content of the electrode in terms of the number of moles. .

  A silicon carbide semiconductor device that does not cause peeling of the upper conductor film deposited on the silicide electrode by eliminating the generation of precipitated carbon that causes peeling of the upper conductor film, using the silicide electrode as a low-carbon-containing silicide electrode, It is possible to provide a method for manufacturing a silicon carbide semiconductor device, a joined body of a transition metal silicide and a metal film in the silicon carbide semiconductor device, and a joined body of a transition metal silicide and a metal film in the silicon carbide semiconductor device. It becomes.

  In order to solve the above problem, in other words, in order to achieve the present invention, the inventor of the present application first conducted a thorough investigation of the cause of defects.

  First, the place to peel was identified. FIG. 13 is a cross-sectional view of a main part of an ohmic contact which is a structure used at that time and is manufactured by a conventional technique and has a cause of failure. In the figure, reference numeral 1 denotes an n-type SiC substrate, and a silicide electrode 41 is formed thereon (lower in the figure) by a solid phase reaction (caused by a heating process called contact annealing) with a contact base material and a silicon carbide substrate. Further, an upper conductor film 3 is formed thereon.

  As a result of observing a number of defects in detail, as shown in the cross-sectional structure of FIG. It was found to be one of the silicide interiors 43). Peeling at the electrode-conductor interface 42 was relatively large, approximately 80% of all defects, and the rest was peeling in the silicide interior 43.

  As a result of physical analysis, a large amount of precipitates 44, which appear to be graphite (C), were detected from the peeled surfaces (42 and 43). On the other hand, when the carbon concentration inside the silicide electrode 41 was compared by secondary ion mass spectrometry (SIMS), the carbon concentration in the portion below the peeling surface of the test product that caused the peeling failure was surprisingly non-peeling. It was found that the carbon concentration of the product is more than an order of magnitude lower.

According to metallurgical knowledge, contact base materials such as Ni and Co that are in contact with SiC are heated at a high temperature by Ni + 2SiC → NiSi ₂ + 2C (contact base material: Ni)
It is known that a solid-phase reaction as described above easily forms silicide, but does not form carbide.

  From the above facts and consideration, it is inferred that the peeling failure occurs based on the following generation mechanism.

  Carbon (C) generated by the above solid-phase reaction (contact annealing) is dispersed throughout the silicide electrode 41 as an unstable supersaturated state or fine precipitate. When some kind of stimulus is applied after the upper conductor film 3 is laminated, it is discharged all at once and aggregates (deposits) in the form of precipitates 44 that appear to be graphite at the electrode-conductor interface 42 and the silicide interior 43. Since the precipitate 44 is a brittle material with poor adhesion, it is easily broken when a slight stress is applied, and the upper conductor film 3 is peeled off.

  Based on this analysis result, the present inventor made the following inference. “If the excess carbon dispersed in the silicide electrode can be intentionally discharged and removed as a precipitate that appears as graphite before the upper conductor film is formed, the upper electrode can be prevented from peeling off. Will". As a result of various investigations, we found several methods for exhausting excess carbon and methods for removing precipitates that appear to be graphite, and it was confirmed that applying this method would achieve the effect as inferred. .

  The present invention was thus completed.

  The present invention has been made to solve the above-described problems of the prior art, and the silicon carbide semiconductor device according to the present invention is characterized in that a contact base material is deposited on a silicon carbide substrate and the silicon carbide substrate and the solid phase. In a silicon carbide semiconductor device having a silicide electrode formed by reaction and an upper conductor film deposited on the silicide electrode, the amount of the silicide electrode is smaller than the amount of silicon compared to the number of moles. This is to be a low-carbon silicide electrode containing a large amount of carbon.

  As apparent from the above reaction formula, the number of moles of carbon generated by this reaction (contact annealing) is equal to the number of moles of silicon in the silicide. Therefore, in the present invention, for example, at least a part of the generated carbon is reduced. A silicon carbide semiconductor device having a low carbon content silicide electrode containing a smaller amount of carbon than the amount of silicon deposited and removed outside the silicide electrode as a constituent element is configured.

  Furthermore, in order to more effectively solve the above-mentioned problems of the prior art, the present invention represents the carbon content of the low-carbon silicide electrode in terms of moles and is 1/5 of the silicon content of the electrode. Hereinafter, one of the gist is desirably 1/10 or less.

  The present invention also includes a step of depositing a contact base material on a silicon carbide substrate, heating the silicon carbide substrate on which the contact base material is deposited, and a solid phase reaction between the contact base material and the silicon carbide substrate. A contact annealing step that is a step of forming a silicide electrode by: a surface precipitation step that is a step of precipitating at least a part of carbon generated by the contact annealing step on the surface of the silicide electrode; and the silicide by the surface precipitation step. A deposited carbon removing step which is a step of removing deposited carbon which is carbon deposited on the electrode surface; and after the deposited carbon removing step, an upper portion on the surface of the silicide electrode which has become a low carbon content silicide electrode by the surface deposition step. A method of manufacturing a silicon carbide semiconductor device, comprising: depositing a conductor film. It is formed.

  In the following description, the “precipitated carbon” is considered to be mainly composed of graphite, and the “precipitated carbon” is simply referred to as “graphite”.

  Furthermore, in the present invention, it is one of the gist that the surface precipitation treatment is performed in a non-oxidizing gas atmosphere at a temperature of 100 ° C. or higher and 600 ° C. or lower.

  Furthermore, one of the gist of the present invention is to use a non-oxidizing gas atmosphere to which hydrogen or helium is added in order to effectively carry out the surface precipitation treatment constituted by the heat treatment in the non-oxidizing gas atmosphere. It is said.

  In addition, in order to effectively carry out the surface precipitation treatment constituted by the heat treatment in a non-oxidizing gas atmosphere, the present invention has a gist of raising and lowering the treatment temperature intermittently during the heat treatment. Yes.

  The gist of the present invention is to apply ultrasonic vibration to the substrate during the heat treatment in order to effectively carry out the surface precipitation treatment constituted by the heat treatment in a non-oxidizing gas atmosphere. .

  In the present invention, the graphite removal treatment is performed by mechanically scraping the graphite on the surface of the silicide electrode with a fiber assembly moistened with a liquid, for example, a chemical fiber cloth moistened with pure water. It is one of the gist.

  In addition, in the present invention, it is one of the gist that the graphite removal treatment is performed by removing graphite on the electrode surface with a chemical solution.

  In the present invention, the chemical solution used for the graphite removal treatment is one selected from an ammonium fluoride aqueous solution, a buffered hydrofluoric acid solution, a nitric acid-added phosphoric acid-acetic acid mixed solution, and a photoresist stripping solution. This is one of the gist.

  Further, in the present invention, it is one of the gist that the graphite removal treatment is performed by oxidizing graphite with active oxygen in the gas phase, for example, active oxygen in oxygen plasma.

  In the structure of the silicon carbide semiconductor device according to the present invention, since the silicide electrode on which the upper conductor film is placed does not substantially contain an excessive amount of carbon that can cause peeling, even after forming the upper conductor film, Even when stimulated, no graphite deposition occurs. Since the graphite does not precipitate, the upper conductor film does not peel off. In other words, in the embodiment of the present invention, it is possible to solve the problem that “the upper conductor film is suddenly peeled off to lower the device yield or cause a failure after the device is completed”. I can say that.

  This configuration is made possible by providing a process for forcibly depositing excess carbon in the silicide electrode on the surface as graphite and removing the deposited surface graphite before forming the upper conductor film. is there. The specific method will be described in detail in each embodiment of the present invention described below.

  Hereinafter, some embodiments of the present invention will be specifically described with reference to the drawings. The following drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, and the like. It should be noted that is different from the real thing. Accordingly, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The present invention is applicable to all crystal planes such as 4H, 6H, 3C, and 15R (H is hexagonal, C is cubic, and R is rhombohedral), and all crystal planes of each crystal substrate. However, here, for convenience, the substrate will be described as a 4H—SiC substrate. This is because this substrate is the most promising substrate today as a substrate that gives excellent device characteristics among various silicon carbide substrates.

  In the following description, unless otherwise specified, a substrate in which an epitaxial layer or other film or electrode is formed on a SiC substrate is referred to as “SiC substrate” or simply “substrate”.

[First Embodiment]
Hereinafter, a silicon carbide semiconductor device having a simple ohmic contact, which is a silicon carbide semiconductor device according to the present invention, and a method for manufacturing the same will be described.

FIG. 1 shows a cross-sectional structure of a main part of the silicon carbide semiconductor device in the first embodiment. In the figure, reference numeral 1 denotes an n-type 4H—SiC substrate which is a silicon carbide substrate, and at least the contact surface layer portion is doped with a high-concentration n-type impurity. The contact surface of the substrate 1 is provided with a low-carbon silicide electrode 52 (for example, NiSi ₂ ) formed by contact annealing and containing less carbon than the amount of silicon compared to the number of moles. ing. The carbon content is expressed by the number of moles, and is preferably at least 1/5 or less of the silicon content, desirably 1/10 or less. That is, even in the region where the carbon concentration is 1/5 or more of the silicon concentration, if the carbon concentration is lower than the silicon concentration, a certain effect of the present invention can be obtained, and the occurrence rate of defective peeling of the upper conductor film is also reduced. However, if it is 1/5 or less, a very remarkable effect can be obtained, and the occurrence rate of peeling failure can be reduced by two orders of magnitude or more.

  The low carbon content silicide electrode 52 has a thickness of 20 nm to 500 nm, preferably 50 nm to 250 nm.

  On the low-carbon silicide electrode 52, the upper conductor film 3 is laminated. The upper conductor film 3 may be a metallized film for mounting (for example, a Ti / Ni / Ag laminated film) or a surface wiring (Al film or Cu film) for current extraction.

  An ohmic contact is formed between the substrate 1 and the upper conductor film 3.

  Next, a method for manufacturing the silicon carbide semiconductor device for manufacturing the silicon carbide semiconductor device shown in FIG. 1 will be described with reference to cross-sectional process diagrams shown in FIGS.

Here, an ohmic having an upper conductor film 3 (metallized film) for mounting on the back main surface of a low resistance n ⁺ type 4H-SiC substrate 1 having a (0001) _Si surface on the front main surface, which is a silicon carbide substrate. Although an example of forming a contact will be described, the case where an ohmic contact is formed on the front main surface is basically not different from this.

  In the following description, (step a), (step b),... (Step f) correspond to (a), (b),.

(Process a)
First, an n-type SiC substrate (n ⁺ -type 4H-SiC) 1 which is a silicon carbide substrate on which a contact is to be formed is dry oxidized at 1160 ° C. to grow a thermal oxide film on the back main surface of the substrate, which is immediately buffered By removing with a hydrofluoric acid solution, the high-quality crystal layer is exposed except the low-quality crystal layer present on the surface layer of the substrate ((a) of FIG. 2). This sacrificial oxidation process is a very important process in order to achieve a reduction in contact resistance, but may be omitted if a low resistance contact is not required.

(Process b)
Next, when the n-type SiC substrate 1 is rinsed with ultrapure water and dried, a film forming means such as DC sputtering is used on the entire main surface of the back side of the substrate 1 as shown in FIG. A base material 50 is deposited. As the contact base material 50, a conductive material that forms silicide by contact annealing and generates carbon as a by-product, such as Ni or Co, is used. In the following steps, the contact base material 50 will be described as being made of Ni for convenience.

  The film thickness of the contact base material 50 is one of the factors that strongly influence the occurrence of peeling of the upper conductor film 3. When the film thickness is increased, the amount of carbon generated by subsequent contact annealing increases, and as a result, the risk of film peeling increases. Therefore, the film thickness should be as thin as possible. However, if the film thickness is made too thin, there is a problem that the contact resistance rapidly increases from a certain film thickness, which is not preferable. When the thickness is reduced, the thickness immediately before the contact resistance starts to increase rapidly is the optimum thickness. For example, the optimum thickness of the contact base material 50 is approximately 50 nm when the contact surface is very flat, and approximately 100 nm when the contact surface is a ground surface having fine irregularities. The optimum film thickness varies somewhat depending on the crystal quality and crystal system of the SiC substrate 1 and the state of polishing (or grinding). Generally speaking, the optimum film thickness is generally in the range of 15 nm to 250 nm, and usually in the range of 25 nm to 125 nm.

(Process c)
Next, when the contact base material 50 (Ni which is a transition metal) is deposited, the substrate 1 is immediately placed in a rapid heat treatment apparatus, and in a high-purity Ar atmosphere from which moisture and oxygen are thoroughly removed. A rapid heat treatment (contact annealing) is performed at 1000 ° C. for 2 minutes. This heat treatment, Ni film deposited on the back side main surface (the contact parent material 50) by solid phase reaction with the SiC substrate 1, as shown in FIG. 2 (c), next to the silicide electrode 51, n ⁺ An extremely low contact resistance is exhibited at the interface between the mold substrate 1 and the silicide electrode 51. However, at this point, a part of the excess carbon generated by the solid-phase reaction exists as a graphite layer 54 on the surface of the silicide electrode 51, as shown in FIG. However, the other part exists in a state dispersed throughout the interior. The element distribution on the surface of the silicide electrode at this time is shown in FIG.

(Process d)
Next, when the substrate 1 is heat-treated in a non-oxidizing gas atmosphere in a range of 100 ° C. or higher and 600 ° C. or lower (surface precipitation treatment), the carbon dispersed in the silicide electrode 51 in an unstable state is directed toward the surface. As shown in FIG. 2D, it precipitates as graphite 53. This surface deposition treatment is carried out until the carbon content concentration (molar concentration) in the low carbon content silicide electrode 52 is reduced to at least 1/5 or less, preferably 1/10 or less, relative to the molar concentration of silicon. As a result, the silicide electrode 51 is converted to the low carbon content silicide electrode 52 having a low carbon content as a result of this treatment.

  By this heat treatment, the graphite 53 is always deposited on the surface, not in the low-carbon silicide electrode 52. The reason is that, at this point, since there is no upper conductor film as an obstacle, it is more thermodynamically stable and easier to deposit on the surface where the free space is open than to deposit inside the solid.

  In addition, if this process is implemented with the rapid heat treatment apparatus used by contact annealing, this process can be implemented continuously from the previous process, and the manufacturing process can be rationalized.

Furthermore, when the following conditions (1) to (3) are taken into consideration, the processing time can be shortened, the processing temperature can be reduced, and the processing can be ensured.
(1) Add hydrogen or helium to the processing gas.
(2) Increase or decrease the temperature intermittently.
(3) Apply ultrasonic vibration.

  Taking these into account, an example of practical surface deposition treatment conditions is “temperature constant at 400 ° C., in pure hydrogen gas atmosphere for 20 minutes”.

  Apart from the heat treatment (surface precipitation treatment) in the non-oxidizing gas atmosphere, the substrate 1 is heat treated in an oxygen-containing atmosphere in the range of 100 ° C. to 600 ° C. (carbon diffusion step or carbon concentrated portion removal step). As a result, a part of the graphite layer 54 (FIG. 17) deposited on the surface of the silicide electrode is oxidized. The oxidized graphite layer 54 is decomposed and removed into carbon monoxide, carbon dioxide, or the like. Further, the carbon dispersed in the silicide electrode 51 is diffused to the surface by heat. A part of the carbon diffused to the surface is accumulated on the surface, but a part is oxidized and decomposed. Further, Si and Ni in the vicinity of the surface are oxidized to form a complex oxide layer of Si and Ni. As an example of oxidation, FIG. 15 shows the result of AES analysis of a sample heated in an atmosphere containing oxygen at 500 ° C. for 20 minutes. Thus, the carbon concentration on the surface was about 90% before the heat treatment, but became about 60% after the heat treatment, and it was found that the amount was decomposed and reduced by oxygen (carbon diffusion). At a depth of 200 nm from the surface, a complex oxide film is formed as can be seen from the high oxygen concentration. Except for this portion, the carbon concentration in the silicide electrode decreases along the direction away from the substrate. Further, there was a carbon-concentrated portion (101 part in FIG. 14) at a depth of about 100 nm before the heat treatment, but this portion disappeared after the heat treatment. This is an effect obtained when the substrate is heated to 100 ° C. or more and 600 ° C. or less, and it is considered that the portion of carbon concentrated by heating was thermally diffused to the surface (carbon enrichment portion). Removal). Thus, it has been found that the amount of carbon in the silicide electrode can be reduced by performing heat treatment in an oxygen-containing atmosphere.

Further, the carbon precipitation diffusion step or the carbon enriched portion removal step may be performed in a plasma containing oxygen gas or in an active oxygen atmosphere such as UV (ultraviolet light) / ozone at 100 ° C. or more and 600 ° C. or less. . If this method is used, the decomposition of the graphite layer 54 formed on the surface of the silicide electrode 51 can be further promoted.
This carbon precipitation diffusion step or carbon enrichment removal step is not only in an oxygen atmosphere, but also in a gas atmosphere that is easily combined with other carbon (for example, containing any one of oxygen gas, hydrogen gas, and fluorine gas). Atmosphere).

(Process e)
Next, as shown in FIG. 3E, the graphite 53 that has been heat-treated (surface precipitation treatment) in a non-oxidizing gas atmosphere and deposited on the surface of the low-carbon silicide electrode 52 is removed cleanly (graphite removal treatment). Thus, the low-carbon silicide electrode 52 is exposed.

There are several methods for removing graphite as follows, and any method may be selected.
(1) The friction method. The graphite 53 on the surface of the silicide electrode is formed with a chemical fiber cloth (for example, a Berglin cloth (trade name)) moistened with pure water by a method similar to that used in post-processing (cleaning) of chemical mechanical polishing (CMP). This is a mechanical scraping method. Furthermore, generally, it is also possible to mechanically scrape the graphite 53 with a fiber assembly moistened with a liquid. However, when the low carbon content silicide electrode 52 is formed in the depression, these methods are not suitable, and the following method is used.
(2) Chemical solution method. A method of removing the graphite 53 with a chemical solution. In this case, the graphite 53 is not necessarily dissolved in the chemical solution but is removed by being dispersed in the chemical solution. Suitable chemicals include, but are not limited to, an aqueous ammonium fluoride solution, a buffered hydrofluoric acid solution, a mixed solution of nitric acid-added phosphoric acid and acetic acid, aqua regia, and a photoresist stripping solution. It is more effective to spray a chemical solution on the surface of the silicide electrode or immerse the substrate in a chemical solution tank to which ultrasonic vibration is applied.
(3) Oxidation method. In this method, the substrate is placed in an active oxygen atmosphere such as oxygen plasma or UV (ultraviolet light) / ozone, and the graphite 53 is oxidized and removed by active oxygen in the gas phase. For this purpose, a commercially available photoresist incinerator (asher) can be used without modification.

  If the above three methods are performed at the same time, the process can be carried out more effectively. For example, when rubbing with a chemical fiber cloth moistened with a buffered hydrofluoric acid solution (combination of (1) and (2)), the treatment can be completed in several tens of seconds.

When heat treatment (carbon diffusion step or carbon concentrated portion removal step) is performed in an oxygen-containing atmosphere in step d,
The graphite 53 and composite oxide (not shown) deposited on the surface of the low carbon content silicide electrode 52 are removed to expose the low carbon content silicide electrode 52 (graphite / composite oxide removal step).

  The complex oxide can be removed by using a chemical solution such as a buffered hydrofluoric acid solution or an aqueous ammonium fluoride solution. The graphite 53 is weakened by being partially oxidized and decomposed in the previous step, but it has hindered the penetration of the etching solution to some extent. At this time, if mechanical friction or ultrasonic vibration is applied, the removal of the graphite 53 can be promoted, the etching solution can easily reach the composite oxide, and the etching further proceeds. FIG. 16 shows the result of AES analysis performed on the sample after performing this step. Thus, it can be seen that the graphite 53 and the composite oxide are reliably removed.

  The graphite / complex oxide removing step may be performed by etching using a halogen-based gas, for example, a gas that forms a fluorocarbon polymer, for example, trifluoromethane. If this method is used, contamination by the etching solution in which the oxide film is dissolved can be prevented as compared with the case where the etching solution is used.

Further, the graphite / complex oxide removing step may be performed by a vapor phase etching method. For example, under a pressure of 0.13 to 1.3 hPa, a mixed gas of hydrogen fluoride (HF) and water vapor, a mixed gas of hydrogen fluoride (HF) and anhydrous methyl alcohol (CH ₃ OH) or isopropyl alcohol, or hydrogen fluoride ( The gas phase etching oxide film by HF) can be removed. Alternatively, there is a method in which the oxide is removed by placing the substrate 1 in a mixed gas of hydrogen (H ₂ ) and a small amount of hydrogen fluoride (HF) and irradiating ultraviolet rays having a wavelength of several hundred nm, for example, 200 nm to 300 nm. By using these methods, there is an advantage that the generation of particles is extremely small.

  This step exposes the surface of the low-contained silicide electrode 52, which is the surface of the electrode that does not easily peel off. The carbon atom concentration on the surface is preferably 30% or less, and desirably 5% or less.

(Process f)
Next, when the graphite 53 on the low carbon content silicide electrode 52 is removed, the substrate 1 is sufficiently cleaned, and immediately after the low carbon content silicide electrode 52 of the substrate 1 is formed by DC sputtering or electron beam evaporation. For example, Ti, Ni, and Ag are sequentially deposited as the upper conductor film 3 by using the film means. In addition, when the upper conductor film 3 needs to be patterned, photolithography and etching are continuously performed. In this way, the final structure of the ohmic contact ((f) in FIG. 3) is completed. This final structure is the same as that of the silicon carbide semiconductor device according to the present invention shown in FIG. Low-carbon silicide electrode 52 and upper conductor film 3 constitute a joined body of a transition metal silicide and a metal film in the silicon carbide semiconductor device.

  As is clear from the configuration shown in FIG. 1, the low carbon-containing silicide electrode 52 on which the upper conductor film 3 is deposited is a film that does not substantially contain an excessive amount of carbon that can cause peeling. Therefore, the upper conductor film 3 does not peel off. That is, it can be said that the first embodiment solves the problem that “the upper conductor film 3 is suddenly peeled off to reduce the yield of the device and cause a failure after the device is completed”.

  The configuration shown in FIG. 1 is made possible by forcing the excess carbon in the silicide electrode into graphite as a graphite before forming the upper conductor film 3 in the above-described method for manufacturing a silicon carbide semiconductor device. This is because a process for removing the deposited surface graphite was provided.

  In the embodiment, the conductor film is attached to the silicon carbide semiconductor device as an example. However, it can be used to attach a metal film to other transition metal carbides (TiC or the like), and is not limited to the silicon carbide substrate.

[Second Embodiment]
The second embodiment is an example in which the present invention is applied to a vertical Schottky diode, which is one of two-terminal devices.

FIG. 4 shows a cross-sectional view of the main part of a vertical Schottky diode which is a silicon carbide semiconductor device according to the present invention. Reference numeral 1 denotes a silicon carbide substrate, which is an n ⁺ type single crystal 4H—SiC substrate having an impurity concentration of 1 × 10 ¹⁹ / cm ³ or more, and has a thickness of 10 μm and nitrogen on the (0001) _Si surface which is the front main surface. The first n ⁻ type epitaxial layer 4 doped with 5 × 10 ¹⁵ / cm ³ is homoepitaxially grown.

In a predetermined region of the surface layer portion of the n ⁻ type epitaxial layer 4, an annular p-type electric field relaxation region 9 _a1 , 9 _a2 , 9 _a3 ,... 9 _an having a width of 2 μm formed by ion implantation and activation annealing is 2 μm. It is formed at intervals. Field relief regions _{9 a1, 9 a2, 9 a3} , the number of the ...... _{9 an} (n) depends breakdown voltage. For example, in the case of a 1000V breakdown voltage, it is sufficient that there are five (n = 5).

Reference numeral 5 denotes a field insulating film having an opening 6 that covers the front main surface of the substrate 1. A Schottky electrode 7 in contact with the n ⁻ -type epitaxial layer 4 is disposed on the bottom surface of the opening 6 and forms a Schottky junction with the epitaxial layer 4. The outer edge of the Schottky electrode 7 is placed on the p-type electric field relaxation region 9 _a1 (the innermost p-type annular region). Reference numeral 8 denotes a front-side main surface wiring, which is disposed so as to mechanically and electrically contact the Schottky electrode 7 and close the field opening 6. When viewed in a plan view, the outer edge of the front main surface wiring 8 is designed to be outside the outer edge of the Schottky electrode 7 and inside the outer edge of the p-type field relaxation region 3 _a1 . Shall.

  Reference numeral 52 denotes a low-carbon silicide electrode (ohmic electrode) provided on the back main surface of the substrate 1. On the low carbon content silicide electrode 52, the back side main surface upper conductive film 3 for the purpose of die bonding is placed.

  Rectification appears between the Schottky electrode 7 and the upper conductive film 3, and this silicon carbide semiconductor device functions as a vertical Schottky diode.

  Next, a method of manufacturing the vertical Schottky diode having the configuration shown in FIG. 4 will be described with reference to the sectional process diagrams shown in FIGS. In the following description, (step a), (step b),..., (Step g) correspond to (a), (b),.

(Process a)
First, an n ⁺ type 4H—SiC substrate 1, which is a silicon carbide substrate obtained by homoepitaxial growth of an n ⁻ type epitaxial layer 4 having a thickness of about 10 μm on the front side main surface, was prepared (purchased) and shown in FIG. Thus, p-type field relaxation regions 9 _a1 , 9 _a2 , 9 _a3 ,... 9 _an are formed on the surface of the n ⁻ -type epitaxial layer 4 by high-temperature selective ion implantation.

For this purpose, first, an SiO ₂ film having a thickness of about 1.5 μm is deposited on the entire front main surface of the substrate 1 by the CVD method, and an SiO ₂ film deposited on the region where the high concentration impurity region is to be formed is deposited. It is selectively removed by photolithography (patterning using a photoresist) and dry and wet combined etching techniques. Here, the dry and wet combined etching technique means that the substrate surface is subjected to plasma damage when the SiO ₂ film is removed by anisotropic dry etching such as reactive ion etching (RIE) or inductively coupled plasma etching (ICP). Therefore, dry etching is stopped immediately before the SiO ₂ film is completely removed, and the remaining portion is removed by wet etching using a buffered hydrofluoric acid solution or the like.

When the SiO ₂ film has been etched, the photoresist is removed from the substrate 1 and washed sufficiently, and then a thin SiO ₂ film having a thickness of 10 nm to 30 nm is formed on the surface of the substrate 1 by low pressure chemical vapor deposition (LPCVD). To form a through-SiO ₂ film.

In this way, formed where the resulting ion implantation mask, the Al ⁺ ions on the substrate surface by injecting multistage ion, p-type electric field relaxation region _{9 a1, 9 a2, 9 a3} , the precursor region of the ...... _{9 an} To do. An example of the ion implantation conditions for the p-type electric field relaxation region is as follows.

Substrate temperature 700 ° C
Acceleration energy / dose 1st stage 300 keV / 8.3 × 10 ¹⁵ / cm ²
Second stage 190 keV / 3.2 × 10 ¹⁵ / cm ²
Third stage 150 keV / 2.1 × 10 ¹⁵ / cm ²
4th stage 100 keV / 1.9 × 10 ¹⁵ / cm ²
5th stage 60 keV / 1.7 × 10 ¹⁵ / cm ²
6th stage 30 keV / 9.4 × 10 ¹⁴ / cm ²
When the ion implantation is completed, the substrate 1 is immersed in a buffered hydrofluoric acid solution to remove all the SiO ₂ films (mask film and through film) on the front and back, and after drying, a high-purity Ar atmosphere at a temperature of 1650 ° C. Among them, activation annealing is performed for about 1 minute to activate the precursor region of the p-type electric field relaxation region to be p-type electric field relaxation regions 9 _a1 , 9 _a2 , 9 _a3 ,... 9 _an . Thus, the structure shown in FIG. 5A is completed.

(Process b)
Next, when the activation of the p-type field relaxation region is completed, the substrate 1 is sufficiently washed and dried, and then a thermal oxide film is grown on the front and back surfaces of the substrate by sacrificing oxidation in a dry oxygen atmosphere at 1100 ° C. Thereafter, the substrate is immersed in a buffered hydrofluoric acid solution to remove the thermal oxide film on the substrate surface (sacrificial oxidation). The thickness of the thermal oxide film is less than 50 nm, preferably 5 nm or more and 20 nm or less.

When the sacrificial oxidation of the substrate surface is completed, the substrate 1 is thoroughly cleaned and then thermally oxidized in a dry oxygen atmosphere at 1100 ° C. to form a thermal oxide film having a thickness of about 5 nm to 20 nm on the entire front and back main surfaces of the substrate 1. As shown in FIG. 5B, a thick (600 nm thick) SiO ₂ film is deposited thereon using means such as atmospheric pressure chemical vapor deposition (APCVD). Then, a field insulating film 5 having a two-layer structure composed of a thermal oxide film and an APCVD-SiO ₂ film is formed. By this thermal oxidation, a thermal oxide film 13 having a thickness of 100 nm or more is also formed on the main surface on the back side of the substrate.

  The thermal oxide film under the field insulating film 5 has an effect of stabilizing the interface between the field insulating film 5 and the surface of the SiC substrate 1, improving the withstand voltage of the vertical device, and suppressing variations thereof. The thermal oxide film 13 on the main surface on the back side of the substrate has the effect of removing the low-quality crystal layer on the main surface on the back side of the substrate and reducing the contact resistance.

(Process c)
Next, after applying a protective photoresist on the field insulating film 5, the substrate 1 is dipped in a buffered hydrofluoric acid solution, and the thermal oxide film 13 formed on the back side main surface is removed. 1 Expose the back main surface. Subsequently, after sufficiently rinsing and drying the substrate 1 with ultrapure water, a contact base material is deposited on the exposed back main surface of the substrate 1 using a film forming means such as DC sputtering. At this time, it is preferable to vapor-deposit the peripheral portion of the back surface of the substrate using a shadow mask or the like so that the ohmic electrode base material does not adhere. For example, Ni or Co having a thickness of 100 nm can be used as the contact base material.

When the contact matrix is deposited, the substrate is immersed in a dedicated photoresist stripper solution to completely remove the protective photoresist. Then, the substrate is sufficiently washed, rinsed and dried, and immediately installed in a rapid heat treatment apparatus, and subjected to rapid heat treatment (contact annealing) at 1000 ° C. for 2 minutes in a high-purity Ar atmosphere. As a result of this heat treatment, the contact base material (Ni film or the like) deposited on the back surface undergoes a solid-phase reaction with the back main surface of the n ⁺ -type SiC substrate 1 as shown in FIG. It becomes the silicide electrode 51 containing carbon and exhibits extremely low contact resistance with respect to the substrate 1. The contact resistance of the ohmic electrode 9 achieved here is 10 ⁻⁶ Ωcm ² or less, and this value is negligibly small with respect to the ON resistance of the Schottky diode.

(Process d)
Next, the surface precipitation treatment step, the carbon diffusion step or the carbon concentrated portion removal step (FIG. 2 (d)) and the graphite removal treatment step or the graphite / composite oxide film removal step (FIG. 2) described in the first embodiment. 3 (e)), the silicide electrode 51 containing excessive carbon is converted into a low-carbon silicide electrode 52 and deposited on the surface thereof as shown in FIG. 6 (d). Remove graphite and complex oxide.

(Process e)
Next, after the formation of the low-carbon silicide electrode 52, photolithography is performed on the front main surface of the substrate 1 to form a photoresist pattern 19 for hollowing out the opening 6 on the surface of the field insulating film 5.

Subsequently, a photoresist 20 was applied to the main surface of the back side of the substrate 1 to completely cover and protect the low-carbon silicide electrode 52, and after the post-baking of the front and back photoresists, a buffered hydrofluoric acid solution was used. The wet etching or the dry / wet combined etching described above is performed to form the opening 6 in the field insulating film 5 and the n ⁻ type epitaxial layer 4 is exposed at the bottom of the opening 6 (opening etching).

  In this way, when the SiC epitaxial layer 4 is exposed in the opening 6, the substrate 1 is sufficiently rinsed with ultrapure water, dried, placed in a high vacuum electron beam deposition apparatus without interposing the hair, and is applied to the entire surface of the substrate 1. When a desired Schottky electrode material (here, Ti having a thickness of 50 nm) 21 is formed, a structure as shown in FIG. If the Schottky electrode material 21 is a material that is easily oxidized or dissolved with pure water or a photoresist stripper solution, such as Ti or Al, further, an anti-oxidation material is formed on the film. For example, Pt may be continuously formed in a thickness range of 50 nm to 150 nm.

(Process f)
Next, the substrate 1 is immersed in a dedicated photoresist stripper solution to completely remove the photoresist on the front and back surfaces of the substrate 1. FIG. 6 (f) shows the cross-sectional shape of the substrate after the stripper solution is sufficiently rinsed with ultrapure water or the like and dried. As is apparent from the figure, the structure is such that the Schottky electrode 7 is left only at the bottom of the opening 6 (the surface of the n ⁻ -type epitaxial layer 4), and the electrode film on the photoresist is removed along with the dissolution of the photoresist. It ’s done. Note that, when an oxidation-preventing conductive film is deposited, a structure in which an anti-oxidation conductive film of the same shape is stacked on the Schottky electrode 7 is obtained.

(Process g)
Next, using a means such as DC magnetron sputtering, a thick surface wiring material is vapor-deposited on the entire front main surface of the substrate 1, and then the wiring material is dried using a well-known photolithography and dry etching method such as RIE. When the front side main surface wiring 8 is patterned, the structure shown in FIG. As the surface wiring material, for example, a laminated film in which 50 nm thick Ti and 2 μm thick Al are continuously deposited can be used.

(Process h)
Finally, a conductive material used for die bonding is deposited on the entire back surface (on the low carbon-containing silicide electrode 52) of the cleaned and dried substrate 1 by means of DC magnetron sputtering or the like. When the upper conductor film 3 is formed, the Schottky die auto having the final structure shown in FIG. 4 is completed. An example of the upper conductor film 3 is a Ti / Ni / Ag film in which Ti (50 nm thickness), Ni (100 nm thickness) and Ag (150 nm thickness) are laminated in this order, but the present invention is of course limited to this. Not a thing.

  As is clear from the above description, even in the case of the second embodiment, the low-carbon-containing silicide electrode 52 on the back side main surface on which the upper conductor film 3 is deposited has an excessive amount of carbon that causes peeling. Therefore, no graphite is deposited inside the low carbon content silicide electrode 52 or at the interface between the silicide electrode 52 and the upper conductor film 3. Therefore, the upper conductor film 3 does not peel off. That is, in the second embodiment, it can be said that the problem that “the upper conductor film 3 is suddenly peeled off to reduce the yield of the device and cause a failure after the device is completed” is solved.

  The reason why the low carbon content silicide electrode 52 which does not contain an excessive amount of carbon that causes peeling is made possible in the manufacturing method according to the second embodiment of the present invention is that the silicide is formed before the upper conductor film 3 is formed. This is because a process for forcibly depositing excess carbon in the electrode as graphite on the surface and removing the deposited surface graphite is provided.

When 1000 vertical Schottky diodes having a Schottky electrode area of about 1 × 1 mm ² were manufactured based on the structure of the semiconductor device according to the present invention and the manufacturing method thereof, the failure mode in which the upper conductor film 3 peels is None were observed.

[Third Embodiment]
The third embodiment is an example in which the present invention is applied to a vertical MOSFET (metal-oxide-semiconductor structure field effect transistor) which is one of three-terminal switching devices. This example is also an example in which the present invention is applied to a device having silicide electrode type ohmic contacts on both the front side and the back side of the SiC substrate.

  FIG. 8 shows a cross section of a main part of a unit cell 70 of a SiC semiconductor MOSFET which is a silicon carbide semiconductor device according to the present invention. A unit cell is the smallest unit of an element area. In a power element, a large number of unit cells are arranged in parallel in the vertical and horizontal directions to increase current. In the following description, reference numeral 70 is used to mean both an element region and a unit cell.

Reference numeral 71 denotes a silicon carbide substrate which is an n ⁺ type single crystal 4H—SiC substrate doped with a high concentration of impurities. The surface (upper main surface in the figure) has a thickness of 10 μm and nitrogen is added at 1 × 10 ⁻¹⁶ / cm ^3. The n ⁻ type epitaxial layer 72 is homoepitaxially grown. In addition to 4H, SiC substrates of all crystal systems such as 6H, 3C, and 15R (H is hexagonal, C is cubic, and R is rhombohedral) can be used.

the n ^- -type epitaxial layer 72 surface in a predetermined region, a p-type impurity n ^- p-type base region 73a and 73b were added higher than the impurity concentration of the type epitaxial layer 72 is formed spaced apart.

N ⁺ -type source regions (high-concentration impurity regions) 74a and 74b, which are shallower than the p-type base region and doped with high-concentration impurities, are formed in the surface layer predetermined regions of the p-type base regions 73a and 73b. p ⁺ -type base regions 75a and 75b to which p-type impurities are added at a high concentration are arranged in part of the p-type base regions 73a and 73b and in the outer surface layers of the n ⁺ -type source regions 74a and 74b. It is installed. The impurity concentrations of the n ⁻ type epitaxial layer 72, the p type base regions (73a and 73b), and the n ⁺ type source regions (74a and 74b) are set to increase in this order.

  A gate oxide film 75 is provided on the front main surface of the SiC substrate 71 on which the impurity regions are formed. A conductive polycrystalline silicon gate electrode 76 is provided on the gate oxide film 75. A polycrystalline silicon oxide film 77 is disposed on the side and top surfaces of the gate electrode 76. On the gate oxide film 75 and the polycrystalline silicon oxide film 77, an interlayer insulating film 78 is formed.

79a and 79b are source windows opened in the interlayer insulating film 78 / gate oxide film 75 and penetrating through the n ⁺ type source regions 74a and 74b and the p ⁺ type base regions 75a and 75b on the surface of the SiC substrate 71. Source electrodes 80a and 80b serving as first low-carbon silicide electrodes are placed on the bottoms of the source windows 79a and 79b. The source electrodes 80a and 80b have a function of simultaneously providing ohmic contact to the n ⁺ -type source regions 74a and 74b and the p ⁺ -type base regions 75a and 75b. Reference numeral 82 denotes a front main surface wiring for connecting the n ⁺ type source region and the p ⁺ type base region to an external circuit and other circuit elements on the same substrate, and is a kind of upper conductor film.

  On the other hand, on the back main surface of the substrate 71, a drain electrode 81 is provided as a second low carbon content silicide electrode that provides an ohmic contact to the drain of the MOSFET cell. On the drain electrode 81, a back main surface wiring 61 (a kind of upper conductor film) for the purpose of smooth die bonding is placed.

  With this configuration, the silicon carbide semiconductor device functions as a vertical metal-oxide-semiconductor structure field effect transistor.

  Next, a method for manufacturing a MOSFET cell using the 4H-SiC substrate having the configuration shown in FIG. 8 will be described with reference to FIGS. In the following description, (step a), (step b),..., (Step h) correspond to (a), (b),.

(Process a)
First, an n ⁺ -type 4H—SiC substrate 71, which is a silicon carbide substrate obtained by homoepitaxially growing an n ⁻ -type epitaxial layer 72 having a thickness of about 10 μm on the surface side, is prepared (purchased). The precursor regions of the p-type base regions (73a and 73b), the n ⁺ -type source regions (74a and 74b), and the p ⁺ -type base regions (75a and 75b) in predetermined regions by the high-temperature selective ion implantation method described in FIG. Are sequentially formed. An example of ion implantation conditions for each region is as follows.

Ion implantation conditions for p-type base region Impurity Al ⁺ ion Substrate temperature 750 ° C.
Acceleration voltage / dose 360 keV / 5 × 10 ¹³ / cm ²
p ⁺ type base region ion implantation conditions Ion species Al ⁺
Injection temperature 750 ° C
Acceleration voltage / Dose
30 keV 1.0 × 10 ¹⁵ / cm ²
50 keV 1.0 × 10 ¹⁵ / cm ²
70 keV 2.0 × 10 ¹⁵ / cm ²
100 keV 3.0 × 10 ¹⁵ / cm ²
n ⁺ type source region ion implantation conditions Ion species P ⁺ (phosphorus)
Injection temperature 500 ° C
Acceleration voltage / Dose
40 keV 5.0 × 10 ¹⁴ / cm ²
70 keV 6.0 × 10 ¹⁴ / cm ²
100 keV 1.0 × 10 ¹⁵ / cm ²
160 keV 2.0 × 10 ¹⁵ / cm ²
When the high temperature ion implantation is completed, the final ion implantation mask formed on the SiC substrate 71 is removed by immersing it in a buffered hydrofluoric acid solution, the substrate is sufficiently washed, dried, and then subjected to activation annealing. All the precursor regions on the front and back of 71 are activated at a time to form p-type base layers 73a and 73b, n ⁺ -type source regions 74a and 74b, and p ⁺ -type base regions 75a and 75b. FIG. 9A shows the structure at this stage.

  The activation is placed on a high-purity carbon susceptor so that the front main surface of the substrate 71 faces upward (the back surface of the substrate is in contact with the susceptor), and a high-purity inert gas (for example, Ar) atmosphere or slightly It is carried out by performing a rapid heat treatment for 1 minute to several minutes at a temperature of 1600 ° C. or higher in a high purity inert gas atmosphere containing silane.

(Process b)
After the activation of the impurity layers on the front and back of the substrate 71, the substrate 71 is sufficiently washed and dried, and then a sacrificial oxidation is performed in a dry oxygen atmosphere at 1100 ° C. to grow a thermal oxide film on the surface of the substrate 71. Then, the substrate is immersed in a buffered hydrofluoric acid solution to remove the thermal oxide film on the substrate surface (sacrificial oxidation treatment). The thickness of the thermal oxide film is less than 50 nm, preferably 5 nm to 20 nm. By this sacrificial oxidation treatment, a contaminated layer or an irregular layer that causes a device failure is appropriately removed from the substrate surface.

When the sacrificial oxidation treatment is completed, the substrate is sufficiently cleaned, and then thermally oxidized in a dry oxygen atmosphere at 1100 ° C. to grow a thermal oxide film having a thickness of about 5 nm to 20 nm on the entire front and back main surfaces of the substrate 71. By depositing a thick (600 nm thick) SiO ₂ film on the front main surface of the substrate 71 using means such as atmospheric pressure chemical vapor deposition (APCVD), it is shown in FIG. 9B. Thus, a field insulating film 100 having a two-layer structure composed of a thermal oxide film and an APCVD-SiO ₂ film is formed. By this thermal oxidation, a temporary thermal oxide film 97 having a thickness of 100 nm or more is also formed on the back main surface.

  The thermal oxide film under the field insulating film 100 has an effect of stabilizing the interface between the field insulating film 100 and the surface of the SiC substrate 71, increasing the voltage resistance of the vertical device, and suppressing variations thereof.

(Process c)
Next, the field insulating film 100 on the substrate surface is selectively etched by using well-known photolithography and wet etching (or the above-described dry and wet combined etching), and the field region and the element region from which the field insulating film 100 has been removed ( 70) of FIG. 8 is formed. The temporary thermal oxide film 97 disappears by wet etching. The structure of the element region 70 at this time is the same as that in the previous figure, but the field insulating film 100 exists in a portion other than the element region 70, and the structure of the entire SiC substrate 71 is different.

Subsequently, the substrate 71 is sufficiently cleaned again, and in the final stage of the cleaning, in order to remove the chemical oxide film (SiO ₂ ) generated on the surface of the element region 70, the buffer 71 is added to a buffered hydrofluoric acid solution for 5 seconds to 10 seconds. After immersing for a second and completely rinsing the buffered hydrofluoric acid solution with ultrapure water, it is dried and immediately thermally oxidized to form a gate oxide film 75 of a desired thickness (for example, 40 nm thick here) on the substrate surface of the element region 70. Grow. Due to this gate oxidation, a temporary thermal oxide film 98 grows again on the back main surface. The conditions for the gate oxidation are not limited to this, but for example, dry oxidation at a temperature of 1160 ° C. is preferable. The important point here is that the thermal oxidation temperature is set higher than any heat treatment temperature in all subsequent processes.

Next, a polycrystalline silicon film 84 having a thickness of 300 nm to 400 nm is formed on the entire surface of the front side main surface and the back side main surface of the substrate 71 by a low pressure CVD method using a silane material (growth temperature 600 ° C. to 700 ° C.). P (phosphorus) is added to the polycrystalline silicon film by a known thermal diffusion method (treatment temperature: 900 ° C. to 950 ° C.) using phosphorus chlorate (POCl ₃ ) and oxygen to impart conductivity. Subsequently, an unnecessary portion of the polycrystalline silicon film on the substrate surface side is applied by applying a photoresist to the substrate surface and using photolithography and reactive ion etching (RIE) using C ₂ F ₆ and oxygen as an etchant. 9 is formed and the gate electrode 76 is formed, the structure shown in FIG. 9C is obtained.

(Process d)
Next, the etched substrate 71 is sufficiently cleaned and sufficiently cleaned, and then thermally oxidized in a dry oxygen atmosphere at 900 ° C., and the polycrystalline silicon film on the surface of the gate electrode 76 and the polycrystalline silicon film on the back side main surface is formed. Thermal oxide films 77 and 85 are generated.

Next, as illustrated in FIG. 10D, an interlayer insulating film 78 is deposited on the entire front main surface of the substrate 71. As the interlayer insulating film 78, an approximately 1 μm thick SiO ₂ film (NSG) formed by APCVD using silane and oxygen as raw materials, or phosphosilicate glass (PSG) to which phosphorus is added, and further boron is added thereto. Boron phosphosilicate glass (BPSG) is suitable, but is not limited to this. Thereafter, the substrate 71 is placed in a normal diffusion furnace, and a gentle heat treatment is performed for several tens of minutes in an N ₂ atmosphere to increase the density of the interlayer insulating film 78. The heat treatment temperature at this time is appropriately selected within a temperature lower than the formation (thermal oxidation) temperature of the gate insulating film, for example, in the range of 900 ° C. to 1000 ° C.

(Process e)
Next, using known photolithography and dry / wet combined etching means, source window 79a, 79b and gate window (because it is outside the element region, non-existing in the interlayer insulating film 78 and the gate oxide film 75 on the main surface of the substrate 71). Open the display). At this time, the polycrystalline silicon oxide film 85 on the back main surface of the substrate 71 is also removed.

  After the etching is completed, the substrate 71 on which the photoresist mask is attached is sufficiently rinsed with ultrapure water, dried, and immediately contacted on the substrate main surface by a film forming means such as electron beam evaporation or DC magnetron sputtering. When the photoresist is peeled off after that, as shown in FIG. 10E, contact base materials 87a and 87b (not shown at the bottom of the gate window) are provided only at the bottom of the source windows 79a and 79b and the gate window. It becomes the structure that left. For example, Ni or Co having a thickness of 50 nm can be used as the contact base material, but other desired materials may be used.

(Process f)
Next, after sufficiently cleaning and drying the substrate 71, a protective resist material (a photoresist may be used) having a thickness of 1 μm or more is applied to the entire front main surface, and dry etching using CF ₄ and O ₂ is performed. Then, the polycrystalline silicon film 84 on the back main surface is completely removed. Subsequently, the substrate 71 is immersed in a buffered hydrofluoric acid solution, the SiO ₂ film 98 on the back side main surface is removed, and a clean crystal surface is exposed on the back surface of the substrate.

  Then, the substrate 71 with the protective resist material on the front side is sufficiently washed and dried, and then quickly installed in a deposition apparatus maintained at a high vacuum to deposit a desired contact matrix on the back surface of the substrate. To do. As this back side main surface contact base material, for example, a Ni film having a thickness of 50 nm to 150 nm can be used.

When film formation of the contact matrix 89 is completed, the protective resist on the front side is completely removed using a special release agent, and the substrate 71 is sufficiently washed. After the substrate 71 is dried, it is immediately installed in a rapid heat treatment apparatus, and heat treatment (contact annealing) is performed at 1000 ° C. for 2 minutes in a high-purity Ar atmosphere. As shown in FIG. 11 (f), this heat treatment allows contact base materials 87a and 87b (the bottom of the gate window is not shown) of the source window and the gate window, and an n ⁺⁺ type drain region (high concentration) formed on the back surface of the substrate. Impurity layer) The contact base material at the upper part of the substrate 60 undergoes a solid phase reaction with the underlayer to form source electrodes 88a and 88b and drain electrodes 89 as silicide electrodes containing excess carbon, and low resistance ohmic contacts to the source and drain (A gate contact at the bottom of the gate window is also formed at the same time, but not shown here). The formed source electrodes 88a and 88b and the drain electrode 89 both exhibit extremely low contact resistance of 10 ⁻⁶ Ωcm ² or less.

(Process g)
When the contact annealing is completed, the surface precipitation treatment step, carbon diffusion step or carbon concentrated portion removal step ((d) in FIG. 2) and the graphite removal treatment step or the graphite / composite oxide described in the first embodiment are performed. The removal step (FIG. 3E) is similarly performed to remove excess carbon from the source electrodes 88a and 88b and the drain electrode 89, and the source electrodes 80a and 80b and the drain electrode 81 as low-carbon-containing silicide electrodes. To form the structure shown in FIG.

(Process h)
Next, after the substrate 71 is sufficiently cleaned and dried, a front side main surface wiring (front side main surface upper conductor film) material, for example, Al is formed on the entire surface of the front side main surface by DC magnetron sputtering or the like. When this is patterned by a dry etching technique (such as RIE), the photoresist is peeled off, washed and dried, a front main surface wiring 82 as shown in FIG. 12 (h) is completed.

  When inserting a conductor such as Ti, TiN, TaN for the purpose of improving the adhesion, contact resistance, and heat resistance of both conductors between the front-side main surface wiring 82 and the source electrodes 80a, 80b, The surface side wiring film material is formed after these materials are formed first. When the surface side wiring film material is Al, these materials can be continuously patterned with the same etchant gas as Al.

(Process i)
Finally, a back main surface wiring (back main surface upper conductor film) material used for die bonding mounting or the like is applied to the entire back main surface (on the drain electrode 81) of the substrate 71 using means such as DC magnetron sputtering. When the rear surface side wiring 61 is formed by vapor deposition, a silicon carbide semiconductor device vertical MOSFET having the structure shown in FIG. 8 is completed. An example of the back side main surface wiring material is a Ti / Ni / Ag film in which Ti (50 nm thickness), Ni (100 nm thickness), and Ag (150 nm thickness) are laminated in this order. However, the present invention is of course limited to this. Not a thing.

  Even in the case of the third embodiment in which both the front main surface and the back main surface of the substrate 71 have low-carbon silicide electrodes, the source electrodes 80a and 80b as the silicide electrodes and the drain electrode 81 are amounts that cause separation. Since the excess carbon is removed, graphite does not precipitate inside the silicide electrode or at the silicide electrode / upper conductor film interface after the device is completed. Therefore, the defect that the upper conductor film, that is, the source electrode and the drain electrode is peeled off does not occur. That is, it can be said that the third embodiment of the present invention solves the problem that “the upper conductor film is suddenly peeled off to lower the yield of the device and cause a failure after the device is completed”.

  The silicide electrodes 80a, 80b, 81 that do not contain an excessive amount of carbon that causes separation are formed in the source electrode and the drain in the manufacturing method step (step g) of the third embodiment. This is because a process for forcibly depositing excess carbon in the electrode as graphite on the surface and removing graphite deposited on the surface is provided.

Based on the third embodiment, ²⁰⁰ power MOSFETs having an element region area of about 0.25 × 0.25 mm ² were manufactured, and a temperature cycle test was conducted. A large number caused peeling on the front side wiring or the back side wiring, and the defect rate was 95% or more, whereas in the element according to the present invention, no peeling occurred.

It is principal part sectional drawing of the silicon carbide semiconductor device in the 1st Embodiment of this invention. It is a manufacturing process figure explaining the manufacturing method of the silicon carbide semiconductor device in the 1st Embodiment of this invention. It is a continuation of FIG. It is principal part sectional drawing of the silicon carbide semiconductor device in the 2nd Embodiment of this invention. It is a manufacturing process figure explaining the manufacturing method of the silicon carbide semiconductor device in the 2nd Embodiment of this invention. It is a continuation of FIG. FIG. 7 is a continuation of FIG. It is principal part sectional drawing of the silicon carbide semiconductor device in the 3rd Embodiment of this invention. It is a manufacturing process figure explaining the manufacturing method of the silicon carbide semiconductor device in the 3rd Embodiment of this invention. It is a continuation of FIG. It is a continuation of FIG. It is a continuation of FIG. It is principal part sectional drawing of the ohmic contact which is manufactured by the prior art and has the cause of a defect inherent. It is the elemental analysis result of the silicide electrode after a contact annealing process. FIG. 4 is an elemental analysis result 3 of the silicide electrode after the carbon diffusion step or the carbon concentrated portion removal step. It is the elemental analysis result of the silicide electrode after a graphite and complex oxide removal process. It is the surface enlarged view of (c) of FIG.

Explanation of symbols

1: n-type SiC substrate, 3: upper conductor film, 4: n ⁻ type epitaxial layer, 5: field insulating film, 6: opening, 7: Schottky electrode, 8: front side main surface wiring, 9 _a1 , 9 _a2 , 9 _a3 ,... 9 _an : p-type electric field relaxation region, 13: thermal oxide film, 19: photoresist pattern, 20: photoresist, 21: Schottky electrode material, 41: silicide electrode, 42: electrode-conductor surface 43: Inside of silicide, 44: Graphite, 50: Contact base material, 51: Silicide electrode, 52: Silicide electrode with low carbon content, 53: Graphite, 54: Graphite layer, 60: n ⁺⁺ type drain region, 61: Main back side surface wiring, 70: element region, 71: ^{n +} -type SiC substrate, 72: n ^- -type epitaxial layer, 73: n-type epitaxial layer, 73a, 73b: p-type base Source region, 74a, 74b: ^{n +} -type source region, 75: gate oxide film, 75a, 75b: ^{p +} -type base region, 76: gate electrode, 77: polycrystalline silicon oxide film, 78: interlayer insulating film, 79a, 79b: Source window, 80a, 80b: Source electrode, 81: Drain electrode, 82: Front side main surface wiring, 84: Polycrystalline silicon film, 85: Polycrystalline silicon oxide film, 97: Thermal oxide film, 87a, 87b: Contact Base material, 88a, 88b: source electrode, 89: drain electrode, 98: thermal oxide film, 100: field insulating film.

Claims (35)

In a silicon carbide semiconductor device having a silicide electrode formed by depositing a contact base material on a silicon carbide substrate and causing a solid phase reaction with the silicon carbide substrate, and an upper conductor film deposited on the silicide electrode,
The silicon carbide semiconductor device, wherein the silicide electrode is a low carbon content silicide electrode containing a smaller amount of carbon than the amount of silicon in terms of moles.   2. The silicon carbide semiconductor device according to claim 1, wherein the carbon content of the low-carbon silicide electrode is expressed by the number of moles and is 1/5 or less of the silicon content of the electrode.   The silicon carbide semiconductor device according to claim 1, wherein the low-carbon silicide electrode has a thickness of 20 nm to 500 nm.   The Schottky electrode in contact with the main surface opposite to the main surface on which the low-carbon silicide electrode is formed functions as a vertical Schottky diode. 3. The silicon carbide semiconductor device according to 3.   4. The silicon carbide according to claim 1, wherein the silicon carbide has a source electrode and a drain electrode composed of the low-carbon silicide electrode and functions as a vertical metal-oxide-semiconductor field effect transistor. Semiconductor device. A silicon carbide semiconductor device manufacturing method for manufacturing the silicon carbide semiconductor device according to claim 1,
Depositing a contact matrix on a silicon carbide substrate;
A contact annealing step which is a step of heating a silicon carbide substrate on which the contact base material is deposited and forming a silicide electrode by a solid phase reaction between the contact base material and the silicon carbide substrate;
A surface deposition step which is a step of depositing at least part of the carbon generated by the contact annealing step on the surface of the silicide electrode;
A precipitated carbon removing step that is a step of removing precipitated carbon that is carbon deposited on the surface of the silicide electrode by the surface precipitation step;
And a step of depositing an upper conductor film on the surface of the silicide electrode that has become a low-carbon silicide electrode by the surface deposition step after the deposited carbon removing step. Method.   The method for manufacturing a silicon carbide semiconductor device according to claim 6, wherein a thickness of the contact base material is 15 nm or more and 250 nm or less.   The method for manufacturing a silicon carbide semiconductor device according to claim 6, wherein the surface deposition step is performed in a non-oxidizing gas atmosphere at a temperature of 100 ° C. or higher and 600 ° C. or lower.   9. The method for manufacturing a silicon carbide semiconductor device according to claim 8, wherein the surface deposition step is performed in a non-oxidizing gas atmosphere to which hydrogen or helium is added.   The method for manufacturing a silicon carbide semiconductor device according to claim 8, wherein the surface deposition step is performed by intermittently raising and lowering a processing temperature.   The method for manufacturing a silicon carbide semiconductor device according to claim 8, wherein the surface deposition step is performed while applying ultrasonic vibration to the silicon carbide substrate.   The method for manufacturing a silicon carbide semiconductor device according to claim 6, wherein the precipitated carbon removal step is performed by mechanically scraping the precipitated carbon with a fiber assembly moistened with a liquid.   The method for manufacturing a silicon carbide semiconductor device according to claim 6, wherein the precipitated carbon removal step is performed by removing the precipitated carbon with a chemical solution.   The chemical solution for removing the deposited carbon is one selected from an ammonium fluoride aqueous solution, a buffered hydrofluoric acid solution, a nitric acid-added phosphoric acid-acetic acid mixed solution, aqua regia, and a photoresist stripping solution. Item 14. A method for manufacturing a silicon carbide semiconductor device according to Item 13.   The method for manufacturing a silicon carbide semiconductor device according to claim 6, wherein the deposited carbon removal step is performed by oxidizing and removing the deposited carbon with active oxygen in a gas phase.   The method for manufacturing a silicon carbide semiconductor device according to claim 6, wherein the contact annealing step and the surface deposition step are continuously performed in one heat treatment apparatus. A silicon carbide semiconductor device manufacturing method for manufacturing the silicon carbide semiconductor device according to claim 4,
A process of covering both main surfaces of the silicon carbide substrate with a thermal oxide film;
Removing at least a portion of the thermal oxide film on the backside main surface of the silicon carbide substrate to expose the backside main surface of the silicon carbide substrate;
Depositing a contact matrix on the exposed backside main surface;
A contact annealing step which is a step of heating a silicon carbide substrate on which the contact base material is deposited and forming a silicide electrode by a solid phase reaction between the contact base material and the silicon carbide substrate;
A surface deposition step which is a step of depositing at least part of the carbon generated by the contact annealing step on the surface of the silicide electrode;
A precipitated carbon removing step that is a step of removing precipitated carbon that is carbon deposited on the surface of the silicide electrode by the surface precipitation step;
A step of depositing an upper conductor film on the surface of the silicide electrode which has become a low carbon content silicide electrode by the surface deposition step after the deposited carbon removing step;
After the surface deposition step,
Removing at least a portion of the thermal oxide film on the front main surface of the silicon carbide substrate to expose the front main surface of the silicon carbide substrate;
Forming a Schottky electrode on the exposed front-side main surface. A method for manufacturing a silicon carbide semiconductor device, comprising: A silicon carbide semiconductor device manufacturing method for manufacturing the silicon carbide semiconductor device according to claim 5,
The front main surface of the silicon carbide substrate is sequentially subjected to selective impurity ion implantation to obtain a precursor region of an n ⁺ type source region, a precursor region of a p type base region, and a precursor region of a p ⁺ type base region Forming a step;
Activating the precursor region by heat treatment to form an n ⁺ type source region, a p type base region, and a p ⁺ type base region;
Coating the front and back main surfaces of the silicon carbide substrate in which each region is formed with a thermal oxide film;
The n ⁺ -type the thermal oxide film and the source region upper p ⁺ -type base region each removing at least a portion of the upper portion of the thermal oxide layer to expose the n ⁺ -type source regions and the p ⁺ -type base region, Depositing a contact matrix on the exposed n ⁺ -type source region and p ⁺ -type base region;
At least a portion of the thermal oxide film on the backside main surface of the silicon carbide substrate is removed to expose the backside main surface of the silicon carbide substrate, and a contact base material is deposited on the exposed backside main surface of the silicon carbide substrate. Process,
The n ⁺ -type source region, which is a silicide electrode, by heating the silicon carbide substrate having the contact base material deposited on both the front and back main surfaces, and solid-phase reaction between the contact base material and the silicon carbide substrate And a contact annealing step, which is a step of forming a source electrode in contact with the p ⁺ type base region and a drain electrode in contact with the back main surface of the silicon carbide substrate,
A surface deposition step which is a step of depositing at least part of the carbon generated by the contact annealing step on the surface of the silicide electrode;
A precipitated carbon removing step that is a step of removing precipitated carbon that is carbon deposited on the surface of the silicide electrode by the surface precipitation step;
A step of depositing an upper conductor film on each of the surface of the source electrode and the surface of the drain electrode, which has become a low-carbon silicide electrode by the surface deposition step, after the deposited carbon removing step. A method for manufacturing a silicon carbide semiconductor device. A junction of a transition metal silicide and a metal film in a silicon carbide semiconductor device,
The carbon concentration in the transition metal silicide decreases along the direction away from the silicon carbide substrate, or the carbon atom concentration in the portion of the transition metal silicide in contact with the metal film is 30 at% or less. A joined body of a transition metal silicide and a metal film in a silicon carbide semiconductor device. A method of manufacturing a joined body of a transition metal silicide and a metal film in a silicon carbide semiconductor device,
Depositing a transition metal contact matrix on a silicon carbide substrate;
A contact annealing step which is a step of heating a silicon carbide substrate on which the contact base material is deposited and forming a silicide electrode which is a transition metal silicide by a solid phase reaction between the contact base material and the silicon carbide substrate;
A carbon diffusion step, which is a step of modifying the carbon concentration profile in the silicide electrode into a form in which the carbon concentration decreases along a direction away from the silicon carbide substrate;
Removing the graphite and the composite oxide on the surface of the silicide electrode;
And a step of depositing an upper conductor film on the surface of the silicide electrode. A method of manufacturing a joined body of a transition metal silicide and a metal film in a silicon carbide semiconductor device. A method of manufacturing a joined body of a transition metal silicide and a metal film in a silicon carbide semiconductor device,
Depositing a transition metal contact matrix on a silicon carbide substrate;
A contact annealing step which is a step of heating a silicon carbide substrate on which the contact base material is deposited and forming a silicide electrode which is a transition metal silicide by a solid phase reaction between the contact base material and the silicon carbide substrate;
A carbon enriched portion removing step which is a step of removing a carbon concentration maximum region existing between the silicide electrode surfaces from the silicon carbide substrate;
Removing the graphite and the composite oxide on the surface of the silicide electrode;
And a step of depositing an upper conductor film on the surface of the silicide electrode. A method of manufacturing a joined body of a transition metal silicide and a metal film in a silicon carbide semiconductor device.   The carbon diffusion step or the carbon enriched portion removing step is performed by heating the silicon carbide substrate to 100 ° C. or higher and 600 ° C. or lower in an oxygen-containing atmosphere. Of manufacturing a joined body of a transition metal silicide and a metal film in the silicon carbide semiconductor device of FIG.   The carbon diffusion step or the carbon enriched portion removing step is performed by heating the silicon carbide substrate to 100 ° C. or more and 600 ° C. or less in plasma containing oxygen gas. A method for producing a joined body of a transition metal silicide and a metal film in the silicon carbide semiconductor device according to claim 1.   The atmosphere when performing the carbon diffusion step or the carbon enriched portion removing step includes any one of oxygen gas, hydrogen gas, and fluorine gas. A method for producing a joined body of a transition metal silicide and a metal film in the silicon carbide semiconductor device described above.   25. The transition metal in a silicon carbide semiconductor device according to claim 20, wherein the step of removing the graphite and the composite oxide on the surface of the silicide electrode is performed by removing with a chemical solution. A method of manufacturing a bonded body of a silicide and a metal film.   26. The method for producing a joined body of a transition metal silicide and a metal film in a silicon carbide semiconductor device according to claim 25, wherein the chemical solution is a buffered hydrofluoric acid solution or an ammonium fluoride aqueous solution.   27. The transition metal silicide in a silicon carbide semiconductor device according to claim 25 or 26, wherein the step of removing graphite and composite oxide on the surface of the silicide electrode is performed while applying ultrasonic vibration. A method for producing a joined body with a metal film.   28. The silicon carbide semiconductor according to claim 25, 26, or 27, wherein the step of removing graphite and composite oxide on the surface of the silicide electrode is performed while applying mechanical friction to the surface of the silicide electrode. A method of manufacturing a joined body of a transition metal silicide and a metal film in an apparatus.   25. The silicon carbide semiconductor device according to claim 20, wherein the step of removing the graphite and the composite oxide on the surface of the silicide electrode is performed by etching using a halogen-based gas. Of manufacturing a bonded body of transition metal silicide and metal film.   30. The method of manufacturing a joined body of a transition metal silicide and a metal film in a silicon carbide semiconductor device according to claim 29, wherein the halogen-based gas is a gas forming a fluorocarbon polymer.   31. The method of manufacturing a joined body of a transition metal silicide and a metal film in a silicon carbide semiconductor device according to claim 29, wherein the halogen-based gas is a gas containing hydrogen fluoride. A method for manufacturing a silicon carbide semiconductor device, comprising:
A process of covering both main surfaces of the silicon carbide substrate with a thermal oxide film;
Removing at least a portion of the thermal oxide film on the backside main surface of the silicon carbide substrate to expose the backside main surface of the silicon carbide substrate;
Depositing a contact matrix on the exposed backside main surface;
A contact annealing step which is a step of heating a silicon carbide substrate on which the contact base material is deposited and forming a silicide electrode by a solid phase reaction between the contact base material and the silicon carbide substrate;
A carbon diffusion step, which is a step of modifying the carbon concentration profile in the silicide electrode into a form in which the carbon concentration decreases along a direction away from the silicon carbide substrate;
Removing the graphite and the composite oxide on the surface of the silicide electrode;
After the carbon diffusion step, and having a step of depositing an upper conductor film on the silicide electrode surface that is a low carbon content silicide electrode,
After the carbon diffusion step,
Removing at least a portion of the thermal oxide film on the front main surface of the silicon carbide substrate to expose the front main surface of the silicon carbide substrate;
Forming a Schottky electrode on the exposed front-side main surface. A method for manufacturing a silicon carbide semiconductor device, comprising: A method for manufacturing a silicon carbide semiconductor device, comprising:
A process of covering both main surfaces of the silicon carbide substrate with a thermal oxide film;
Removing at least a portion of the thermal oxide film on the backside main surface of the silicon carbide substrate to expose the backside main surface of the silicon carbide substrate;
Depositing a contact matrix on the exposed backside main surface;
A contact annealing step which is a step of heating a silicon carbide substrate on which the contact base material is deposited and forming a silicide electrode by a solid phase reaction between the contact base material and the silicon carbide substrate;
A carbon enriched portion removing step which is a step of removing a carbon concentration maximum region existing between the silicide electrode surfaces from the silicon carbide substrate;
Removing the graphite and the composite oxide on the surface of the silicide electrode;
And a step of depositing an upper conductor film on the surface of the silicide electrode which is a low carbon content silicide electrode after the carbon enriched portion removing step,
After the carbon enrichment removal step,
Removing at least a portion of the thermal oxide film on the front main surface of the silicon carbide substrate to expose the front main surface of the silicon carbide substrate;
Forming a Schottky electrode on the exposed front-side main surface. A method for manufacturing a silicon carbide semiconductor device, comprising: A method for manufacturing a silicon carbide semiconductor device, comprising:
The front main surface of the silicon carbide substrate is sequentially subjected to selective impurity ion implantation to obtain a precursor region of an n ⁺ type source region, a precursor region of a p type base region, and a precursor region of a p ⁺ type base region Forming a step;
Activating the precursor region by heat treatment to form an n ⁺ type source region, a p type base region, and a p ⁺ type base region;
Coating the front and back main surfaces of the silicon carbide substrate in which each region is formed with a thermal oxide film;
The n ⁺ -type the thermal oxide film and the source region upper p ⁺ -type base region each removing at least a portion of the upper portion of the thermal oxide layer to expose the n ⁺ -type source regions and the p ⁺ -type base region, Depositing a contact matrix on the exposed n ⁺ -type source region and p ⁺ -type base region;
At least a portion of the thermal oxide film on the backside main surface of the silicon carbide substrate is removed to expose the backside main surface of the silicon carbide substrate, and a contact base material is deposited on the exposed backside main surface of the silicon carbide substrate. Process,
The n ⁺ -type source region, which is a silicide electrode, by heating the silicon carbide substrate having the contact base material deposited on both the front and back main surfaces, and solid-phase reaction between the contact base material and the silicon carbide substrate And a contact annealing step, which is a step of forming a source electrode in contact with the p ⁺ type base region and a drain electrode in contact with the back main surface of the silicon carbide substrate,
A carbon diffusion step, which is a step of modifying the carbon concentration profile in the silicide electrode into a form in which the carbon concentration decreases along a direction away from the silicon carbide substrate;
Removing the graphite and the composite oxide on the surface of the silicide electrode;
And a step of depositing an upper conductor film on each of the surface of the source electrode and the surface of the drain electrode which are low-carbon silicide electrodes after the carbon diffusion step. Manufacturing method. A method for manufacturing a silicon carbide semiconductor device, comprising:
The front main surface of the silicon carbide substrate is sequentially subjected to selective impurity ion implantation to obtain a precursor region of an n ⁺ type source region, a precursor region of a p type base region, and a precursor region of a p ⁺ type base region Forming a step;
Activating the precursor region by heat treatment to form an n ⁺ type source region, a p type base region, and a p ⁺ type base region;
Coating the front and back main surfaces of the silicon carbide substrate in which each region is formed with a thermal oxide film;
The n ⁺ -type the thermal oxide film and the source region upper p ⁺ -type base region each removing at least a portion of the upper portion of the thermal oxide layer to expose the n ⁺ -type source regions and the p ⁺ -type base region, Depositing a contact matrix on the exposed n ⁺ -type source region and p ⁺ -type base region;
At least a portion of the thermal oxide film on the backside main surface of the silicon carbide substrate is removed to expose the backside main surface of the silicon carbide substrate, and a contact base material is deposited on the exposed backside main surface of the silicon carbide substrate. Process,
The n ⁺ -type source region, which is a silicide electrode, by heating the silicon carbide substrate having the contact base material deposited on both the front and back main surfaces, and solid-phase reaction between the contact base material and the silicon carbide substrate And a contact annealing step, which is a step of forming a source electrode in contact with the p ⁺ type base region and a drain electrode in contact with the back main surface of the silicon carbide substrate,
A carbon enriched portion removing step which is a step of removing a carbon concentration maximum region existing between the silicide electrode surfaces from the silicon carbide substrate;
Removing the graphite and the composite oxide on the surface of the silicide electrode;
And after the carbon enriched portion removing step, a step of depositing an upper conductor film on each of the surface of the source electrode and the surface of the drain electrode which are low-carbon silicide electrodes. A method for manufacturing a silicon semiconductor device.

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