JP2007180862A - Image encoding device and image coding method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image encoding device or the like which is capable of fast encoding by reducing the number of cycles required for processing without causing the degradation of image quality. <P>SOLUTION: A quantization part 230 quantizes a conversion factor in each orthogonal conversion block in accordance with a quantization parameter. An inverse quantization part 240 restores orthogonal conversion blocks from conversion factors obtained by inverse conversion of orthogonal conversion factors quantized in accordance with the quantization parameter. The inverse quantization of orthogonal conversion factors is processed in parallel (for example, by double parallel processing or quadruple parallel processing). An inverse orthogonal conversion part 250 uses restored orthogonal conversion blocks to restore a difference macro block. When restoring the difference macro block, the inverse orthogonal conversion part 250 preferentially execute inverse orthogonal conversion operation of pixels in the rightmost column of each 4×4 block constituting the difference macro block, which are used in intraprediction of a right adjacent 4×4 block, by an instruction of a general control part 260. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to MPEG series and H.264. More particularly, the present invention relates to a technology for improving the efficiency of image coding processing using intra prediction.

  As a compression technique for digital images (including digital moving images, hereinafter simply referred to as “images”), H.P. H.264 / AVC (ITU-T Recommendation H.264 and ISO / IEC 14496-10 Advanced Video Coding) is standardized. H. H.264 / AVC (hereinafter abbreviated as “H.264”) image coding and decoding methods are nearly twice as high as conventional MPEG2 (ISO / IEC 133818-2). However, since a large amount of calculation is required, application to an angle of view with a small number of pixels is common.

  FIG. 2 is an example of a block diagram illustrating a functional configuration of a conventional image encoding device 400 based on H.264. As illustrated in FIG. 6, the image encoding device 400 includes a block dividing unit 10, a difference processing unit 15, an orthogonal transform unit 20, a quantization unit 30, an encoding unit 130, an accumulation buffer 140, an inverse quantization unit 40, and an inverse unit. Orthogonal transformation unit 50, addition processing unit 55, deblocking filter 60, frame memories 70 and 71, motion estimation unit 80, intra estimation unit 90, mode selection unit 100, mode switch 105, intra prediction unit 110, motion compensation unit 120, rate A control unit 150 and an overall control unit 460 are provided.

  In general, each picture of the input image 11 is divided into unit blocks composed of a predetermined number of pixels, and encoding is performed in this unit. This unit block is called a macro block, and is composed of one luminance signal (Y signal) block composed of 16 pixels × 16 lines (hereinafter referred to as “16 × 16 pixels”) and 8 pixels spatially corresponding thereto. It is composed of two color difference signal (Cr signal and Cb signal) blocks of × 8 lines (hereinafter referred to as “8 × 8 pixels”).

  Upon receipt of the input image 11, the block dividing unit 10 divides each picture into macro blocks (hereinafter referred to as “input macro blocks”), and outputs them to the difference processing unit 15.

  The difference processing unit 15 spatially corresponds to each pixel of the input macroblock of the macroblock generated by the intra prediction unit 110 or the motion compensation unit 120 (hereinafter referred to as “prediction macroblock”). Difference processing is performed between each pixel (hereinafter referred to as “difference macroblock”), and the difference macroblock is output to the orthogonal transform unit 20.

  The orthogonal transform unit 20 performs orthogonal transform processing on the difference macroblock acquired from the difference processing unit 15 to transform the pixel region representation into the frequency region representation in units of orthogonal transform blocks. In this case, the orthogonal transformation processing may be performed by pipeline processing such as 2-parallel or 4-parallel. The size of the orthogonal transform block is 8 × 8 pixels in the conventional MPEG system. In H.264, 4 pixels × 4 lines (hereinafter referred to as “4 × 4 pixels”) or 8 × 8 pixels.

  The orthogonal transform unit 20 configures an orthogonal transform block that collects only the DC components of each orthogonal transform block of 4 × 4 pixels for each signal component, and further performs orthogonal transform. Each transform coefficient in the orthogonal transform block is output to the quantization unit 30.

  The quantization unit 30 quantizes the transform coefficient in each orthogonal transform block according to the quantization parameter acquired from the rate control unit 150 and outputs the quantized coefficient to the encoding unit 130. The quantized transform coefficient (hereinafter referred to as “orthogonal transform coefficient”) is supplied to the encoding unit 130 and simultaneously to the inverse quantization unit 40.

  The encoding unit 130 receives the quantized transform coefficient from the quantization unit 30 and performs encoding. H. An encoding unit 130 compliant with H.264 performs encoding using CAVLC (Context-based Adaptive Variable Length Coding) or CABAC (Context-based Adaptive Binary Arithmetic Coding) using variable length coding. The encoded image signal is stored in the storage buffer 140.

  The inverse quantization unit 40 restores the orthogonal transform block from the transform coefficient obtained by inverse quantization of the orthogonal transform coefficient quantized according to the quantization parameter acquired from the rate control unit 150.

  The inverse orthogonal transform unit 50 reconstructs the differential macroblock using the reconstructed orthogonal transform block. The restored difference macroblock is input to the addition processing unit 55 together with the predicted macroblock.

  The addition processing unit 55 performs addition processing on each pixel of the restored difference macroblock and prediction macroblock to generate a reproduction macroblock. This reproduced macroblock is transmitted to the deblocking filter 60 and further stored in the frame memory 70 for use in prediction processing.

  Note that the deblocking filter 60 removes block distortion included in a decoded image composed of reproduced macroblocks. The decoded image from which block distortion has been removed is stored in the frame memory 71.

  Next, a prediction method and a prediction type for generating the prediction macroblock will be described.

  There are roughly two types of prediction methods, which are called intra prediction (also referred to as “intra-screen prediction”) and motion compensation prediction (also referred to as “motion-compensated interframe prediction” or “inter prediction”), respectively. Below, the outline | summary of intra prediction is demonstrated.

  H. H.264 intra prediction is a method of predicting pixels in a macroblock using encoded pixels in a frame of a decoded image, and there are two types of prediction. The two types of prediction are distinguished by the block size (4 × 4 pixels or 16 × 16 pixels) at the time of performing intra prediction, and “intra 4 × 4 prediction” and “intra 16 × 16 prediction”, respectively. being called.

  In intra prediction, prediction is performed by using pixels of neighboring blocks in units of blocks composed of the above 4 × 4 pixels or 16 × 16 pixels.

  FIG. 7A shows an encoding target pixel (16 pixels from pixel a to pixel p) predicted by intra 4 × 4 prediction and an encoded adjacent pixel (13 pixels from A to M) used for intra prediction. It is a figure which shows arrangement | positioning. Here, the encoding target pixel is a pixel in the encoding target macroblock output from the block dividing unit 10. On the other hand, the encoded adjacent pixel is a pixel read from the frame memory 70 as a decoded or restored macroblock or block pixel.

  7B to 7J are diagrams showing the prediction direction in intra 4 × 4 prediction. Based on the encoded pixel values of adjacent pixels, H. The target pixel is calculated by an arithmetic expression defined in H.264. Here, the prediction direction at this time is indicated by a prediction mode number (prediction mode 0 to prediction mode 8). The prediction direction of prediction mode 0 in FIG. 7B is vertically downward, and that of prediction mode 1 in FIG. 7C. The prediction direction is horizontal, the prediction in prediction mode 2 in FIG. 7D is DC (average), the prediction direction in prediction mode 3 in FIG. 7E is diagonally lower left, and the prediction direction in prediction mode 4 in FIG. Is diagonally lower right, the prediction direction of prediction mode 5 in FIG. 7G is vertically right, the prediction direction of prediction mode 6 in FIG. 7H is horizontally downward, and the prediction direction of prediction mode 7 in FIG. Indicates the vertical left direction, and the prediction direction of the prediction mode in FIG.

  The intra 4 × 4 prediction is applied to prediction of a luminance signal. For example, in the case of the prediction mode 0, the prediction image is generated by performing the vertical downward prediction using the decoded pixel data adjacent to the upper side of the 4 × 4 pixel block of the prediction target pixel. This prediction mode 0 is an effective prediction mode when there are vertical edges and boundaries in the image area to be predicted. Similarly, prediction modes other than mode 0 are also effective prediction modes for edges and boundaries in a specific direction, and a part of intra prediction processing is performed using decoded pixels of adjacent blocks.

  As described above, in the intra prediction, since the prediction process is performed using the calculation result for the surrounding blocks, it is necessary to complete the inverse orthogonal transform process for the surrounding blocks. If the inverse orthogonal transform processing of the peripheral blocks is not completed, the processing is performed after the processing is completed, and processing delay occurs.

  FIG. 8 is a diagram for explaining the order of intra prediction in orthogonal transform blocks constituting a macroblock. As shown in FIG. 8, when performing intra prediction in units of 4 × 4 blocks, processing is performed in the order of “block 0”, “block 1”, “block 2”,... “Block 15”. Become. Here, in order to perform intra prediction of block 1, peripherals necessary for processing of block 1 are not performed until intra prediction processing, orthogonal transformation processing, quantization processing, inverse quantization processing, and inverse orthogonal transformation processing are performed on block 0. Block information (in this case, each block information on the upper level of block 1 has been processed) is obtained. That is, while orthogonal transformation processing, quantization processing, inverse quantization processing, and inverse orthogonal transformation processing are being performed on block 0, intra prediction of block 1 cannot be performed, and processing wait occurs. In the case of the block 4, since the processing has already been completed for the block 1 necessary for the intra prediction, the processing can be continued after the processing of the block 3.

  Thus, in intra prediction, there are places that can be processed continuously by processing blocks and places that cannot be processed. Therefore, if this order is well devised, the number of places where continuous processing can be performed increases, pipeline processing can be executed efficiently, and processing time can be shortened.

In Patent Document 1, there is a proposal for shortening the pipeline processing time by efficiently changing the processing order of intra prediction in this way.
JP 2004-140473 A

Here, H. The relationship between the processing time required for the H.264 processing and the processing amount will be examined. For example, a high-definition video (1920 × 1088 pixels) is converted to H.264. In the case of compression encoding with H.264, the number of processes per macroblock (hereinafter also referred to as “MB”) expressed in units of 16 × 16 pixels is as follows:
(1920 × 1088) ÷ (16 × 16) = 8,160MB (1)
If the frame rate is 30 frames per second,
8,160 × 30fps = 244,800MB / sec (2)
It becomes.

This is because if the operating frequency of the CPU is 100 MHz, the number of cycles that can be spent for compression encoding of one macroblock is:
100MHz ÷ 244,800 = 408 cycles (3)
It becomes.

  Here, considering the processing cycle in the case of performing orthogonal transform processing in units of 4 × 4 pixels, the number of cycles required for two-dimensional orthogonal transform processing is simply four rows in the horizontal direction and vertical, assuming that four pixels are processed simultaneously. It requires 4 columns in the direction and requires about 4 + 4 = 8 cycles. Since one macro block performs 16 orthogonal transform operations, 16 × 8 = 128 cycles, and 128 + 128 = 256 cycles are consumed for the orthogonal transform processing when considering the inverse orthogonal transform processing.

  Furthermore, when considering the quantization process and the inverse quantization process, the above 408 cycles will be exceeded, and the encoding process cannot be realized as it is.

  In this way, H.264 requires enormous processing operations. According to H.264, compression encoding of a large amount of data such as a high-definition image is difficult to realize simply by processing. For this reason, it is necessary to improve processing efficiency by devising a calculation algorithm, increasing the parallel degree of calculation, or increasing the frequency.

  For example, as shown in FIG. 9, orthogonal transform processing and inverse orthogonal transform processing are generally performed in units of rows or columns (that is, units of 4 pixels or units of 8 pixels), but quantization processing is performed in units of pixels. Therefore, it is necessary to provide a buffer between the blocks to absorb the difference in processing time.

  FIG. 10A is an equation representing an orthogonal transformation operation in H264. FIG. 10B is an expression representing the inverse orthogonal transform operation in H264.

  FIG. 11A is a diagram illustrating a state of matrix operation in the row direction and the column direction in the orthogonal transform operation, and FIG. 12A is a diagram illustrating a state in which this orthogonal transform operation is realized by butterfly operation. .

  FIG. 11B is a diagram showing the state of the matrix operation in the row direction and the column direction in the inverse orthogonal transform operation. FIG. 12B shows how the inverse orthogonal transform operation is realized by the butterfly operation. FIG.

  As shown in FIGS. 11A and 11B, in the conventional butterfly operation, the calculation order in the row direction and the column direction is in ascending order (that is, i = 0..3, j = 0... 3).

  The intra prediction shown in the above-mentioned Patent Document 1 is a method for improving the efficiency of the processing, and realizes the efficiency of the pipeline processing by changing the order of the intra processing. Instead of processing order, the blocks are processed in the order of shortening the processing waiting time.

  Therefore, in the above method, only the intra prediction process is optimized to reduce the time required for the pipeline process, and the orthogonal transform process and the quantization process other than the intra prediction process are not considered.

  Furthermore, in order to speed up the pipeline processing, the peripheral macroblocks to be referred to are partially substituted with different macroblock information, or are processed as those that cannot be referred to.

  The present invention has been made in view of the above problems. An object of the present invention is to provide an image encoding apparatus and the like that can reduce the number of cycles required for processing without causing deterioration in image quality and can perform high-speed encoding in an encoding method such as H.264.

  In order to solve the above-described problem, an image encoding device according to the present invention includes a first process and a second process that can be performed on pixel data in units of rows or columns, and includes a predetermined number of processes. An image encoding apparatus that encodes a picture to be encoded for each unit block composed of pixels, wherein the operation is performed with priority on pixel-unit or column-unit pixel data used in the second process. 1 processing means, and second processing means for starting the second processing upon completion of the operation on the pixel data in units of rows or columns necessary for starting the second processing in the first processing. And

  As a result, H.C. In an encoding method such as H.264, it is possible to provide an image encoding device or the like that can reduce the number of cycles required for processing without causing image quality degradation and can perform high-speed encoding.

  The first processing means preferentially executes a part of the inverse orthogonal transform operation in the inverse orthogonal transform process on the pixel data of the rightmost column in the first unit block used in the intra prediction process, The second processing means uses the pixel data of the right end column unit in the first unit block after the inverse orthogonal transform operation, and uses the pixel data of the second unit block adjacent to the right of the first unit block. Intra prediction processing is started.

  Further, the first processing means reverses the column unit in the first unit block so that the pixel data in the row unit in the first unit block used in the inverse orthogonal transform process is preferentially calculated. The quantization processing is executed with a parallelism degree N that represents parallel processing in units of N pixels adjacent to the left and right, and the second processing means is configured to perform the row unit after the inverse quantization processing in the first unit block is finished. Using the pixel data, the execution of the inverse orthogonal transform process for the first unit block is started.

  Further, the second processing means may preferentially execute the inverse orthogonal transform process on the pixel data of the rightmost column unit in the first unit block used in the intra prediction process.

  The image encoding device may further include third processing means for executing a quantization process on the column-unit pixel data in the first unit block with the parallelism N.

  Furthermore, the present invention can be realized as an image encoding method using characteristic constituent means in the image encoding apparatus as steps, or as a program for causing a personal computer or the like to execute these steps. Needless to say, the program can be widely distributed via a recording medium such as a DVD or a transmission medium such as the Internet.

  As described above, the image coding apparatus according to the present invention is necessary for the computation of the subsequent processing block (for example, intra coding processing) in the orthogonal transform processing and the quantization processing by controlling the computation order. Since the minimum data is preferentially calculated, speeding up of parallel calculation is promoted, and the encoding process can be performed more efficiently.

  Hereinafter, embodiments of an image encoding device according to the present invention will be described with reference to the drawings. In the following embodiments, the present invention will be described with reference to the drawings. However, the present invention is not intended to be limited thereto.

  FIG. 1 is a block diagram showing a functional configuration of an image encoding device 200 according to the present embodiment. As shown in FIG. 1, the image coding apparatus 200 includes a block dividing unit 10, a difference processing unit 15, an orthogonal transform unit 20, a quantization unit 230, a coding unit 130, a storage buffer 140, an inverse quantization unit 240, and an inverse unit. Orthogonal transformation unit 250, addition processing unit 55, deblocking filter 60, frame memories 70 and 71, motion estimation unit 80, intra estimation unit 90, mode selection unit 100, mode switch 105, intra prediction unit 110, motion compensation unit 120, rate A control unit 150 and an overall control unit 260 are provided. Note that the same reference numerals are given to the same functional configurations as those of the image encoding device 400 according to the conventional technique, and the description thereof is omitted.

  The quantization unit 230 quantizes the transform coefficient in each orthogonal transform block according to the quantization parameter acquired from the rate control unit 150 and outputs the quantized coefficient to the encoding unit 130. Note that the quantization of the transform coefficient is performed in parallel on the left and right adjacent N pixel units (specifically, two parallel or four parallel, etc. on a plurality of adjacent pixel units) according to an instruction from the overall control unit 260. Pipeline processing). N in this case is referred to as “parallelism”. In the present embodiment, the quantization process is an example of the third process of the present invention, and the quantization unit is an example of the third processing means of the present invention.

  The inverse quantization unit 240 restores the orthogonal transform block from the transform coefficient obtained by inverse quantization of the orthogonal transform coefficient quantized according to the quantization parameter acquired from the rate control unit 150. In addition, in the relationship with the intra prediction process mentioned later or an intra prediction part, the inverse orthogonal transformation process in this Embodiment is an example of the 1st process of this invention, and an inverse orthogonal transformation part is a 1st process means of this invention. It is an example. Further, in the relationship with the quantization process and the quantization unit, the inverse quantization process in the present embodiment is an example of the first process of the present invention, and the inverse quantization unit is the first process of the present invention. It is an example of a means.

  Although details will be described later, since the quantization unit 230 and the inverse quantization unit 240 perform parallel processing in consideration of the processing contents of the subsequent stages, the processing is performed in comparison with the conventional simple parallel processing. It is possible to reduce time (the number of cycles required for processing).

  The inverse orthogonal transform unit 250 restores the differential macroblock using the restored orthogonal transform block. At the time of restoration of the difference macroblock, the inverse orthogonal transform unit 250, according to the instruction of the overall control unit 260, in each 4 × 4 block constituting the difference macroblock, the intra prediction process of the right adjacent 4 × 4 block. First, the inverse orthogonal transform operation of the pixel in the rightmost column, which is the pixel of the column unit used in the above, is executed first. For example, when the inverse orthogonal transform operation in the column direction is executed for 4 × 4 blocks in 4 parallel 8 cycles, the inverse orthogonal transform operation of the pixel in the rightmost column is first performed (as described later, the inverse orthogonal operation in the column direction). By executing the conversion unit in the order of j = 3.0., It is possible to shorten six cycles compared to the conventional case (conventionally, the inverse orthogonal transformation operation of the pixel in the leftmost column is first ( I.e. j = 0..3) in order)). Note that, in relation to the intra prediction process and the intra prediction unit, the inverse orthogonal transform process in the present embodiment is an example of the first process of the present invention, and the inverse orthogonal transform unit is an example of the first processing means of the present invention. It is. Further, in relation to the inverse quantization process and the inverse quantization unit, the inverse orthogonal transform process in the present embodiment is an example of the second process of the present invention, and the inverse orthogonal transform unit is the second process of the present invention. It is an example of a means.

  The intra prediction unit 110 predicts the pixels in the macroblock using the encoded pixels in the frame of the decoded image. For example, in the inverse orthogonal transform process, the intra prediction process is started as soon as the calculation for the pixel data in units of rows necessary for the start of the intra prediction process is completed. In the present embodiment, the intra prediction process is an example of the second process of the present invention, and the intra prediction unit is an example of the second processing means of the present invention.

  The overall control unit 260 is a microcomputer that includes, for example, a RAM and a ROM that stores a control program, and controls the entire image coding apparatus 200. In particular, the overall control unit 260 determines the degree of parallelism in the quantization unit 230 and the inverse quantization unit 240, and the calculation order for restoring the differential macroblock in the inverse orthogonal transform unit 250 (specifically, the column direction (The operation order is set so that j = 3.0).

  FIGS. 2A to 2C are diagrams for explaining a difference in calculation speed depending on the degree of parallelism in the quantization process in the quantization unit 230 and the inverse quantization process in the inverse quantization unit 240 according to the present embodiment. FIG. In general, since the quantization process and the inverse quantization process are pixel-by-pixel processes, one cycle is required to process one pixel when parallel processing is not performed. On the other hand, when 8 × 8 pixels are processed in 2 parallel, 8 × 8 ÷ 2 = 32 cycles, and similarly when 8 × 8 pixels are processed in 4 parallel, 8 × 8 ÷ 4 = 16 cycles are required. To do.

  FIG. 2A shows an example in which a quantization process or an inverse quantization process is performed on an orthogonal transform block composed of 8 × 8 pixels with a parallel degree “1” (that is, no parallel processing is performed).

  In this case, the processing order of the quantization processing is expressed by pixel numbers “00” → “10” →... “70” → “01” →... “02” →. .. Processed in the order of “77”. Thereafter, the inverse quantization process is performed in the same order as the quantization process. In the case of the inverse quantization process, the inverse quantization is performed for all pixels in the uppermost row (eight pixels of pixel numbers “00” to “07”) when the pixel number is finished to “07”. When the process is completed, the inverse orthogonal transform process, which is the next process, can be started. That is, the inverse orthogonal transform process can be started even if the inverse quantization process is not finished for the seven pixels in the shaded portions of the pixel numbers “17” to “77” shown in FIG.

  On the other hand, as shown in FIG. 2B, when the inverse quantization process is performed with the degree of parallelism “2” (that is, two pixels are processed in parallel), when the pixel number reaches “06 & 07” ( When the inverse quantization process is completed for all the pixels in the uppermost row), the inverse orthogonal transform process, which is the next stage process, can be started. That is, the inverse orthogonal transformation process is started even if the inverse quantization process is not finished for the 14 pixels in the shaded portions of the pixel numbers “16” to “76” and “17” to “77” shown in FIG. can do.

  Similarly, as shown in FIG. 2C, when the inverse quantization process is performed with a degree of parallelism of “4” (that is, four pixels are processed in parallel), the pixel number is “04 & 05 & 06 & 07”. The inverse orthogonal transform process, which is the next stage process, can be started. That is, for the 28 pixels in the shaded portions of pixel numbers “14” to “74”, “15” to “75”, “16” to “76”, and “17” to “77” shown in FIG. Can start the inverse orthogonal transform process even if the inverse quantization process is not completed.

  In addition, when the parallel processing is performed between the pixels adjacent to the left and right as described above and the parallel processing is performed between the pixels adjacent to each other in the vertical direction, in the case of “parallel degree 2”, “parallel” In the case of “degree 4”, a difference of 6 cycles occurs. That is, in the case where parallel processing is performed between pixels adjacent to the left and right according to the present invention, the processing in the next stage is earlier in 4 cycles in the case of “parallel degree 2” and 6 cycles in the case of “parallel degree 4”. The inverse orthogonal transform process can be started.

  As described above, when the quantization process and the inverse quantization process (for example, a block of 8 × 8 pixels) in the present embodiment are executed with a parallelism of 2, 32 cycles, Compared to the case of processing in 2 parallels, it is possible to shorten the cycle by 4 cycles. Similarly, in the case of executing at a parallel degree of 4 and 16 cycles, 6 cycles each in comparison with the case of simply processing in 4 parallels. It can be shortened.

  FIGS. 3A and 3B are diagrams illustrating a state of the inverse orthogonal transform process in the inverse orthogonal transform unit 250 according to the present embodiment. As shown in FIG. 3A, when the differential macroblock is restored, the inverse orthogonal transform unit 250 performs an orthogonal transform block of each 4 × 4 pixels constituting the differential macroblock according to an instruction from the overall control unit 260. Performs first the inverse orthogonal transform operation on the pixels in the rightmost column used for intra prediction of the respective orthogonal transform blocks on the right.

  As shown in FIG. 3A, the row direction calculation in the inverse orthogonal transform process in the inverse orthogonal transform unit 250 is performed in units of columns from the top to the bottom (ie, i = 0 .. 3). However, there is no difference in calculation speed even if the operation is performed in units of rows from the bottom to the top (that is, i = 3.0). However, with respect to the column direction calculation in the inverse orthogonal transform process, the calculation is performed in units of columns from left to right (ie, j = 0 .. 3) and from right to left (ie, j = 3.0). ) Results in a difference in calculation speed of 3 cycles. That is, with reference to FIG. 3A, in the case of inverse orthogonal transform processing (orthogonal transform processing is also the same), conventionally, when calculating four pixels in the column direction (and row direction) simultaneously, In the present invention, since the calculation is performed from the right end, the calculation is completed as the first column, and the processing time of (4-1) = 3 cycles can be reduced. Therefore, the column direction calculation in the inverse orthogonal transform process is performed in units of columns from right to left (that is, j = 3.0) (see FIG. 3B).

  FIG. 4 is a flowchart showing an operation flow of the image coding apparatus 200 according to the present embodiment.

  First, the overall control unit 260 sets the calculation order in the column direction in the inverse orthogonal transform unit 250 in descending order (for example, j = 3.0). Furthermore, the overall control unit 260 specifies the degree of parallelism in the quantization unit 230 and the inverse quantization unit 240. In addition, about this parallel degree, you may prescribe | regulate and it is good also as receiving a change from a user.

  Thereafter, after the above settings, the overall control unit 260 performs orthogonal transform processing and quantization processing (S103), inverse quantization processing and (S104), and intra prediction processing (S105) for each macroblock of the encoding target picture. ) Is executed (S102 to S106). In addition, about the macroblock which finished the said orthogonal transformation process and quantization process (S103), an encoding process is performed (S107).

  FIG. 5 is a time chart showing an outline of a calculation cycle of the image coding apparatus 200 according to the present embodiment. FIG. 5 shows orthogonal transform processing, quantization processing, inverse quantization processing, and part of inverse orthogonal transform processing for an 8 × 8 pixel block. In FIG. 5, the orthogonal transform process is performed in parallel using two processors (TA and TB). Similarly, parallel processing using two processors is performed for inverse orthogonal transform processing (ITB and ITA). Further, the orthogonal transform process and the inverse orthogonal transform process are performed for each row (for example, the first row indicated by “h0” is composed of pixel numbers “00” to “07”) and for each column (for example, “v0”). The first column indicated by is composed of pixel numbers “00” to “70”) and processed in two cycles (for example, “cycle 0” and “cycle 1” for “h0” in the orthogonal transformation process). Yes.

  On the other hand, the quantization processing (Q1 and Q2) and the inverse quantization processing (IQ1 and IQ2) in FIG. 5 are executed with two parallelisms using two processors, respectively. Therefore, in the case of FIG. 5, at least six processors are used.

  Further, as shown in FIG. 5, since the inverse quantization process in the first row at the time of “cycle 37” is completed, the inverse orthogonal transform process can be activated in “cycle 38”. It is also shown that there is.

  As described above, according to the image coding apparatus according to the present invention, a part of the processes affecting the subsequent processes are completed quickly, so that it is possible to improve the calculation speed of the entire coding process.

  The present invention is expected to be adopted as a compression method with the spread of digital broadcasting and high-definition movies in the future. With regard to H.264 / AVC, it becomes possible to increase the processing efficiency with a simple configuration, and it will be used in more and more applications in the future.

It is a block diagram which shows the function structure of the image coding apparatus 200 which concerns on this invention. (A)-(c) is a figure for demonstrating the difference of the calculation speed by the parallel degree in the quantization process in this invention, and a dequantization process. (A) is a figure which shows the order of the inverse orthogonal transformation process in the inverse orthogonal transformation part which concerns on this invention. (B) is a figure which shows the mode of the matrix calculation of the inverse orthogonal transformation process in the inverse orthogonal transformation part which concerns on this invention. It is a flowchart which shows the flow of operation | movement of the image coding apparatus which concerns on this invention. It is a time chart which shows the outline | summary of the calculation cycle of the image coding apparatus which concerns on this invention. H. 2 is an example of a block diagram illustrating a functional configuration of a conventional image encoding device compliant with H.264. (A) is a figure which shows arrangement | positioning of the encoding object pixel predicted by intra 4x4 prediction, and the encoding adjacent pixel used for intra prediction. (B)-(j) is a figure which shows the prediction direction of each prediction mode in intra 4x4 prediction. It is a figure for demonstrating the order of the intra prediction in the orthogonal transformation block which comprises a macroblock. It is an example of the block diagram which shows the function structure in which the parallel processing in the conventional image coding apparatus is possible. (A) is an equation representing an orthogonal transformation operation in H264. (B) is an expression representing the inverse orthogonal transform operation in H264. (A) is an expression representing a matrix operation of an orthogonal transform operation in H264. (B) is an expression representing a matrix operation of the inverse orthogonal transform operation in H264. (A) is a figure which shows a mode that orthogonal transformation calculation is implement | achieved by butterfly calculation. (B) is a figure which shows a mode that an inverse orthogonal transformation calculation is implement | achieved by a butterfly calculation.

Explanation of symbols

10 block division unit 11 input image 12 bit stream 15 difference processing unit 20 orthogonal transform unit 30, 230 quantization unit 40, 240 inverse quantization unit 50, 250 inverse orthogonal transform unit 55 addition processing unit 60 deblocking filter 70, 71 frames Memory 80 Motion estimation unit 90 Intra estimation unit 100 Mode selection unit 105 Mode switch 110 Intra prediction unit 120 Motion compensation unit 130 Encoding unit 140 Accumulation buffer 150 Rate control unit 200, 400 Image encoding device 260, 460 Overall control unit

Claims (8)

An image that includes a first process and a second process that can be performed on pixel data in units of rows or columns, and that encodes a picture to be encoded for each unit block that includes a predetermined number of pixels. An encoding device comprising:
First processing means for preferentially executing calculation on pixel data in units of rows or columns used in the second processing;
Image coding comprising: second processing means for starting the second processing upon completion of computation on pixel data in units of rows or columns necessary for starting the second processing in the first processing. apparatus. The first processing means preferentially executes a part of the inverse orthogonal transform operation in the inverse orthogonal transform process on the pixel data of the right end column unit in the first unit block used in the intra prediction process,
The second processing means uses the pixel data of the right end column unit in the first unit block after the inverse orthogonal transform operation, and uses the pixel data of the second unit block adjacent to the right of the first unit block. The image predicting apparatus according to claim 1, wherein an intra prediction process is started for. The first processing means uses inverse quantization in units of columns in the first unit block so that pixel data in units of rows in the first unit block used in inverse orthogonal transform processing is preferentially calculated. The processing is executed with a parallelism N representing parallel processing in units of N pixels adjacent to the left and right,
The second processing means starts execution of an inverse orthogonal transform process for the first unit block using pixel data in units of rows after the inverse quantization process in the first unit block is completed. The image encoding device according to claim 1. The second processing means further includes
The image coding apparatus according to claim 3, wherein the inverse orthogonal transform process is preferentially performed on pixel data of a rightmost column unit in the first unit block used in the intra prediction process. The image encoding device further includes:
The image coding apparatus according to claim 3, further comprising third processing means for executing quantization processing on pixel data in units of columns in the first unit block at the parallelism N. An image that includes a first process and a second process that can be performed on pixel data in units of rows or columns, and that encodes a picture to be encoded for each unit block that includes a predetermined number of pixels. An encoding method comprising:
A first processing step for preferentially performing an operation on pixel data in units of rows or columns used in the second processing;
And a second processing step of starting the second processing upon completion of the operation on pixel data in units of rows or columns necessary for starting the second processing in the first processing. Method. An image that includes a first process and a second process that can be performed on pixel data in units of rows or columns, and that encodes a picture to be encoded for each unit block that includes a predetermined number of pixels. A program for use in an encoding device to be executed by a computer,
The program is
A first processing step for preferentially performing an operation on pixel data in units of rows or columns used in the second processing;
And a second processing step of starting the second process upon completion of the operation on pixel data in units of rows or columns necessary for starting the second process in the first process. An integration including a first process and a second process that can be performed on pixel data in units of rows or columns, and encoding a picture to be encoded for each unit block composed of a predetermined number of pixels. A circuit,
First processing means for preferentially executing calculation on pixel data in units of rows or columns used in the second processing;
An integrated circuit, comprising: second processing means for starting the second processing upon completion of the operation on pixel data in units of rows or columns necessary for starting the second processing in the first processing.

Images