JP2014075708A - Moving image encoder and moving image encoding method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To compress and encode a moving image without increasing a frequency of hardware and without thinning access.SOLUTION: A moving image encoder includes a processor for controlling an encoding operation for encoding an encoding object consisting of the prescribed number of pixels in a block unit. The processor includes: means for monitoring a synchronization signal of a video; means for monitoring register access during controlling of the encoding operation; means for determining whether register access which the register access monitoring means monitors is completed or not in a period of the synchronization signal which the synchronization signal monitoring means monitors; and means for controlling the register access in accordance with a determination result of the register access completion determination means. When the number of accesses of the register is large and encoding processing of a frame is not performed in time, register setting which can be set after encoding is started is performed after starting of encoding. Thus, a failure of the encoding processing is prevented while image quality is kept to be sufficient.

Description

  The present invention relates to a moving picture coding apparatus and a moving picture coding method, and particularly to a technique suitable for use in compression coding of moving picture data.

  In recent years, digital devices capable of recording moving images, such as digital video cameras and hard disk recorders, have become widespread. In these digital devices, in order to efficiently record a moving image having a large amount of information on a recording medium such as a flash memory or a hard disk with a limited capacity, the moving image data is compressed and encoded. MPEG2 and H.264 are listed as typical moving image compression encoding systems.

  In these moving image compression coding systems, one frame or one field is divided into areas of a predetermined number of pixels called macroblocks (hereinafter referred to as MB), and motion compensation prediction, DCT conversion processing, quantum processing is performed in units of the macroblocks. And entropy coding. In addition, in these moving image compression coding systems, in order to efficiently perform coding and improve image quality, a method of performing control for each 1 MB line or for each MB unit with a predetermined number of MBs as one unit. Is disclosed (see Patent Document 1 and Patent Document 2).

JP 2003-189111 A JP 2007-235705 A

  However, when recording a moving image in real time using the techniques described in Patent Document 1 and Patent Document 2, it is performed using dedicated hardware called an ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array). Most of the cases. When encoding using these dedicated hardware, the built-in CPU reads the register to set image quality parameters such as the target code amount and encoding difficulty for each MB line or MB unit. Access or write access is required.

  For this reason, when the techniques described in Patent Document 1 and Patent Document 2 are used for recent HD (High Definition) images and higher resolutions, the CPU often causes read access and write access to the register. End up. For this reason, there is a problem that processing of one picture is not in time for a vertical synchronization signal (hereinafter referred to as V period) of a moving image.

As a method for solving the above-mentioned problems, a method of increasing the frequency of hardware or reducing the number of accesses by using the same value in units of multiple MB lines and multiple MB units may be considered. However, when such a method is used, new problems such as an increase in power consumption and deterioration in image quality occur, and this is not always the best solution.
In view of the above-described problems, an object of the present invention is to make it possible to compress and encode a moving image without performing hardware frequency increase and access thinning.

The moving picture coding apparatus according to the present invention controls a coding operation in which a screen is divided into a matrix in units of a block to be coded composed of a predetermined number of pixels, and coding is performed in units of the blocks. In the moving picture encoding apparatus including a processor, the processor includes synchronization signal monitoring means for monitoring a video synchronization signal;
Whether the register access monitored by the register access monitoring means is completed during the period of the synchronization signal monitored by the synchronization signal monitoring means and the register access monitoring means for monitoring register access when controlling the encoding operation Register access completion determining means for determining whether or not, and register access control means for controlling register access according to the determination result of the register access completion determining means, wherein the register access control means includes the synchronization signal monitoring means and According to the monitoring state of the register access monitoring means, control is performed so that the specific register is accessed after the start of encoding in the register access.

  According to the present invention, it is possible to compress and encode a moving image while maintaining good image quality without performing hardware frequency increase and access thinning.

It is a flowchart which shows the 1st Embodiment of this invention and shows the procedure in the case of performing a specific register access after an encoding start. 1A and 1B are timing charts illustrating a case where a specific register access is performed before the start of encoding, and FIG. 1B is a timing chart illustrating a case where a specific register access is performed after the start of encoding. It is. It is a block diagram which shows schematic structure of an encoding apparatus. It is a flowchart which shows 2nd Embodiment and shows the procedure in the case of performing a specific register access after an encoding start. It is a timing chart which shows 2nd Embodiment and shows a control timing. It is a figure which shows the division area | region of the register setting which concerns on 2nd Embodiment.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
In describing the first embodiment of the present invention, the overall configuration of the moving picture coding apparatus of the present invention will be described with reference to FIG.

FIG. 3 is a block diagram showing an overall configuration of an encoding apparatus 300 suitable for implementing or adapting the present invention.
In FIG. 3, the frame rearrangement division unit 301 rearranges the moving image input to the encoding device 300 according to the encoded picture type, and encodes a block to be encoded (macro) composed of a predetermined number of pixels. The screen is divided into a matrix in units of blocks).

  The subtracter 302 performs subtraction between the data of the encoding target image input from the frame rearrangement division unit 301 and predicted image data described later, and outputs the result to the orthogonal transformation unit 303 as image residual data. The orthogonal transform unit 303 performs orthogonal transform processing on the image residual data output from the subtracter 302 and outputs DCT coefficients to the quantization unit 304.

  The quantization unit 304 quantizes the DCT coefficient using a predetermined quantization parameter and outputs it to the entropy coding unit 315. In addition, the DCT coefficient quantized by the quantization unit 304 is also used to generate predicted image data, and is therefore output to the inverse quantization unit 305. The inverse quantization unit 305 inversely quantizes the DCT coefficient quantized by the quantization unit 304.

  The inverse orthogonal transform unit 306 performs inverse orthogonal transform on the DCT coefficient inversely quantized by the inverse quantization unit 305, and outputs a local decoded image. The adder 307 adds a local decoded image and predicted image data described later and outputs the result to the frame memory 308. Further, a filtering process is performed by the deblocking filter 309 on the sum of the local decoded image and predicted image data described later, and the result is output to the frame memory 310.

  The intra prediction unit 311 performs an intra-frame prediction process using an image stored in the frame memory 308, and generates predicted image data. In addition, the inter prediction unit 312 performs inter-frame prediction processing based on the motion vector information detected by the motion detection unit 313 using the image stored in the frame memory 310, and generates predicted image data.

  The motion detection unit 313 detects a motion vector for each macroblock, and outputs the detected motion vector information to the inter prediction unit 312, the entropy encoding unit 315, and the stream transmission unit 317. The switch 314 is a selection unit for selecting whether to use intra prediction or inter prediction, and selects one of the output from the intra prediction unit 311 and the output from the inter prediction unit 312 and selects the selected prediction. The image data is output to the subtracter 302 and the adder 307.

  The entropy encoding unit 315 performs entropy encoding on the input data and outputs it to the stream buffer 316. The stream buffer 316 accumulates the data output from the entropy encoding unit 315, and outputs the data according to the instruction from the stream transmission unit 317. The stream transmission unit 317 outputs encoded data at a bit rate according to the target bit rate. The CPU 318 as a processor unit includes a synchronization signal monitoring unit 3181, a register access monitoring unit 3182, a register access completion determination unit 3183, and a register access control unit 3184, which will be described later, and controls and encodes the encoding operation of the encoding device 300.

  FIG. 1 is a flowchart illustrating a procedure when a specific register access is performed after the start of encoding according to the first embodiment of this invention. FIG. 2 is a diagram illustrating control timing, FIG. 2A is a timing chart illustrating a case where a specific register access is performed before the start of encoding, and FIG. 2B is a specific register. It is a timing chart which shows the case where access is performed after encoding start.

First, in S100, the CPU 318 waits for the encoding completion timing 200 and proceeds to S101.
In S101, the CPU 318 determines the macroblock (MB) line at the register read timing 201 regarding the generated code amount, the encoding difficulty level, and the motion search result that are the encoding results of the previous picture necessary for encoding the next picture. The register is read every time, and the process proceeds to S102.

In S102, the CPU 318 calculates the target code amount for each 1 MB of the next encoded picture from the generated code amount and the encoding difficulty level at the encoding setting calculation timing 202, and proceeds to S103.
In S103, at the register write start timing 203, the CPU 318 starts register write with respect to the target code amount and motion search prediction for each 1 MB line necessary before starting the encoding of the next picture, and proceeds to S104.

  In S104, the completion determination is performed by the register access completion determination unit 3183 of the CPU 318. When it is determined that the compression encoding process for one picture including the register access is not in time within the video synchronization signal period (in one cycle), the process proceeds to S105 at the encoding start timing 204. On the other hand, if it is determined that it is in time, the process proceeds to S107 at the encoding start timing 205. This determination is made based on the monitoring status information of the synchronization signal monitoring unit 3181 that monitors the period of the video synchronization signal of the CPU 318 and the register access monitoring unit 3182 that monitors the progress of register access.

  In S105, the register access control unit 3184 sets the target code amount for each MB line and the register write for motion search prediction for the predetermined MB line in the screen. Then, control is performed so as to start compression encoding of a picture without register writing of the specific register, and the process proceeds to S106.

  In S106, the register access control unit 3184 sets one or more blocks for each remaining MB line as a unit after the start of encoding and before compression encoding of the corresponding portion is performed, as indicated by the remaining register write timing 206. The target code amount of the block unit and the register search for motion search prediction are performed, and this flow ends.

In S107, the CPU 318 starts encoding the picture and ends this flow.
In the present embodiment, the register write has been described as an example, but the same can be achieved by register read. In this case, before the encoding completion timing 200, the generated code amount, the encoding difficulty level, and the motion search result for each MB line that can be register-read are register-read, and after the encoding is completed, the rest is register-read.
In the present embodiment, an example related to the MB line has been described, but the same can be done with an MB unit.

  As described above, in the present embodiment, the register access completion determination unit 3183 determines whether the encoding is completed within the video synchronization signal period from the information of the synchronization signal monitoring unit 3181 and the register access monitoring unit 3182. . The necessary settings before the start of encoding are register write before the start of encoding, and registers that can be set after the start of encoding are written after the start of encoding, so that encoding is performed while maintaining good image quality. Is possible.

(Second Embodiment)
In the first embodiment, the case where the video synchronization signal and the screen resolution are fixed has been described, but in this embodiment, the case where the video synchronization signal and the screen resolution are variable will be described. Note that a block diagram showing the overall configuration of a suitable encoding apparatus to which the present invention is implemented or applied is the same as that of the first embodiment described above, and is therefore omitted.

  FIG. 4 is a flowchart illustrating a procedure when a specific register access is performed after the start of encoding according to the second embodiment of this invention. FIG. 5 is a timing chart showing the control timing according to the embodiment of the present invention.

  First, in S400, the register access completion determination unit 3183 determines, at the encoding setting calculation timing 500, whether or not the compression encoding process including the register access from the resolution and the frame rate is within the video synchronization signal period. If it is determined that it is in time, the process proceeds to S401, and if it is determined that it is not in time, the process proceeds to S402.

  In S401, it is not necessary to perform register read for each MB line before completion of picture after register write for each MB line is started from the resolution and frame rate, so the process proceeds to S407 without setting anything. .

  In S402, the register access completion determination unit 3183, at the encoding setting calculation timing 500, partly after the picture encoding start timing 501 regarding the target code amount and motion search prediction that require register write for each MB line. Do. Then, it is determined whether or not the compression encoding process including the register access is in time for the video synchronization signal period. If it is determined that it is not in time, the process proceeds to S403. If it is determined that it is not in time, the process proceeds to S404.

  In S403, the register access control unit 3184 sets a division value corresponding to the resolution and the frame rate for the target code amount and motion search prediction that require register write for each MB line, and proceeds to S407.

  In S404, the register access completion determination unit 3183 encodes a part of the generated code amount, encoding difficulty level, and motion search result that require register read for each MB line at the encoding setting calculation timing 500. This is performed before completion timing 502. Then, it is determined whether or not the compression encoding process including the register access is in time for the video synchronization signal period. If it is determined that it is not in time, the process proceeds to S405. If it is determined that it is not in time, the process proceeds to S406.

  In S405, the register access control unit 3184 sets a division value corresponding to the resolution and the frame rate for the generated code amount, encoding difficulty level, and motion search result that require register read for each MB line, and proceeds to S407. .

  In S406, the register access control unit 3184 performs the register encoding and the register reading once every MB line at the encoding setting calculation timing 500, so that the compression encoding process including the register access is performed within the video synchronization signal period. Calculate whether it is in time. Specifically, calculation is performed regarding the target code amount, motion search prediction, generated code amount, encoding difficulty level, and motion search result that require register write and register read for each MB line, and the process proceeds to S407.

  In S407, the register access control unit 3184 controls compression encoding according to the register write division value, the register read division value, and the register access thinning information, and ends this flow.

  In the present embodiment, when register write division is necessary, the register access control unit 3184, as shown in the register write 503 timing, registers a part of the target code amount and motion search prediction register write after the encoding start timing 501. The compression encoding is controlled so that

  When register read division is necessary, the register access control unit 3184, as shown in the timing of the register read 504, sets a part of the generated code amount, the encoding difficulty level, and the motion search result before the encoding completion timing 502. Control compression encoding to perform register read.

FIG. 6 is a diagram illustrating divided areas for register settings according to the second embodiment.
In FIG. 6, 600 is one picture, 601 is an MB composed of a predetermined number of pixels, and 602 is an MB line in which the macroblocks are grouped in the horizontal direction. The register access completion determination unit 3183 performs division processing for those requiring register write and register read for each MB line from the resolution and the frame rate.
In FIG. 6, as indicated by a white arrow, the MB line is divided into an MB line above a predetermined position and an MB line below a predetermined position in the screen, and encoding starts as indicated by a register write 503 and a register read 504. Split processing is performed before and after the encoding is completed.

  In the present embodiment, an example related to the MB line has been described, but the same can be done with an MB unit. In the present embodiment, an example corresponding to the resolution and the frame rate has been described. However, the same can be applied to the clock frequency used by the encoding device 300 and the CPU 318. In that case, the resolution or frame rate is N times the same as the case where the clock frequency is 1 / N.

As described above, in the present embodiment, it is determined from the resolution and the frame rate whether or not the compression encoding process including the register access is in time within the video synchronization signal period. The necessary settings before the start of encoding are register write before the start of encoding, and registers that can be set after the start of encoding are written after the start of encoding, so that encoding is performed while maintaining good image quality. Is possible.
It should be noted that the present invention is not limited to the above embodiment within the scope of the technical idea of the present invention, and should be adapted as appropriate by changing the target circuit form.

(Other embodiments)
The present invention can also be realized by executing the following processing. That is, software (computer program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various computer-readable storage media. Then, the computer (or CPU, MPU, etc.) of the system or apparatus reads out and executes the program.

300 Coding Device 301 Frame Rearrangement Divider 302 Subtractor 303 Orthogonal Transformer 304 Quantizer 305 Inverse Quantizer 307 Adder 306 Inverse Orthogonal Transformer 308, 310 Frame Memory 309 Deblocking Filter 311 Intra Predictor 312 Inter Prediction Unit 313 motion detection unit 314 switch 315 entropy encoding unit 316 stream buffer 317 stream transmission unit 318 CPU
3181 Synchronization signal monitoring unit 3182 Register access monitoring unit 3183 Register access completion determination unit 3184 Register access control unit

Claims (16)

In a moving image encoding apparatus including a processor that controls an encoding operation in which a screen is divided into a matrix in units of an encoding target block including a predetermined number of pixels and encoding is performed in units of the block ,
The processor is
Synchronization signal monitoring means for monitoring video synchronization signals;
Register access monitoring means for monitoring register access when controlling the encoding operation;
Register access completion judging means for judging whether or not the register access monitored by the register access monitoring means is completed during the period of the synchronization signal monitored by the synchronization signal monitoring means;
Register access control means for controlling register access according to the judgment result of the register access completion judgment means,
The register access control means controls to perform access to a specific register after the start of encoding in the register access according to the monitoring state of the synchronization signal monitoring means and the register access monitoring means. Video encoding device.   2. The moving picture encoding apparatus according to claim 1, wherein the specific register is a target code amount of a block unit having one or more blocks as a unit.   2. The moving picture coding apparatus according to claim 1, wherein the specific register is a generated code amount of a block unit having one or more blocks as a unit.   2. The moving picture encoding apparatus according to claim 1, wherein the specific register is an encoding difficulty level of a block unit having one or more blocks as a unit.   The moving picture coding apparatus according to claim 1, wherein the specific register is a motion search result of a block unit in which one or more blocks are used as a unit.   6. The moving picture encoding apparatus according to claim 1, wherein the register access control unit changes the specific register in accordance with a cycle of the synchronization signal.   The moving image encoding apparatus according to claim 1, wherein the register access control unit changes the specific register according to the resolution of the video.   The moving picture encoding apparatus according to claim 1, wherein the register access control unit changes the specific register according to a clock frequency of the processor. In the moving picture coding method in which the inside of a screen is divided in a matrix form in units of blocks to be coded composed of a predetermined number of pixels, and a coding operation for performing coding in units of the blocks is controlled by a processor.
The processor is
A synchronization signal monitoring step for monitoring a video synchronization signal;
A register access monitoring step of monitoring register access when controlling the encoding operation;
A register access completion determination step for determining whether or not the register access monitored by the register access monitoring step is completed during the period of the synchronization signal monitored by the synchronization signal monitoring step;
Performing a register access control step for controlling register access according to the determination result of the register access completion determination step,
In the register access control step, control is performed so that a specific register is accessed after the start of encoding in the register access according to the monitoring state of the synchronization signal monitoring step and the register access monitoring step. Video encoding method.   10. The moving picture encoding method according to claim 9, wherein the specific register is a target code amount of a block unit having one or more blocks as a unit.   10. The moving picture encoding method according to claim 9, wherein the specific register is a generated code amount of a block unit with one or more blocks as a unit.   10. The moving picture encoding method according to claim 9, wherein the specific register is an encoding difficulty level of a block unit having one or more blocks as a unit.   10. The moving picture encoding method according to claim 9, wherein the specific register is a motion search result of a block unit with one or more blocks as a unit.   The moving image encoding method according to claim 9, wherein the register access control step changes the specific register according to a cycle of the synchronization signal.   15. The moving picture encoding method according to claim 9, wherein the register access control step changes the specific register according to the resolution of the video.   16. The moving picture encoding method according to claim 9, wherein the register access control step changes the specific register according to a clock frequency of the processor.

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