JP4879269B2 - Decoding method and apparatus - Google Patents

Description

  The present invention relates to a decoding method and apparatus. The present invention relates to a decoding method and apparatus for decoding moving image data encoded (that is, compressed) by a moving image encoding standard such as H.264.

H. H.264 or MPEG (Moving Picture Experts Group) 4-AVC (Advanced Video Coding) is developed by JVT which is a joint standardization organization between ISO and ITU-T (ISO / IEC 14496-10 or ITU-T Q6 / 16). ), A new compression / decompression technology standardized in 2003. H. The 264-AVC system (hereinafter simply referred to as the H.264 system) is known to be used in broadcasting for portable terminals called “one segment broadcasting” among terrestrial digital television broadcasting. H. In the H.264 system, 4 × 4 pixel integer conversion, 9-direction intra prediction, 7 types of sub macroblock division, minimum 4 × 4 pixel motion vector, multiframe reference, and in-loop New technologies such as filters and arithmetic codes have been introduced to achieve high compression rates. H. By using the H.264 system, it is said that the same reproduction image quality can be obtained with a half stream size compared to the MPEG2 system.
However, H. The algorithm employed in the H.264 method has a large amount of processing because importance is placed on coding efficiency. For this reason, H.C. For signal processing apparatuses that perform H.264 encoding and decoding (encoding and decoding), a configuration that performs parallel processing by software and a configuration that performs parallel processing by dedicated hardware have been used.

  When performing image processing by parallel processing using software or hardware, there are a method of assigning processing in units of images and a method of assigning in units of processing. In the case of hardware implementation, a method of assigning in units of processing is often adopted. In the case of parallel processing by software, either method can be adopted, but when the method of assigning processing in units of images is adopted, there is little bias in processing between processors, and the number of processors can be increased to increase the screen size. Expansion becomes easy.

  However, H. Each process of the H.264 system has a complicated data dependency, and many synchronization processes are required when performing parallel processing.

H. A H.264 encoding and decoding method is proposed in Patent Document 1, for example. H. For example, Non-Patent Document 1 proposes a method of performing H.264 decoding in parallel processing.
JP 2005-354361 A Yen-Kuang Chen et al., "Implementation of H.264 Encoder and Decoder on Personal Computers", Special Issue on Emerging H.264 / AVC Video Coding Standard, Journal of Visual Communication and Image Representation, Kumar, Mandal and Panchanathan

  H. In the H.264 system, there are many data dependencies between macro blocks (MB), and there is a limit to MBs that can be operated in parallel in parallel processing. For example, H.M. In the H.264 decoding process, there is a process that requires MB data on the left, upper left, upper, and upper right of the MB of interest in a process in MB units. In the case of such processing, in order to start the processing of the target MB, it is necessary to complete the processing of the left, upper left, upper, and upper right MBs of the target MB and transfer data. For this reason, when MB processing as described above is performed by software processing of a plurality of processors or hardware processing of a decoder, synchronization processing such as waiting for processing completion and data transfer frequently occurs, resulting in an increase in overhead. There was a problem that.

  Therefore, the present invention relates to H.264. It is a general object to provide a decoding method and apparatus capable of performing efficient processing for image processing that requires processing having complicated data dependency such as decoding processing of H.264 system.

  The above problem is a decoding method in which a plurality of processing units perform parallel processing in units of macroblocks on encoded image data to be processed, and each processing unit is responsible for processing. A plurality of macroblock lines are allocated to the target macroblock processed by each processing unit, and the processing result of the reference macroblock of the macroblock line that precedes the macroblock line to which the target macroblock belongs is used. And processing the target macroblock of the first macroblock line within the processing range of the second processing unit using the processing result of the reference macroblock of the last macroblock line within the processing range of the first processing unit. Can be achieved by a decoding method characterized in that

  The above problem includes a plurality of processing units that perform parallel processing of encoded image data to be processed in units of macroblocks, and a plurality of macroblock lines are assigned to a processing range in which each processing unit is responsible for processing. The processing of the target macroblock processed by each processing unit is performed using the processing result of the reference macroblock of the macroblock line that precedes the macroblock line to which the target macroblock belongs. The target macroblock of the first macroblock line within the processing range of the second processing unit is processed using the processing result of the reference macroblock of the last macroblock line within the processing range of the second processing unit. Can be achieved by a decoding device.

  In accordance with the present invention, H.264. It is possible to realize a decoding method and apparatus capable of performing efficient processing for image processing that requires processing having complicated data dependency, such as H.264 decoding processing.

H. FIG. 3 is a diagram for explaining data dependency of a decoding process of the H.264 method. It is a figure explaining the processing order and data transfer which can be considered when a processor is allocated for every MB. It is a figure explaining the processing order and data transfer of this invention at the time of allocating a processor for every MB. It is a figure explaining the processing order and data transfer of this invention at the time of allocating a processor for every MB. It is a figure explaining the case where two processors are used for the processing order and data transfer of 1st Example. It is a flowchart explaining the outline of the process of 1st Example. FIG. 6 is a diagram showing the overhead of the first embodiment in comparison with a comparative example. It is a figure explaining the case where three processors are used for the processing order and data transfer of 1st Example. It is a flowchart explaining the process of three processors in 1st Example. It is a figure explaining the case where two processors are used for the processing order and data transfer of 2nd Example. It is a flowchart explaining the outline of the process of 2nd Example. It is a figure explaining the case where three processors are used for the processing order and data transfer of 2nd Example. It is a flowchart explaining the process of three processors in 2nd Example.

Explanation of symbols

11, 21 processor

  H. In the H.264 system, there are many data dependencies between macro blocks (MB), and there is a limit to MBs that can be operated in parallel in parallel processing. H. Intra prediction, motion vector (MV) prediction, and deblocking filter (DF) processing, which are H.264 processes, have data dependency that requires MB data around the MB of interest. For this reason, synchronous processing including processing completion waiting, data delivery, etc. frequently occurs. In addition, there is a limit to MB that can be calculated in parallel.

  Therefore, the present invention provides a parallel processing order focusing on the locality of the encoded image data (moving image data) and simplification of the synchronization processing within this limitation.

  H. In the H.264 decoding process, there is a process in units of MB that requires data of reference MBs on the left, upper left, upper, and upper right of the target MB indicated by hatching as shown in FIG. FIG. 2A and 2B are diagrams for explaining data dependence in a H.264 decoding process, where FIG. 2A shows data dependence in the case of intra prediction and MV prediction, and FIG. 2B shows data dependence in the case of DF processing. In FIG. 1, each rectangular area represents one MB. As can be seen from FIG. 1, in order to start processing of the target MB, in the case of intra prediction or MV prediction, processing of the reference MB on the left, upper left, upper and upper right of the target MB is completed and data is transferred. In the case of DF processing, it is necessary to complete processing of the reference MB above the target pixel and transfer data.

  For this reason, when the decoding apparatus performs the MB processing as described above by the software processing of a plurality of processors or the hardware processing of a decoder, it may be performed in the processing order as shown in FIG. FIG. 2 is a diagram illustrating a possible processing order and data transfer in which a processor (or decoder) is allocated to each MB in the case of intra prediction as an example. In FIG. 2, each rectangular area indicates one MB, a thick solid line arrow indicates the processing order, a thin solid line arrow indicates data transfer, and two processors # 1 and # 2 are used for convenience of explanation. To do. However, if this possible processing order is used, the processors # 1 and # 2 that perform processing change for each macroblock line (MB line), and synchronization processing such as waiting for processing completion and data delivery is frequently performed. Occurs and the overhead becomes large.

  Therefore, in the present invention, the decoding apparatus performs software processing of a plurality of processors or hardware processing of a plurality of decoders, that is, a plurality of processes, on encoded image data (moving image data) to be processed. 3 to perform processing in units of MB as described above, the range in which each processor (or decoder) is in charge of processing (hereinafter also referred to as a processing range) is set to a plurality of MB lines instead of every 1 MB line. Processing is performed in the order of priority for MBs arranged in a substantially vertical direction as shown in FIG. 4 (that is, directions other than the horizontal direction on the same MB line). 3 and 4 are diagrams for explaining the processing order and data transfer according to the present invention in which a processor is assigned to each MB in the case of intra prediction. 3 and 4, each rectangular area indicates one MB, a thick solid line arrow indicates a processing order, and a thin solid line arrow indicates data transfer. For convenience of explanation, two processors # 1 and # 2 are used in FIG. 3, three processors # 1 to # 3 are used in FIG. 4, and each processor # 1, # 2, and # 3 is responsible for processing. It is assumed that the range is every 4 MB line.

  According to the present invention, the boundaries of processing ranges handled by different processors or different decoders are reduced, and an increase in overhead due to synchronization processing can be suppressed. For example, as shown in FIG. 3, when two processors # 1 and # 2 perform the above MB decoding process, if the number of MB lines in the processing range in charge of each processor # 1 and # 2 is N, The number of synchronization processes can be reduced to 1 / N times as compared with the above conceivable method. Before the first synchronization process, for example, one processor # 1 needs to process (N + 1) N / 2 MBs, and during that time, the other processor # 2 cannot start the process. When the total number of MBs to be processed is TM and the processing amount per MB is A, the condition OH × TM × (N−1) / N> A × (N + 1) × N / 2 is satisfied. In this case, the effect of reducing the synchronization overhead OH can be obtained by introducing the present invention.

  In the DB processing, the processing of the present invention for allocating a processor for each MB is similar to the case of the intra prediction, and MBs arranged in a substantially vertical direction (that is, directions other than the horizontal direction on the same MB line) The same effects as described above can be obtained in the order of priority, and details thereof will be described together with the following examples.

  Embodiments of the decoding method and apparatus of the present invention will be described below with reference to the drawings.

(First embodiment)
First, a first embodiment of the decoding method and apparatus according to the present invention will be described with reference to FIGS.

  FIG. 5 is a diagram for explaining the processing sequence and data transfer of the first embodiment when two processors are used. In FIG. 5, each rectangular area indicates one MB, a number in each rectangular area indicates a processing order, and a thin solid line arrow indicates data transfer. For convenience of explanation, it is assumed in FIG. 5 that two processors # 1 and # 2 are used, and the range in which each processor # 1 and # 2 takes charge of processing is every 3 MB line.

  As in intra prediction or MV prediction, when processing the target MB in one frame of the encoded image data (moving image data) to be processed, reference MB data including the upper right of the target MB is required. In this case, processing is performed in the order as shown in FIG. Each MB line is composed of, for example, 5 MBs, and each MB is composed of, for example, data of 16 × 16 pixels.

  When the processing of the target MB is completed, the processing of the reference MB on the lower left is performed next. When processing reaches the target MB of the last (bottom or bottom) MB line of the processing range of the processor that is processing, the unprocessed MB of the top (first) MB line of this processing range Of these, the leftmost MB is processed as the target MB. If there is no unprocessed MB in the first MB line, the candidate for the target MB is searched from the second MB line from the top, and if there is no candidate in the second MB line, the third MB below it Search for candidates from the line. Since the number of MB lines in the processing range handled by each processor # 1, # 2 or each dedicated hardware (decoder) is 3, in this way, 3 (3 + 1) / 2 = 6 MBs are first processed. Thereafter, the process of performing one synchronization process for the process of three MBs is repeated until the end of the processing range (the rightmost MB of the lowest MB line) is reached. In this way, the processing is repeated until the processing of all MBs in each processing range is completed.

  That is, as shown in FIG. 5, when the processing of the leftmost noticed MB “1” of the first MB line is completed, the processor # 1 unprocessed of the first MB line and leftmost MB “2” "Is processed as a target MB. Next, MB “3” in the second MB line diagonally lower left is processed as the target MB, and the leftmost MB “4” in the first MB line is processed as the target MB. Next, processing is performed with the MBs “5” and “6” in the second and third MB lines diagonally lower left as the target MB, and processing of six MBs is performed. Thereafter, the process of performing one synchronization process for the processes of three MBs is repeated until the end of the processing range (the rightmost MB of the lowest MB line) is reached.

  On the other hand, the processor # 2 performs processing in the same processing order as the processor # 1, but the processing result of the processor # 1 transferred in the synchronous processing is processed for the processing of the first MB line to be processed first. Use. That is, at the time when the first six MBs and the next three MBs are processed by the processor # 1, the processor # 2 has the MBs “6” and “9” of each third MB line. In the MB line processed by the processor # 2 using the processing result, the leftmost attention MB “1” of the first MB line is processed. When the processing of the leftmost noticed MB “1” of the first MB line is completed, the processor # 2 is the third MB line when the next three MBs are processed by the processor # 1. In the MB line processed by processor # 2 using the processing result of MB “12”, the leftmost MB “2” in the unprocessed first MB line is processed as the target MB. After that, the processor # 2 uses the processing order of the processor # 1 for the processing of the first MB line in the MB line processed by the processor # 2, using the processing order of the processor # 1. The process is repeated until all MBs in the processing range have been processed.

  Assuming that the number of MB lines in the processing range handled by each processor # 1, # 2 or each dedicated hardware (decoder) is N, N (N + 1) / 2 MBs are processed first. The MB process and one synchronization process are repeated until the right end of the processing range is reached. As a result, in the repetitive part of the processing range, one synchronization process is required for every N MBs, and the synchronization process can be reduced to 1 / N compared with the above-described method (hereinafter referred to as a comparative example). .

  When the overhead of synchronization processing is OH, in this embodiment, as shown in FIG. 7A, the number of times of synchronization processing is 1 / N as compared with the comparative example of FIG. 7B. FIG. 7 is a diagram showing the overhead OH of the first embodiment in comparison with the comparative example. In FIG. 7, the hatched rectangular area indicates MB processing, and the black rectangular area indicates synchronization processing. In the present embodiment, the processor # 2 can start processing at a timing delayed by the processing of {N (N + 1) / 2 + N} MBs after the processor # 1 starts processing. It can be seen that when the size is large and the overhead OH of the synchronization processing is large, the processing can be performed more efficiently than the comparative example.

  FIG. 6 is a flowchart for explaining the outline of the processing of the first embodiment. The processing shown in FIG. 6 is executed by the processor 11. The processor 11 is an information processing apparatus having a known configuration including a CPU, a storage unit, and the like, and the decoding apparatus has a configuration in which a plurality of such processors 11 are connected so as to be capable of parallel processing.

  In FIG. 6, step S1 processes the first N (N + 1) / 2 MBs. Thereby, the processing of MBs “1” to “6” of the first to third MB lines shown in FIG. 5 is performed. In step S2, the processes in steps S3 and S4 are repeated until the rightmost MB of each MB line in the processing range of one frame of the encoded image data to be processed is processed. In step S3, N MBs are processed, and in step S4, synchronous processing including waiting for completion of processing, data transfer, and the like is performed. In step S5, it is determined whether or not steps S2 to S4 have been performed for the last MB line in the processing range. If the determination result is NO, the process returns to step S2, and if YES, the process ends.

  When two processors # 1 and # 2 are used for parallel processing as described above, each processor # 1 and # 2 performs the processing shown in FIG. 6, but in the case of processor # 2, attention is paid when performing processing on the target MB. The same processing as in the case of the processor # 1 is required in that the data of the reference MB including the upper right of the MB is required. However, when processing the MB of the first MB line in the MB line processed by the processor # 2, The MB line processed by the processor # 1 is different only in that the processing result for the MB of the third MB line is used.

  FIG. 8 is a diagram for explaining the processing sequence and data transfer in the first embodiment when three processors are used, and FIG. 9 is a flowchart for explaining the processing of the three processors in the first embodiment. In FIG. 8, each rectangular area indicates one MB, the numbers in each rectangular area indicate the processing order from the upper left to the upper right and the lower right of the processing range, and the thin solid arrows indicate data transfer. For convenience of explanation, it is assumed that the processing range in which each processor # 1, # 2, # 3 is in charge of processing is every N macroblock (MB) lines, and each MB line is composed of W MBs. Here, N and W are both integers of 2 or more, and N ≠ W or N = W, but preferably N <W. Each MB is composed of data of 16 × 16 pixels, for example.

  When reference MB data including the upper right of the target MB is required when processing the target MB in one frame of the encoded image data to be processed, such as intra prediction or MV prediction, FIG. Processing is performed in the order shown in FIG.

  FIG. 9 shows the processing of the three processors # 1, # 2, and # 3. The processor # 1 performs steps S101-1 to S108-1, the processor # 2 performs steps S101-2 to S108-2, S111-2 to S113-2, and the processor # 3 performs steps S101-3 to S108-3. , S111-3 to S113-3. In FIG. 9, substantially the same steps are indicated by subscripts “−1” to “−3” corresponding to the processors # 1 to # 3 attached to the same reference numerals.

  First, the processing of processor # 1 will be described. When the processing of the processor # 1 is started, step S101-1 sets a variable i (integer) to i = 1. Step S102-1 performs processing of the i-th MB “i”, and step S103-1 determines whether or not the MB is located at the left end of the processing range. If the decision result in the step S103-1 is NO, a step S104-1 decides whether or not the MB is located at the lower end of the processing range. If the decision result in the step S104-1 is NO, the step S105-1 performs a process on the lower left MB of the current MB, and the process returns to the step S103-1. On the other hand, if the decision result in the step S104-1 is YES, the step S106-1 performs data transfer to the processor # 2, and the step S107-1 determines whether i = (W + N-1). . In the data transfer in step S106-1, the processing result of the MB of the Nth MB line is transferred to the processor # 2. If the decision result in the step S107-1 is NO, the step S108-1 increments i to i = i + 1, and the process returns to the step S102-1. If the decision result in the step S107-1 is YES, the process of the processor # 1 is finished.

  Next, the processing of processor # 2 will be described. When the processing of the processor # 2 is started, the step S101-2 sets the variable i (integer) to i = 1. In step S111-2, a synchronization process for waiting for data transfer from the processor # 1 is performed. Therefore, initially, the processing result of the MB of the Nth MB line processed by the processor # 1 that is necessary for the processor # 2 to process the first MB “1” of the first MB line is the processor # 2. When transferred from 1, the process proceeds to step S112-2. In step S112-2, it is determined whether i ≦ W. If the determination result is YES, step S113-2 performs a synchronization process for waiting for data transfer from the processor # 1. Therefore, when the processing result of the MB of the Nth MB line processed by the processor # 1 necessary for the processor # 2 to process the MB is transferred from the processor # 1, the processing proceeds to step S102-2. move on. If the decision result in the step S112-2 is NO, the process advances to a step S102-2. The other processing of the processor # 2 is basically the same as the processing of the processor # 1.

Next, the processing of processor # 3 will be described. When the processing of processor # 3 is started, step S101-3 sets variable i (integer) to i = 1. In step S111-3, a synchronization process for waiting for data transfer from the processor # 2 is performed. Therefore, initially, the processing result of the MB of the Nth MB line processed by the processor # 2 which is necessary for the processor # 3 to process the first MB “1” of the first MB line is the processor # 3. When transferred from 2, the process proceeds to step S112-3. In step S112-3, it is determined whether i ≦ W. If the determination result is YES, step S113-3 performs a synchronization process for waiting for data transfer from the processor # 2. Therefore, when the processing result of the MB of the Nth MB line processed by processor # 2 necessary for processor # 3 to process the MB is transferred from processor # 2, the process proceeds to step S102-3. move on. If the decision result in the step S112-3 is NO, the process advances to a step S102-3. Other processing of the processor # 4 is basically the same as the processing of the processor # 2.
(Second embodiment)
Next, a second embodiment of the decoding method and apparatus according to the present invention will be described with reference to FIGS.

  FIG. 9 is a diagram for explaining the processing order and data transfer of the second embodiment when two processors are used. In FIG. 9, each rectangular area indicates one MB, a number in each rectangular area indicates the processing order, and a thin solid line arrow indicates data transfer. For convenience of explanation, it is assumed in FIG. 9 that two processors # 1 and # 2 are used, and the processing range in which each processor # 1 and # 2 takes charge of processing is every 3 MB line.

  When the reference MB data above the target MB is required when processing the target MB in one frame of the encoded image data to be processed as in the DF processing, as shown in FIG. Process in order. Each MB line is composed of, for example, four MBs, and each MB is composed of data of 16 × 16 pixels, for example.

  When the processing for the target MB is completed, the next MB is processed. When processing reaches the target MB of the last (bottom) MB line in the processor's processing range, the leftmost MB among the unprocessed MBs in the top (first) MB line of this processing range Processing as the target MB is performed. Since each processor # 1, # 2 or each dedicated hardware (decoder) is in charge of 3 MB lines, the process of performing one synchronization process for the process of 3 MBs in this way, Repeat until the end of the processing range (the rightmost MB of the bottom MB line) is reached. In this way, the processing is repeated until the processing of all MBs in each processing range is completed.

  That is, as shown in FIG. 10, when the processing of the leftmost target MB “1” of the first MB line is completed, the processor # 1 determines the second MB line located below the MB “1”. Processing is performed with the leftmost MB “2” as the target MB. Next, processing is performed with the leftmost MB “3” of the third MB line located below MB “2” as the target MB. Next, the leftmost MB “4” of the first MB line is processed as the target MB, and MBs “5” and “6” in the second and third MB lines located below are processed. Process as the MB of interest. Thereafter, similarly, the process of performing one synchronization process for the process of three MBs is repeated until the end of the processing range (the rightmost MB of the lowest MB line) is reached.

  On the other hand, the processor # 2 performs processing in the same processing order as the processor # 1, but the processing result of the processor # 1 transferred in the synchronous processing is processed for the processing of the first MB line to be processed first. Use. That is, when the first three MBs are processed by the processor # 1, the processing result of the MB “3” of the third MB line is used, and the first MB line processed by the processor # 2 is processed. The processing of the leftmost noticed MB “1” of the MB line is performed. When the processing of the leftmost noticed MB “1” of the first MB line is completed, the process is performed with MB “2” of the second MB line as the noticed MB. Processor # 2 thereafter processes all MBs in the processing range using the processing order of processor # 1 and the processing result of processor # 1 for the processing of the first MB line. Repeat the process until is finished.

  If the number of MB lines in the processing range handled by each processor # 1, # 2 or each dedicated hardware (decoder) is N, N MB processing and one synchronization processing will reach the right end of the processing range. Repeat until Thereby, in the repetition part of a processing range, one synchronous process is needed for every N MB, and a synchronous process can be reduced to 1 / N compared with the said comparative example.

  FIG. 11 is a flowchart for explaining the outline of the processing of the second embodiment. The process shown in FIG. 10 is executed by the processor 21. The processor 21 is an information processing apparatus having a known configuration including a CPU, a storage unit, and the like, and the decoding apparatus has a configuration in which a plurality of such processors 21 are connected so as to be capable of parallel processing.

  In FIG. 11, step S21 repeats the processing of steps S22 and S23 until the rightmost MB of each MB line in the processing range is processed. In step S22, N MBs are processed, and in step S23, synchronization processing including waiting for completion of processing, data transfer, and the like is performed. In step S24, it is determined whether or not steps S21 to S23 have been performed for the last MB line in the processing range. If the determination result is NO, the process returns to step S21, and if it is YES, the process ends.

  When two processors # 1 and # 2 are used for parallel processing as described above, each processor # 1 and # 2 performs the processing shown in FIG. 11, but in the case of processor # 2, attention is paid when performing processing on the target MB. The processing is the same as that in the case of the processor # 1 in that the data of the reference MB including the MB is required. However, in the MB line processed by the processor # 2, the processing of the first MB line is performed by the processor # 1. The only difference is that the processing result for the MB of the third MB line is used.

  FIG. 12 is a diagram for explaining the processing sequence and data transfer of the second embodiment when three processors are used, and FIG. 13 is a flowchart for explaining the processing of the three processors in the second embodiment. In FIG. 12, each rectangular area represents one MB, the numbers in each rectangular area indicate the processing order from the upper left to the upper right and the lower right of the processing range, and the thin solid arrows indicate data transfer. For convenience of explanation, the processing range in which each processor # 1, # 2, # 3 is in charge of processing is, for example, for each P, Q, R macroblock (MB) line in accordance with the processing performance, and each MB. A line shall consist of W MBs. Here, P, Q, R, and W are all integers of 2 or more, and P, Q, and R may be equal to or different from N, but are preferably smaller than W. In this embodiment, P, Q, and R satisfy the relationship P> R> Q, but the relationship is not limited to this. Each MB is composed of data of 16 × 16 pixels, for example.

  As shown in FIG. 12, when the processing for the target MB in one frame of the encoded image data to be processed is required as in the DF processing, the reference MB data including the upper part of the target MB is required. Processes in the correct order.

  FIG. 13 shows the processing of the three processors # 1, # 2, and # 3. The processor # 1 performs steps S201-1 to S207-1, the processor # 2 performs steps S201-2 to S207-2 and S211-2, and the processor # 3 performs steps S201-3 to S207-3 and S211-3. I do. In FIG. 13, substantially the same steps are indicated by subscripts “−1” to “−3” corresponding to the processors # 1 to # 3 attached to the same reference numerals.

  First, the processing of processor # 1 will be described. When the processing of the processor # 1 is started, the step S201-1 sets a variable i (integer) to i = 1. Step S202-1 performs processing of the i-th MB “i”, and step S203-1 determines whether or not the MB is located at the lower end of the processing range. If the decision result in the step S203-1 is NO, the step S204-1 performs a process on the MB below the current MB, and the process returns to the step S203-1. On the other hand, if the decision result in the step S203-1 is YES, a step S205-1 performs data transfer to the processor # 2, and a step S206-1 decides whether i = (W + P-1). . In the data transfer in step S205-1, the MB processing result of the Pth MB line is transferred to the processor # 2. If the decision result in the step S206-1 is NO, the step S207-1 increments i to i = i + 1, and the process returns to the step S202-1. If the decision result in the step S206-1 is YES, the process of the processor # 1 is finished.

  Next, the processing of processor # 2 will be described. When the processing of processor # 2 is started, step S201-2 sets variable i (integer) to i = 1. In step S211-2, a synchronization process for waiting for data transfer from the processor # 1 is performed. Therefore, initially, the processing result of the MB of the Pth MB line processed by the processor # 1 that is necessary for the processor # 2 to process the first MB “1” of the first MB line is the processor # 2. When transferred from 1, the process proceeds to step S202-2. The other processing of the processor # 2 is basically the same as the processing of the processor # 1, but step S206-2 determines whether i = (W + Q-1).

  Next, the processing of processor # 3 will be described. When the processing of processor # 3 is started, step S201-3 sets variable i (integer) to i = 1. A step S211-3 performs a synchronization process waiting for data transfer from the processor # 2. Therefore, initially, the processing result of the MB of the Qth MB line processed by the processor # 2 which is necessary for the processor # 3 to process the first MB “1” of the first MB line is the processor # 3. When transferred from 2, the process proceeds to step S202-3. The other processing of the processor # 4 is basically the same as the processing of the processor # 2, but step S206-3 determines whether i = (W + R-1).

  In each of the above embodiments, the decoding apparatus performs the above-described MB unit processing on the encoded image data to be processed by software processing of a plurality of processors. When performing the above-described MB unit processing by hardware processing, it is possible to use a plurality of physically separate decoders as a decoder, or physically use a plurality of decoder units within a single decoder. It goes without saying that it is good.

  The present invention relates to H.264. The present invention can be applied to image processing that requires complicated data-dependent processing such as H.264 decoding processing.

  While the present invention has been described with reference to the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments, and various modifications and improvements can be made within the scope of the present invention.

Claims (12)

A decoding method for performing parallel processing in units of macroblocks on a plurality of processing units for encoded image data to be processed,
Assign multiple macroblock lines to the processing range that each processing unit is in charge of processing,
The process of the first several target macroblock to respective processing unit to process said target macroblock using the processing result of the reference macroblock of the macroblock line remarked macroblock preceding one from the macroblock lines belonging And performing synchronization processing for each of the second several macroblocks after the processing of the first several macroblocks ,
The target macroblock of the first macroblock line within the processing range of the second processing unit is processed using the processing result of the reference macroblock of the last macroblock line within the processing range of the first processing unit. A decoding method characterized by the above. The decoding method according to claim 1, wherein the processing of the plurality of processing units is performed by software processing of a plurality of processors or hardware processing of a plurality of decoders. The processing of each processing unit is H.264. 264-AVC standard intra prediction or motion vector prediction,
The decoding method according to claim 1 or 2, wherein the reference macroblock is located at the upper right of the corresponding macroblock of interest. The processing of each processing unit is H.264. 264-AVC standard compliant deblocking filter processing,
The decoding method according to claim 1 or 2, wherein the reference macroblock is positioned above the corresponding target macroblock. 5. The decoding method according to claim 1, wherein the first number is represented by N (N + 1) / 2, where N is the number of the plurality of macroblock lines . The second number is the number of the macroblock lines
The encoding method according to claim 1, wherein: A plurality of processing units that perform parallel processing of encoded image data to be processed in units of macroblocks,
A plurality of macro block lines are assigned to the processing range in which each processing unit is in charge of processing,
Processing of the first several target macroblock to respective processing unit to process the remarked macroblock using said processing result of one preceding reference macroblock of the macroblock line from macroblock line belonging target macroblock And a synchronization process is performed for each of the second several macroblocks after the processing of the first several macroblocks ,
Using the processing result of the reference macroblock of the last macroblock line within the processing range of the first processing unit, the target macroblock of the first macroblock line within the processing range of the second processing unit is processed. A decoding device characterized by the above. 8. The decoding apparatus according to claim 7 , wherein the plurality of processing units include a plurality of processors that perform software processing or a plurality of decoders that perform hardware processing. The processing of each processing unit is H.264. 264-AVC standard intra prediction or motion vector prediction,
The decoding apparatus according to claim 7 or 8 , wherein the reference macroblock is located at an upper right of the corresponding macroblock of interest. The processing of each processing unit is H.264. 264-AVC standard compliant deblocking filter processing,
The decoding device according to claim 7 or 8 , wherein the reference macroblock is located on the corresponding target macroblock. The decoding apparatus according to any one of claims 7 to 10 , wherein the first number is represented by N (N + 1) / 2 where N is the number of the plurality of macroblock lines . The second number is the number of the macroblock lines
The decoding device according to any one of claims 7 to 11.

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