JPH11234678A - Image transmission method by splitting - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image transmission method by splitting in order to encode an image received in various formats efficiently at pluralities of coders in the coders in common use for high definition HD TV/n-channel standard definition SD TV. SOLUTION: An image received by a video signal distributor 2 is divided into a size of a SDTV valid pixel or below to be pixels of a multiple of 16 in longitudinal and lateral directions and fed to each of coders 31-3n to attain excellent coding. For example, in the case of dividing an HDTV image, one line is divided into pluralities of liens to form an image fed to each coder to be lateral 720 pixels × longitudinal 480 lines (45MB × 30MB), so that the coders are used efficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal encoding apparatus for encoding video signals of various formats such as a high quality video signal (HDTV signal) and a normal quality video signal (SDTV signal). The present invention relates to an image division transmission method for inputting a video signal to an encoder.

[0002]

2. Description of the Related Art In recent years, digitization of image information has been studied in view of a demand for higher image quality. However, digitizing an image generally requires a huge amount of data. Data compression is performed by an encoding device. As a method of compressing the image signal, a high efficiency coding method employing transform coding such as DCT (Discrete Cosine Transform) having a high compression rate and small deterioration of image quality due to compression has become mainstream. In this high-efficiency coding method, one frame of an input image signal is divided into, for example, a block of 16 pixels × 16 pixels, and DCT processing is performed for each block (DCT block). JPEG (Joint Photo) is one of the high-efficiency
graphic Coding Experts Group) and H.C. 261 etc., and MPEG (Moving
Picture Experts Group) 1 and MPEG2.

[0003] In these standards, not only compression by DCT (intra-frame compression) within one frame but also inter-frame compression for reducing redundancy in the time axis direction by using correlation between frames is adopted. I have. This inter-frame compression utilizes the property that a general moving image is very similar in the preceding and succeeding frames, and obtains a difference between the preceding and succeeding frames and calculates a difference value by DC.
By performing the T processing, the bit rate is further reduced.

[0004] Recently, an IC (integrated circuit) chip and an IC chipset equipped with an encoding circuit and a decoding circuit which enable encoding and decoding in accordance with these standards have been developed. In these IC chips or IC chip sets, usually, the number of video pixels that can be processed alone is determined. For example, in an IC chip or an IC chip set for a current NTSC television signal, an HDTV (High
-Definition TV) television signals cannot be processed alone.

In order to encode and decode a video signal having a pixel number exceeding the number of video pixels that can be processed by an IC chip or an IC chip set alone, a plurality of IC chips or IC chip sets are prepared and an input stage is provided. And then supplies it to each IC chip or IC chip set. That is, at the time of encoding, an input video signal is divided into a plurality of pieces and supplied to each IC chip or IC chip set. At the time of decoding, an encoded bit stream is divided into a plurality of pieces and each
To give to chips or IC chipset.

[0006] Fig. 3 shows a configuration diagram of such a conventional HDTV encoder (encoder). In FIG.
When the video signal for use is input to the video signal distributor 2, the screen is divided into n in the slice direction as shown in FIG. 2 and supplied to the respective encoding units 31 to 3n. In order to improve the coding efficiency especially near the slice boundary, the data locally decoded in each of the coding units 31 to 3n is supplied to the adjacent coding units 31 to 3n via the local signal line 4. ,
Encoding is performed in each of the encoding units 31 to 3n.

[0007] Thereafter, the video signal of the divided screen encoded by the encoding unit 31 is supplied to the output interface (I / F) 6 through the system bus 5 and output as a bit stream. The video signals of the respective divided screens encoded by the encoding units 32 to 3n are sequentially transferred to the encoding units 31 to 3 (n-1) via the local signal line 4 and passed through the system bus 5. Output interface (I / F)
6 is output as a bit stream. Note that CP
A U (central processing unit) 1 is a control unit that performs overall signal control including these timings.

[0008] In recent years, video programs for HDTV signals have been increasing, but there is still much demand for video programs for NTSC signals. And in the United States, HDTV signals and N
It is required that one encoding device encodes both video signals of the HDTV signal and the NTSC signal, for example, such as a broadcast mixed with a TSC signal. In such a situation, when considering an HDTV / n-channel SDTV shared coding apparatus, a configuration as shown in FIG. 4 can be considered. Each of the encoding units 31 to 3n is composed of an IC chip that can encode a single channel SDTV signal by itself.

[0009] In FIG. 1, when an HDTV signal is input, the same operation as that of the above-described HDTV encoder is shown in FIG. And, for example, NTS
An n-channel SDTV signal such as C
Is input to each of the encoding units 31 to 31 for each channel.
3n. The video signals encoded by the encoding units 31 to 3n are respectively output to output interfaces (I / Fs) 61 to 6 via system buses 5b, 5a and 5c.
n and output as a bit stream for each channel.

[0010]

When a video signal encoding apparatus as shown in FIG. 4 is considered to realize an HDTV / n-channel SDTV shared encoding apparatus, a video signal distributor (video division apparatus) 2 requires: In accordance with the format of the input video signal, it is necessary to appropriately distribute the video signal to each of the encoding units 31 to 3n. However, conventionally, there is no such an encoding device, and thus the video signal is efficiently distributed according to the format of the video signal. The way was not considered.

Accordingly, the present invention provides an image division transmission method for efficiently encoding an image input in various formats with a plurality of encoders in such an HDTV / n-channel SDTV shared encoding device. The purpose is to do.

[0012]

As means for solving the above-mentioned problems, the following image division transmission method is provided.

[0013] 1. An image division transmission method for dividing a screen of an input digital image signal and supplying the divided screen to a plurality of encoders, wherein the screen of the input image signal is divided by the number of pixels in a vertical direction of a DCT macroblock. Is divided into divided images having a number of pixels in the vertical direction and an integer number of pixels in the horizontal direction that are integral multiples of the number of pixels in the SDTV screen and an integer less than the number of effective pixels in the SDTV screen. An image division transmission method, wherein one encoder is transmitted so as to correspond to one divided image.

[0014] 2. In the image division transmission method described in 1 above,
In the divided image supplied to one encoder, the number of pixels in the vertical direction and the number of pixels in the horizontal direction are each an integral multiple of 16 with respect to the luminance signal, and the vertical direction is 480 lines or less and the horizontal direction is 720 pixels or less. An image division transmission method, characterized in that:

[0015] 3. In the image division transmission method according to the above item 1,
If the number of vertical pixels of the screen of the input image signal is not an integer multiple of the number of vertical pixels of the DCT macroblock, or if the number of horizontal pixels is not an integer multiple of the number of horizontal pixels of the DCT macroblock,
An image division transmission method, wherein a divided image is generated after adding a dummy pixel so as to be an integral multiple.

[0016] 4. An image division transmission method according to any one of the above [1] and [2] or [3], wherein the division image is transmitted at the same pixel rate as the SDTV pixel rate.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In an MPEG encoding apparatus using a plurality of SDTV encoders, the number of pixels that can be encoded by each encoder is limited to the number of pixels of an SDTV image. That is, in the case of the NTSC broadcasting system, one screen (one frame) is composed of 704 pixels (pixels) in the horizontal direction (horizontal direction) × 480 lines in the vertical direction (vertical direction). It is sufficient if the encoding can be performed, but a normal SDTV encoder can encode a common intermediate format of 720 pixels horizontally and 576 lines vertically established in consideration of compatibility with the PAL broadcasting system and the like. Designed for

Hereinafter, M using a plurality of SDTV encoders will be described.
An embodiment of an image division transmission method will be described using an example of an image division apparatus that distributes and supplies an image signal to each encoder in a PEG encoding apparatus. In this SDTV encoder, the horizontal 16 (pixel) based on the luminance signal
X Encoding is performed in units of DCT macroblocks of 16 (vertical) pixels, so that one encoder is 45 x 36 = 1
It is possible to encode 620 blocks.

Therefore, the input image is divided into 1620 blocks or less in units of 16 (pixels) × 16 (pixels) DCT macroblocks, and the image is divided into multiples of 16 in both the vertical and horizontal directions. If supplied to the encoder, good encoding can be performed. Further, for example, in the case of dividing an HDTV image, one line is divided into a plurality of lines, and an image to be supplied to one encoder is horizontally 720 (pixels) × 480 vertically (4 lines).
With 5 MB × 30 MB), the encoder can be used efficiently.

In the ordinary SDTV encoder described above, the SDTV whose clock frequency (pixel rate of the luminance signal (Y)) of the D1 interface is 13.5 MHz is used.
It operates by input on the interface. Therefore, when an image for HDTV or an image with another pixel rate supplied at a pixel rate of 74.25 MHz of the luminance signal is input, the pixel rate of the luminance signal is set to 1
By setting the frequency to 3.5 MHz, it is possible to transmit to the encoder in the same transmission format irrespective of the type of the input image, so that it is possible to use a normally used SDTV image encoder. It is possible to provide an inexpensive encoding device.

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. First, FIG. 1 shows an example of a frame configuration of an image input to the image dividing apparatus of the present invention. In the figure, w indicates the number of pixels arranged in the horizontal direction of the screen, and L indicates the number of lines arranged in the vertical direction of the screen. Then, SAV (START AV) and EAV (END
AV) is data indicating the start and end of a line, respectively, and is data conforming to the SMPTE standard.

The following table shows the line numbers (L) of the lines which are the boundaries of the effective pixels of the HDTV (interlace) image signal, the 720 (progressive) image signal, and the 480 (progressive) image signal in the image frame configuration example.
(A) to L (D)) and the number of pixels in the horizontal direction (aw,
bw). In the progressive mode 720P and 480P image signals, only one field up to the line number 250 is defined.

Various digital image signals to be input are supplied to the image dividing device (the video signal distributor 2 in FIG. 4) in such a frame configuration. When the pixel order at this time is represented using the pixel number of the luminance signal, the luminance signal (Y) and the color difference signals (Cb, Cr) are represented by Cb0, Y0, Cr.
0, Y1, Cb2, Y2, Cr2, Y3,...

Next, a clock generation process in the image dividing apparatus when an HDTV image is input will be described with reference to a block diagram shown in FIG. In the image division device 2 of the video signal encoding device shown in FIG.
When an HDTV video signal of 1024 lines × 30 frames is inputted, a clock is generated by a clock generator as shown in FIG. 5 to create divided screens to be output to the encoders 31 to 3n. The input HD
The total number of pixels of the video signal for TV is 2200 pixels × 11
It is assumed that 25 lines × 30 frames.

The respective frequencies of the input HDTV image are frame frequency fv = 30 Hz and line frequency fh =
fv × 1125 = 33.75 kHz and sampling frequency fs = fh × 2200 = 74.25 MHz. At this time, each frequency of the divided screen output from the image dividing device 2 is set to a frame frequency pfv = 30 Hz and a line frequency pf
h = 15 kHz, sampling frequency pfs = 13.5 MH
If z, the number of line samples is pfs / pfh = 90
0 samples and the number of lines per frame is pfh
/ Pfv = 500 lines.

In FIG. 5, the line frequency fh of the HDTV image can be obtained by detecting the horizontal synchronization signal of the input HDTV image. Then, the line frequency fh is supplied to one input of the phase comparator 80. The phase comparator 80 outputs the phase difference from the other input to the voltage variable crystal oscillator 82. The voltage variable crystal oscillator 82 generates a clock signal having a phase adjusted frequency of 74.25 MHz (sampling frequency fs). This signal is divided by a 1/2200 frequency divider 8
4 to be divided, and supplied as a 33.75 kHz signal to the other input of the phase comparator 80 to match the phase with the line frequency fh of the input HDTV image.

Further, the signal (pfs / 2) divided by the 1/11 divider 85 is supplied to one input of the phase comparator 81. The phase comparator 81 outputs the phase difference from the other input to the voltage variable crystal oscillator 83. The voltage variable crystal oscillator 83 generates a clock signal having a phase-adjusted frequency of 27 MHz (twice the sampling frequency pfs). Then, this signal is １ ／
The sampling frequency pfs (1
A signal of 3.5 MHz is output and further supplied to a １ ／ frequency divider 86, and a signal obtained by dividing pfs by １ ／ is supplied to the other input of the phase comparator 81.

A clock signal having a frequency twice the sampling frequency pfs output from the variable voltage crystal oscillator 83 is supplied to a 1/1800 frequency divider 88 and
/ 1800 (1/2 times the number of line samples) to output a line frequency pfh, and this signal is further supplied to a 1/500 frequency divider 89 to be 1/500
(1 / number of lines per frame), and outputs the frame frequency pfv.

[0029] With this configuration, the frame frequency pfv, the line frequency pfh, and the sampling frequency pf of the divided screen are obtained from the line frequency fh of the HDTV image.
s can be output. Further, the sampling frequency fs and frame frequency fv (= pf
Since v) can also be output, a divided screen can be easily output by using clock signals of these frequencies.

Hereinafter, a method of dividing and transmitting various input images having the configuration shown in FIG. 1 will be described. First, a case where an HDTV image (1920 × 1080) is input at a sampling frequency of 74.25 MHz in an interlace will be described with reference to FIGS. 6 to 9.

[0031] The HDTV image input through the interlace is
As shown in FIG. 6, considering only luminance signals in odd and even frames, 1920 pixels horizontally and 54 pixels vertically, respectively.
Pixels of 0 line (pixel) are input. Then, since the encoder at the subsequent stage encodes each frame for each 16 (pixel) × 16 (pixel) macroblock, each frame is added with four lines of dummy pixels to make 544 vertical lines and 120 horizontal lines. Block, length 68
Encoding is performed using a macro block (MB) of a block. Here, one encoder uses 1 as described above.
Since only 620 blocks can be encoded, first, considering division in the slice direction of the screen, eight encoders (corresponding to the encoders 31 to 38 in FIG. 4; The divided image divided into 64 lines (4 MB vertically) is input to the ninth encoder (corresponding to the encoder 39 in FIG. 4, but not shown).
A divided image of a line (vertical 2 MB) is input.

At this time, the sampling frequency is 74.25 MH
Therefore, as shown in FIG. 7A, one line of the divided image input to the eight encoders is divided into three every 640 pixels, and divided as shown in FIG. 7B. Considering a macro block of 16 pixels horizontally × 16 pixels vertically after arranging lines vertically, the sampling frequency is 1
A divided image of 12 blocks (192 lines) is vertically formed at 3.5 MHz. The divided images thus formed are
In addition to the output to the encoders, the ninth encoder divides one line into three for each 640 pixels as shown in FIG. 8A, and is divided as shown in FIG. By outputting a divided image of 6 blocks (96 lines) in which lines are arranged vertically, an HDTV image can be satisfactorily encoded by nine encoders having an SDTV interface.

The structure of the 4: 2: 2 HDTV image is as follows.
As shown in FIG. 9, the 8-bit luminance sample point is 1 /
While sampling is performed at every (13.5 MHz) (13.5 M rate), the color difference signals Cb and Cr (8 bits each) are each halved at 1 / (6.75 MHz) (6.7 pixels).
(5M rate) sample points, which are input in parallel. Accordingly, the input format to the encoder after the conversion into the divided screen has the same relationship.
Cb0, Y0, Cr0, Y1, Cb2, Y at M rate
2, Cr2, Y3,...

Next, a case where a progressive (non-interlace) 4: 3 high-definition image (720P: 1280 × 720) is input at a sampling frequency of 74.25 MHz will be described with reference to FIGS. . FIG.
As shown in the figure, since the number of macroblocks per frame is 80 blocks in width and 45 blocks in length, considering division in the slice direction of the screen, 112 lines (7 MB in height) are assigned to each of the six encoders. The divided image is input to the seventh encoder, and 48 lines (3 MB vertically) are input to the seventh encoder.
Will be input.

At this time, the sampling frequency is 74.25 MH
Therefore, as shown in FIG. 11A, one line of the divided image input to the six encoders is divided into two for each 640 pixels, and divided as shown in FIG. 11B. Considering a macro block of 16 pixels horizontally × 16 pixels vertically after arranging lines vertically, the sampling frequency is 1
A divided image of 14 blocks (224 lines) is vertically formed at 3.5 MHz. The divided image thus formed is represented by 6
In addition to the output to each of the encoders, the seventh encoder divides one line into two for each 640 pixels as shown in FIG. 12A and is divided as shown in FIG. 6 blocks (96 lines) with lines arranged vertically
, A 720P high-definition image can be satisfactorily encoded by seven encoders having an SDTV interface.

As shown in FIG. 13, the structure of the 4: 2: 2 720P high-definition image is such that 8-bit luminance sample points are sampled at 1 / (13.5 MHz) at 13.5 M rate. On the other hand, each of the color difference signals Cb and Cr (8 bits each) is a half (1 / 75.75 MHz) (6.
75M rate), and these are input in parallel. Therefore, the input format to the encoder after the conversion into the divided screen also has the same relationship.
Cb0, Y0, Cr0, Y1, Cb2, Y at 7M rate
2, Cr2, Y3,...

[0037] Finally, progressive (non-interlace)
FIG. 14 shows a case where a 4: 3 image (480P: 720 × 480) is input at a sampling frequency of 27 MHz.
This will be described with reference to FIGS. As shown in FIG. 14, since the number of macroblocks per frame is 45 blocks in width and 30 blocks in height, considering division in the slice direction of the screen, 240 lines (15 MB in height) are assigned to each of the two encoders. ) Each divided image is input.

At this time, since the sampling frequency is 27 MHz, as shown in FIG. 15A, one line of the divided image input to each encoder remains at 720 pixels, as shown in FIG. And the sampling frequency is 13.5 MH
With z, a divided image of 15 blocks (240 lines) is completed vertically. By outputting the divided images thus formed to two encoders, a 480P image can be satisfactorily encoded by two encoders (for interless) having an SDTV interface.

As shown in FIG. 16, the structure of the 4: 2: 2 480P high-definition image is such that 8-bit luminance sample points are sampled at every 1 / (13.5 MHz) (13.5 M rate). On the other hand, each of the color difference signals Cb and Cr (8 bits each) is a half (1 / 75.75 MHz) (6.
75M rate), and these are input in parallel. Therefore, the input format to the encoder after the conversion into the divided screen also has the same relationship.
Cb0, Y0, Cr0, Y1, Cb2, Y at 7M rate
2, Cr2, Y3,...

[0040]

As described above, according to the image division transmission method of the present invention, a divided image having a size divisible by a DCT macroblock (16 × 16 pixels) and a size equal to or smaller than an effective pixel of an SDTV is obtained. Therefore, if a plurality of SDTV encoders are prepared, even high-definition images such as HDTV can be satisfactorily encoded.

The present invention can be implemented by adding dummy pixels to an image having a size that cannot be divided by a DCT macroblock (16 × 16 pixels).
Further, the pixel rate supplied to each encoder is represented by SDT.
V is the same as the pixel rate of normal SDTV
The encoder for use can be used as it is, and there is an effect that an encoding device corresponding to various input images can be manufactured at low cost.

[Brief description of the drawings]

FIG. 1 is a configuration diagram for explaining a frame configuration of a video signal input in an embodiment of an image division transmission method according to the present invention.

FIG. 2 is a diagram illustrating an example of screen division of an HDTV video signal.

FIG. 3 is a configuration diagram illustrating an example of a conventional HDTV video signal encoding device.

FIG. 4 is a configuration diagram illustrating an example of an HDTV / SDTV shared video signal encoding device.

FIG. 5 is a block diagram showing an embodiment of a clock generation device used in the image dividing device.

FIG. 6 is a diagram for explaining a method of dividing and transmitting an HDTV image.

FIG. 7 is a diagram for explaining divided images of HDTV images input to encoders 1 to 8;

8 is a diagram for explaining a divided image of an HDTV image input to an encoder 9. FIG.

FIG. 9 is a diagram for explaining a sample structure of an HDTV image.

FIG. 10 is a diagram for explaining a method of dividing and transmitting a 720P image.

FIG. 11 is a diagram for describing a divided image of a 720P image input to encoders 1 to 6;

12 is a diagram for describing a divided image of a 720P image input to the encoder 7. FIG.

FIG. 13 is a diagram illustrating a sample structure of a 720P image.

FIG. 14 is a diagram for explaining a method of dividing and transmitting a 480P image.

FIG. 15 is a diagram illustrating a divided image of a 480P image input to encoders 1 and 2;

FIG. 16 is a diagram illustrating a sample structure of a 480P image.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU (control part) 2 Video signal distributor (image division apparatus) 31-3n Encoding part 4 Local communication line 5, 50-5n, 5a, 5b, 5c System bus 6, 61-6n Output interface (output I / F) 71-7n bus bridge

Claims (4)

[Claims] An image division transmission method for dividing a screen of an input digital image signal and supplying the divided screen to a plurality of encoders, wherein the screen of the input image signal is divided by the number of pixels in a vertical direction of a DCT macroblock. Is divided into divided images having a number of pixels in the vertical direction and an integer number of pixels in the horizontal direction that are integral multiples of the number of pixels in the SDTV screen and an integer less than the number of effective pixels in the SDTV screen. An image division transmission method, wherein one encoder is transmitted so as to correspond to one divided image. 2. The image division transmission method according to claim 1, wherein the number of pixels in the vertical direction and the number of pixels in the horizontal direction based on the luminance signal is an integral multiple of 16 pixels in the divided image supplied to one encoder. 480 lines or less in the vertical direction and 720 pixels or less in the horizontal direction. 3. The image division transmission method according to claim 1, wherein the number of vertical pixels on the screen of the input image signal is not an integral multiple of the number of vertical pixels of the DCT macroblock, or the number of horizontal pixels. An image division transmission method, wherein, when is not an integral multiple of the number of pixels in the horizontal direction of the DCT macroblock, a divided image is generated after adding a dummy pixel so as to be an integral multiple. 4. The image division transmission method according to claim 1, wherein the pixel rate of the divided image is set to be the same as the pixel rate of SDTV and transmitted. Transmission method.