JP2007178811A - Liquid crystal display apparatus and control method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display apparatus and a control method therefor, which can obtain dot-reversed picture quality while performing the same control as reversal between rows or columns, and is easy to manufacture, and can reduce power consumption. <P>SOLUTION: The liquid crystal display apparatus comprises: pixel arrays having liquid crystal elements (1, 2, 11), respectively; gate lines (G); source lines(S); and thin film transistor circuits (3 to 8, 12 to 15) in which the gates are connected to gate lines, and voltage is applied to the corresponding liquid crystal elements starting with one selected from among the source lines when the gate lines are activated, and these thin film transistor circuits are configured by connecting two or more transistors in series between the source line corresponding to each pixel and the liquid crystal element. The same operation as alternating current between row and column is attained by alternating current between rows or alternating current between columns by including a p-channel transistor depending on a pixel position. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device and a control method thereof.

  Images displayed on the liquid crystal display device are displayed in units of frames. In this case, a voltage is applied between the pixel electrode and the counter electrode in accordance with the brightness and color of the display image for each pixel in a frame unit. However, in order to improve display quality, an alternating current that inverts the voltage for each frame. Drive control is performed.

  Various types of AC drive control have been proposed in the past, such as inter-frame AC that inverts the polarity of the entire frame for each frame, inter-row AC or inter-column AC that inverts for each row or column, and a staggered unit. There is an inter-matrix exchange that is reversed by.

  In general, the write characteristics are not necessarily the same when the polarity is opposite, and the write characteristics vary locally. For this reason, a level asymmetry before and after inversion occurs and flicker is generated. Become. On the other hand, in the case of inter-frame exchange, a tendency for mismatched levels appears in the entire frame, so that flicker is likely to occur and the overall image quality is likely to be adversely affected. In the case of line-to-line exchange and column-to-column exchange, the image quality is intermediate between these.

  On the other hand, in the inter-frame alternating current, it is only necessary to invert all the pixels at the same time for each frame. Therefore, the control is extremely easy. It becomes.

  For this reason, the clock frequency for control can be lowered and the power consumption can be reduced in a method in which flicker hardly occurs with the same image quality.

  For this reason, it has been proposed to perform the same effect as dot inversion with simple control.

An example of this is disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2000-267634). In Patent Document 1, gate wiring for performing row selection is alternately wired between two rows for each column. What is being disclosed is disclosed.
JP 2000-267634 A

  However, in the device described in Patent Document 1, row selection control is as easy as usual and an image quality similar to that of dot inversion can be obtained. However, if the gate wiring does not meander between two rows for each column. In addition, there are problems that there are manufacturing difficulties and unnecessary parasitic capacitance is likely to occur.

  The present invention has been made to solve such a conventional problem. While performing the same control as the inversion between rows or columns, the image quality of dot inversion can be obtained, the manufacturing is easy, and the power consumption is reduced. An object of the present invention is to provide a liquid crystal display device and a control method thereof that can be reduced.

According to a first aspect of the invention,
A pixel array arranged in a matrix and each having a liquid crystal element;
Gate lines provided in a plurality of row units of the pixel array;
Source lines provided in a plurality of column units of the pixel array;
A thin film transistor circuit for applying a voltage to the corresponding liquid crystal element from a selected one of the source lines when a gate is connected to the gate line and the gate line is activated;
The thin film transistor circuit is formed by connecting a plurality of transistors including a combination of an n-channel transistor and a p-channel transistor between a corresponding source line and a liquid crystal element for each pixel in series. Is provided.

According to a second aspect of the invention,
A pixel array arranged in a matrix and each having a liquid crystal element;
A gate line provided in a row unit of the pixel array and provided between two pairs of rows;
A plurality of source lines that are provided in units of columns of the pixel array and supply voltages of opposite polarities for each column;
Left and right selection lines that are provided between the pair of two rows and supply a signal for selecting one of the source lines on both sides of the pixel;
A first n-channel transistor and a p-channel transistor connected in series and having a gate connected to the left and right selection line, and a connection point between these connection points and the liquid crystal element, and a gate connected to a gate line corresponding to the liquid crystal element An active matrix liquid crystal display device including the second n-channel transistor is provided.

According to a third aspect of the invention,
A pixel array arranged in a matrix and each having a liquid crystal element;
A counter electrode provided on the entire pixel array;
Gate lines provided in a plurality of row units of the pixel array;
Source lines provided in a plurality of column units of the pixel array;
A thin film transistor circuit for applying a voltage to the corresponding liquid crystal element from a selected one of the source lines when a gate is connected to the gate line and the gate line is activated;
An auxiliary capacitor provided between a connection point between the transistor and the liquid crystal element and the counter electrode;
The thin film transistor circuit is formed by connecting a plurality of transistors including a combination of an n-channel transistor and a p-channel transistor between a corresponding source line and a liquid crystal element for each pixel in series. Is provided.

According to a fourth aspect of the invention,
A pixel array arranged in a matrix and each having a liquid crystal element;
A counter electrode provided on the entire pixel array;
A gate line provided in a row unit of the pixel array and provided between two pairs of rows;
A plurality of source lines that are provided in units of columns of the pixel array and supply voltages of opposite polarities for each column;
Left and right selection lines that are provided between the pair of two rows and supply a signal for selecting one of the source lines on both sides of the pixel;
A first n-channel transistor and a p-channel transistor connected in series and having a gate connected to the left and right selection line, and a connection point between these connection points and the liquid crystal element, and a gate connected to a gate line corresponding to the liquid crystal element A second n-channel transistor,
There is provided an active matrix liquid crystal display device including a connection point between the second n-channel transistor and the liquid crystal display element and an auxiliary capacitor provided between the counter electrodes.

According to a fifth aspect of the present invention,
A pixel array arranged in a matrix and each having a liquid crystal element;
Gate lines provided in a plurality of row units of the pixel array;
Source lines provided in a plurality of column units of the pixel array;
A thin film transistor circuit for applying a voltage to the corresponding liquid crystal element from a selected one of the source lines when a gate is connected to the gate line and the gate line is activated;
An auxiliary capacitor connected to a connection node of the thin film transistor circuit and the liquid crystal display element;
A counter electrode connected to the auxiliary capacitor,
The counter electrode stores a large amount of electric charge in the auxiliary capacitor during writing of the liquid crystal element, and the potential is changed so as to increase the absolute value of the potential of the connection node of the liquid crystal display element after the writing is completed. An active matrix display device is provided.

  In the first and second aspects of the present invention, a plurality of transistors each having a gate line connected to a liquid crystal display element are provided for each pixel, and this is selectively controlled, so that the same image quality as inter-matrix AC control is achieved by inter-row AC control. In addition, since the clock frequency can be reduced if the image quality is the same, power consumption can be reduced.

  In the third and fourth aspects of the present invention, the polarity of the source line is alternated for each column, and the transistor driven by the gate line is appropriately selected in the transistor circuit composed of a plurality of transistors, so that With AC control, it is possible to obtain the same image quality as with inter-matrix control, and if the image quality is the same, the clock frequency can be reduced, so that power consumption can be reduced.

  In the fifth aspect of the present invention, the auxiliary capacitor connected to the connection node of the thin film transistor circuit and the liquid crystal display element is made to change the potential of its counter electrode, so that more charge is accumulated in the auxiliary capacitor during writing of the liquid crystal element. Since the potential is changed so as to increase the absolute value of the potential of the connection node of the liquid crystal display element after the writing is completed, writing of the liquid crystal can be performed with a lower voltage, and power consumption can be reduced.

  Hereinafter, some embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a circuit diagram showing a configuration of a control circuit in a pixel portion in the liquid crystal display device according to the first embodiment of the present invention.

  FIG. 1 shows a control circuit for four rows and three columns, and a pair of two gate lines GaN and GbN and a next pair of GaN + 1 and GbN + 1 are shown between two adjacent rows. . Here, a configuration for two rows and two columns in the upper left will be described.

The liquid crystal 1 _MN is connected to the source line SM via an n-channel transistor 3 _MN and an n-channel transistor 5 _MN connected in series with the n-channel transistor 3 _MN. The gate of the transistor 3 _MN is connected to the gate line GaN and the gate of the transistor 5 _MN is connected. Is connected to the gate line GbN.

The liquid crystal 2 _MN in the next row is connected to the source line SM via an n-channel transistor 4 _MN and a p-channel transistor 6 _MN connected in series to the liquid crystal 2 _MN. The gate of the transistor 4 _MN is connected to the gate line GaN. the gate of the transistor _{6 MN} is connected to the gate line GBN.

In the next column, the liquid crystal 1 _{(M + 1) N} is connected to the source line SM + 1 via the n-channel transistor 3 _{(M + 1) N} and the p-channel transistor 5 _MN connected in series _therewith , and the transistor 3 _{(M + 1)} The gate of _N is connected to the gate line GaN, and the gate of the transistor 5 _{(M + 1) N} is connected to the gate line GbN.

The liquid crystal 2 _{(M + 1) N} in the next row is connected to the source line SM + 1 via an n-channel transistor 4 _{(M + 1) N} and an n-channel transistor 6 _{(M + 1) N} connected in series to the liquid crystal 2 _{(M + 1) N.} The gate of _MN is connected to the gate line GaN, and the gate of the transistor 6 _MN is connected to the gate line GbN.

  In conventional liquid crystal display devices, p-channel transistors were never used due to manufacturing limitations, but recently, low-temperature polysilicon technology has been used, and as a result, p-channel transistors can be formed. It is.

  2 and 3 are waveform diagrams showing voltage waveforms applied to the source line and the gate line in such a circuit, and FIG. 3 shows a voltage waveform after one vertical scanning period (field period) in FIG.

As shown in FIGS. 2 and 3, the source potential alternates every horizontal scanning period. First, as shown in FIG. 2, when the gate lines GaN and GbN are both high, the n-channel transistor 3 _MN and the n-channel transistor 5 _MN connected in series thereto are turned on, so that a positive source voltage is applied to the liquid crystal 1 _MN. Is applied. At this time, in the adjacent column, a positive source voltage is applied to the liquid crystal 2 _{(M + 1) N} in the next row.

In the next horizontal scanning period, the gate lines GaN is high, the gate lines GbN becomes wax, p-channel transistor 6 _MN conducts while the n-channel transistor 5 _MN is interrupted, the negative source to the liquid crystal 2 _MN A voltage is applied. In the adjacent column, a negative source voltage is applied to the liquid crystal 1 _{(M + 1) N} in the previous row.

  In the next horizontal scanning period, the driven gate line shifts to the next set of GaN + 1 and GbN + 1, and thereafter the same operation is sequentially repeated on all the gate lines. Therefore, the liquid crystal to which a positive source voltage is applied and the liquid crystal to which a negative source voltage is applied are in a staggered arrangement.

  In the next vertical scanning period shown in FIG. 3, the potential of the gate line Gb is inverted. As a result, the polarity of the voltage applied to each liquid crystal is completely opposite to that shown in FIG.

  In this way, two transistors are arranged in series between the liquid crystal and the gate wiring in each pixel, and two of the adjacent rows and columns are n-channel, and one of the two is a p-channel. Thus, inter-matrix AC type liquid crystal driving can be performed without requiring complicated gate wiring or connection of special liquid crystal.

FIG. 4 shows a modification of the configuration shown in FIG. 1, and employs a configuration in which three transistors connected in series are provided between a gate line and a liquid crystal. That is, in addition to the configuration shown in FIG. 1, an n-channel transistor 7 _MN is connected between the n-channel transistor 5 _MN and the source line SM, and an n-channel transistor is connected between the p-channel transistor 6 _MN and the source line SM. 8 _MN is connected. The gate of the added n-channel transistors _{7 MN} and _{8 MN,} as well as the gate of the transistor _{3 MN} and the transistor _{4 MN} is connected to the gate line GaN. Such a configuration is the same in adjacent rows.

  In the configuration shown in FIG. 4, since the p-channel transistor is interposed between two n-channel transistors that can be stably formed, there are few malfunctions.

In FIG. 5, the two transistors added in FIG. 4 are shared by one transistor. The n-channel transistor _7MN in FIG. 4 is omitted, and the transistor _5MN is also connected in series to the transistor _8MN .

  In this embodiment, stable operation can be expected despite the fact that the number of transistors is one less than in the case of FIG.

  Although the above embodiment has been described by taking the inter-row alternating current as an example, it is also possible in the case of the inter-column alternating current. FIG. 6 is a circuit diagram showing an example of a configuration that realizes inter-column alternating current. Here, a configuration of (n to n + 3) rows (m to m + 2) columns is shown, but in particular, (n to n + 1) rows ( The m to m + 1) columns will be described in detail.

First, looking at m columns and n rows, an n-channel transistor 12 _mn and a p-channel transistor 14 _mn are connected in series between the source line Sm and the source line Sm + 1 of the next column, and their gates are connected to the left and right selection lines L / R. Has been. An n-channel transistor 13 _mn is connected between a connection node between the transistor 12 _mn and the transistor 14 _mn and the liquid crystal 11 _mn , and its gate is connected to the gate line Gn.

In the next row of the same column, a p-channel transistor 12 _{m (n + 1)} and a p-channel transistor 14 _{m (n + 1)} are connected in series between the source line Sm and the source line Sm + 1 of the next column, and these gates are connected to the left and right selection lines. Connected to L / R. An n-channel transistor 13 _{m (n + 1)} is connected between a connection node between the transistor 12 _{m (n + 1)} and the transistor 14 _{m (n + 1)} and the liquid crystal 11 _{m (n + 1)} , and its gate is connected to the gate line Gn + 1. .

As for the adjacent m + 1 column, in the nth row, an n-channel transistor 12 _{(m + 1) n} and a p-channel transistor 14 _{(m + 1) n} are connected in series between the source line Sm + 1 and the source line Sm + 2 in the next column, and these gates are It is connected to the selection line L / R. An n-channel transistor 13 _{(m + 1) n} is connected between a connection node between the transistor 12 _{(m + 1) n} and the transistor 14 _{(m + 1) n} and the liquid crystal 11 _{(m + 1) n} , and its gate is connected to the gate line Gn. .

In the next row of the same column, a p-channel transistor 12 _{(m + 1) (n + 1)} and an n-channel transistor 14 _{(m + 1) (n + 1)} are connected in series between the source line Sm + 1 and the source line Sm + 2 of the next column. Are connected to the left / right selection line L / R. An n-channel transistor 13 _{(m + 1) (n + 1)} is connected between a connection node between the transistor 12 _{(m + 1) (n + 1)} and the transistor 14 _{(m + 1) (n + 1)} and the liquid crystal 11 _{(m + 1) (n + 1)} , and the gate thereof is It is connected to the gate line Gn + 1.

  Next, control of this circuit will be described with reference to FIGS. FIG. 7 shows a waveform applied to the left and right selection lines and the gate line in a certain vertical scanning period, and FIG. 8 shows the next vertical scanning period.

  The left / right selection line L / R supplies a signal that determines whether the source voltage applied to the liquid crystal is supplied from the left or right source line of the liquid crystal. As described above, the n-channel transistor and the p-channel transistor connected in series between the two source lines are arranged in opposite positions for each row.

  As shown in FIG. 7, when the L / R line is high, the transistor 12 is turned on and connected to the left source line in the nth row, whereas the transistor 14 is turned on and connected to the right source line in the n + 1th row. Connected to the source line.

Since a positive source potential is always applied to the left source line Sm and a negative source potential is always applied to the right source line Sm + 1, a positive source potential is applied to the liquid crystal 11 _mn when the gate line Gn is high. Then, a negative source potential is applied to the liquid crystal 11 _{m (n + 1)} when the gate line Gn + 1 is high.

Looking at the adjacent column, since the potential is similarly supplied from the left source line, a negative source potential is applied to the liquid crystal 11 _{m (m + 1) n,} and a positive source is applied to the liquid crystal 11 _{(m + 1) (n + 1).} A potential is applied.

  As described above, with the elapse of the horizontal scanning period, the liquid crystals having the positive potential and the negative potential are distributed in a staggered manner.

  Next, as shown in FIG. 8, when the left / right selection line L / R is set to low, the p-channel transistor is turned on, so that the source line connected by each liquid crystal is opposite to that in FIG. The polarity of the potential applied to the liquid crystal is reversed.

  In this manner, inter-matrix AC type liquid crystal driving can be performed without the need for complicated gate wiring or connection of special liquid crystals, as in the case of AC between rows.

  FIG. 9 shows a modification of the embodiment shown in FIG. 6. The basic configuration is that the transistors 12 and 14 are connected in common without being connected to the source line, and an n-channel transistor is connected between the common connection point and the source line. 15 and the gate thereof is connected to the gate line, and a voltage is applied to the liquid crystal through a path through the three transistors 15, 12, 13 or 15, 14, 13.

  In this embodiment, the number of malfunctions is smaller than that of the circuit shown in FIG. 6 and the leakage current can be reduced, so that the power consumption can be further reduced.

  FIG. 10 shows a further modification of the embodiment shown in FIG. 1 and shows the basic four pixels described in FIG. 1, and the same components are given the same reference numerals for detailed description. Omitted.

In this embodiment, in the upper left pixel, the auxiliary capacitor _9MN connected to the connection point between the n-channel transistor _3MN and the liquid crystal is positively used, and the other side of the auxiliary capacitor is connected to the counter electrode CN. Yes. Similarly in the adjacent column, the auxiliary capacitor 9 _{(M + 1) N} is connected to the counter electrode CN.

Also in adjacent rows, likewise the auxiliary capacitor _{10 MN} and _{10 (M + 1)} the other side of the _N is also connected to the counter electrode _{C N.}

  Also in this embodiment, as in the case of FIG. 1, an inverted potential is applied to the source line every horizontal scanning period.

The operation in the configuration of FIG. 10 will be described with reference to FIG.
The counter electrode _CN is once pulled down to the negative side while the gate lines Ga and Gb are both high. Expressing connection node of the liquid crystal and the storage capacitor in P, the the P1 node during a first horizontal scanning period is supplied voltage from the source line SM, with writing to the liquid crystal 1 _MN is performed, it is also charged auxiliary capacitor 9MN .

By the gate line GbN becomes row in the next horizontal scanning period, the charge accumulated in the auxiliary capacitor 9 _MN is supplied to the liquid crystal 1 _MN, the potential of the P1 node further rises. This phenomenon is called kickback. On the other hand, in the pixel in the adjacent column, the gate line GbN becomes low, the p-channel transistor 5 _{(M + 1) N} is turned on, a negative voltage is supplied from the source line GbN, and writing to the liquid crystal 1 _{(M + 1) N} is performed. At the same time, the auxiliary capacitor 9 ( _{M + 1) N} is charged to the negative side.

  Since the potential of the counter electrode CN becomes zero at the end of the horizontal scanning period, the potential of the P1 node is stabilized at a level slightly lower than the peak value, and the potential of the P2 node is at a level further lower than that at the start of writing. Stabilize. Such an operation is so-called capacitive driving.

  At the end of the vertical scanning period, P1 and P2 perform exactly opposite operations. As is clear from FIG. 11, the voltage difference at the time of stabilization is larger than the voltage difference at the start of writing on the positive side and the negative side. Large, high-contrast and high-quality image quality can be obtained, and if the image quality is the same, the absolute value of the voltage supplied to the source line can be lowered, and low power consumption can be realized.

  This embodiment is characterized in that capacitive driving is performed in common in adjacent portions.

  12 is a modification of the embodiment described with reference to FIG. 6. The same reference numerals are assigned to the same components as those in FIG. 6, and the description thereof is omitted.

  6 differs from the configuration of FIG. 6 in that a transistor 13 that is switched according to the level of the gate line and applies the voltage of one of the left and right source lines to the liquid crystal and an auxiliary capacitor 16 having one end connected to the connection node of the liquid crystal. And two counter electrodes are arranged in the inter-row portion next to the inter-row portion where the gate line is provided, and an auxiliary capacitor is connected to the counter electrode.

  Specifically, two counter electrodes Cn and Cn + 1 corresponding to the n and n + 1 rows are disposed, and the counter capacitors Cmn and 16m (n +1) is connected, and the auxiliary capacitor (16m + 1) n) and 16 (m + 1) (n + 1) are connected to the counter electrode Cn + 1.

  The operation of this configuration is basically the same as in FIG. 6, and by combining capacitive driving, the same image quality as in the case of inter-matrix AC control can be obtained by inter-column AC control with lower power consumption. .

  The capacitive driving as described above is commonly performed in adjacent portions, not only in the configuration in which the inter-matrix AC is realized by the special control shown in FIG. 1 or FIG. The power consumption can be reduced even when applied to the inter-column AC and inter-matrix AC controls.

  FIG. 13 is a circuit diagram showing an embodiment applied in the case of normal inter-row AC control. Only the four basic pixels will be described. The liquid crystal element 21mn is connected to the source line Sn via the n-channel transistor 22mn whose gate is connected to the gate line GN. A capacitor 23 mn is connected, and the other end is connected to the counter electrode CN. This connection relationship is the same in the other three pixels adjacent thereto.

  This embodiment is configured to perform inter-row alternating current, and when all n rows of liquid crystal elements are driven to the positive side, all n + 1 rows of liquid crystal display elements are driven to the negative side. Then, special driving is performed on the counter electrode connected to the auxiliary electrode in common in the two rows.

  FIG. 14 shows a state of driving for such a counter electrode. During the first horizontal scanning period, the gate line GN is turned on so that the n rows of transistors are turned on in order to drive the n rows of liquid crystal elements to the positive side. The high voltage is supplied to the counter electrode CN, and is lowered below the reference level. As a result, the level of the P1 node rises, writing into the liquid crystal element is performed, and the auxiliary capacitor 23MN is charged. During this period, the level of the node P2 decreases in the (N + 1) th row.

  In the next horizontal scanning period, a high voltage is supplied to the gate line GN + 1, but the level of the counter electrode CN is also inverted to the positive side. As a result, the potential at the P1 node further rises, the potential at the P2 node becomes a negative write potential, and the auxiliary capacitor 23M (N + 1) is also charged to the negative side. For this reason, when the gate line GN + 1 returns to the reference potential, the auxiliary capacitor 23M (N + 1) further lowers the P2 potential.

  After the vertical scanning period, high level signals similar to those described above appear on the gate lines GN and GN + 1, but this time P2 is driven to the positive side and P1 is driven to the negative side.

  In this way, by swinging the potential of the counter electrode in synchronization with the selection of the gate line, the potential of the liquid crystal driving node can be greatly changed using the charging of the auxiliary capacitor. The power consumption can be reduced by reducing the potential.

  FIG. 15 is a circuit diagram illustrating an embodiment applied to inter-column AC control. The difference from the case of FIG. 13 is that the counter electrode control is divided every two rows and one column. That is, as shown in FIG. 15, the auxiliary capacitances 23mn and 23m (n + 1) of the pixel portions in the n rows and n + 1 rows of the m columns are connected to the counter electrode CN, and the auxiliary capacitors 23n and n + 1 rows of the pixel portions in the m + 1 columns are supported. Capacitors 23 (m + 1) n and 23 (m + 1) (n + 1) are connected to the counter electrode CN + 1.

  The operation of this configuration has been described with reference to FIG. 16, and the level of the node P1 is raised by raising the gate line GN and the level of the node P2 is lowered to write to each liquid crystal element. In the horizontal scanning period, the level of the node P3 is raised by setting the gate line GN + 1 to high, and the level of the node P4 is lowered to write the liquid crystal elements.

  At this time, by increasing the potential of the counter electrode CN and decreasing the potential of the counter electrode CN + 1, the potentials of the nodes P1 and P3 that are already at the high level further increase, and the potentials of the nodes P2 and P4 that are already at the low level. Is further reduced.

  By applying a high level to the gate line GNGN + 1 after the vertical scanning period has elapsed, an inter-column AC that exchanges positive and negative in units of columns can be realized.

  FIG. 17 is a circuit diagram illustrating an embodiment applied to inter-matrix AC control. Since this configuration itself is exactly the same as in FIG. 15, detailed description thereof is omitted.

  FIG. 18 is a waveform diagram showing the operation, and the difference from the case of AC between columns in FIG. 16 is that the polarity of the counter electrode is exchanged between positive and negative in synchronization with the activation of the gate line. The change in potential of the liquid crystal element connection node due to this is exactly the same as described with reference to FIG.

  As described above, by charging and discharging the auxiliary capacitor connected to the connection node between the liquid crystal element and the selection transistor by controlling the voltage of the counter electrode, writing to the liquid crystal can be surely performed with a lower operating voltage.

  Each of the embodiments described above is not restrictive, and can be applied to all modifications that can be conceived by those skilled in the art without departing from the spirit of the present invention.

FIG. 3 is a circuit diagram illustrating a configuration of a control circuit in a pixel portion of the liquid crystal display device according to the first embodiment of the present invention. It is a wave form diagram which shows the voltage waveform applied to the source line and gate line in FIG. FIG. 3 is a waveform diagram showing voltage waveforms applied to a source line and a gate line after the vertical scanning period of FIG. 2. It is a circuit diagram which shows the modification of the structure of FIG. It is a circuit diagram which shows the further modification of the structure of FIG. It is a circuit diagram which shows the structure of the control circuit in the pixel part of the liquid crystal display device concerning the 2nd Embodiment of this invention. FIG. 7 is a waveform diagram showing voltage waveforms applied to left and right selection lines and gate lines in FIG. 6. FIG. 8 is a waveform diagram showing voltage waveforms applied to left and right selection lines and gate lines after the vertical scanning period of FIG. 7. It is a circuit diagram which shows the modification of the structure of FIG. It is a circuit diagram which shows the structure of the control circuit in the pixel part of the liquid crystal display device concerning the 3rd Embodiment of this invention. It is a wave form diagram which shows the voltage change in the gate line in FIG. 10, a counter electrode, and a liquid crystal connection node. It is a circuit diagram which shows the structure of the control circuit in the pixel part of the liquid crystal display device concerning the 4th Embodiment of this invention. It is a circuit diagram explaining the Example which performs inter-line alternating current control of the liquid crystal display device concerning this invention which utilizes the charging / discharging of auxiliary capacity | capacitance by the electric potential operation of a counter electrode. It is a wave form diagram explaining the operation | movement in FIG. It is a circuit diagram explaining the other Example which performs alternating current control between columns. It is a wave form diagram explaining the operation | movement in FIG. It is a circuit diagram explaining the other Example which performs alternating current control between matrixes. It is a wave form diagram explaining the operation | movement in FIG.

Explanation of symbols

1, 2, 11, 21 Liquid crystal element 3, 4, 5, 6, 7, 8, 12, 13, 14, 15, 22 Transistor 9, 16, 23 Auxiliary capacitor C Counter electrode Ga, Gb Gate line L / R Left and right Selection line S Source line

Claims (19)

A pixel array arranged in a matrix and each having a liquid crystal element;
Gate lines provided in a plurality of row units of the pixel array;
Source lines provided in a plurality of column units of the pixel array;
A thin film transistor circuit for applying a voltage to the corresponding liquid crystal element from a selected one of the source lines when a gate is connected to the gate line and the gate line is activated;
The thin film transistor circuit is formed by connecting a plurality of transistors including a combination of an n-channel transistor and a p-channel transistor between a corresponding source line and a liquid crystal element for each pixel in series. .   2. The active matrix liquid crystal display device according to claim 1, wherein two of the gate lines corresponding to adjacent rows forming a pair are arranged between the adjacent rows as a gate line pair.   Of the plurality of transistors connected in series in the transistor circuit, two transistors in one diagonal position in the pixel array are n-channel transistors, and one in the other diagonal position is one n-channel transistor. The other is a p-channel transistor, wherein one gate of the two transistors is connected to one of the gate line pair, and the other gate of the two transistors is connected to the other of the gate line pair, respectively. The active matrix type liquid crystal display device according to claim 2.   When two rows to be paired are selected for the pair of gate lines, one of them is applied with a high level every horizontal scanning period, and the other is switched from high to low after the horizontal scanning period for one row is completed. 3. The active matrix type liquid crystal display device according to claim 2, wherein control is performed such that the opposite level change occurs, and the high to low or the opposite level change is exchanged every vertical scanning period. . In the pixel array, three transistors connected in series in the pixel array are n-channel transistors at one diagonal position, and those at the other diagonal position are on both sides of the central p-channel transistor. Consists of three transistors with n-channel transistors,
The gate of the center of the three transistors in each pixel in the adjacent row of the same column is connected to one of the gate line pair, and the gates of the other four transistors are connected to the other of the gate line pair. The active matrix liquid crystal display device according to claim 2.   4. The active matrix type according to claim 3, wherein the two transistors in the two rows and the source line are connected via an additional n-channel transistor provided in any one row. 5. Liquid crystal display device. A pixel array arranged in a matrix and each having a liquid crystal element;
A gate line provided in a row unit of the pixel array and provided between two pairs of rows;
A plurality of source lines that are provided in units of columns of the pixel array and supply voltages of opposite polarities for each column;
Left and right selection lines that are provided between the pair of two rows and supply a signal for selecting one of the source lines on both sides of the pixel;
A first n-channel transistor and a p-channel transistor connected in series and having a gate connected to the left and right selection line, and a connection point between these connection points and the liquid crystal element, and a gate connected to a gate line corresponding to the liquid crystal element Active liquid crystal display device comprising the second n-channel transistor.   8. The active matrix display device according to claim 7, wherein the n-channel transistor and the p-channel transistor connected in series are connected between adjacent source lines.   The n-channel transistor and the p-channel transistor connected in series are connected in series with the opposite conductivity type transistors in adjacent columns, and corresponding row gate lines between these connection points and source lines existing between these adjacent columns. 8. The active matrix liquid crystal display device according to claim 7, further comprising an n-channel transistor having a gate connected to the gate. 10. The gate line is controlled so that an active state moves to an adjacent row every horizontal scanning period, and a state of the left and right selection lines is alternated every column scanning period. An active matrix liquid crystal display device according to any one of the above. A pixel array arranged in a matrix and each having a liquid crystal element;
A counter electrode provided on the entire pixel array;
Gate lines provided in a plurality of row units of the pixel array;
Source lines provided in a plurality of column units of the pixel array;
A thin film transistor circuit for applying a voltage to the corresponding liquid crystal element from a selected one of the source lines when a gate is connected to the gate line and the gate line is activated;
An auxiliary capacitor provided between a connection point between the transistor and the liquid crystal element and the counter electrode;
The thin film transistor circuit is formed by connecting a plurality of transistors including a combination of an n-channel transistor and a p-channel transistor between a corresponding source line and a liquid crystal element for each pixel in series. .   12. The active matrix liquid crystal display device according to claim 11, wherein two of the gate lines corresponding to adjacent rows forming a pair are arranged between the adjacent rows as a gate line pair.   Of the plurality of transistors connected in series in the transistor circuit, two transistors in one diagonal position in the pixel array are n-channel transistors, and one in the other diagonal position is one n-channel transistor. The other is a p-channel transistor, wherein one gate of the two transistors is connected to one of the gate line pair, and the other gate of the two transistors is connected to the other of the gate line pair, respectively. The active matrix liquid crystal display device according to claim 12. When two rows to be paired are selected for the pair of gate lines, one of them is applied with a high level every horizontal scanning period, and the other is switched from high to low after the horizontal scanning period for one row is completed. The reverse level change occurs, and control is performed such that the high-to-low level change or the reverse level change is exchanged every vertical scanning period.
13. The active matrix liquid crystal display device according to claim 12, wherein the counter electrode is controlled to alternate between a low level and a high level every horizontal scanning period. A pixel array arranged in a matrix and each having a liquid crystal element;
A counter electrode provided on the entire pixel array;
A gate line provided in a row unit of the pixel array and provided between two pairs of rows;
A plurality of source lines that are provided in units of columns of the pixel array and supply voltages of opposite polarities for each column;
Left and right selection lines that are provided between the pair of two rows and supply a signal for selecting one of the source lines on both sides of the pixel;
A first n-channel transistor and a p-channel transistor connected in series and having a gate connected to the left and right selection line, and a connection point between these connection points and the liquid crystal element, and a gate connected to a gate line corresponding to the liquid crystal element A second n-channel transistor,
An active matrix liquid crystal display device comprising a connection point between the second n-channel transistor and the liquid crystal display element and an auxiliary capacitor provided between the counter electrodes.   16. The active matrix liquid crystal display device according to claim 15, wherein the n-channel transistor and the p-channel transistor connected in series are connected between adjacent source lines.   The n-channel transistor and the p-channel transistor connected in series are connected in series with the opposite conductivity type transistors in adjacent columns, and corresponding row gate lines between these connection points and source lines existing between these adjacent columns. 16. The active matrix display device according to claim 15, further comprising an n-channel transistor having a gate connected to the gate.   18. The active state of the gate line is shifted to an adjacent row every horizontal scanning period, and the state of the left and right selection lines is controlled to alternate every column scanning period. An active matrix display device according to any one of the above. A pixel array arranged in a matrix and each having a liquid crystal element;
Gate lines provided in a plurality of row units of the pixel array;
Source lines provided in a plurality of column units of the pixel array;
A thin film transistor circuit for applying a voltage to the corresponding liquid crystal element from a selected one of the source lines when a gate is connected to the gate line and the gate line is activated;
An auxiliary capacitor connected to a connection node of the thin film transistor circuit and the liquid crystal display element;
A counter electrode connected to the auxiliary capacitor,
The counter electrode stores a large amount of electric charge in the auxiliary capacitor during writing of the liquid crystal element, and the potential is changed so as to increase the absolute value of the potential of the connection node of the liquid crystal display element after the writing is completed. An active matrix display device characterized by being a thing.

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