JP5667359B2 - Pixel circuit, pixel circuit driving method, driving circuit, and electro-optical device - Google Patents

Description

  The present invention relates to a method for driving a pixel circuit. Specifically, the present invention relates to a driving method of an active matrix electro-optical device with ultra-low power consumption.

  As a technology for realizing an ultra-low power consumption electro-optical device (such as an LCD), a MIP (Memory In Pixel) technology in which an SRAM (Static Random Access Memory) -based memory circuit is built in each pixel is known. However, the conventional SRAM-based MIP requires at least six transistors in a pixel, and cannot meet the demand for higher definition of a display image required for a smartphone or the like. In addition, it is difficult to reduce the number of process masks in a CMOS configuration, and it is difficult to meet low cost requirements.

  In such a situation, Japanese Patent Publication No. 2006-523323 discloses an invention capable of realizing an ultra-low power consumption active matrix array device with a simple pixel circuit configuration of three pixel internal transistors.

JP-T-2006-523323

  However, the prior art AC timing described in Patent Document 1 (Japanese Patent Publication No. 2006-523323) cannot be operated normally, and the implementation of the invention is difficult. Further, since the refresh operation for the off pixel is not performed, the image data written in the off pixel cannot be kept. Further, when polarity inversion driving is performed as in an LCD, the applied voltage to the electro-optic element is inverted in the positive direction (hereinafter referred to as positive refresh), and the applied voltage is inverted in the negative direction (hereinafter referred to as negative refresh). The active timing of each control signal is different every time. This complicates the configuration of peripheral circuits, particularly the scanning line driving circuit, and increases the circuit scale of the control circuit for controlling the scanning line driving circuit, which makes it difficult to reduce the size and consumes unnecessary power. . In addition, since the period from the positive refresh to the negative refresh and the period from the negative refresh to the positive refresh, that is, the period in which the voltage between the terminals of the electro-optic element is positive and the period in which the negative polarity is negative are different, Since a DC voltage is applied to the liquid crystal layer, the life of the liquid crystal is adversely affected. Further, in the prior art, one end of the electro-optic element is connected to the common electrode and one end of the storage capacitor is set to a fixed voltage, so that direct current is applied to the liquid crystal layer, which adversely affects the life of the liquid crystal. Become.

  The present invention has been made in view of these problems.

  In the present invention, the AC timing is improved to simplify the peripheral circuit, and low power consumption control is performed to reduce wasteful power consumption. Further, by reducing the voltage level required for each control signal, the peripheral circuit can be further simplified, and the power consumption can be further reduced. It is another object of the present invention to provide a driving method capable of realizing a long life of the electro-optic element with less direct current applied to the electro-optic element, and thereby realizing an ultra-low power consumption electro-optic device.

  The pixel circuit controlled by a plurality of control signals according to the present invention includes an electro-optical element having one end connected to the counter electrode and a sampling on the first control signal line for sampling the voltage level held in the electro-optical element. A first switch element controlled by a control signal, a second switch element controlled by an image data refresh control signal on the second control signal line, and an image data capturing control signal on the third control signal line for capturing image data And a first capacitance element that holds a voltage level sampled by the sampling control signal, and the second switch element is taken in via the third switch element. Image data reflection on the second control signal line by controlling writing of the image data to the electro-optic element. Gerhard control signal, prior to said image data refresh control signal is activated, characterized in that it is preset at a predetermined voltage level.

  The pixel circuit driving method controlled by a plurality of control signals according to the present invention includes a first driving step of writing image data to an electro-optical element in the pixel circuit, and a second driving method of refreshing the written image data. A step of sampling a voltage level corresponding to image data held in the pixel circuit via a first switch element controlled by a sampling control signal. And applying a voltage supplied via the second switch element controlled by the voltage level corresponding to the sampled image data and the voltage level of the image data refresh control signal to the electro-optic element, Refreshing the image data held in the circuit, the image data Data refresh control signal, prior to said image data refresh control signal is activated, characterized in that it is preset at a predetermined voltage level.

  The driving circuit of the pixel circuit controlled by a plurality of control signals in the present invention includes a first driving unit that writes image data to an electro-optic element in the pixel circuit, and a second that refreshes the written image data Driving means, and the second driving means samples the voltage level corresponding to the image data held in the pixel circuit via the first switch element controlled by a sampling control signal. And applying a voltage supplied via the second switch element controlled by the voltage level corresponding to the sampled image data and the voltage level of the image data refresh control signal to the electro-optic element, Means for refreshing image data held in the circuit, and the image data refresh control Items, before the image data refresh control signal is activated, characterized in that it is preset at a predetermined voltage level.

  The electro-optical device according to the present invention includes an active matrix array circuit in which the pixel circuits are arranged in a matrix, and a drive circuit for the pixel circuits that drives the pixel circuits.

  In the present invention, the image data refresh control signal is preset at a predetermined voltage level before the image data refresh control signal becomes active, so that the voltage level required for each control signal is reduced.

  In addition, the preset provides an effect of enabling control according to the characteristics of the switch element and the characteristics of the electro-optic element.

  Furthermore, during the low power consumption period, image data written to each electro-optic element during the normal drive period, which is the normal display period, can be retained by periodic refresh operations in which the number of active control signals is less than during normal display. As a result, the power consumption can be greatly reduced.

  In normal display, the peripheral circuit must always be operated. However, in the low power consumption period of the present invention, the written image data only needs to be driven for a period of regular refreshing. During this period, the operation of the peripheral circuit can be stopped. As a result, the consumption current of the peripheral circuit is also at the quiescent current level, and thus there is an effect that the power consumption can be further greatly reduced.

  In the active matrix array circuit in which the pixel circuits are arranged in a matrix, the data signal input to the data line of each pixel circuit can be a common signal in all the pixels in the low power consumption driving period. Also in this respect, there is an effect that power consumption can be reduced.

1 is a block diagram of an active matrix electro-optical device according to an embodiment of the present invention. FIG. It is a pixel circuit block diagram by one Embodiment of this invention. FIG. 3 is a diagram for explaining a basic operation principle in the pixel circuit of FIG. 2. 10 is a timing chart showing a possibility of a problem in the control of the active matrix electro-optical device according to the conventional invention. It is a 1st AC timing chart in a 1st embodiment of the present invention. It is a 2nd AC timing chart in 2nd Embodiment of this invention. It is a 3rd AC timing chart in a 3rd embodiment of the present invention.

(1) First Embodiment FIG. 1 is a block diagram of an active matrix electro-optical device using a pixel circuit according to a first embodiment of the present invention.

  The active matrix electro-optical device includes an active matrix array circuit 100 in which pixel circuits are arranged in an array, a scanning line drive circuit 101, a data line drive circuit 102, a drive voltage generation circuit 103, and an image processing circuit. 104 and a control circuit 105.

  The control circuit 105 controls the scanning line drive circuit 101, the data line drive circuit 102, the drive voltage generation circuit 103, and the image processing circuit 104, thereby controlling the active matrix array circuit 100. To drive.

The drive voltage generation circuit 103 generates voltage levels V ₁ , V ₃ , V ₄ , and V ₅ of control signals that control the pixel circuit, and supplies the voltage levels to the scanning line drive circuit 101. Further, the high voltage level V _DH and the low voltage level V _DL of the data signal are generated and supplied to the data line driving circuit 102. Further, the counter electrode voltage signal _VCOM is generated and supplied to the counter electrode (not shown) and the active matrix array circuit 100, and the voltage level thereof is controlled.

The image processing circuit 104 processes the image data D _IN inputted from outside of the electro-optical device, and supplies to the data line driving circuit 102 generates the image data D _OUT suitable for the electro-optical device.

  The scanning line driving circuit 101 receives a voltage having a plurality of voltage levels generated by the driving voltage generation circuit 103 and generates a control signal that is controlled by the control circuit 105 and drives the active matrix array circuit 100. To do.

  The data line driving circuit 102 receives image data processed by the image processing circuit 104 and is controlled by the control circuit 105.

  Here, one pixel in the active matrix electro-optical device includes RGB sub-pixels, and each sub-pixel includes the same pixel circuit.

  FIG. 2 shows a configuration diagram of a pixel circuit which is one sub-pixel of the active matrix array circuit 100 according to the first embodiment of the present invention.

  In FIG. 2, a circuit 201 is one of the pixel circuits in the odd-numbered rows of the active matrix array circuit 100, and a circuit 202 is one of the pixel circuits in the even-numbered rows. In the present embodiment, each pixel circuit may be the same.

The pixel circuit 201 includes a switch element _{SW 1, SW 2, SW 3} , and the sampling capacitor _{C 2} capacitance is _{C SMP,} capacitance and the holding capacitor _{C 1} is _{C ST,} electrostatic And an electro-optic element LC having a capacitance C _LC . Wherein the electro-optical element LC and the holding capacitor _{C 1,} are connected in parallel to one end, the data signal DATA through the switch element _SW 3, SW ₂ is supplied, the other end of the holding capacitor _{C 1} in is supplied with opposed electrode voltage signal V _COM from the common signal supply line, the other end of the electro-optical element LC is the counter electrode voltage signal V _COM supplied from the counter electrode. In the embodiment in FIG. 2, the switch elements SW ₁ , SW ₂ , SW ₃ are composed of n-type channel transistors, but are not limited to this, and may be composed of other switch elements. For example, when a p-type channel transistor is used, it can be applied by reviewing the polarity of the input signal. The electro-optical element LC is configured as a liquid crystal, but is not limited to this, and may be an organic EL or the like.

  In the prior art described in Patent Document 1 (Japanese Patent Publication No. 2006-523323), one end of the electro-optic element and the first capacitive sub-element which is a holding capacitor are connected in common as in the present invention. A data signal is supplied to one end, and the other end of the electro-optic element is connected to a counter electrode (common electrode). However, it is stated that the other end of the first capacitive sub-element is connected to an addressing conductor in the next column, for example, unlike the present invention.

The pixel circuits 201 and 202 are supplied with the data signal DATA, the counter electrode voltage signal V _{COM of the} electro-optical element LC, and the image data capturing control signals G ₁ and G for controlling the supply of the data signal DATA into the pixel circuit. ₂ , sampling control signals ENA ₁ and ENA ₂ for controlling the timing of sampling the voltage level corresponding to the voltage level of the node N ₁ to the sampling capacitor C ₂ , the electro-optical element LC in the pixel circuits 201 and 202, and the holding circuit Image data refresh control signals SET ₁ and SET ₂ for controlling the timing for refreshing the capacitor C ₁ are input to control the pixel circuits 201 and 202. Here, the last code 1 and 2 of each control signal indicates whether the control signal (1) is for odd rows or the control signal (2) for even rows.

Although detailed control and operation will be described later, the switch element SW ₁ is controlled by a sampling control signal ENA and samples a voltage level corresponding to the voltage level of the node N _{1 in} the sampling capacitor C ₂ . The switching element SW ₂ is controlled by the image data refresh control signal SET and the sampling capacitor C ₂ of the voltage level. The switch element SW ₃ is controlled by an image data capturing control signal G and supplies a data signal DATA into the pixel circuits 201 and 202.

Incidentally, the capacitance _{C SMP} of the sampling capacitor _{C 2} is the total capacitance of the capacitance _{C LC} of the capacitance _{C ST} and the electro-optical element LC retention capacitor _{C 1,} to 1/10 or less Is desirable. That this is because the variations in the charge held in the capacitance C _LC of the holding capacitor C ₁ and the electro-optical element LC at the time of sampling so as not to affect the display is a small volume as possible However, on the other hand, a certain capacity or more is required to secure a sufficient voltage level for driving the switch element.

  Next, a control operation principle of the pixel circuit according to the first embodiment of the present invention will be described with reference to FIGS. Since the pixel circuits 201 and 202 are the same circuit, here, description will be given based on the operation in the pixel circuit 201 of one sub-pixel in an odd row.

  FIGS. 3A to 3C show the control operation principle of the pixel circuit. However, FIG. 3 is only a principle, and the actual control will be described in more detail in the AC timings after FIG.

In the normal display shown in FIG. 3A, the G ₁ signal that is an image data capture control signal and the SET ₁ signal that is an image data rewrite control signal (image data refresh control signal during the refresh operation) are activated. As a result, the switch elements SW ₃ and SW ₂ are turned on. Therefore, the voltage level of the data signal DATA can be applied to the holding capacitor C ₁ and the electro-optical element LC via the switch elements SW ₃ and SW ₂ . After the electrostatic capacitance C _LC of the holding capacitor C ₁ and the electro-optical element LC is charged to a voltage level corresponding to the data signal level, image data capture control signals G ₁ and the image data rewrite control signal SET ₁ inactive Then, the switch elements SW ₃ and SW ₂ are turned off. In order to reliably control the switching element SW _2, before the image data capture control signals G ₁ and the image data rewrite control signal SET ₁ active, it is desirable to a sampling control signal ENA ₁ active advance .

After the normal display is completed, the sampling operation shown in FIG. In the sampling operation, the switching element SW ₁ is turned on by activating the sampling control signal ENA ₁ . Accordingly, the voltage level corresponding to the data held in the capacitance C _LC of the holding capacitor C ₁ and the electro-optical element LC is sampled in the sampling capacitor C _2. After sampling, the switching element SW ₁ is turned off by making the sampling control signal ENA ₁ inactive.

After the sampling operation, the refresh operation shown in FIG. 3C is performed. In the refresh operation, the image data refresh control signal SET ₁ is set to a predetermined active level, and on / off control of the switch element SW ₂ is performed based on the voltage level and the voltage level held in the sampling capacitor C ₂ . Depending on the on / off state switching element SW _2, applies the voltage level of the data signal DATA to the holding capacitor C ₁ and the electro-optical element LC.

  In the period in which the sampling operation and the refresh operation are periodically repeated as appropriate (hereinafter referred to as a low power consumption period), image data is refreshed based on the self-storing data of each pixel. Refresh is possible. Therefore, in the low power consumption period other than the sampling operation and the refresh operation, the peripheral circuit operation can be stopped and the charging / discharging current of the DATA line accompanying the data rewriting does not occur, so that the power consumption can be reduced. Become.

Based on the above operation principle, when the control by the circuit and various control signals in the prior art of Patent Document 1 (Japanese Patent Publication No. 2006-523323) is examined, the following equations (5) and (6) are not satisfied. during the refresh operation of the pixel, it is the switch element SW ₂ that must not originally off and cause when not turned off, as a result, there is a possibility that the malfunction oFF pixels becomes an oN pixel after the refresh operation occurs It became clear (FIG. 4).

In Patent Document 1, one end of the first capacitive sub-element that is a holding capacitor is connected to each scanning line in common or adjacent to the scanning line. However, in such a configuration, the differential voltage between the V _COM voltage supplied to the common electrode of the electro-optic element and the signal voltage supplied from the one end of the first capacitive subelement, and the first capacitive subelement The voltage generated according to the capacitance ratio between the capacitance of the element and the capacitance of the second capacitive sub-element, which is an electro-optic element, is superimposed as a DC voltage on the voltage across the electro-optic element. This causes a problem in the display of the element. Furthermore, when the electro-optic element is a liquid crystal, it is needless to say that the superimposition of the DC voltage has an adverse effect on the life of the liquid crystal.

Therefore, in the embodiment of the present invention, the image data refresh control signal SET ₁ which is one of the control signals of the pixel circuit 201 is preset with a predetermined voltage before the control signal is activated, thereby malfunctioning in the off pixel. And the number of voltage levels required for control is reduced.

Further, by supplying a common electrode voltage signal V _COM one end of the holding capacitor C ₁ and shared by all pixels, and the differential voltage between the counter electrode voltage signal V _COM to be supplied to one end of the electro-optical element LC, said to eliminate the voltage generated in accordance with the capacitance ratio of the capacitance of the capacitance electro-optical element LC retention capacitor C _1. As a result, unnecessary DC voltage is not superimposed on the inter-terminal voltage V _LC of the electro-optical element, flicker can be prevented, and the life of the electro-optical element can be extended.

  Hereinafter, the first AC timing according to the first embodiment of the present invention will be described in detail with reference to FIGS.

  FIG. 5 shows a first AC timing chart of control signals for controlling the pixel circuits 201 and 202 according to the embodiment of the present invention shown in FIG. In order to clarify the timing of the control signal and the necessary voltage required for the operation in the first embodiment of the present invention, it will be described in detail below with reference to FIG.

Here, in FIG. 5, driving for each odd row by the control signals ENA ₁ , G ₁ , SET ₁ and driving for each even row by the control signals ENA ₂ , G ₂ , SET ₂ so as to result in line inversion driving. In the example of driving, driving is performed in groups. Needless to say, the frame inversion driving can be realized by inputting the control signal to the odd rows shown in FIG.

Now, it is assumed that the switch elements SW ₁ , SW ₂ , SW ₃ are transistors whose threshold voltage V _th is 1 [V]. Then, a vertical alignment liquid crystal with an on-voltage of 4 [V] is used for the electro-optical element LC, and the high voltage level V _DH and the low voltage level V _DL of the counter electrode voltage signal V _COM and the data signal DATA are set to V _DH = 4 [ V], V _DL = 0 [V]. Furthermore, the voltage levels that each control signal can take are set to V ₁ = 12 [V], V ₃ = 4 [V], V ₄ = 0 [V], V ₅ = -4 [V]. It is not limited to the voltage setting.

For example, the voltage level V ₅ is the low voltage level V _DL (= 0 [V]) of the data signal DATA−the amplitude voltage (= 4 [V]) of the counter electrode voltage signal V _COM + the threshold voltage V _th (= 1 [V ], And V ₁ is the high voltage level V _DH (= 4 [V]) of the data signal DATA + the amplitude voltage (= 4 [V]) of the counter electrode voltage signal V _COM + the threshold voltage V _th ( = 1 [V]) or more.

Further, the voltage levels V _DL , V _DH of the data signal DATA are offset according to the threshold voltage V _th of the transistor, and the settings of the voltage levels V ₁ , V ₃ , V ₄ , V ₅ are appropriately changed accordingly. Also good. Further, the kickback voltage and the like when the transistor SW ₃ and transistor SW ₂ is turned off, a DC voltage to the liquid crystal layer is superposed, it may flicker occurs. In this case, the offset voltage may be applied by independently controlling the voltage levels of the common electrode voltage signal _VCOM and the data signal DATA.

The voltage level _{V 2} shown in FIG. 5 is determined necessarily according to the respective voltage level _V DH _{of, V DL, V 1, V} 3, V 4, V 5 of the voltage setting, in this case V ₂ = 8 [V].

  Conditions necessary for setting each control signal for controlling the pixel circuit 201 according to the embodiment of the present invention shown in FIG. 2 are listed below. The first AC timing shown in FIG. 5 is obtained by setting the timing and voltage of each control signal based on this setting condition.

・ V _COM signal (counter electrode voltage signal)
During the sampling and refresh period, the common electrode voltage signal _VCOM has an L level period and an H level period.

・ DATA signal (data signal)
(A) During the sampling and refresh period, the data signal DATA is changed from the H level to the L level at least once during the period when the common electrode voltage signal _VCOM is at the L level.
(B) During the sampling and refresh period, the data signal DATA is changed from the H level to the L level at least once during the period when the common electrode voltage signal _VCOM is at the H level.

・ ENA signal (sampling control signal)
(A) The sampling control signal ENA is preferably active before the image data capturing control signal G is active and during the period when the counter electrode voltage signal _VCOM is at the H level. The counter electrode voltage signal V _COM period of L level, the voltage level at node N _1, the inactive voltage level of the control signal may the same level, when to activate the sampling control signal ENA at this time, the sampling This is because not be able to charge the capacitor C ₂ caused.
(B) active voltage of the sampling control signal ENA is, it is desirable that the voltage _{V 1.} This is because the voltage level of the node N ₁ is the maximum, the voltage level V of the high voltage level V _DH (= 4 [V]) of the data signal DATA + the amplitude voltage (= 4 [V]) of the counter electrode voltage signal V _{COM. 2} (= 8 [V]), the voltage level higher than the threshold voltage _Vth is required as the active voltage. This is also because the peripheral circuit can be simplified by setting the active voltage to the voltage V ₁ uniformly with other control signals.
(C) inactive voltage of the sampling control signal ENA is, it is desirable that the voltage _{V 5.} This is because the peripheral circuit can be simplified by making it the same as the inactive voltage of other control signals.

・ G signal (image data capture control signal)
(A) During the sampling and refresh period, the image data capture control signal G is active during a period including both the H level and L level of the data signal DATA.
(B) In the positive refresh period becomes active in the period polarity and the polarity of the common electrode voltage signal V _COM of the data signal DATA is reversed polarity, the polarity and the counter electrode voltage signal V _COM polarity same polarity of the data signal DATA Inactive during a certain period (refresh periods R _P1 , R _P2 in FIG. 5).
(C) In the negative refresh period becomes active in the period polarity and the polarity of the common electrode voltage signal V _COM of the data signal DATA is the same polarity, the polarity and the counter electrode voltage signal V _COM polarity opposite the polarity of the data signal DATA Inactive during a certain period (refresh periods _RN1 , _RN2 in FIG. 5).
(D) active voltage of the image data capture control signals G, it is desirable that the voltage V _1. This is because the peripheral circuit can be simplified by making it the same as the active voltage of the sampling control signal ENA.
(E) inactive voltage of the image data capture control signals G, it is desirable that the voltage V _5. This is because the peripheral circuit can be simplified by making it the same as the inactive voltage of other control signals.

・ SET signal (image data rewrite control signal / image data refresh control signal)
(A) During the sampling and refresh period, the image data refresh control signal SET becomes active while the data signal DATA is at the H level and the image data capture control signal G is active.

(B) image data refresh control signal SET, before the refresh period, it is desirable to preset to an intermediate level of the voltage of the node N ₁ in the inactive voltage and the sampling period of the control signal.

More specifically, when the on-image data is held before the positive polarity refresh period (the voltage of the node N ₁ is V _N1 = 0 [V]), the preset voltage V _PST is switched when the control signal falls. to turn off the element SW _2,
V _PST > − (V _th + V _DL ) + V _N1 + V ₅ (1)
When the off-image data is held before the positive refresh period (the voltage of the node N ₁ is V _N1 = 4 [V]), the preset voltage V _PST is the switch element SW at the falling edge of the control signal. To turn on ₂ ,
V _PST ≦ − (V _th + V _DL ) + V _N1 + V ₅ (2)
It becomes. Therefore, from the expressions (1) and (2) and the voltage setting condition described above, the voltage range in which V _PST can be set in the positive refresh period is
−1 [V] ≧ V _PST > −5 [V] (3)
It becomes. In the sampling periods Samp ₁ and Samp ₃ in FIG. 5, the preset voltage V _PST may be set as appropriate based on the voltage range of the equation (3), but setting the voltage V ₅ = −4 [V] More desirable. This is because the peripheral circuit can be simplified by making it the same as the voltage level of other control signals.

On the other hand, when the on-image data is held before the negative polarity refresh period (the voltage of the node N ₁ is V _N1 = 8 [V]), the preset voltage V _PST is the switch element SW when the control signal falls. To turn on ₂ ,
V _PST ≦ − (V _th + V _DL ) + V _N1 + V ₅ (4)
When the off-image data is held before the negative polarity refresh period (the voltage at the node N ₁ is V _N1 = 4 [V]), the preset voltage V _PST is the switching element SW at the falling edge of the control signal. To turn off ₂ ,
V _PST > − (V _th + V _DL ) + V _N1 + V ₅ (5)
It becomes. Therefore, from the equations (4) and (5) and the voltage setting condition described above, the voltage range in which V _PST can be set in the negative refresh period is
3 [V] ≧ V _PST > −1 [V] (6)
It becomes. In the sampling periods Samp ₂ and Samp ₄ in FIG. 5, the preset voltage V _PST may be appropriately set based on the settable voltage range of the equation (6), but the voltage V ₄ = 0 [V] is set. Is more desirable. This is because the peripheral circuit can be simplified by making it the same as the voltage level of other control signals.

If this preset does not operate, the need to reduce the inactive voltage after the active image data refresh control signal SET at a negative refresh voltage level lower than the voltage V ₅ is produced. However, advance by preset on the basis of the above conditions, the inactive voltage of the image data refresh control signal SET is unified to the voltage V _5, the peripheral circuit together becomes possible to reduce the number of voltage level of the control signal It can be simplified.

Active voltage _{V SET} of (c) image data refresh control signal SET is to turn on the switching element SW ₂ at the rising edge of the control signal,
V _SET ≧ V _th + V _DH −V _N1 + V _PST (7)
It becomes.

When ON image data is held before the positive refresh period (the voltage at the node N ₁ is V _N1 = 0 [V]), the preset voltage V _{PST is set} to the voltage V ₅ = −4 [V] as described above. If set,
V _SET ≧ 1 [V] (8)
When the off-image data is held before the positive refresh period (the voltage at the node N ₁ is V _N1 = 4 [V]), the preset voltage V _{PST is set} to the voltage V ₅ = −4 [V as described above. ]
V _SET ≧ −3 [V] (9)
It becomes. Therefore, from the equations (8) and (9), the active voltage V _SET of the image data refresh control signal _SET is
V _SET ≧ 1 [V] (10)
It becomes. In the positive refresh periods R _P1 and R _P2 in FIG. 5, the active voltage V _SET of the image data refresh control signal SET may be set as appropriate based on the settable voltage range of the equation (10), but the voltage V ₃ = 4 [V] is more desirable. This is because the peripheral circuit can be simplified by making the active voltage level of the control signal the same.

On the other hand, when ON image data is held before the negative polarity refresh period (the voltage of the node N ₁ is V _N1 = 8 [V]), the preset voltage V _{PST is set} to the voltage V ₄ = 0 [V] as described above. If set to
V _SET ≧ −3 [V] (11)
When the off-image data is held before the negative polarity refresh period (the voltage at the node N ₁ is V _N1 = 4 [V]), the preset voltage V _{PST is set} to the voltage V ₄ = 0 [V] as described above. If set to
V _SET ≧ 1 [V] (12)
It becomes. Therefore, from the expressions (11) and (12), the active voltage V _SET of the image data refresh control signal _SET is
V _SET ≧ 1 [V] (13)
It becomes. In the negative polarity refresh periods R _N1 and R _N2 in FIG. 5, the active voltage V _SET of the image data refresh control signal SET may be appropriately set based on the settable voltage range of the equation (13), but the voltage V ₃ = 4 [V] is more desirable. This is because the peripheral circuit can be simplified by making the active voltage level of the control signal the same.

(D) an inactive voltage of the image data refresh control signal SET, it is desirable that the voltage V _5. This is because the peripheral circuit can be simplified by making it the same as the inactive voltage of other control signals.

  Based on the above, the timing and voltage level of each control signal will be described with reference to FIGS.

First, in the normal display period ND, data writing of moving image gradation display or still image low power consumption display by normal line inversion driving is performed. Here, ENA signal is a control signal, G signal, active voltage of the SET signal is active the voltage V ₁ of the control signal in the sampling period and the refresh period, similarly inactive voltage control signal in the sampling period and the refresh period the inactive voltage _{V 5.} Introduction to turn on the switching element SW ₁ of the ENA signal by activating the, to equalize the voltage level of node N ₁ and the node N _2. Thereafter By active at the same time the G signal and the SET signal to turn on the switching element SW ₃ and SW _2. With such a voltage setting and control timing, a desired voltage is applied to the holding capacitor C ₁ and the electro-optic via the switch elements SW ₃ and SW ₂ regardless of the holding voltages of the nodes N ₁ and N ₂ before the data writing. it can be held in the capacitance C _LC of the element LC.

As for the voltage levels of the ENA signal, the G signal, and the SET signal, which are control signals, the active voltage is the voltage V ₁ and the inactive voltage is the voltage V ₅ , but the present invention is not limited to this. However, it is advantageous in that the peripheral circuits can be simplified by using the voltages V ₁ and V ₅ .

After the data is written in the normal display period ND, a sampling operation and a positive / negative refresh operation are performed. In the positive / negative refresh operation, the active voltage of the image data refresh control signals SET ₁ and SET ₂ is set to the voltage V ₃ .

First, in the sampling period Samp ₁ , the sampling control signal ENA ₁ is activated and the switch element SW ₁ is turned on while the common electrode voltage signal V _COM is at the H level (voltage V _DH ). Thus, (in the case of on-pixel voltage V _4, the voltage V ₃ in the case of _off-pixels) of the voltage node N ₁ is sampled in the sampling capacitor C _2. The sampling capacitor C _2, after the electric charge corresponding to the voltage of the node N ₁ is charged, the sampling control signal ENA ₁ becomes inactive, the switch element SW ₁ is turned off.

Thereafter, a refresh period in which a positive refresh operation or a negative refresh operation is performed is entered. In FIG. 5, the sampling period Samp ₁ is followed by a refresh period R _P1 in which a positive refresh operation is performed in an odd row.

In the positive refresh period _RP1 , in the period in which the common electrode voltage signal V _COM is at the L level (voltage V _DL ) and the data signal DATA is changed from the H level (voltage V _DH ) to the L level (voltage V _DL ), the image data a capture control signal _{G 1} to activate, turn on the switch element SW _3. As a result, the data signal DATA reaches the node N ₃ via the switch element SW ₃ .

Then, during the period in which the data signal DATA is at the H level, the image data refresh control signal SET ₁ is changed from the voltage V ₅ that is the inactive voltage of the control signal to the voltage V ₃ that is the active voltage of the control signal. The voltage of N ₂ is changed by the voltage fluctuation (= 8 [V]) of the image data refresh control signal SET ₁ + the charging voltage of the sampling capacitor C ₂ .

At this time, if the pixel is an ON pixel, the voltage at the node N ₂ is the voltage V ₂ . This is a voltage sufficiently higher than the voltage at the node N ₃ , that is, the voltage V _DH (= voltage V ₃ ) of the data signal DATA that has passed through the switch element SW ₃ . Thus, the switch element SW ₂ is turned on. Accordingly, the voltage V _DH (= voltage V ₃ ) of the data signal DATA is applied to the holding capacitor C ₁ and the electrostatic capacitance C _LC of the electro-optic element LC via the switch elements SW ₃ and SW ₂ .

Off in the case of the pixel, the voltage of the node N ₂ becomes the voltage V _1. This is a voltage sufficiently higher than the voltage at the node N ₃ , that is, the voltage V _DH (= voltage V ₃ ) of the data signal DATA that has passed through the switch element SW ₃ . Thus, the switch element SW ₂ is turned on. Accordingly, the voltage V _DH (= voltage V ₃ ) of the data signal DATA is applied to the holding capacitor C ₁ and the electrostatic capacitance C _LC of the electro-optic element LC via the switch elements SW ₃ and SW ₂ .

Thereafter, in a period in which the data signal DATA is at the L level, the voltage of the node N ₂ is changed by changing the image data refresh control signal SET ₁ from the voltage V ₃ that is the active voltage of the control signal to the voltage V ₅ that is the inactive voltage. Is changed by the voltage fluctuation of the image data refresh control signal SET ₁ (= −8 [V]) + the charging voltage of the sampling capacitor C ₂ .

At this time, if the ON pixel, the voltage of the node N ₂ becomes the voltage V _4. This is the same voltage as the voltage at the node N ₃ , that is, the voltage V _DL (= voltage V ₄ ) of the data signal DATA that has passed through the switch element SW ₃ . Accordingly, the switch element SW ₂ is turned off, because the node _{N 1} is disconnected with the data signal DATA, the capacitance _{C LC} of the holding capacitor _{C 1} and the electro-optical element LC, the voltage at the node _{N 1,} which is held is maintained at a voltage V ₃ is the voltage.

Here, the inter-terminal voltage V _LC of the electro-optic element LC is the voltage of the node N _{1 -the} voltage of the counter electrode voltage signal V _COM . Since the common electrode voltage signal V _COM is an L level section, the inter-terminal voltage V _LC of the electro-optic element LC is the voltage V ₃ (4 [V]) that is the voltage of the node N ₁ −the common electrode voltage signal V _COM. Voltage V _DL (0 [V]), that is, +4 [V], and the positive-polarity refresh operation of the on-pixel ends.

In the case of an off pixel, the voltage at the node N ₂ becomes the voltage V ₃ , which is sufficiently higher than the voltage at the node N ₃ , that is, the voltage V _DL (= voltage V ₄ ) of the data signal DATA that has passed through the switch element SW _3. High voltage. Thus, the switch element SW ₂ is turned on. Accordingly, the voltage V _DL (= voltage V ₄ ) of the data signal DATA is applied to the holding capacitor C ₁ and the electrostatic capacitance C _LC of the electro-optic element LC via the switch elements SW ₃ and SW ₂ . Thereafter, the image data capture control signal G ₁ is becomes inactive, switching off of the switching element SW _3. As a result, the node N ₁ is disconnected from the data signal DATA, so that the voltage at the node N ₁ is maintained at the held voltage V ₄ by the holding capacitor C ₁ and the electrostatic capacitance C _LC of the electro-optic element LC.

Here, since the common electrode voltage signal V _COM is an L level section, the inter-terminal voltage V _LC of the electro-optical element LC is the voltage V ₄ (0 [V]) − the common electrode voltage which is the voltage of the node N _1. The voltage V _DL (0 [V]) of the signal V _COM becomes 0 [V], that is, the off-pixel positive polarity refresh operation ends.

Next, the sampling period Samp _{2 in} which sampling for the negative polarity refresh operation of the even-numbered row is performed.

In the sampling period Samp ₂ , the image data refresh control signal SET ₂ is preset to the voltage V ₄ and the sampling control signal ENA ₂ is made active while the counter electrode voltage signal V _COM is at the H level (voltage V _DH ). to turn on the element SW _1. As a result, the voltage of the node N ₁ (the voltage V _{2 in} the case of the on pixel and the voltage V _{3 in} the case of the off pixel) is sampled by the sampling capacitor C ₂ . The sampling capacitor C _2, after the electric charge corresponding to the voltage of the node N ₁ is charged, the sampling control signal ENA ₂ becomes inactive, the switch element SW ₁ is turned off.

After the end of the sampling period Samp _2, into the negative refresh period R _N2 performing negative refresh operation in the even rows.

In the negative refresh period _RN2 , the image data is output in a period in which the common electrode voltage signal _VCOM is at the H level (voltage _VDH ) and the data signal DATA is changed from the H level (voltage _VDH ) to the L level (voltage _VDL ). a capture control signal _{G 2} to activate, turn on the switch element SW _3. As a result, the data signal DATA reaches the node N ₃ via the switch element SW ₃ .

Then, during the period when the data signal DATA is at the H level, the image data refresh control signal SET ₂ is changed from the voltage V ₄ that is the preset voltage of the control signal to the voltage V ₃ that is the active voltage of the control signal, thereby the _second voltage the voltage variation of the image data refresh control signal _{SET 2 (= 4 [V]} ) + is changed by the charge voltage of the sampling capacitor C _2.

At this time, if the pixel is an off pixel, the voltage of the node N ₂ becomes the voltage V ₂ . This is a voltage sufficiently higher than the voltage at the node N ₃ , that is, the voltage V _DH (= voltage V ₃ ) of the data signal DATA that has passed through the switch element SW ₃ . Thus, the switch element SW ₂ is turned on. Accordingly, the voltage V _DH (= voltage V ₃ ) of the data signal DATA is applied to the holding capacitor C ₁ and the electrostatic capacitance C _LC of the electro-optic element LC via the switch elements SW ₃ and SW ₂ .

On the case of the pixel, the voltage of the node N ₂ becomes the voltage V _1. This is a voltage sufficiently higher than the voltage at the node N ₃ , that is, the voltage V _DH (= voltage V ₃ ) of the data signal DATA that has passed through the switch element SW ₃ . Thus, the switch element SW ₂ is turned on. Accordingly, the voltage V _DH (= voltage V ₃ ) of the data signal DATA is applied to the holding capacitor C ₁ and the electrostatic capacitance C _LC of the electro-optic element LC via the switch elements SW ₃ and SW ₂ .

Thereafter, during the period when the data signal DATA is at the L level, the voltage of the node N ₂ is changed by changing the image data refresh control signal SET ₂ from the voltage V ₃ that is the active voltage of the control signal to the voltage V ₅ that is the inactive voltage. Is changed by the voltage fluctuation (= −8 [V]) of the image data refresh control signal SET ₂ + the charging voltage of the sampling capacitor C ₂ .

At this time, if the off-pixel, the voltage of the node N ₂ becomes the voltage V _4. This is the same voltage as the voltage at the node N ₃ , that is, the voltage V _DL (= voltage V ₄ ) of the data signal DATA that has passed through the switch element SW ₃ . Accordingly, the switch element SW ₂ is turned off, because the node _{N 1} is disconnected with the data signal DATA, the capacitance _{C LC} of the holding capacitor _{C 1} and the electro-optical element LC, the voltage at the node _{N 1,} which is held is maintained at a voltage V ₃ is the voltage.

Here, since the common electrode voltage signal V _COM is an H level section, the inter-terminal voltage V _LC of the electro-optic element LC is the voltage V ₃ (4 [V]) − the common electrode voltage, which is the voltage of the node N _1. The voltage V _DH (4 [V]) of the signal V _COM becomes 0 [V], and the negative refresh operation of the off pixel is finished.

In the case of an on-pixel, the voltage at the node N ₂ becomes the voltage V ₃ , which is sufficiently higher than the voltage at the node N ₃ , that is, the voltage V _DL (= voltage V ₄ ) of the data signal DATA that has passed through the switch element SW _3. High voltage. Thus, the switch element SW ₂ is turned on. Accordingly, the voltage V _DL (= voltage V ₄ ) of the data signal DATA is applied to the holding capacitor C ₁ and the electrostatic capacitance C _LC of the electro-optic element LC via the switch elements SW ₃ and SW ₂ . Thereafter, the image data capture control signals G ₂ becomes inactive, switching off of the switching element SW _3. As a result, the node N ₁ is disconnected from the data signal DATA, so that the voltage at the node N ₁ is maintained at the held voltage V ₄ by the holding capacitor C ₁ and the electrostatic capacitance C _LC of the electro-optic element LC.

Here, since the common electrode voltage signal V _COM is an H level section, the inter-terminal voltage V _LC of the electro-optic element LC is the voltage V ₄ (0 [V]) − the common electrode voltage, which is the voltage of the node N _1. The voltage V _DH (4 [V]) of the signal V _COM becomes -4 [V], and the negative-polarity refresh operation of the on-pixel ends.

  The peripheral drive circuit is stopped for a certain period from the end of the positive / negative refresh operation to the next sampling operation and refresh operation.

Thereafter, the same control as described above is performed in the even-row sampling period Samp ₃ , the even-row positive polarity refresh period R _P2 , the odd-row sampling period Samp ₄ , and the odd-row negative polarity refresh period RN ₁ . Thereafter, the same control is repeated.

  In the negative polarity refresh operation, the presetting of the image data refresh control signal SET is performed simultaneously with the activation of the sampling control signal ENA, but is not limited to this. The period can be preset as long as it is a period from the end of the positive refresh operation to the time when the image data refresh control signal SET in the next negative refresh operation becomes active and the sampling control signal ENA is inactive. It is. However, the presetting of the image data refresh control signal SET is preferably synchronized with the sampling control signal ENA from the viewpoint of simplification of the peripheral circuit.

  According to the timing setting and voltage setting of each control signal described above, control is performed to write and maintain the off voltage not only to the on pixel but also to the off pixel. Thereby, the problem that the off-pixel voltage concerned in Patent Document 1 becomes unstable can be solved.

  In addition, when an odd-numbered row performs a positive refresh in a certain refresh period, an even-numbered row performs a negative-polarity refresh, and in the next refresh period, an odd-numbered row performs a negative-polarity refresh and an even-numbered row performs a positive-polarity refresh. By doing so, AC conversion of the liquid crystal applied voltage waveform and line inversion driving are realized.

According to the driving method based on the control signal, it is possible to hold data written in each pixel in the normal display period ND by performing a regular refresh operation, so that power consumption can be reduced. . For example, consider a case where a VGA (640 × 480) electro-optical device is driven by line inversion. Here, the power consumption P can be generally expressed as P = CFV ² . In normal display, a data signal input to the data line for writing data to each pixel connected to each scanning line is amplified 240 times during one frame. On the other hand, in the driving method of the present invention, the amplitude of the data signal input in one frame (= from the odd-numbered / even-numbered sampling and refresh operations to the next sampling and refresh operations) is only twice. Therefore, in the present invention, the frequency F is 1/120 that of the normal display. Therefore, if other C and V are the same, the power consumption P is 1/120, and the power consumption can be greatly reduced.

  Furthermore, in normal display, the peripheral circuit must always be operated. However, in the present invention, it is only necessary to drive the period of the sampling operation and the refresh operation, and the operation of the peripheral circuit is stopped in other periods. I can do it. For this reason, since the current consumption of the peripheral circuit is also at the quiescent current level, the power consumption can be significantly reduced as well.

  Further, the data signal input to each data line may be a common signal in all pixels on the active matrix array circuit in the sampling operation and the refresh operation, and power consumption can be reduced also in this respect.

(2) Second Embodiment Since the circuit configuration in the second embodiment is the same as that in the first embodiment, the description thereof is omitted.
FIG. 6 shows a second AC timing chart of control signals according to the second embodiment of the present invention.

  At the first AC timing in FIG. 5, the control signals ENA, G, and SET for positive polarity refresh become active and the control signals ENA, G, and SET for the next negative polarity refresh become active. And the interval from when the control signal ENA, G, SET for the negative polarity refresh becomes active until the control signal ENA, G, SET for the next positive polarity refresh becomes different. ing.

  Therefore, the intervals between the sections P1 and P2 where the inter-terminal voltage of the electro-optical element is positive and the sections N1 and N2 where the negative voltage is negative are different. Therefore, this difference in distance becomes a direct current application to the electro-optic element in the long term, which affects the life of the liquid crystal. In addition, control with such a timing control signal is not preferable because the configuration of the scanning line driving circuit becomes complicated.

Therefore, at the second AC timing shown in FIG. 6, by adjusting the polarity inversion timing of the common electrode voltage signal V _COM and the data signal DATA, the sampling control signal ENA, the image data capture control signal G, and the image data refresh control signal SET are activated. The timing interval was kept constant.

  As a result, it is possible to prevent the application of direct current to the liquid crystal applied voltage that has occurred due to the shift in the interval of the active timing at the first AC timing, and there is an effect of further extending the life of the liquid crystal. In addition, the configuration of the scanning line driving circuit can be simplified.

  Since the specific operation is the same as that described in the first embodiment, the description is omitted here.

(3) Third Embodiment Since the circuit configuration in the third embodiment is the same as that in the first embodiment, the description thereof is omitted.
FIG. 7 shows a third AC timing chart of control signals according to the third embodiment of the present invention.

Further, at the third AC timing in FIG. 7, the polarity inversion timing of the counter electrode voltage signal V _COM and the data signal DATA is adjusted so that the active time of the sampling control signal ENA is the same as the active time of the image data capture control signal G. By doing so, the configuration of the scanning line driving circuit can be further simplified, and unnecessary parts can be reduced. As a result, the power consumption can be further reduced than before, and the manufacturing cost can be reduced.

  Similarly to the control at the second AC timing in FIG. 6, it is possible to prevent the direct current application to the liquid crystal applied voltage caused by the deviation of the interval of the active timing at the first AC timing in FIG. There is also an effect.

  When the electro-optical device of the present invention is used in a portable device such as a mobile phone, power consumption can be greatly reduced when performing a display that does not require frequent screen rewriting such as a standby screen display or a clock display. It becomes.

  The embodiments of the present invention have been described in detail above with reference to the drawings. However, the scope of the present invention is not limited to these embodiments. It will be apparent to those skilled in the art that many modifications and variations can be made without departing from the spirit and scope of the invention, which are also within the scope of the invention.

DESCRIPTION OF SYMBOLS 100 Active matrix array circuit 101 Scan line drive circuit 102 Data line drive circuit 103 Drive voltage generation circuit 104 Image processing circuit 105 Control circuit 201,202 Pixel circuit V _COM counter electrode voltage signal DATA Data signal ENA Sampling control signal G Image data acquisition control Signal SET Image data rewrite control signal / image data refresh control signal SW ₁ , SW ₂ , SW ₃ switch element C ₁ holding capacitor C ₂ sampling capacitor LC electro-optic element C _SMP sampling capacitor capacitance C _ST holding capacitor electrostatic Capacitance C Capacitance of _LC electro-optic element V Terminal voltage of _LC electro-optic element

Claims (18)

In a pixel circuit controlled by a plurality of control signals,
One end is connected to a counter electrode, and the counter electrode is supplied with a voltage signal that changes between an L level voltage and an H level voltage;
A first switch element controlled by a sampling control signal on a first control signal line to sample a voltage level held in the electro-optic element;
A second switch element controlled by an image data refresh control signal on the second control signal line;
A third switch element controlled by an image data capture control signal on the third control signal line to capture image data;
A first capacitive element that holds a voltage level sampled by the sampling control signal;
Comprising
The second switch element controls writing of the image data captured via the third switch element to the electro-optic element;
The image data refresh control signal on the second control signal line is generated before the image data refresh control signal is changed from inactive to active while the voltage signal of the H level voltage is supplied to the counter electrode. A pixel circuit, wherein the pixel circuit is preset to an intermediate level between a voltage of the image data refresh control signal when active and a voltage level held in the electro-optical element when the voltage is sampled.   The pixel circuit further includes a second capacitor element having one end connected to the other end of the electro-optic element and the other end connected to a common signal supply line, and the signal supplied to the counter electrode and the common signal 2. The pixel circuit according to claim 1, wherein signals supplied to the supply line are the same. In a driving method of a pixel circuit controlled by a plurality of control signals,
The driving method is:
A first drive for writing image data to an electro-optical element in which one end of the pixel circuit is connected to a counter electrode, and a voltage signal changing between an L level voltage and an H level voltage is supplied to the counter electrode. Steps,
A second driving step for refreshing the written image data;
Comprising
The second driving step includes:
Sampling a voltage level corresponding to image data held in the pixel circuit via a first switch element controlled by a sampling control signal;
By applying a voltage supplied via a second switch element controlled by a voltage level corresponding to the sampled image data and a voltage level of the image data refresh control signal to the electro-optic element, Refreshing the image data held in the
Comprising
The image data refresh control signal is generated when the image data refresh control signal is inactive before the image data refresh control signal changes from inactive to active while a voltage signal having an H level voltage is supplied to the counter electrode. A pixel circuit driving method, wherein a preset level is set to an intermediate level between a voltage of a data refresh control signal and a voltage level held in the electro-optical element when the voltage is sampled.   The step of refreshing the image data held in the pixel circuit further includes the step of supplying the image data to the pixel circuit via a third switch element controlled by an image data capture control signal. The pixel circuit driving method according to claim 3. Intermediate level that will be the preset driving method of the pixel circuit according to 請 Motomeko 4 you, wherein a voltage level corresponding to the characteristics of the second switching element. The step of refreshing the image data has two operations, a first refresh operation and a second refresh operation,
Intermediate level that is the preset driving method of the pixel circuit according to claim 4 or claim 5, characterized in that said first voltage level different in refresh operation and the second refresh operation.   The first and second refresh operations are a refresh operation for performing polarity inversion from negative polarity to positive polarity and a refresh operation for performing polarity inversion from positive polarity to negative polarity, respectively. 7. A driving method of a pixel circuit according to 6.   8. The pixel according to claim 4, wherein the inactive voltages of the sampling control signal, the image data refresh control signal, and the image data capture control signal are at the same level. 9. Circuit driving method.   9. The pixel circuit driving method according to claim 4, wherein active voltages of the sampling control signal and the image data capturing control signal are at the same level. 10.   The time for activating the first switch element by the sampling control signal is equal to the time width for activating the third switch element by the image data capturing control signal. 2. A driving method of a pixel circuit according to claim 1. The step of refreshing the image data held in the pixel circuit, the driving method of the pixel circuit according to claims 3 to any one of claims 10, characterized in row Ukoto at regular intervals. In a driving circuit of a pixel circuit controlled by a plurality of control signals,
The drive circuit is
A first drive for writing image data to an electro-optical element in which one end of the pixel circuit is connected to a counter electrode, and a voltage signal changing between an L level voltage and an H level voltage is supplied to the counter electrode. Means,
Second driving means for refreshing the written image data;
Comprising
The second driving means includes
Means for sampling a voltage level corresponding to image data held in the pixel circuit via a first switch element controlled by a sampling control signal;
By applying a voltage supplied via a second switch element controlled by a voltage level corresponding to the sampled image data and a voltage level of the image data refresh control signal to the electro-optic element, Means for refreshing the image data held in
Comprising
The image data refresh control signal is generated when the image data refresh control signal is inactive before the image data refresh control signal changes from inactive to active while a voltage signal having an H level voltage is supplied to the counter electrode. A driving circuit for a pixel circuit, wherein the driving circuit is preset to an intermediate level between a voltage of a data refresh control signal and a voltage level held in the electro-optical element when the voltage is sampled.   13. The pixel circuit driving circuit according to claim 12, further comprising means for stopping an operation of a peripheral circuit of the pixel circuit after refreshing image data held in the pixel circuit. An active matrix array circuit in which the pixel circuits according to claim 1 are arranged in a matrix,
The pixel circuit driving circuit according to claim 12, wherein the pixel circuit is driven.
An electro-optical device comprising: The preset intermediate level is a voltage level according to the characteristics of the second switch element.
The pixel circuit driving method according to claim 3, wherein the pixel circuit is driven. The step of refreshing the image data has two operations, a first refresh operation and a second refresh operation,
16. The pixel circuit driving method according to claim 3, wherein the preset intermediate level is a voltage level different between the first refresh operation and the second refresh operation. The first and second refresh operations are a refresh operation for performing polarity inversion from negative polarity to positive polarity and a refresh operation for performing polarity inversion from positive polarity to negative polarity, respectively. 17. A driving method of a pixel circuit according to 16. 17. The pixel circuit driving method according to claim 15, wherein the step of refreshing the image data held in the pixel circuit is performed at regular intervals.

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