JP2007165439A - Ferroelectric memory, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a ferroelectric memory for reliably preventing deterioration in characteristics by residual gas, such as hydrogen, generated during a manufacturing process by a simple process, and to provide the ferroelectric memory. <P>SOLUTION: The ferroelectric memory 1 comprises a drive element section 3 formed on a substrate 4; and a ferroelectric capacitor 2 that is arranged on the drive element section 3 via an interlayer insulating film 6 and composed of a lower electrode 8, an upper electrode 10, and a ferroelectric layer 9 held between the pair of electrodes. A first conductive section 12 for electrically connecting the drive element section 3 and the lower electrode 8 is formed on the interlayer insulating film 6. A first hydrogen barrier film 7 is provided at a part excluding an area above the first conductive section 12 between the interlayer insulating film 6 and the lower electrode 8. A second conductive section 20 is connected to the upper electrode 10 in the ferroelectric capacitor 2. The upper surface and the side of the ferroelectric capacitor 2 are covered with a second hydrogen barrier film 13 excluding the connection section of the upper electrode 10 and the second conductive section 20. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a ferroelectric memory having a ferroelectric capacitor and a ferroelectric memory obtained thereby.

A ferroelectric memory has a structure in which a plurality of ferroelectric memory elements are formed by sandwiching a ferroelectric layer made of a ferroelectric material such as PZT (lead zirconate titanate) between a pair of electrodes. ing.
As a method for manufacturing a ferroelectric memory, a transistor or the like is formed on a silicon substrate, the transistor is covered with a first interlayer insulating film, and a plug electrically connected to the transistor is formed in the first interlayer insulating film. Embedded in the contact hole. Then, after forming a ferroelectric capacitor through the plug, a second interlayer insulating film is formed to cover the ferroelectric capacitor, and a contact hole for exposing the ferroelectric capacitor to the second interlayer insulating film is formed. A plug made of tungsten or the like is buried in the contact hole.

  However, in the above manufacturing process, hydrogen is generated in the process of forming the second interlayer insulating film covering the ferroelectric capacitor or the process by dry etching, and the ferroelectric layer is exposed to a hydrogen atmosphere (reducing atmosphere). End up. In general, since the ferroelectric layer is made of a metal oxide, the oxide constituting the ferroelectric layer is reduced by hydrogen when exposed to a hydrogen atmosphere, and the ferroelectric layer is damaged. As a result, the characteristics of the ferroelectric memory deteriorate.

As a measure for preventing such hydrogen damage, a method of covering the ferroelectric capacitor with an interlayer insulating film, providing a hydrogen barrier film on the interlayer insulating film, and further providing an interlayer insulating film again covering the hydrogen barrier film It has been known. However, there is a problem that the ferroelectric memory is deteriorated by residual gas components such as hydrogen and moisture desorbed from the interlayer insulating film due to heat generated in the process after the formation of the ferroelectric capacitor.
Therefore, there is a technique for preventing the residual gas described above from entering the ferroelectric layer by providing hydrogen barrier films on the upper and lower sides of the ferroelectric capacitor and suppressing deterioration of the characteristics of the ferroelectric memory during the manufacturing process ( For example, see Patent Document 1).
Japanese Patent Laid-Open No. 11-8355

By the way, the ferroelectric capacitor is formed by patterning by etching.
However, etching generally performed when forming a ferroelectric capacitor is overetching, so that the hydrogen barrier film provided on the lower side of the ferroelectric capacitor is also etched. Therefore, it is very difficult to perform the etching with the hydrogen barrier film left, and there is a problem that the characteristic deterioration of the ferroelectric memory due to the manufacturing process cannot be sufficiently prevented.

  The present invention has been made in view of such circumstances, and is a ferroelectric memory that reliably prevents characteristic deterioration due to residual gas such as hydrogen generated during the above-described manufacturing process by a simple process. An object of the present invention is to provide a manufacturing method and a ferroelectric memory.

  A method for manufacturing a ferroelectric memory according to the present invention includes a drive element unit formed on a base, a lower electrode and an upper electrode disposed on the drive element unit via an interlayer insulating film, and a pair of these electrodes. In a method for manufacturing a ferroelectric memory comprising a ferroelectric capacitor comprising a ferroelectric layer sandwiched between the first and second layers, a step of providing a first insulating film so as to cover the drive element portion formed on the substrate; Forming a first contact hole in the first insulating film and providing a first conductive portion in the first contact hole; and a first hydrogen for exposing the first conductive portion on the first insulating film. A step of providing a barrier film; a step of providing a precursor layer of the ferroelectric capacitor on the first hydrogen barrier film so as to be connected to the first conductive portion; and at least reaching the first insulating film Etching the precursor layer until Forming a ferroelectric capacitor in which a bottom surface excluding the top of the first conductive portion is covered with the first hydrogen barrier film; and covering the top surface and the side surface of the ferroelectric capacitor. A step of providing a second hydrogen barrier film on the insulating film; a step of providing a second insulating film so as to cover the ferroelectric capacitor after providing the second hydrogen barrier film; and Forming a second contact hole that exposes the upper electrode in the hydrogen barrier film, and providing a second conductive portion in the second contact hole.

According to the method for manufacturing a ferroelectric memory of the present invention, the first hydrogen barrier film is formed in a state where the first conductive portion that is conductive to the drive element portion is exposed, and the strong resistance provided on the first hydrogen barrier film is provided. Since the precursor layer of the dielectric capacitor is etched, the bottom surface side of the ferroelectric capacitor is formed in a state where the portion other than the connection portion with the first conductive portion is covered with the first hydrogen barrier film.
Then, a second hydrogen barrier film is provided so as to cover the upper surface and the side surface of the ferroelectric capacitor, and the second insulating film is formed by forming the ferroelectric capacitor in which the upper surface, the side surface, and the bottom surface are covered with the hydrogen barrier film. Damage due to hydrogen (reducing atmosphere) generated when forming the second contact hole in the second insulating film or the like can be prevented.
Further, in the etching process of the precursor layer, it is sufficient to reach at least the first insulating film, and therefore over-etching is allowed, so that it is not necessary to strictly control the etching conditions, and the etching process can be simplified. It becomes a highly stable manufacturing method with a high margin.
Therefore, it is possible to provide a ferroelectric memory having high reliability and productivity in which characteristic deterioration due to damage to the ferroelectric capacitor during the manufacturing process is prevented.

In the method for manufacturing a ferroelectric memory, it is preferable that the first hydrogen barrier film is formed of an oxide having a hydrogen barrier property.
In this way, damage due to hydrogen from the lower surface side of the ferroelectric capacitor can be reliably prevented regardless of the conductivity of the hydrogen barrier film. In addition, since the first hydrogen barrier film at the connection portion between the first conductive portion and the lower electrode is removed, for example, when the first hydrogen barrier film is made of a conductive Ir oxide However, it is possible to prevent such a problem that the first conductive portion is oxidized and the conductivity is lowered.

  The ferroelectric memory of the present invention is sandwiched between a pair of electrodes and a driving element section formed on a base, and a lower electrode and an upper electrode disposed on the driving element section via an interlayer insulating film. In the ferroelectric memory comprising the ferroelectric capacitor comprising the ferroelectric layer, the drive element portion and the lower electrode of the ferroelectric capacitor are electrically connected to the interlayer insulating film. A first conductive portion is formed, and a first hydrogen barrier film is provided between the interlayer insulating film and the lower electrode of the ferroelectric capacitor except for the portion on the first conductive portion. The second conductive portion is connected to the upper electrode of the capacitor, and the upper surface and side surfaces of the ferroelectric capacitor are covered with a second hydrogen barrier film except for the connection portion between the upper electrode and the second conductive portion. It is characterized by.

According to the ferroelectric memory of the present invention, since the lower electrode provided with the first hydrogen barrier film is provided at a portion other than the first conductive portion, for example, the first conductive portion conducting to the drive element portion is exposed. In this state, the first hydrogen barrier film is formed, and the ferroelectric capacitor is formed by performing over-etching that reaches at least the interlayer insulating film with respect to the precursor layer. In this way, by allowing over-etching, the etching conditions are not strictly set, the etching process is simplified, a large margin can be obtained during etching, and the etching process is highly stable.
Further, for example, when the second interlayer insulating film is provided to cover the ferroelectric capacitor, the top surface, the side surface, and the bottom surface are covered with the first and second hydrogen barrier films. It is possible to prevent damage due to hydrogen (reducing atmosphere) generated during formation or contact hole formation when forming the second conductive portion in the second interlayer insulating film.
The ferroelectric memory of the present invention formed in this way is highly reliable because it is not damaged by hydrogen during the manufacturing process and the like, and the deterioration of characteristics is prevented.

In the ferroelectric memory, it is preferable that the second hydrogen barrier film is provided on a surface of the interlayer insulating film exposed without being covered with the ferroelectric capacitor.
In this case, by providing the second hydrogen barrier film so as to cover the exposed interlayer insulating film, for example, the hydrogen contained in the interlayer insulating film is double-barrier by the second hydrogen barrier film. Therefore, the ferroelectric capacitor is better prevented from being exposed to a hydrogen atmosphere.

A ferroelectric memory manufacturing method and a ferroelectric memory according to an embodiment of the present invention will be described below.
First, an embodiment of a ferroelectric memory according to the present invention will be described.

FIG. 1 is a side sectional view showing a schematic configuration of a ferroelectric memory according to the present embodiment. Reference numeral 1 in the drawing denotes a ferroelectric memory. Similar to the DRAM cell, this ferroelectric memory 1 has a structure in which a charge as information is stored in a storage capacitor. A ferroelectric capacitor 2 and a driving transistor for operating the ferroelectric capacitor 2 are provided. The driving transistor 3 is formed on a substrate 4.
As shown in FIG. 1, the ferroelectric capacitor 2 is formed by sandwiching a ferroelectric layer 9 between a pair of electrodes composed of an upper electrode 10 and a lower electrode 8.

  The substrate 4 includes a silicon substrate 5, and the driving transistor 3 is formed on the surface layer portion of the silicon substrate 5. As the driving transistor 3, a known configuration can be applied. For example, a thin film transistor (TFT) or a MOSFET can be used. In the illustrated example, a MOSFET is used, a source region SR, a drain region DR, and a channel region (not shown) are formed, and a gate electrode 3a is formed on the channel region via a gate insulating film. .

  With this configuration, the driving transistor 3 is formed on the base 4. Here, the ferroelectric memory 1 according to the present embodiment is a so-called 1T1C system in which a memory cell has one transistor and one ferroelectric capacitor. In each memory cell, the drive transistor 3 corresponding to each ferroelectric capacitor 2 is separated by an element isolation region such as LOCOS or trench isolation (not shown) formed in the silicon substrate 5.

Further, a first interlayer insulating film 6 is formed on the silicon substrate 5 on the substrate 4 so as to cover the driving transistor 3. The first interlayer insulating film 6 is made of silicon oxide (SiO ₂ ), and is planarized by CMP (Chemical Mechanical Polishing) or the like as necessary.

The ferroelectric capacitor 2 is formed on the substrate 4 on which the first interlayer insulating film 6 is formed as described above.
As described above, the ferroelectric capacitor 2 includes the lower electrode 8 formed on the first interlayer insulating film 6, the ferroelectric layer 9 formed on the lower electrode 8, and the ferroelectric layer 9. It is a stack type comprising the upper electrode 10 formed thereon. The lower electrode 8 and the upper electrode 10 are made of platinum (Pt), iridium (Ir), iridium oxide (IrO ₂ ) or the like, and the ferroelectric layer 9 is made of Pb (Zr, Ti) O ₃ (PZT). And (Pb, La) (Zr, Ti) O ₃ (PLZT), and those obtained by adding a metal such as niobium (Nb) to these materials.

Here, a contact hole formed so as to penetrate through the first interlayer insulating film 6 communicates with the bottom of the lower electrode 8.
Specifically, a plurality of first contact holes 11 are formed in the first interlayer insulating film 6, and a first plug (first electrode) made of tungsten (W) or the like is formed in the first contact holes 11. 1 conductive portion) 12 is embedded. Here, the first contact hole 11 includes a capacitor contact hole 11 a communicating with the drain region DR of the driving transistor 3 and a base contact hole 11 b communicating with the source region SR of the driving transistor 3.

  With such a configuration, the lower electrode 8 is connected to the plug 12 formed in the capacitor contact hole 11a. The first plug 12 is connected to the drain region DR of the driving transistor 3 so that the ferroelectric capacitor 2 is operated by the driving transistor 3.

Further, the second interlayer insulating film 14 is provided on the first interlayer insulating film 6 so as to cover the ferroelectric capacitor 2. As a material constituting the second interlayer insulating film 14, silicon oxide (SiO ₂ ) can be used similarly to the first interlayer insulating film 6.
A plurality of second contact holes 17 are formed in the second interlayer insulating film 14, and a second plug (second conductive portion) made of tungsten (W) or the like is formed in the second contact holes 17. ) 20 is buried. Here, the second contact hole 17 communicates with a second capacitor contact hole 17 a communicating with the upper electrode 10 in the ferroelectric capacitor 2 and a base contact hole 11 b communicating with the source region SR of the driving transistor 3. It consists of a second base contact hole 17b.

The second plug 20 is connected to the first plug 12 provided in the base contact hole 11b by the second base contact hole 17b communicating with the base contact hole 11b. It has become.
The second plug 20 is connected to a wiring or the like (not shown) on the second interlayer insulating film 14, thereby energizing the upper electrode 10 of the ferroelectric capacitor 2 and the source region of the driving transistor 3. The SR and drain region DR are energized.

  Meanwhile, a first hydrogen barrier film 7 is provided between the first interlayer insulating film 6 and the lower electrode 8. Here, as described above, since the plug 12 is connected to the lower electrode 8, the first hydrogen barrier film 7 is provided in a portion other than on the first plug 12. .

  As such a first hydrogen barrier film 7, a hydrogen barrier material made of an oxide having hydrogen barrier properties can be used. Specifically, the hydrogen barrier material includes an oxide of aluminum (Al), an oxide of titanium (Ti), an oxide of iridium (Ir), and SrRuOx (strontium ruthenium) which is a composite oxide of Sr (strontium). Oxide) or the like, and in this embodiment, aluminum oxide (AlOx) is used.

Here, the Ir oxide and SrRuOx are conductive hydrogen barrier films, and the Al oxide and Ti oxide are insulating hydrogen barrier films. The first hydrogen barrier film 7 may be insulative or conductive as long as it is made of an oxide having hydrogen barrier properties as described above.
When the first hydrogen barrier film 7 is made of an Ir oxide and has conductivity, tungsten (W) constituting the first hydrogen barrier film 7 and the plug 12 is oxidized. However, in the present invention, the first hydrogen barrier film 7 at the connecting portion between the first plug 12 and the lower electrode 8 is removed to remove the above-described problem. The first plug 12 made of tungsten is prevented from being oxidized.

  The first hydrogen barrier film 7 is formed to have a thickness of about 5 nm to 30 nm. If the thickness is less than 5 nm, the hydrogen barrier effect of the first hydrogen barrier film 7 may not be sufficiently obtained. If the thickness exceeds 30 nm, the etching load for forming a contact hole described later increases.

  On the other hand, a second hydrogen barrier film 13 is formed on the ferroelectric capacitor 2 so as to cover the upper surface (that is, the upper electrode 10) and side surfaces thereof. In the present embodiment, the surface of the first interlayer insulating film 6 exposed without being covered with the ferroelectric capacitor 2 is covered with the second hydrogen barrier film 13. That is, the second hydrogen barrier film 13 is interposed between the second interlayer insulating film 14 and the ferroelectric capacitor 2 and the first interlayer insulating film.

  Note that, as described above, since the second plug 20 is connected to the upper electrode 10, the second hydrogen barrier film 13 is formed of the ferroelectric except for the connection portion with the upper electrode 10. The upper and side surfaces of the body capacitor are covered.

  As the second hydrogen barrier film 13, an insulating hydrogen barrier film is used. Specifically, the above-described insulating aluminum (Al) oxide and titanium (Ti) oxide can be employed. In the present embodiment, aluminum oxide ( AlOx) is used. Thereby, the hydrogen barrier property can be imparted to the ferroelectric capacitor 2 without conducting between the upper electrode 10 and the lower electrode 8.

  The second hydrogen barrier film 13 is formed to a thickness of about 20 nm to 100 nm. If the thickness is less than 20 nm, the hydrogen barrier effect of the second hydrogen barrier film 13 may not be sufficiently obtained. If the thickness exceeds 100 nm, the etching load for forming a contact hole described later increases.

  With such a configuration, the ferroelectric capacitor 2 is covered with the second hydrogen barrier film 13 at the top and side except for the connection portion with the second plug 20 and with the first plug 12. The bottom surface of the lower electrode 8 excluding the connection portion is covered with the first hydrogen barrier film 7.

According to the ferroelectric memory 1 according to the present embodiment, the first hydrogen barrier film 7 is provided on the bottom surface except on the first plug 12, and the upper surface and the side surface are covered with the second hydrogen barrier film 13. Since the capacitor 2 is provided, as will be described later, for example, when the second interlayer insulating film 14 is provided so as to cover the ferroelectric capacitor 2, the ferroelectric capacitor is caused by hydrogen present in the second interlayer insulating film 14. 2 can be prevented from deteriorating.
Therefore, the ferroelectric memory 1 of the present embodiment is highly reliable because it is not damaged by hydrogen during the manufacturing process or the like and the deterioration of characteristics is prevented.

(Manufacturing method of ferroelectric memory)
Next, an embodiment of a method for manufacturing the ferroelectric memory 1 according to the present invention will be described based on the method for manufacturing the ferroelectric memory 1 having such a configuration.
First, as shown in FIG. 2A, a drive transistor 3 is formed on a silicon substrate 5 by a known method in advance, and then SiO ₂ is formed as a first interlayer insulating film 6 to cover the drive transistor 3 by a CVD method or the like. Deposited by. The thickness of the first interlayer insulating film 6 is set to about 1500 nm so that the ferroelectric capacitor 2 is not exposed when planarization is performed in the next process.

  Here, the first interlayer insulating film 6 is planarized by a chemical mechanical polishing method or the like. By flattening the first interlayer insulating film 6 in this way, it is possible to reduce the thickness of the first interlayer insulating film 6 immediately above the ferroelectric capacitor 2, and thus lead to the ferroelectric capacitor 2 described later. The formation of the first contact hole 11 can be facilitated. Further, since the planarization process is performed by a chemical mechanical polishing method, the process becomes relatively easy, and the process can be stabilized.

Prior to the formation of the ferroelectric capacitor 2, the first interlayer insulating film 6 is formed and then etched to form the first contact hole 11.
Specifically, as shown in FIG. 2B, a resist pattern (not shown) is formed on the first interlayer insulating film 6 by a known method, and RIE (reactivity) is further formed using this resist pattern as a mask. The capacitor contact hole 11a communicating with the drain region DR of the drive transistor 3 is etched by an ion etching method, an etching method using ICP (inductively coupled plasma), an etching method using ECR (electron cyclotron resonance) plasma, or the like. Then, a base contact hole 11b leading to the source region SR of the driving transistor 3 is formed.

  Then, a conductive material is embedded in these first contact holes 11. The conductive material is formed / embedded by first forming titanium (Ti) and titanium nitride (TiN) as an adhesion layer by a sputtering method or the like, and then forming tungsten (W). In this way, the first plug 12 is formed by filling the first contact hole 11 with the conductive material.

Subsequently, a first hydrogen barrier film 7 exposing the first plug 12 is provided on the first interlayer insulating film 6.
Specifically, as shown in FIG. 2C, the first hydrogen barrier film 7 made of AlOx or the like is formed by, for example, sputtering or CVD. The first hydrogen barrier film 7 made of AlOx is formed to have a thickness of about 5 nm to 30 nm as described above.
Thereafter, the first hydrogen barrier film 7 is etched by a known method to remove a portion immediately above the first plug 12 connected to the drain region DR of the driving transistor 3.

Next, a precursor layer of the ferroelectric capacitor 2 is provided on the first hydrogen barrier film 7 so as to be connected to the first plug 12 and become conductive.
Specifically, as shown in FIG. 2 (d), the materials constituting the lower electrode 8, the ferroelectric layer 9, and the upper electrode 10 are sequentially formed and laminated to form a precursor layer 2A. Form. Examples of such a film forming method include a spin coating method, a dipping method, a sputtering method, an MOCVD method, and a laser ablation method. At this time, the lowermost layer of the precursor layer 2A corresponding to the lower electrode 8 is in a conductive state with the first plug 12 in the portion where the first hydrogen barrier film 7 is removed.

Next, the ferroelectric layer 2 is formed by patterning the precursor layer 2A by etching.
Specifically, as shown in FIG. 2 (e), a resist pattern (not shown) is formed on the precursor layer 2A, and this resist pattern is used as a mask to carry out a RIE (reactive ion etching) method, The ferroelectric capacitor 2 is formed by using an etching method using ICP (inductively coupled plasma).

  By the way, when the ferroelectric capacitor 2 is formed, the etching is stopped when the first hydrogen barrier film 7 provided between the precursor layer 2A and the first interlayer insulating film 6 is reached. However, such an etching process (so-called just etching) requires strict control of the etching conditions, and the etching process becomes very complicated.

  Therefore, in the present invention, the ferroelectric capacitor 2 is formed by etching the precursor layer 2A until at least the first interlayer insulating film 6 is reached. That is, the ferroelectric capacitor 2 is formed by over-etching up to the first interlayer insulating film 6. In this way, by allowing over-etching, the process becomes simpler than that for the purpose of just etching, it is possible to increase the margin at the time of etching, and a high-yield, high-stability etching process. Become.

Through the above process, the ferroelectric capacitor 2 in which the ferroelectric layer 9 is sandwiched between the upper electrode 10 and the lower electrode 8 is manufactured. In the present embodiment, as shown in FIG. 2E, the surface of the first interlayer insulating film 6 where the ferroelectric capacitor 2 is not provided has a step due to the above-described over-etching.
In the ferroelectric capacitor 2, the portion of the lower electrode 8 except for the top of the plug 12 is covered with the first hydrogen barrier film 7.

Subsequently, as shown in FIG. 3A, a second hydrogen barrier film 13 is provided on the first interlayer insulating film 6 so as to cover the upper surface and side surfaces of the ferroelectric capacitor 2.
Specifically, the second hydrogen barrier film 13 made of AlOx or the like is formed by, for example, sputtering or CVD. As described above, the thickness of the second hydrogen barrier film 13 made of AlOx is formed to be about 20 nm to 100 nm.
By this step, the surface of the first interlayer insulating film 6 exposed without being covered by the ferroelectric capacitor 2, that is, the first interlayer insulating film exposed by removing the first hydrogen barrier film 7 by overetching. The surface of 6 is covered with the second hydrogen barrier film 13. In addition, as described above, the side surface portions 6a that respectively connect the surfaces of the first interlayer insulating film 6 that are stepped by over-etching are also covered with the second hydrogen barrier film 13.

After the second hydrogen barrier film 13 is thus provided, a second interlayer insulating film 14 is formed so as to cover the ferroelectric capacitor 2 as shown in FIG. Specifically, after the SiO ₂ is deposited by the CVD method or the like, the second interlayer insulating film 14 is planarized by a CMP (Chemical Mechanical Inspection) process. Thus, the second hydrogen barrier film 13 is provided between the first interlayer insulating film 6 and the second interlayer insulating film 14.

Next, a resist pattern (not shown) is formed on the second interlayer insulating film 14 by a known method. Further, using this resist pattern as a mask, an RIE (reactive ion etching) method or ICP (inductively coupled plasma) is used. The second interlayer insulating film 14 and the second hydrogen barrier film 13 are collectively etched by an etching method using ECR or an etching method using ECR (electron cyclotron resonance) plasma to form a second contact hole 17 at a desired position. To do.
Note that, for example, even when hydrogen (hydrogen atmosphere) is generated during the formation process of the second interlayer insulating film 14 and the formation process of the second contact hole 17, the ferroelectric capacitor 2 has a hydrogen barrier as described above. Since it is covered with the films 7 and 13, the characteristics are not deteriorated by the hydrogen.

  Specifically, as shown in FIG. 3C, the second contact hole forming step includes a second capacitor contact hole 17 a communicating with the upper electrode 10 in the ferroelectric capacitor 2, and the driving transistor 3. A base contact hole 17b communicating with the first plug 12 conducting to the source region SR is formed.

Then, titanium (Ti) and titanium nitride (TiN) are formed as an adhesion layer in these second contact holes 17 by sputtering or the like, and then tungsten (W) is formed, and the second plug 20 is formed. Form.
Therefore, as shown in FIG. 1, in the source region SR of the driving transistor 3, a two-stage plug including the first plug 12 and the second plug 20 that is electrically connected thereto is formed.

  When the second plug 20 is formed in this way, as shown in FIG. 4, for example, the wiring 30 connected to the second plug 20 connected to the upper electrode 10 of the ferroelectric capacitor 2 is secondly connected. A third interlayer insulating film 31 is formed on the interlayer insulating film 14 and further covering the wiring 30. Then, a contact hole 31 a communicating with the second plug is formed in the third interlayer insulating film 31, a third plug 32 is formed in the contact hole 31 a, and an Al wiring 34 electrically connected to the third plug 32 is formed. Form. In this way, a device including the ferroelectric memory 1 of the present invention is completed.

According to such a method for manufacturing the ferroelectric memory 1, the first hydrogen barrier film 7 is formed in a state in which the first plug 12 conducting to the driving transistor 3 is exposed, and the first hydrogen barrier film 7 is formed on the first hydrogen barrier film 7. Since the precursor layer 2A of the provided ferroelectric capacitor 2 is etched, the first hydrogen barrier film is formed on the bottom surface side (lower electrode 8) of the ferroelectric capacitor 2 except for the connection portion with the first plug 12. 7 is formed in a state covered with 7.
Then, a second hydrogen barrier film 13 is provided so as to cover the upper surface and the side surface of the ferroelectric capacitor 2, and the upper surface, the side surface, and the bottom surface are covered with the first and second hydrogen barrier films 7, 13. 2 is formed, the damage caused by hydrogen (reducing atmosphere) generated when the second interlayer insulating film 14 is formed or when the second contact hole 17 is formed in the second interlayer insulating film 14 is improved. Can be prevented.

Further, in the etching process of the precursor layer 2A, since the over etching reaching at least the first interlayer insulating film 6 is allowed, the etching process can be simplified without strictly controlling the etching conditions. The width (margin) is large and the stability is high.
Therefore, it is possible to provide the ferroelectric memory 1 having high reliability and productivity, in which characteristic deterioration due to damage to the ferroelectric capacitor 2 during the manufacturing process is prevented.

  Such a ferroelectric memory 1 includes a mobile phone, a personal computer, a liquid crystal device, an electronic notebook, a pager, a POS terminal, an IC card, a mini-disc player, a liquid crystal projector, and an engineering work station (EWS), a word processor, a television, The present invention can be applied to various electronic devices such as a viewfinder type or a monitor direct-view type video tape recorder, an electronic desk calculator, a car navigation device, a device equipped with a touch panel, a clock, a game device, and an electrophoresis device.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. For example, when forming the base contact hole 11b and the second base contact hole 17b communicating with the source region SR of the driving transistor 3 and the first and second plugs 12 and 20 embedded in the contact holes 11b and 17b, After the second interlayer insulating film 14 is provided on the first interlayer insulating film 6 via the second hydrogen barrier film 13, the contact that communicates with the source region SR from the second interlayer insulating film 14 at once. A hole may be formed, and tungsten (W) may be embedded in the contact hole. In this embodiment, the 1T1C type ferroelectric memory has been described. However, the present invention can also be applied to a 2T2C type ferroelectric memory.

1 is a side sectional view showing a schematic configuration of a ferroelectric memory. (A)-(e) is a figure explaining the manufacturing process of a ferroelectric memory. (A)-(c) is a figure explaining the manufacturing process following FIG. FIG. 4 is a diagram for explaining the manufacturing process of the ferroelectric memory following FIG. 3.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Ferroelectric memory, 2 ... Ferroelectric capacitor, 2A ... Precursor layer, 3 ... Drive transistor (drive element part), 4 ... Base | substrate, 6 ... 1st insulating film, 7 ... 1st hydrogen barrier film, 8 ... Lower electrode, 9 ... Ferroelectric layer, 10 ... Upper electrode, 11 ... First contact hole, 12 ... First plug (first conductive part), 13 ... Second hydrogen barrier film, 14 ... Second interlayer insulating film , 17 ... second contact hole, 20 ... second plug (second conductive part)

Claims (4)

A driving element portion formed on a base, and a ferroelectric layer composed of a lower electrode, an upper electrode, and a ferroelectric layer sandwiched between the pair of electrodes, disposed on the driving element portion via an interlayer insulating film. In a method for manufacturing a ferroelectric memory comprising a dielectric capacitor,
Providing a first insulating film so as to cover the drive element portion formed on the substrate;
Forming a first contact hole in the first insulating film and providing a first conductive portion in the first contact hole;
Providing a first hydrogen barrier film exposing the first conductive portion on the first insulating film;
Providing a precursor layer of the ferroelectric capacitor on the first hydrogen barrier film so as to be connected to the first conductive portion;
Etching the precursor layer until it reaches at least the first insulating film, and forming a ferroelectric capacitor in which a bottom surface excluding the top of the first conductive portion is covered with the first hydrogen barrier film;
Providing a second hydrogen barrier film on the first insulating film so as to cover an upper surface and a side surface of the ferroelectric capacitor;
Providing the second hydrogen barrier film and then providing a second insulating film covering the ferroelectric capacitor;
Forming a second contact hole that exposes the upper electrode in the second insulating film and the second hydrogen barrier film, and providing a second conductive portion in the second contact hole. A method for manufacturing a ferroelectric memory.   2. The method of manufacturing a ferroelectric memory according to claim 1, wherein the first hydrogen barrier film is formed of an oxide having a hydrogen barrier property. A driving element portion formed on a base, and a ferroelectric layer composed of a lower electrode, an upper electrode, and a ferroelectric layer sandwiched between the pair of electrodes, disposed on the driving element portion via an interlayer insulating film. In a ferroelectric memory comprising a dielectric capacitor,
The interlayer insulating film is formed with a first conductive portion that electrically connects the driving element portion and the lower electrode of the ferroelectric capacitor,
Between the interlayer insulating film and the lower electrode of the ferroelectric capacitor, a first hydrogen barrier film is provided at a portion other than on the first conductive portion,
The second conductive part is connected to the upper electrode of the ferroelectric capacitor,
The ferroelectric memory according to claim 1, wherein an upper surface and a side surface of the ferroelectric capacitor are covered with a second hydrogen barrier film except for a connection portion between the upper electrode and the second conductive portion. 4. The ferroelectric memory according to claim 3, wherein the second hydrogen barrier film is provided on a surface of the interlayer insulating film exposed without being covered with the ferroelectric capacitor.

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