JP2007157977A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of improving operational reliability, and capable of contributing to realizating to high-speed operation by suppressing short-circuitings among memory cells. <P>SOLUTION: A capacitor 102 employs an impurity region, formed below the capacitor 102 in an active region 7 as lower electrode. The upper electrode 22 of the capacitor 102 is provided with a recess 10 on the side surface thereof. The recess 10 is provided on the active region 7. In another words, the width of upper electrode 22 in the section of the active region is narrower than that in the section of a separated region. Accordingly, when ions for forming the source/drain region of a MOS (metal oxide semiconductor) transistor are implanted, the ions can be implanted into the active region 7 that is further inside than the width W<SB>U2</SB>of the upper electrode 22. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a capacitor formed on a semiconductor substrate, such as a DRAM (Dynamic Random Access Memory).

  As a conventional semiconductor memory device, a DRAM cell is known which includes a MOS (Metal-Oxide Semiconductor) transistor and a capacitor having an impurity diffusion layer connected to the source / drain region of the MOS transistor as a lower electrode ( For example, Patent Documents 1 and 2).

  For example, in Patent Document 1, an active region in which a DRAM cell is formed is defined by a trench above a semiconductor substrate, and an isolation insulating film (field insulating film) is formed in the trench. A recess (cavity) exposing the inner wall of the trench (side wall of the active region) is formed above the isolation insulating film, and the capacitor of the DRAM cell extends from the upper surface of the active region to the inner wall of the trench exposed in the recess. By forming so, the effective area of the capacitor is increased and the capacity is increased.

  In the DRAM cell of Patent Document 1, the sidewalls formed on the gate electrode side surface and the capacitor upper electrode side surface of the MOS transistor are thick, and the upper part of the source / drain region of the MOS transistor connected to the capacitor is completely on these sidewalls. It was covered with. Therefore, the upper surface of the source / drain region cannot be silicided to reduce the resistance between the MOS transistor and the capacitor. This hinders high-speed operation of the semiconductor memory device.

  On the other hand, Patent Document 2 discloses a DRAM cell structure in which a sidewall on the side surface of the gate electrode of the MOS transistor and a sidewall on the side surface of the capacitor upper electrode are separated from each other, and the silicide is formed above the source / drain region of the MOS transistor. A technique for reducing the resistance by forming a layer has been suggested.

JP-T-2004-527901 JP 2004-311853 A

  In order to extend the capacitor of the DRAM cell from the upper surface of the active region to the inner wall of the trench as in Patent Documents 1 and 2, naturally, the lower electrode and the upper electrode constituting the capacitor are extended from the upper surface of the active region to the inner wall of the trench. It must be formed to extend. Hereinafter, these forming methods will be briefly described.

  In a conventional DRAM cell manufacturing process, an impurity diffusion layer functioning as a lower electrode (hereinafter referred to as a “lower diffusion layer”) is used as an ion implantation mask as an etching mask when a recess is formed above an isolation insulating film. It is formed by the ion implantation used. The upper electrode is formed in the same process as the gate electrode of the MOS transistor, and is formed by depositing an electrode material such as polysilicon on the entire surface including the inside of the recess and patterning it. Therefore, a part of the upper electrode is embedded in the recess, but the portion in the recess in the upper electrode needs to be completely covered by the portion outside the recess and the side wall of the side. Otherwise, the portion of the upper electrode in the recess is exposed between adjacent cells, and its surface forms a silicide layer that is integral with the upper portion of the source / drain region of the MOS transistor. This is because the electrodes are short-circuited and cause failure or malfunction. This problem can be avoided by increasing the thickness of the sidewall. However, as described above, it is difficult to reduce the resistance due to silicidation between the MOS transistor and the capacitor. Is desirable. Therefore, in manufacturing a conventional DRAM cell, the upper electrode is formed to be somewhat wider than the recess in consideration of dimensional variation and misalignment.

  As described above, in the ion implantation for forming the lower diffusion layer of the capacitor, the etching mask at the time of forming the recess is used as a mask, so that ions are not implanted outside the width of the recess. In the ion implantation for forming the source / drain regions of the MOS transistor, the upper electrode of the capacitor is also used as a mask together with the gate electrode, so that ions are not implanted below the upper electrode. Therefore, when the upper electrode is formed wider than the recess, ions are implanted below the edge portion of the upper electrode (the portion outside the recess width) in both the lower diffusion layer forming process and the source / drain region forming process. A region that is not formed is formed, and the resistance of the portion becomes high. As a result, the connection resistance between the MOS transistor and the capacitor becomes high, the read / write margin of the DRAM cell becomes small, the operation reliability is lowered, and the high-speed operation of the semiconductor memory device is hindered. .

  The present invention has been made to solve the above-described problems, and provides a semiconductor device having a capacitor that can reduce wiring resistance while suppressing failure and malfunction due to a short circuit. Objective.

  A semiconductor device according to the present invention is formed so as to extend from an upper surface of the active region to an inner wall of the trench, a trench formed in an upper portion of a semiconductor substrate, an active region defined by the trench in the semiconductor substrate. A first electrode which is a doped impurity diffusion layer, a dielectric layer formed on the surface of the impurity diffusion layer, and a second electrode formed on the dielectric layer and partially embedded in the trench A capacitor, and the second electrode has a recess on a side surface on the active region.

A first aspect of the method for manufacturing a semiconductor device according to the present invention includes (a) a step of defining an active region in the semiconductor substrate by forming a trench in the upper portion of the semiconductor substrate;
(B) a step of forming an isolation insulating film in the trench; and (c) a step of forming a recess on the upper side of the isolation insulating film by etching using a first resist mask in which a capacitor formation region is opened as a mask. (D) forming an impurity diffusion layer serving as a first electrode of the capacitor on the active region and on the inner wall of the recess by first ion implantation using the first resist mask as a mask; and (e) Forming a dielectric layer on the impurity diffusion layer, then forming an electrode material on the entire surface including the inside of the recess, and (f) etching using a second resist mask covering the capacitor formation region as a mask, Patterning the electrode material to form a second electrode of the capacitor; and (g) second ion implantation performed in a self-aligned manner with respect to the second electrode, And a step of implanting ions of the same conductivity type as the first ion implantation sexual region, the second resist mask is one that has a recessed portion on a side surface on the active region.

  A second aspect of the method for manufacturing a semiconductor device according to the present invention includes: (a) a step of defining an active region in the semiconductor substrate by forming a trench in the upper portion of the semiconductor substrate; and (b) in the trench. A step of forming an isolation insulating film; and (c) a step of forming a recess in the upper portion of the isolation insulating film by etching using the first resist mask in which the capacitor formation region is opened as a mask; A step of forming an impurity diffusion layer serving as a first electrode of the capacitor on the active region and on the inner wall of the recess by first ion implantation using one resist mask as a mask; and (e) a dielectric on the impurity diffusion layer. Forming a body layer, and then forming an electrode material on the entire surface including the inside of the recess; and (f) etching using a second resist mask covering the capacitor formation region as a mask. Forming a second electrode of the capacitor by patterning the electrode material by (g), and (g) second ion implantation performed in a self-aligned manner with respect to the second electrode to form the first electrode in the active region. And a step of implanting ions of the same conductivity type as the ion implantation, and the first resist mask has a recess on a side surface on the active region.

  A third aspect of the method for manufacturing a semiconductor device according to the present invention includes: (a) an ion implantation step for forming an impurity diffusion layer serving as an electrode of a capacitor in the active region of the semiconductor substrate; and (b) in the active region. An ion implantation process for channel doping for threshold adjustment of the MOS transistor to be formed, and when the conductivity types of ions to be implanted are different between the processes (a) and (b), the process (b) However, this is performed using at least a resist mask covering the capacitor formation region as a mask.

  According to the semiconductor device of the present invention, since the second electrode of the capacitor has a recessed portion on the side surface on the active region, the width of the second electrode is larger than that of the entire second electrode even after the second electrode is formed. Ion implantation into the inner active region can be performed. Therefore, it is difficult to form a high-resistance region with a low impurity concentration at the edge portion of the second electrode, and the wiring resistance in a semiconductor device including a capacitor such as a DRAM can be reduced.

  According to the first aspect of the method for manufacturing a semiconductor device of the present invention, the second resist mask for patterning the second electrode serving as the mask for the second ion implantation has a recess on the side surface on the active region. Therefore, the second electrode is formed so as to have a recess on the side surface on the active region. Therefore, in the second ion implantation, ion implantation into the active region inside the width of the entire second electrode can be performed. Therefore, it is difficult to form a high-resistance region with a low impurity concentration at the edge portion of the second electrode, and the wiring resistance in a semiconductor device including a capacitor such as a DRAM can be reduced.

  According to the second aspect of the method for manufacturing a semiconductor device of the present invention, the first resist mask serving as a mask for etching for forming the recess and the first ion implantation has a recess on the side surface on the active region. Therefore, in the first ion implantation, ion implantation into the active region outside the width of the entire recess can be performed. Therefore, it is difficult to form a high-resistance region with a low impurity concentration at the edge portion of the second electrode, and the wiring resistance in a semiconductor device including a capacitor such as a DRAM can be reduced.

  According to the third aspect of the method of manufacturing a semiconductor device according to the present invention, when the conductivity type of ions to be implanted is different between the step of forming the impurity diffusion layer to be the capacitor electrode and the channel doping step of the MOS transistor, Since channel doping is performed using a resist mask covering the capacitor formation region as a mask, the impurity concentration of the impurity diffusion layer can be prevented from being lowered by the channel doping. Therefore, it is difficult to form a high-resistance region with a low impurity concentration at the edge portion of the second electrode, and the wiring resistance in a semiconductor device including a capacitor such as a DRAM can be reduced.

<Embodiment 1>
First, in order to clarify the difference between the present invention and the prior art, the structure and manufacturing method of a conventional semiconductor device serving as a base will be described prior to the description of the present invention.

  FIG. 1 is a circuit diagram of a general DRAM cell. The DRAM cell 100 includes a PMOS transistor 101 that is an access transistor for writing, refreshing, and reading data, and a capacitor 102 that accumulates charges corresponding to data. In the PMOS transistor 101, the gate terminal is connected to the word line WL, one of the source / drain terminals is connected to the bit line BL, and the other is connected to one terminal of the capacitor 102. The other terminal of the capacitor 102 is connected to a predetermined power source.

  FIG. 2A is a cross-sectional view of a conventional DRAM cell. In the figure, two DRAM cells 100 adjacent in the extending direction of the bit line BL are shown. That is, a DRAM cell 100 comprising a PMOS transistor 101 and a capacitor 102 is shown on the left and right in FIG.

  The DRAM cell 100 is formed in the silicon substrate 1, and an isolation trench 40 that defines an active region is formed between the DRAM cells 100 in the silicon substrate 1. An isolation insulating film 4 that is STI (shallow trench isolation) is formed in the isolation trench 40. The isolation insulating film 4 is a high-density plasma oxide film, and an inner wall oxide film 5 that is a thin thermal oxide film is interposed at the boundary between the isolation insulating film 4 and the silicon substrate 1. Although the silicon substrate 1 is a P-type substrate and is not shown in the figure, an N well is formed in the formation region of the DRAM cell 100, and the area near the depth of the bottom of the isolation insulating film 4 in the N well. A channel cut layer is formed on the substrate.

  Each of the PMOS transistors 101 includes a gate oxide film 11, a polysilicon gate electrode 12 formed thereon, a sidewall 13 formed on a side surface of the gate electrode 12, and the gate electrode 12 on the surface portion of the silicon substrate 1. The source / drain regions 14 and 15 are formed in a self-aligned manner. Silicide layers 121, 141, 151 are formed on the gate electrode 12 and the source / drain regions 14, 15, respectively. The bit line BL is formed on the interlayer insulating film 6 covering the DRAM cell 100, and the bit line BL is connected to the source / drain region 14 through the contact 16 and the silicide layer 141. In this example, the silicide layer 151 is formed on the source / drain region 15, thereby reducing the resistance between the PMOS transistor 101 and the capacitor 102.

  Each of the capacitors 102 includes a P-type impurity diffusion layer 24 (hereinafter referred to as “lower diffusion layer 24”) functioning as a lower electrode (first electrode), an upper electrode 22 (second electrode), an upper electrode 22 and a lower diffusion. An insulating film 21 (hereinafter referred to as “dielectric layer 21”) that is a dielectric layer between the layers 24. As shown in FIG. 2A, the upper electrode 22 is shared by the capacitors 102 formed on both sides thereof. A silicide layer 221 is formed on the upper electrode 22.

  The P-type lower diffusion layer 24 included in the capacitor 102 is connected to the same P-type source / drain region 15 included in the PMOS transistor 101. That is, the lower diffusion layer 24 is electrically connected to the source / drain region 15 and corresponds to an electrode on the side connected to the source / drain terminal of the PMOS transistor 101 in the capacitor 102 of the circuit of FIG. .

  In the isolation insulating film 4, a recess 41 exposing the inner wall of the isolation trench 40 (that is, the side wall of the active region) is formed in the formation region of the capacitor 102 (formation region of the upper electrode 22). Therefore, in the cross section of FIG. 2A, the isolation insulating film 4 remains only at the bottom of the isolation trench 40. The lower diffusion layer 24 and the dielectric layer 21 extend from the upper surface of the active region to the inner wall of the isolation trench 40 (the inner wall of the recess 41), and a part of the upper electrode 22 is embedded in the recess 41. With this configuration, not only the upper surface of the active region but also the inner wall of the isolation trench 40 can contribute as an effective area of the capacitor 102, and the capacitance of the capacitor 102 increases.

  In the DRAM cell array, the DRAM cells 100 are also arranged in the extending direction of the word lines WL. The gate electrode 12 functions as a word line WL and extends in a direction perpendicular to the bit line BL. FIG. 3 shows a top view of a conventional DRAM cell 100. As shown in FIG. 3, the active region 7 in which the DRAM cell 100 is formed in the silicon substrate 1 is defined by the isolation insulating film 4 (that is, the isolation trench 40). FIG. 2A corresponds to the cross section along the line AA in FIG. 3, and shows a cross section along the active region 7 defined by the isolation trench 40 (isolation insulating film 4). I understand.

  FIG. 2B is a cross-sectional view taken along the line BB in FIG. 3 and shows a cross section along the isolation region between the DRAM cells 100 adjacent to each other in the extending direction of the word line WL (gate electrode 12). ing.

  As shown in FIG. 2B, in the isolation region between the DRAM cells 100 adjacent to each other in the extending direction of the gate electrode 12, the inner wall of the isolation trench 40 (FIG. 2B) Then, a recess 41 that exposes (not shown, indicated by reference numeral 71 in FIG. 3) is formed. The lower diffusion layer 24 and the dielectric layer 21 are also formed on the inner wall 71 thereof. Thereby, the inner wall 71 of the isolation trench 40 can also contribute to the effective area of the capacitor 102, further increasing the capacitance of the capacitor 102.

  As described above, the recess 41 needs to be completely covered by the portion of the upper electrode 22 outside the recess 41 and the side wall 23 on the side surface. Otherwise, the upper surface of the portion of the upper electrode 22 in the recess 41 is exposed in the isolation region between the DRAM cells 100, and a silicide layer integral with the silicide layer 151 above the source / drain region 15 is formed on the upper surface. This is because a short circuit between the source / drain region 15 and the upper electrode 22 is caused.

Therefore, as shown in FIG. 3, if the width of the recess 41 is defined as W _R , the width of the upper electrode 22 is defined as W _U , and the widths of the sidewalls 13 and 23 are defined as W _S ,
W _U / 2 + W _S −W _R / 2 ≧ 0 (1)
Need to be.

Here, the dimensional variation of the recess 41 is σ _R , the alignment accuracy of the mask pattern of the recess 41 is σ _AR , the dimensional variation of the upper electrode 22 is σ _U , the alignment accuracy of the mask pattern of the upper electrode 22 is σ _AU , and the side The dimensional variation of the width W _S of the wall 13 is represented by σ _S. In that case, in order to satisfy the above formula (1), design values (for example, dimensions on a photomask) W _R0 , W _U0 , W _S0 of the dimensions W _R , W _U , W _S are set as follows:
W _U0 / 2 + W _S0 −W _R0 / 2 ≧ √ (σ _R ² + σ _AR ² + σ _U ² + σ _AU ² + σ _S ² ) (2)
It is good to decide to satisfy the relationship.

However, if the thickness (width W _S ) of the side wall 23 is increased, it becomes difficult to form the silicide layer 151 between the PMOS transistor 101 and the capacitor 102. Therefore, the thickness of the side wall 23 may be appropriately thin. desirable. Therefore, in the manufacture of the conventional DRAM cell, the width W _U of the upper electrode 22 is formed to be somewhat larger than the width W _{R of the} recess 41 as shown in FIG. (Ie, W _R <W _U ).

  FIG. 4 is a top view of a conventional DRAM cell array. 2A and 2B correspond to the cross sections along the lines AA and BB in FIG. 4, respectively, and FIG. 3 corresponds to the region H in FIG. In FIG. 4, only the isolation insulating film 4, the active region 7, the recess 41, the gate electrode 12, and the upper electrode 22 are shown, and the side walls 13 and 23, the contacts 16, and the like are omitted. As shown in the figure, in the conventional DRAM cell array, the upper electrode 22 is formed to have a constant width wider than the recess 41.

  Next, a conventional DRAM cell manufacturing method will be described. 5-20 is a figure for demonstrating the said manufacturing method. 5, 8, 11, 12, 13, 14, 17, 18, 19, and 20, the diagrams (a) and (b) in FIG. It corresponds to the cross section shown in a) and (b).

  First, the upper surface of the silicon substrate 1 is thermally oxidized to form a pad oxide film 51, and a mask pattern of the active region 7 is formed thereon with a silicon nitride film using a photolithography technique. Then, an isolation trench 40 is formed in the silicon substrate 1 by etching using this as a mask. Thereby, an active region 7 is defined on the silicon substrate 1.

  Thereafter, the inner wall oxide film 5 is formed on the inner wall of the isolation trench 40 by thermal oxidation, and the inside of the isolation trench 40 is filled with a high-density plasma oxide film. Then, by removing the excessive high density plasma oxide film on the upper surface of the silicon substrate 1 by CMP, the isolation insulating film 4 is formed in the isolation trench 40. Thereafter, when the silicon nitride film which is the mask pattern of the active region 7 is removed, the structures shown in FIGS. 5A and 5B are obtained. FIG. 6 shows a pattern 201 of the active region 7 in the photomask, and FIG. 7 shows a top view of the silicon substrate 1 immediately after the formation of the isolation insulating film 4. FIGS. 5A and 5B correspond to cross sections taken along lines AA and BB in FIG. 7, respectively.

Next, using a photolithography technique, a resist mask 52 (first resist mask) in which an opening is formed in the pattern of the recess 41 is formed on the silicon substrate 1 (FIGS. 8A and 8B). At this time, a channel cut layer (not shown) is implanted for cell separation. FIG. 9 shows a pattern 202 of the resist mask 52 in the photomask, and FIG. 10 is a top view of the silicon substrate 1 when the resist mask 52 is formed. FIGS. 8A and 8B correspond to cross sections taken along lines AA and BB shown in FIG. 10, respectively. As shown in FIG. 10, in the conventional manufacturing method, the resist mask 52 is formed with a constant width. That is, the resist mask 52 is formed so that the width of the opening is the width W _{R of the} recess 41 both on the active region 7 and on the isolation insulating film 4.

  Then, the recess 41 is formed as shown in FIGS. 11A and 11B by removing the upper portions of the isolation insulating film 4 and the inner wall oxide film 5 by etching using the resist mask 52 as a mask.

  Subsequently, by using the resist mask 52 as a mask, P type ions (for example, boron ions) are implanted into the silicon substrate 1, so that the resist mask 52 is opened on the active region 7 as shown in FIGS. The lower diffusion layer 24 is formed on the inner wall of the recess 41 (inner wall of the isolation trench 40). Then, after removing the resist mask 52 and the pad oxide film 51, a pad oxide film 56 is formed again, and ion implantation for channel doping for adjusting the threshold value of the PMOS transistor 101 is performed (FIG. 13A). , (B)).

Thereafter, the pad oxide film 56 is removed, an oxide film 53 is formed on the entire surface of the silicon substrate 1, and a polysilicon film 54 as an electrode material is formed thereon. Then, a resist mask 55 having a pattern of the gate electrode 12 and the upper electrode 22 is formed on the polysilicon film 54 by photolithography as shown in FIGS. The corresponding one is referred to as “resist mask 55a”, and the one corresponding to the upper electrode 22 is referred to as “resist mask 55b”). FIG. 15 shows the patterns 203a and 203b of the resist masks 55a and 55b in the photomask. FIG. 16 is a top view of the silicon substrate 1 when the resist masks 55a and 55b are formed. FIGS. 14A and 14B correspond to cross sections taken along lines AA and BB in FIG. 16, respectively. As shown in FIG. 16, in the conventional method, the resist mask 55b for forming the upper electrode 22 is formed with a constant width. That is, the resist mask 55b is formed to have the width W _U of the upper electrode 22 on the active region 7 and on the isolation insulating film 4 as shown in FIGS. 14 (a) and 14 (b).

  Thereafter, the polysilicon film 54 is patterned by etching using the resist masks 55a and 55b as masks to form the gate electrode 12 and the upper electrode 22 (FIGS. 17A and 17B).

  By performing ion implantation, the source / drain regions 14 and 15 of the PMOS transistor 101 are formed in a self-aligned manner with respect to the gate electrode 12 and the upper electrode 22. In this example, the source / drain regions 14 and 15 are formed by two ion implantation steps. That is, a step (FIGS. 18A and 18B) of forming the low concentration regions 14a and 15a at a relatively shallow position of the silicon substrate 1, and then the side walls 13 and 23 are formed on the gate electrode 12 and the upper electrode 22, respectively. The source / drain regions 14 and 15 are formed by performing the steps (FIGS. 19A and 19B) of forming the high concentration regions 14b and 15b at relatively deep positions after the formation.

  Then, for example, a metal film such as cobalt is deposited and subjected to heat treatment, and the unreacted metal film is removed, whereby silicide layers 121, 141, 151, and 221 are formed in a self-aligned manner (FIG. 20A). , (B)). Thereby, the DRAM cell 100 including the PMOS transistor 101 and the capacitor 102 is formed.

  Then, an interlayer insulating film 6 of silicon oxide film is formed on the DRAM cell 100, contacts 16 and 35 are formed therein, and a bit line BL is formed on the interlayer insulating film 6, thereby forming the figure. The structure of the DRAM cell 100 shown in 2 (a) and (b) is completed.

Here, problems of the method for manufacturing the conventional DRAM cell 100 described above will be described. As described with reference to FIGS. 11 and 12, ion implantation (first ion implantation) for forming the lower diffusion layer 24 of the capacitor 102 is performed using a resist mask used as an etching mask when the recess 41 is formed. This is executed using 52 as a mask. On the other hand, as shown in FIGS. 18 and 19, in the ion implantation (second ion implantation) for forming the source / drain region 15 of the PMOS transistor 101, the upper electrode 22 serves as a mask. Conventionally, the width of the opening portion of the resist mask 52 (the width W _{R of the} recess 41) has been formed smaller than the width W _{U of} the upper electrode 22, so the edge portion of the upper electrode 22 (outside the width of the recess 41). Under the portion (the portion of the region E shown in FIG. 20A), no ions are implanted by the first ion implantation or the second ion implantation. Even if ions implanted into the silicon substrate 1 diffuse to some extent in the silicon substrate 1, the impurity concentration in the region E becomes lower than the other portions, and the portion becomes high resistance. As a result, the wiring resistance between the PMOS transistor 101 and the capacitor 102 is increased, leading to a decrease in the write / read margin of the DRAM cell 100.

  The structure and manufacturing method of the DRAM cell according to the first embodiment of the present invention will be described below. 21A and 21B are sectional views showing the structure of the DRAM cell 100 according to the present embodiment, and FIG. 22 is a top view thereof. FIGS. 21A and 21B correspond to cross sections taken along lines AA and BB in FIG. 22, respectively. FIGS. 21A, 21B, and 22 correspond to FIGS. 2A, 2B, and 3 shown above as the conventional structure, respectively. Also, in each figure shown below, elements having the same functions as those shown in FIGS. 2 to 21 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  As shown in FIG. 22, in the DRAM cell 100 according to the present embodiment, the upper electrode 22 of the capacitor 102 enters the side surface on the active region 7 and has a ridge-shaped recess 10. Therefore, the width of the upper electrode 22 in FIG. 21A, which is a cross section along the active region, is narrower than the width of the upper electrode 22 in FIG. 21B, which is a cross section along the isolation region.

  Next, a method for manufacturing DRAM cell 100 according to the present embodiment will be described. Also in the present embodiment, formation of the isolation insulating film 4 and the recess 41, ion implantation for forming the lower diffusion layer 24 of the capacitor 102 (first ion implantation), and channel doping for adjusting the threshold value of the PMOS transistor 101 are performed. Each step is performed in the same procedure as the conventional method described above with reference to FIGS. 5 to 13 (detailed description here is omitted).

  Then, an oxide film 53 and a polysilicon film 54 are formed on the surface of the silicon substrate 1, and resist masks 55a and 55b having a pattern of the gate electrode 12 and the upper electrode 22 are formed thereon by photolithography. In this embodiment, when forming the resist masks 55a and 55b, the pattern 203b of the resist mask 55b in the photomask is formed into a shape having dents on both sides as shown in FIG. Thereby, the resist mask 55b has a shape having a recess on the side surface on the active region 7 (FIG. 24). That is, the width of the resist mask 55b is not constant, and is narrower on the active region 7 than on the isolation region (FIGS. 25A and 25B).

Then, the polysilicon film 54 is patterned by etching using the resist masks 55a and 55b as masks to form the gate electrode 12 and the upper electrode 22 (FIGS. 26A and 26B). As a result, the upper electrode 22 has a shape having the recess 10 on the side surface on the active region 7 as shown in FIG. That is, the width of the upper electrode 22 is not constant, and the width on the active region 7 (the width W _U1 shown in FIGS. 22 and 26A) is the width on the isolation region (FIG. 22 and FIG. _26B ). The width W _U2 ) shown in FIG.

  Thereafter, ion implantation (second ion implantation) for forming the source / drain regions 14 and 15 of the PMOS transistor 101 is performed in the same manner as in the conventional method. That is, first, the low concentration regions 14a and 15a are formed in a relatively shallow position of the silicon substrate 1 (FIGS. 27A and 27B), and then the sidewalls 13 and 23 are formed, and then the silicon substrate 1 is relatively formed. High concentration regions 14b and 15b are formed at deep positions (FIGS. 28A and 28B).

  Finally, silicide layers 121, 141, 151, and 221 are formed in a self-aligned manner, the interlayer insulating film 6 and contacts 16, 35 are formed in the same manner as in the conventional method, and the bit line is formed on the interlayer insulating film 6. By forming the BL, the structure of the DRAM cell 100 according to the present embodiment shown in FIGS. 21 and 22 is completed.

〓Claim 1, Claim 3, Claim 5
In the present embodiment, ions are also implanted into the recess 10 provided in the upper electrode 22 during the second ion implantation for forming the source / drain region 15. Accordingly, ions are also implanted into the active region 7 inside the entire width (width W _U2 ) of the upper electrode 22 by the second ion implantation. Therefore, a high resistance in which ions are not implanted between the PMOS transistor 101 and the capacitor 102 in either the first ion implantation process for forming the lower diffusion layer 24 or the second ion implantation process for forming the source / drain regions 14 and 15. A small region (region E shown in FIG. 20A) becomes small. Accordingly, since the resistance between the PMOS transistor 101 and the capacitor 102 can be lowered, the write / read margin of the DRAM cell 100 can be increased, which can contribute to the speeding up of the operation. In particular, if the width W _U1 of the upper electrode 22 on the active region 7 is made smaller than the width W _{R of the} recess 41, the first ion implantation step or the second ion implantation step is performed between the PMOS transistor 101 and the capacitor 102. However, the high-resistance region where ions are not implanted can be almost eliminated, which is effective.

〓 Claim 2
Also in this embodiment, the recess 41 needs to be completely covered by the upper electrode 22 and the side wall 23 on the side surface thereof. Therefore, as shown in FIG. 22, if the width of the recess 10 of the upper electrode 22 is defined as W _C , the width of the active region 7 is defined as W _A , and the width of the sidewall 23 is defined as W _S.
W _A / 2 + W _S −W _C / 2 ≧ 0 (3)
Need to be.

  In addition, it is necessary to prevent the position of the recessed portion 10 of the upper electrode 22 including the sidewall 23 from deviating from above the active region 7. For example, let us consider a case where the recess 10 is detached from the active region 7 as shown in FIG. 30 is a cross-sectional view taken along the line CC of FIG. When the recess 10 is removed from the active region 7, the upper surface of the portion embedded in the recess 41 in the upper electrode 22 is exposed in the recess 10 as shown in FIG. A silicide layer integral with the upper silicide layer 151 is formed, and the source / drain region 15 and the upper electrode 22 are short-circuited.

Therefore, taking into account the dimensional variation σ _A of the active region 7, the dimensional variation σ _{U of} the upper electrode 22, the alignment accuracy σ _UA between the active region 7 and the upper electrode 22, and the dimensional variation σ _S of the width of the sidewall 13, Design values (for example, dimensions on a photomask) W _C0 , W _A0 , W _S0 of the dimensions W _C , W _A , W _S of
W _A0 / 2 + W _S0 −W _C0 / 2 ≧ √ (σ _A ² + σ _U ² + σ _UA ² + σ _S ² ) (4)
It is good to decide to satisfy the relationship.

<Embodiment 2>
A method for manufacturing a DRAM cell according to the second embodiment will be described. First, the active region 7 is defined on the silicon substrate 1 by forming the isolation trench 40 in the silicon substrate 1 as in the conventional method (FIG. 5).

Then, a resist mask 52 having an opening in the pattern of the recess 41 is formed on the silicon substrate 1 by using a photolithography technique. However, in this embodiment, the photomask pattern 202 having the concave portions on both sides as shown in FIG. 31 is used at this time so that the resist mask 52 has the concave portions 50 on the side surfaces on the active region 7. Therefore, the width of the resist mask 52 is not constant, and the width on the active region 7 is narrower than the width on the isolation region (FIG. 32). In other words, the opening of the resist mask 52, FIG. 33 (a), the (b), the more the width W _R2 in a cross section along the isolation region than the width W _R1 in a cross section taken along the active region 7 Also become wider.

Subsequently, a recess 41 is formed by etching using the resist mask 52 as a mask (FIGS. 34A and 34B). Next, by performing a step (first ion implantation) of implanting P-type ions (for example, boron ions) into the silicon substrate 1 using the resist mask 52 as a mask, a lower portion is formed on the inner wall of the recess 41 (the inner wall of the isolation trench 40). The diffusion layer 24 is formed (FIGS. 35A and 35B). At this time, ions are implanted into the active region 7 with the opening width (width W _R1 ) of the resist mask 52 in the cross section along the active region 7. That is, in the first ion implantation in the present embodiment, ions are implanted also into the active region 7 outside the width (width W _R2 ) of the recess 41, and the width of the lower diffusion layer 24 formed as a result is the recess 41. Wider than

  Then, after removing the resist mask 52 and the pad oxide film 51, a pad oxide film 56 is formed again, and channel doping for adjusting the threshold value of the PMOS transistor 101 is performed.

  Thereafter, in the same manner as in the conventional method, an oxide film 53 and a polysilicon film 54 are formed on the surface of the silicon substrate 1, and resist masks 55a and 55b having a pattern of the gate electrode 12 and the upper electrode 22 are formed thereon (FIG. 36 (a), (b)). Next, the polysilicon film 54 is patterned by etching using the resist masks 55a and 55b as masks to form the gate electrode 12 and the upper electrode 22 (FIGS. 37A and 37B).

  Then, ion implantation (second ion implantation) for forming the source / drain regions 14 and 15 of the PMOS transistor 101 is performed. That is, first, low concentration regions 14a and 15a are formed at relatively shallow positions in the silicon substrate 1 by ion implantation performed in a self-aligned manner with respect to the gate electrode 12 and the upper electrode 22 (FIGS. 38A and 38B). After that, the sidewalls 13 and 23 are formed on the gate electrode 12 and the upper electrode 22, and then the high concentration regions 14b and 15b are formed at relatively deep positions in the silicon substrate 1 (FIGS. 39A and 39B). .

  Finally, as in the conventional method, silicide layers 121, 141, 151, and 221 are formed in a self-aligned manner, the interlayer insulating film 6 and the contacts 16 and 35 are formed, and the bit line is formed on the interlayer insulating film 6. By forming the BL, the structure of the DRAM cell 100 according to the present embodiment is completed. The completed structure of DRAM cell 100 according to the present embodiment is the same as that shown in FIGS. 2A and 2B and FIG. 3 in appearance (however, as described above, the edge of upper electrode 22 is The region where ions are not implanted in both the first ion implantation step and the second ion implantation step is smaller below the portion).

〓Claim 4, Claim 7 and Claim 8
In the present embodiment, since the resist mask 52 that serves as a mask at the time of the first ion implantation for forming the lower diffusion layer 24 has the recessed portion 50 on the side surface on the active region 7, the first ion By the implantation, ions are also implanted into the active region 7 outside the width of the recess 41. Therefore, a high-resistance region (region E shown in FIG. 20A) where ions are not implanted in the first ion implantation step or the second ion implantation step between the PMOS transistor 101 and the capacitor 102 can be reduced. . Therefore, the resistance between the PMOS transistor 101 and the capacitor 102 can be lowered, the write / read margin of the DRAM cell 100 can be increased, and the operation can be speeded up. In particular, if the opening width W _R1 of the resist mask 52 in the cross section along the active region 7 is made smaller than the width W _U of the upper electrode 22 to be formed thereafter, the first ions are formed between the PMOS transistor 101 and the capacitor 102. The high resistance region where ions are not implanted can be eliminated in both the implantation step and the second ion implantation step, which is effective.

In the present embodiment, it is necessary to prevent the recess 50 of the resist mask 52 from coming off from the active region 7. That is, the relationship between the width W _A of the active region 7 and the width W _M of the recess 50 is
W _A −W _M ≧ 0 (5)
Need to be.

  In addition, it is necessary to prevent the position of the recess 50 of the resist mask 52 from deviating from the active region 7 due to misalignment. For example, consider a case where the dent 50 is removed from the active region 7 as shown in FIG. 41 and 42 are sectional views taken along lines DD and FF in FIG. 40, respectively. Since the resist mask 52 is also used as an etching mask for forming the recess 41, when the recess 50 is removed from the active region 7, the width of the recess 41 is widened at the stepped-off portion, and as shown in FIG. The recess 41 is wider than 22. Then, as shown in FIG. 42, the upper surface of the portion embedded in the recess 41 in the upper electrode 22 is exposed, and a silicide layer integral with the silicide layer 151 on the upper surface of the source / drain region 15 is formed in that portion. The source / drain region 15 and the upper electrode 22 are short-circuited.

Accordingly, the dimensional variation of the active region 7 sigma _A, the dimensional variation of the resist mask 52 sigma _M, the positioning accuracy of the active region 7 and the resist mask 52 in consideration of sigma _MA, dimension W _M, W _A respective design values (For example, dimensions on the photomask) W _M0 , W _A0 ,
W _A0 / 2-W _M0 / 2 ≧ √ (σ _A ² + σ _M ² + σ _MA ² ) (6)
It is good to decide to satisfy the relationship.

<Embodiment 3>
The first embodiment and the second embodiment described above can be combined with each other. In other words, the recess 50 may be provided in the resist mask 52 serving as the first ion implantation mask for forming the lower diffusion layer 24, and the recess 10 may be provided in the upper electrode 22 formed thereafter. By doing so, ions are also implanted into the active region 7 outside the width of the recess 41 by the first ion implantation, and ions are also implanted into the active region 7 inside the width of the upper electrode 22 by the second ion implantation. Will be injected. Therefore, in the active region 7 between the PMOS transistor 101 and the capacitor 102, a region where ions are not implanted by either the first ion implantation or the second ion implantation can be effectively reduced. Therefore, the effect of reducing the resistance between the PMOS transistor 101 and the capacitor 102 is further increased.

  The effect of the present invention is enhanced if the size of the recess 50 of the resist mask 52 and the recess 10 of the upper electrode 22 can be increased. However, as the semiconductor device is further miniaturized, the influence of dimensional variation and misalignment increases, so that it becomes difficult to sufficiently increase the size of the recess 50 of the resist mask 52 and the recess 10 of the upper electrode 22. Conceivable. When the first embodiment and the second embodiment are combined, a high effect can be expected even if the dimensions of the recess 50 of the resist mask 52 and the recess 10 of the upper electrode 22 are small, and high integration of the semiconductor device can be expected. Can contribute.

<Embodiment 4>
In the conventional method for manufacturing the DRAM cell 100 described above, channel doping for adjusting the threshold value of the PMOS transistor 101 is performed in the steps shown in FIGS. As can be seen from FIGS. 13A and 13B, in the conventional method, in channel doping, ions for channel doping are implanted not only in the formation region of the PMOS transistor 101 but also in the formation region of the capacitor 102. It was.

  Therefore, if the ions implanted by channel doping are ions (acceptors here) of the opposite conductivity type to the ions (donors here) implanted by the first ion implantation that forms the lower diffusion layer 24, The impurity concentration (donor concentration) of the lower diffusion layer 24 decreases. In particular, in the conventional method, the ion implantation is not performed below the edge portion of the upper electrode 22 (the region E shown in FIG. 20A) by the first ion implantation or the second ion implantation. There arises a problem that the impurity concentration is lowered and the resistance is further increased.

〓Claim 6, Claim 9, and Claim 10
Therefore, in this embodiment, when channel doping of the PMOS transistor 101 is acceptor implantation, the formation region of the capacitor 102 is covered with a resist mask 60 as shown in FIGS. 43 and 44A and 44B. To do. Accordingly, an acceptor for channel doping can be prevented from being introduced into the formation region of the capacitor 102, and the above problem due to channel doping can be avoided.

  The resist mask 60 serving as a channel dope mask is desirably completely formed over the formation region of the capacitor 102 because it is desirable to completely cover the formation region of the capacitor 102. However, if the resist mask 60 covers the source / drain region 15 between the PMOS transistor 101 and the capacitor 102, the channel doping of the PMOS transistor 101 cannot be performed normally. It is necessary not to cover the whole.

  Therefore, when the distance between the gate electrode 12 of the PMOS transistor 101 to be formed later and the upper electrode 22 of the capacitor 102 is sufficiently long, the end of the resist mask 60 may be set in the vicinity of the middle. However, the miniaturization of the DRAM cell 100 progresses, the dimensional variation between the gate electrode 12 and the upper electrode 22, the dimensional variation of the resist mask 60, the pattern of the gate electrode 12 and the upper electrode 22, and the pattern of the resist mask 60. When the misalignment cannot be ignored, the end of the resist mask 60 should be brought closer to the upper electrode 22 side.

More specifically, the design dimension between the gate electrode 12 and the upper electrode 22 is _L , the dimension variation between the gate electrode 12 and the upper electrode 22 is σ _L , the dimension variation of the resist mask 60 is σ _T , and When the alignment accuracy of the pattern of the gate electrode 12 and the upper electrode 22 and the pattern of the resist mask 60 is σ _TL ,
L / 2 <√ (σ _L ² + σ _T ² + σ _TL ² ) (7)
In this case, the end of the resist mask 60 should be closer to the upper electrode 22 side than the middle between the gate electrode 12 and the upper electrode 22.

  Note that this embodiment mode can be combined with Embodiment Mode 1 and Embodiment Mode 2. That is, also in the channel doping process of the PMOS transistor 101 in the first and second embodiments, the ions implanted by channel doping have the opposite conductivity to the ions implanted by the first ion implantation for forming the lower diffusion layer 24. In the case of a mold, the capacitor 102 may be formed after the formation region of the capacitor 102 is covered with the resist mask 60. Thereby, also in the first embodiment and the second embodiment, it is possible to avoid a high resistance between the PMOS transistor 101 and the capacitor 102 due to channel doping.

It is a circuit diagram of a general DRAM cell. It is sectional drawing of the conventional DRAM cell. It is a top view of a conventional DRAM cell. It is a top view of a conventional DRAM cell array. It is a figure for demonstrating the manufacturing method of the conventional DRAM cell. It is a figure for demonstrating the manufacturing method of the conventional DRAM cell. It is a figure for demonstrating the manufacturing method of the conventional DRAM cell. It is a figure for demonstrating the manufacturing method of the conventional DRAM cell. It is a figure for demonstrating the manufacturing method of the conventional DRAM cell. It is a figure for demonstrating the manufacturing method of the conventional DRAM cell. It is a figure for demonstrating the manufacturing method of the conventional DRAM cell. It is a figure for demonstrating the manufacturing method of the conventional DRAM cell. It is a figure for demonstrating the manufacturing method of the conventional DRAM cell. It is a figure for demonstrating the manufacturing method of the conventional DRAM cell. It is a figure for demonstrating the manufacturing method of the conventional DRAM cell. It is a figure for demonstrating the manufacturing method of the conventional DRAM cell. It is a figure for demonstrating the manufacturing method of the conventional DRAM cell. It is a figure for demonstrating the manufacturing method of the conventional DRAM cell. It is a figure for demonstrating the manufacturing method of the conventional DRAM cell. It is a figure for demonstrating the manufacturing method of the conventional DRAM cell. 1 is a diagram showing a configuration of a DRAM cell according to a first embodiment. 1 is a diagram showing a configuration of a DRAM cell according to a first embodiment. FIG. 6 is a diagram for explaining the method of manufacturing the DRAM cell according to the first embodiment. FIG. 6 is a diagram for explaining the method of manufacturing the DRAM cell according to the first embodiment. FIG. 6 is a diagram for explaining the method of manufacturing the DRAM cell according to the first embodiment. FIG. 6 is a diagram for explaining the method of manufacturing the DRAM cell according to the first embodiment. FIG. 6 is a diagram for explaining the method of manufacturing the DRAM cell according to the first embodiment. FIG. 6 is a diagram for explaining the method of manufacturing the DRAM cell according to the first embodiment. FIG. 10 is a diagram for explaining a problem when misalignment occurs in the manufacturing process of the DRAM cell according to the first embodiment. FIG. 10 is a diagram for explaining a problem when misalignment occurs in the manufacturing process of the DRAM cell according to the first embodiment. FIG. 10 is a diagram for explaining the method of manufacturing the DRAM cell according to the second embodiment. FIG. 10 is a diagram for explaining the method of manufacturing the DRAM cell according to the second embodiment. FIG. 10 is a diagram for explaining the method of manufacturing the DRAM cell according to the second embodiment. FIG. 10 is a diagram for explaining the method of manufacturing the DRAM cell according to the second embodiment. FIG. 10 is a diagram for explaining the method of manufacturing the DRAM cell according to the second embodiment. FIG. 10 is a diagram for explaining the method of manufacturing the DRAM cell according to the second embodiment. FIG. 10 is a diagram for explaining the method of manufacturing the DRAM cell according to the second embodiment. FIG. 10 is a diagram for explaining the method of manufacturing the DRAM cell according to the second embodiment. FIG. 10 is a diagram for explaining the method of manufacturing the DRAM cell according to the second embodiment. FIG. 10 is a diagram for explaining the method of manufacturing the DRAM cell according to the second embodiment. FIG. 10 is a diagram for explaining a problem when misalignment occurs in the manufacturing process of the DRAM cell according to the second embodiment. FIG. 10 is a diagram for explaining a problem when misalignment occurs in the manufacturing process of the DRAM cell according to the second embodiment. FIG. 10 is a diagram for explaining the method of manufacturing the DRAM cell according to the fourth embodiment. FIG. 10 is a diagram for explaining the method of manufacturing the DRAM cell according to the fourth embodiment.

Explanation of symbols

1 silicon substrate, 4 isolation insulating film, 5 oxide film, 6 interlayer insulating film, 7 active region, 11 gate oxide film, 12 gate electrode, 13, 23 sidewall, 14 source / drain region, 15 source / drain region, 16 Contact, 21 Dielectric layer, 22 Upper electrode, 24 Lower diffusion layer, 40 Isolation trench, 41 Recess, 52, 55, 60 Resist mask, 121, 141, 151, 221 Silicide layer, 100 DRAM cell, 101 PMOS transistor, 102 Capacitor.

Claims (10)

A trench formed in the upper portion of the semiconductor substrate;
An active region defined by the trench in the semiconductor substrate;
A first electrode which is an impurity diffusion layer formed so as to extend from the upper surface of the active region to the inner wall of the trench, a dielectric layer formed on the surface of the impurity diffusion layer, and formed on the dielectric layer And a capacitor comprising a second electrode partially embedded in the trench,
The semiconductor device according to claim 1, wherein the second electrode has a recess on a side surface on the active region. The semiconductor device according to claim 1,
A side wall formed on a side surface of the second electrode;
The semiconductor device according to claim 1, wherein the first portion embedded in the trench in the second electrode is completely covered by the second portion outside the trench and the sidewall. (A) a step of defining an active region in the semiconductor substrate by forming a trench above the semiconductor substrate;
(B) forming an isolation insulating film in the trench;
(C) forming a recess in the upper portion of the isolation insulating film by etching using the first resist mask in which the capacitor formation region is opened as a mask;
(D) forming an impurity diffusion layer serving as a first electrode of the capacitor on the active region and on the inner wall of the recess by first ion implantation using the first resist mask as a mask;
(E) after forming a dielectric layer on the impurity diffusion layer, forming an electrode material on the entire surface including the inside of the recess;
(F) patterning the electrode material by etching using a second resist mask covering the capacitor formation region as a mask to form the second electrode of the capacitor;
(G) implanting ions of the same conductivity type as the first ion implantation into the active region by second ion implantation performed in a self-aligned manner with respect to the second electrode,
The method of manufacturing a semiconductor device, wherein the second resist mask has a recessed portion on a side surface on the active region. A method of manufacturing a semiconductor device according to claim 3,
The method of manufacturing a semiconductor device, wherein the first resist mask has a recessed portion on a side surface on the active region. A method of manufacturing a semiconductor device according to claim 3 or 4,
The method of manufacturing a semiconductor device, wherein the second ion implantation is for forming a source / drain region of a MOS transistor formed in the active region. A method of manufacturing a semiconductor device according to claim 5,
(H) further comprising performing a third ion implantation for channel doping for threshold adjustment of the MOS transistor;
When the conductivity types of ions to be implanted are different between the first ion implantation and the third ion implantation, the step (h) is performed with a third resist mask covering at least the capacitor formation region as a mask. A method of manufacturing a semiconductor device. (A) a step of defining an active region in the semiconductor substrate by forming a trench above the semiconductor substrate;
(B) forming an isolation insulating film in the trench;
(C) forming a recess in the upper portion of the isolation insulating film by etching using the first resist mask in which the capacitor formation region is opened as a mask;
(D) forming an impurity diffusion layer serving as a first electrode of the capacitor on the active region and on the inner wall of the recess by first ion implantation using the first resist mask as a mask;
(E) after forming a dielectric layer on the impurity diffusion layer, forming an electrode material on the entire surface including the inside of the recess;
(F) patterning the electrode material by etching using a second resist mask covering the capacitor formation region as a mask to form the second electrode of the capacitor;
(G) implanting ions of the same conductivity type as the first ion implantation into the active region by second ion implantation performed in a self-aligned manner with respect to the second electrode,
The method of manufacturing a semiconductor device, wherein the first resist mask has a recessed portion on a side surface on the active region. A method for manufacturing a semiconductor device according to claim 7, comprising:
The method of manufacturing a semiconductor device, wherein the second ion implantation is for forming a source / drain region of a MOS transistor formed in the active region. A method for manufacturing a semiconductor device according to claim 8, comprising:
(H) further comprising performing a third ion implantation for channel doping for threshold adjustment of the MOS transistor;
When the conductivity types of ions to be implanted are different between the first ion implantation and the third ion implantation, the step (h) is performed with a third resist mask covering at least the capacitor formation region as a mask. A method of manufacturing a semiconductor device. (A) an ion implantation step for forming an impurity diffusion layer serving as an electrode of a capacitor in the active region of the semiconductor substrate;
(B) an ion implantation step for channel doping for adjusting a threshold value of the MOS transistor formed in the active region,
When the conductivity types of ions to be implanted are different between the steps (a) and (b), the step (b) is performed with a resist mask covering at least the capacitor formation region as a mask. A method for manufacturing a semiconductor device.

Images