JP2000195969A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a portion of an active region edge in contact with a trench isolation to be identically formed by providing a second field effect element, having a second gate oxide film which a thickness different from a first gate oxide film, formed in a second active region with the same edge shape as a first active region surrounded by a trench on the principal surface of a substrate. SOLUTION: A gate electrode 9 consists of a polysilicon layer 6 and a metal silicide layer 7, such as tungsten silicide, and a trench isolation is formed by a trench 2 and silicon oxide film 3 and 4. A capacitor 22 is formed with a storage node 18 of a polycrystalline silicon containing phosphorus, a capacitor insulating film 19 of a silicon nitride oxide film, and a cell plate 20 of a polycrystalline silicon containing phosphorus. Every active region is isolated by a trench formed with the trench 2 and the silicon oxide films 3 and 4. Since the silicon oxide film 4 is not caved in along the edge of the trench 2, even if a plurality of gate oxide films with different film thickness are formed on one chip, characteristics of a transistor will not be affected by the shape of the active region in contact with the trench isolation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an isolation structure of a semiconductor device.

[0002]

2. Description of the Related Art Advances in integrated circuit design and process technology have made it possible to manufacture integrated circuits in which high-density storage elements and high-density arithmetic circuits are mounted on the same chip. , High functionality. Among such structures, in particular, MPU (Micro Processing U)
nit) and other advanced integrated logic circuits (hereinafter referred to as logic circuits) and DRAM (Dynamic Random Access Memo)
ry) formed in the same chip is called a logic embedded DRAM (Dynamic Random Access Memory), and a plurality of MOs having different purposes in one chip.
Since it is necessary to fabricate an S-type element, the thickness of the gate oxide film is changed in accordance with each purpose so as to obtain desired transistor characteristics. As the isolation between the elements of such a semiconductor device, a trench isolation that requires a very small area and a small parasitic capacitance as compared with other isolations is effective for high integration and high speed. This trench isolation is performed by forming a groove on the surface of a semiconductor substrate to be an isolation region, and then performing CVD (Chemical Vapor).
A silicon oxide film is buried in the groove by the Deposition method, and the surface is etched to leave an oxide film only in the groove. The active region is formed by bird's beak compared to the case where the separation film is formed by thermal oxidation. This is a method suitable for miniaturization because the shape of the trench isolation can be easily controlled since the decrease in the size can be suppressed.

FIG. 20 is a sectional view showing an element of a conventional semiconductor device, in which a DRAM memory cell and a logic circuit are formed on one semiconductor substrate. In the figure, 101 is a semiconductor substrate, 102 is a groove, 103 and 1
04 is a silicon oxide film, 1051 and 1052 are gate oxide films, 106 is a polysilicon layer, 1061 and 1
062 is an interlayer insulating film, 107 is a metal silicide layer, 10
8 is a side wall, 109 is a gate electrode, 1010 to 1013 are source / drain regions, 1018 is a storage node, 1019 is a capacitor insulating film, 1020
Is a cell plate, 1022 is a capacitor, and the capacitor 1022 is formed of a storage node 1018, a capacitor insulating film 1019, and a cell plate 1020. Further, trench isolation is formed by the trench 102 and the silicon oxide films 103 and 104, and each trench is separated into active regions. And
Gate electrode 109 is formed of polysilicon layer 106, metal silicide layer 107, and the like.

A source / drain region 1011 and a gate electrode 109 of a DRAM memory cell overlap in a horizontal direction at a portion X in the drawing with a gate oxide film 1051 interposed therebetween.
As the miniaturization progresses, the ratio of the width of the overlapping portion to one memory cell increases. For example, in the case of an nMOS, when a voltage higher than the gate electrode 109 is applied to the source / drain region 1011, the source / drain When a high electric field is generated on the surface of the region 1011, the BTBT (Band t
o Band Tunneling) causes leakage current of capacitor 1
022 and the semiconductor substrate 101 in some cases. The fact that no leakage current flows is the most important characteristic for a DRAM memory cell. If a leakage current occurs, the refresh characteristic deteriorates and power consumption and reliability become problematic. ~
About 10 nm (the gate length L ₁ of the DRAM memory cell =
(At about 0.2 μm) to reduce the influence of the gate electrode 109 and the source / drain region 1011 on each other. In addition, in a portion other than the memory cell such as a peripheral portion of the logic portion or the DRAM portion, a high-speed transistor having a high driving capability is required, and it is the most important characteristic that a sufficient ON current flows. Therefore, the gate oxide film 1052 of the transistor in the logic circuit portion is three times larger than the gate oxide film 1051 of the transistor in the DRAM memory cell.
By forming the memory cell as thin as about nm (when the gate length L _{2 is} about 0.2 μm), the memory cell has a structure in which the leakage current is suppressed and the driving capability is increased in portions other than the memory cell.

[0005]

However, when gate oxide films having different film thicknesses are formed on one semiconductor substrate as described above, the gate oxide films are buried in grooves formed in the semiconductor substrate for trench isolation. Where the silicon oxide film adjacent to the active region other than the memory cell
There is a problem that it falls along the edge of the groove.
FIG. 21 is a cross-sectional view showing elements of a conventional semiconductor device.
FIG. 21 is an enlarged view of a Y part shown in FIG. 20. As shown in this figure, the silicon oxide film 1 embedded in the trench 2
04 is formed gently in the memory cell,
In the logic circuit portion, a drop occurs along the boundary between each active region and the groove 102.

FIG. 22 to FIG. 27 are cross-sectional views showing one process of a conventional method of manufacturing a semiconductor device.
1031 is a silicon oxide film and 1021 is a silicon nitride film. First, a silicon oxide film 1031 and a silicon nitride film 1021 are formed on the surface of the semiconductor substrate 101,
After patterning the silicon nitride film 1021 using a photoresist mask (not shown) so as to open the region where the groove 102 is to be formed, the groove 102 is formed using the patterned silicon nitride film 1021 as a mask. FIG.
Is a cross-sectional view of the semiconductor device at the stage when this step has been completed. In FIG. 23, 103 and 104 are silicon oxide films. Referring to FIG. 23, grooves 10 are formed by thermal oxidation.
After a silicon oxide film 103 is formed in 2, a silicon oxide film 104 is embedded in the groove 102 by a CVD method.
FIG. 23 is a cross-sectional view of the semiconductor device at the stage when this step has been completed. Next, the surface of the silicon oxide film 104 is subjected to CMP.
(Chemical Mechanical Polising), the silicon nitride film 1021 and the silicon oxide film 10
31 is removed to complete the trench isolation. FIG. 24 is a cross-sectional view of the semiconductor device after this step has been completed.

In FIG. 25, reference numeral 1053 denotes a gate oxide film, and reference numeral 1042 denotes a resist pattern. Referring to the figure, a gate oxide film 1053 is formed on the entire surface by thermal oxidation.
After the formation of about nm, a resist pattern 1042 covering the active region of the DRAM memory cell is formed, and the gate oxide film 1053 on the surface of the active region of the logic circuit is removed using the resist pattern 1042 as a mask. FIG. 25 is a cross-sectional view of the semiconductor device at the stage when this step has been completed. As can be seen from this figure, since the gate oxide film 1053 is removed only in the logic circuit portion while leaving the gate insulating film 1053 of the memory cell, the boundary portion between the gate oxide film 1053 and the groove 102 in the logic circuit portion has an edge. The shape of the silicon oxide film 104 drops along the line. Then, after removing the resist pattern 1042, a gate oxide film 1052 of about 4 to 7 nm is formed on the entire surface again by thermal oxidation, and then the gate electrode 109 is formed. FIG. 26 is a cross-sectional view showing the elements of the semiconductor device at the stage when this step has been completed.

After that, the side wall 108 and the source
The drain regions 1010 and 1011 or the source
Drain regions 1012 and 1013, interlayer insulating film 10
61, a contact hole 1016, a wiring 1017, an interlayer insulating film 1062, a contact hole 23, a storage node 1018, a capacitor insulating film 1019, and a cell plate 1020 are formed to form the semiconductor device shown in FIG. FIG. 27 is a sectional view taken along the line ZZ in FIG. Although the depression shown in FIG. 27 occurs entirely along the boundary between the trench 102 and the gate oxide film 1052 of the logic circuit portion, the silicon oxide film 104
When the voltage drops, the concentration of the electric field occurs at the end of the active region below the gate electrode, and the reverse narrow channel effect occurs, which causes a problem that the threshold voltage decreases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. Even if a structure including transistors having different gate oxide thicknesses, such as a DRAM memory cell and a logic circuit, is formed on one semiconductor substrate, The silicon oxide film in the portion along the edge of the groove does not fall, and the shape of the end of the active region in the portion in contact with the trench isolation can be formed almost identical, and the transistor characteristics are not affected by the shape of the active region. It is an object of the present invention to obtain a semiconductor device having a trench isolation that can reduce the size of a chip while maintaining the characteristics of each element in a good condition, and a method of manufacturing the same. As a result of a prior art search for the present invention, Japanese Patent Application Laid-Open No. 3-99430 describes a method of manufacturing a semiconductor device having a CMOS structure in which ion channeling is performed by ion implantation using a silicon oxide film and a silicon nitride film as masks. CMO that performs well implantation and ion implantation to gate electrode using one mask
Japanese Unexamined Patent Application Publication No. 9-90, which describes a method of manufacturing an S-structure semiconductor device.
No. 74072, all of which have a uniform gate oxide film thickness.

[0010]

A semiconductor device according to the present invention has a groove formed on a main surface of a semiconductor substrate, a silicon oxide film buried in the groove, and a semiconductor substrate surrounded by the groove. A first field effect element having a first active region provided on a first portion of the surface, a first gate oxide film formed on a main surface of the first active region, A second active region disposed in the second portion of the main surface and surrounded by the groove and having the same end shape as the first active region; and a second active region formed on the main surface of the second active region. , First
A second field-effect element having a second gate oxide film having a thickness different from that of the second gate oxide film.
Despite the fact that gate oxide films of different thicknesses are formed on the surface of a plurality of active regions in one chip, the silicon oxide film along the edge of the groove does not fall down and contacts the trench isolation Since the shape of the active region end portion is substantially the same, the transistor characteristics are not affected by the shape of the active region.

Further, the width of the groove surrounding the first active region and the second active region is the same, and the height from the groove bottom to the surface of the silicon oxide film is the same. Since a margin for the depth of focus can be secured in the photolithography process when patterning the gate electrode passing over the surface, when the gate electrode material deposited on the surface of the second silicon oxide film is etched, the gate electrode material is left behind. No short circuit occurs. On the other hand, in order to prevent the gate electrode material from being left behind, there is no possibility that the etching is performed too much and the gate oxide film, which is an etching stopper, penetrates and is cut down to the surface of the semiconductor substrate.

An interlayer insulating film formed on a surface of the first field-effect element and having an opening reaching the first field-effect field element; and a capacitor connected to the first field-effect element through the opening. Wherein the first gate oxide film is thicker than the second gate oxide film,
DRAM with good refresh characteristics by suppressing leakage current due to thick gate oxide film, and logic circuit with high drive capability due to thin gate oxide film and suppressed threshold reduction by suppressing reverse narrow channel effect In one chip.

A step of forming a groove surrounding the first and second active regions provided on the main surface of the semiconductor substrate; a step of forming a first silicon oxide film filling the groove; Forming a second silicon oxide film covering the second active region; forming a first mask having an opening on the first active region main surface on the second silicon oxide film surface; Etching a second silicon oxide film on the first active region main surface, forming a first gate oxide film on the first active region main surface, and removing the first mask Forming a second mask having an opening on the main surface of the second active region, and etching the second silicon oxide film on the main surface of the second active region;
Removing the mask, forming a second gate oxide film on the first and second active region main surfaces,
Forming a first and a second field effect element on a main surface of a second active region, and forming silicon oxide films having different thicknesses on surfaces of a plurality of active regions in one chip. Is formed, the silicon oxide film in the trench does not fall along the edge of the trench, so that the shape of the portion where the active region is in contact with the trench isolation can be formed almost identically. Transistor characteristics are not affected.

Further, the first mask is a polysilicon film, and the polysilicon film has a selectivity of 50% when dry etching a silicon oxide film.
Since the above can be secured, the silicon oxide film can be etched with better controllability.

A step of forming an interlayer insulating film; a step of forming an opening in the interlayer insulating film that reaches the first field effect element; and a step of forming a capacitor that reaches the first field effect element through the opening. The method further comprises a step of forming a thick gate oxide film of the DRAM memory cell to suppress a leak current, and reducing a gate oxide film in other portions to increase a driving capability. However, since the shape of the active region can be made uniform without dropping along the edge of the groove, the reverse narrow channel effect can be suppressed, and a decrease in the threshold can be suppressed.

After the first mask is formed, a channel of the first field effect element is implanted into the first active region before etching the second silicon oxide film on the main surface of the first active region. Performing a second mask after forming a second mask.
Performing a channel implantation of a second field effect element in the second active region before etching the second silicon oxide film on the main surface of the active region. The channel implantation of the device is performed via the second silicon oxide film, and the second silicon oxide film is removed and the gate oxide film is newly formed, so that the surface of the semiconductor substrate is protected at the time of channel implantation. It is possible,
A gate oxide film having good film quality can be obtained.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 1 and 2 are cross-sectional views of a semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line AA shown in FIG. In FIG. 1, 1 is a semiconductor substrate, 2 is a trench, 3 and 4 are silicon oxide films, 51 and 52 are gate oxide films,
6 is a polysilicon layer, 7 is a metal silicide layer, 8 is a side wall, 9 is a gate electrode, 10 to 15 are source / drain regions, 61 and 62 are interlayer insulating films, 16 and 23 are contact holes, 17 is a wiring, 18 is a storage node, 19 is a capacitor insulating film, 20 is a cell plate, and 22 is a capacitor. The gate electrode 9 is composed of a polysilicon layer 6 and a metal silicide layer 7 such as tungsten silicide.
A trench isolation is formed from silicon oxide film 4. Further, the capacitor 22 contains phosphorus at 1 to 5 × 10 ²⁰ /
a storage node 18 made of polycrystalline silicon containing about ³ cm ^3, a capacitor insulating film 19 made of a silicon oxynitride film having a thickness of about 5 to 10 nm, and 1
It is formed from a cell plate 20 made of polycrystalline silicon containing about 5 × 10 ²⁰ / cm ³ . The trench 2 and the silicon oxide films 3 and 4 form a trench isolation, which is separated for each active region by the trench isolation. Wiring 17 is connected to source / drain region 12 via contact hole 16, and capacitor 22 is connected to source / drain region 11 via contact hole 23. Also, besides this,
Wirings respectively connected to the drain regions 10 and 13 and the gate electrode 9 are formed via contact holes formed in the interlayer insulating film (not shown).

Referring to FIG. 1, for example, a gate length L of a transistor in a logic circuit portion as a first field effect element
_{When 2} = about 200 nm, the width of the groove 2 of the logic circuit portion is about 200 nm to 500 nm, and the depth of the groove 2 is 15 nm.
It is about 0 to 500 nm. However, the width of the groove 2 varies depending on the location and may be about 5000 nm,
In such a case, the width of the groove 2 is adjusted by leaving the semiconductor substrate 1 (dummy pattern) even in a portion where no element is formed, so that the unevenness of the surface of the silicon oxide film 4 after filling is reduced.

A silicon oxide film 3 of about 5 to 30 nm is formed so as to cover the surface of the semiconductor substrate inside the trench 2, and the inside of the trench 2 is filled with a silicon oxide film 4. 4 on the surface of the semiconductor substrate 1 in the active region of the logic circuit.
A gate oxide film 52 having a thickness of about 7 to 7 nm is formed, and a polysilicon layer 6 of about 50 to 150 nm is formed thereon.
A gate electrode 9 made of a metal silicide layer 7 having a thickness of about 0 to 150 nm is formed. Groove 2 in semiconductor substrate 1
If the influence of the defect formed in the semiconductor substrate 1 on the device characteristics is sufficiently small due to the step of forming the silicon oxide film 3, the silicon oxide film 3 may be omitted. The polysilicon layer 6 is made of phosphorus or arsenic (nM) of about 1 × 10 ²¹ / cm ^3.
OS) or an impurity such as boron or boron fluoride (pMOS). The source / drain regions 12 and 13 contain about 1 × 10 ¹⁸ / cm ³ of impurities such as phosphorus or arsenic, or boron or boron fluoride, and further contain 1 × 10 ²⁰ / cm ³ if necessary. It has an LDD (Lightly Doped Drain) structure having a region including a degree (not shown).

Then, for example, the gate length L ₁ of the transistor of the DRAM memory cell as the second field effect element =
At about 200 nm, the width of the groove 2 differs depending on the location,
The minimum separation width is about 100 nm to 200 nm, the other part is about 200 nm to 400 nm, and the depth of the groove 2 is about 150 to 500 nm. Also, the gate oxide film 5
1 has a thickness of about 7 to 10 nm, and the other portions have the same structure as the logic circuit portion. DR
In an AM memory cell, information is accumulated by electric charges accumulated in a capacitor, and refresh (read / write) is performed at regular intervals. When a leak current flows, extra information accumulated in the capacitor is lost. In addition, since the refresh characteristics are deteriorated, it becomes more important to suppress the leak current as compared with the transistors in other parts.

When writing data to the capacitor 22, the voltage applied to each electrode of the memory cell is V _G = 2.0
V, V _B = −1.0 V, and 0 V is applied to a bit line (not shown) connected to the source / drain region 12 to erase data, V _G = 2.0 V, V _B = −1 .0
V, a voltage of about 2.0 V is applied to a bit line (not shown) connected to the source / drain region 10. Also,
When reading data, the voltage applied to the bit line is about 1.0V. In the logic circuit, a channel is formed on the surface of the semiconductor substrate 1 below the gate electrode 9 by applying a voltage to the gate electrode 9, the source / drain regions 10, 11 and the semiconductor substrate 1 (well).
One of the source / drain regions 10 and 11 serves as a source and the other serves as a drain, and operates as a circuit. For example, nMO
In the case of the S transistor, the voltage applied to each electrode of the logic circuit is V _G = 2.5 V, V _D = 2.5 V, V _S = 0
V and V _B = 0. Further, in this embodiment, the semiconductor device in which two transistors are formed in one active region other than the DRAM memory cell portion is described, but the present invention is not limited to this.

According to this semiconductor device, although a plurality of gate oxide films having different thicknesses are formed in one chip, a portion of the silicon oxide film 4 along the edge of the groove 2 drops. In addition, since the shape of the end of the active region at the portion in contact with the trench isolation can be formed substantially the same, there is an effect that the transistor characteristics are not affected by the shape of the active region. As a result, since the gate oxide film is thick, the leakage current is suppressed, the refresh characteristics are good, the power consumption is reduced, and the DR
A high-speed and highly reliable logic circuit can be fabricated on a single chip with a high drive capability due to the thin gate oxide film and AM, which can suppress the reverse narrow channel effect and suppress the lowering of the threshold voltage. The size of the chip can be reduced while maintaining good characteristics of the semiconductor device. Further, in a portion where the width of the trench 2 surrounding each active region is equal, a portion adjacent to the active region where the thick gate oxide film 51 is formed, and a thin gate oxide film 52 are formed. There is no variation in the height of the surface of the silicon oxide film 4 in the portion adjacent to the active region. As a result, a margin with respect to the depth of focus can be ensured in the photolithography process at the time of gate electrode patterning.
When the gate electrode material deposited on the surface is etched, no short circuit occurs due to the remaining gate electrode material. Conversely, in order to prevent the gate electrode material from being left behind, there is no possibility that excessive etching is performed to penetrate the gate oxide film, which is an etching stopper, and scrape down to the semiconductor substrate surface. There is no fear of flowing, and the reliability of the semiconductor device is improved.

FIGS. 3 to 14 show a first embodiment of the present invention.
FIG. 4 is a cross-sectional view showing one step of the method for manufacturing a semiconductor device, showing a portion where a gate oxide film is formed thick (hereinafter referred to as a thick film portion) and a portion where a gate oxide film is formed thin (hereinafter referred to as a thin film portion). In this example, a memory cell and a sense amplifier of a DRAM are formed in a thick film portion, and a logic circuit is formed in a thin film portion. In FIG.
Is a silicon nitride film, and 31 is a silicon oxide film. First, a silicon oxide film 3 is formed on a semiconductor substrate 1 by thermal oxidation.
1 is formed to a thickness of about 5 to 30 nm, and then the silicon nitride film 21 is formed.
Is formed on the order of 100 to 300 nm. FIG. 3 is a cross-sectional view of the semiconductor device at the stage when this step has been completed. next,
Anisotropic etching is performed using a photolithographic pattern (not shown) such as a photoresist formed in a portion other than the formation region of the groove 2 as a mask to pattern the silicon nitride film 21 and then remove the photolithographic pattern. FIG. 4 is a cross-sectional view of the semiconductor device at the stage when this step has been completed.

Then, using the remaining silicon nitride film 21 as a mask, the silicon oxide film 31 and the semiconductor substrate 1 are anisotropically etched, and
500 nm, width 100-500 nm in logic circuit
Grooves 2 are formed. At this time, the width of the groove 2 in the DRAM memory cell is 100 nm to 200 n in the minimum separation width portion.
m, and the other portion is about 200 to 400 nm. FIG. 5 is a cross-sectional view showing the elements of the semiconductor device at the stage when this step has been completed. Next, a silicon oxide film 4 having a thickness of about 300 nm to 1000 nm is formed on the entire surface by a low pressure CVD method, and then the silicon oxide film 4 on the surface of the silicon nitride film 21 is formed by a CMP method using the silicon nitride film 21 as a stopper. The silicon oxide film 4 is removed only inside the opening formed by the trench 2 and the silicon nitride film 21. Thereafter, the silicon nitride film 21 is removed by wet etching with hot phosphoric acid, and then the silicon oxide film 31 is removed.
FIG. 6 is a cross-sectional view at the stage when this step is completed.

In FIG. 7, reference numeral 32 denotes a silicon oxide film. Referring to the figure, a silicon oxide film 32 of about 3 to 15 nm is formed on the surface of semiconductor substrate 1 by thermal oxidation.
FIG. 7 is a cross-sectional view showing the elements of the semiconductor device at the stage when this step has been completed. And in the case of nMOS, nMOS
Forming a mask for opening the portion of the pMOS, and ion-implanting boron or boron fluoride, and in the case of a pMOS, forming a mask for opening the portion of the pMOS and ion-implanting impurities such as phosphorus and arsenic into the DRAM memory. A well (not shown) excluding the channel injection layer is formed in the cell and other portions. The ion implantation for forming the well may be performed simultaneously with the formation of the channel implantation layer, if necessary. In FIG. 8, reference numeral 211 denotes a silicon nitride film;
Is a resist pattern. Referring to the figure, after forming a silicon nitride film 211 on the silicon oxide film 32 to a thickness of about 5 to 30 nm, a resist pattern 41 for opening the active region of the memory cell in the thick film portion is formed. To remove the silicon nitride film 211 on the surface of the semiconductor substrate 1 of the memory cell. Thereafter, boron or boron fluoride is ion-implanted to form a channel implantation layer (not shown) of the memory cell. FIG. 8 is a cross-sectional view showing the semiconductor device at the stage when this step has been completed.

In FIG. 9, reference numeral 42 denotes a resist pattern. Referring to the figure, the resist pattern 41 is removed, and a resist pattern 42 for opening an active region of a sense amplifier using a transistor having a threshold different from that of a memory cell in the thick film portion is formed. Silicon nitride film 21 formed on the surface of semiconductor substrate 1
Remove one. After that, ions such as boron are implanted to form a channel implantation layer (not shown) in the active region of the sense amplifier. FIG. 9 is a cross-sectional view of the semiconductor device at the stage when this step has been completed. If there is a transistor having a different threshold value in the thick film portion, formation of a resist pattern and ion implantation may be repeated in the same manner. In FIG. 10, reference numeral 53 denotes a silicon oxide film. Next, after removing the resist pattern 42, the silicon oxide film 32 of the thick film portion is removed by hydrofluoric acid using the silicon nitride film 211 as a mask, and thermal oxidation is performed again.
A gate oxide film 53 is formed. FIG. 10 is a cross-sectional view of the semiconductor device at the stage when this step is completed.
The gate oxide film 53 is formed on the memory cell and the sense amplifier on the surface, and the silicon oxide film 32 and the silicon nitride film 211 are formed on the logic circuit portion.

In FIG. 11, reference numeral 43 denotes a resist pattern. Referring to the figure, after the silicon nitride film 211 is removed by hot phosphoric acid, a mask is formed with a resist pattern 43 that covers the pMOS active regions in the thick film portion and the thin film portion and opens the nMOS active region in the thin film portion. Then, an impurity such as boron or boron fluoride is ion-implanted to form an nMOS channel implantation layer (not shown) of the logic circuit. In the case of the pMOS, as in the case of the nMOS, channel implantation is performed by covering the active regions of the nMOS in the thick film portion and the thin film portion and ion-implanting phosphorus or arsenic with a mask for opening the active region of the pMOS in the thin film portion. Form a layer (not shown). Then, the silicon oxide film 32
Is removed. FIG. 11 is a cross-sectional view showing the semiconductor device at the stage when this step has been completed. Here, the case where the threshold value of each of the nMOS and the pMOS of the logic circuit portion is one type is described.
If any of the OSs has a different threshold, it is necessary to repeat the channel injection by dividing the masking method according to the conductivity type and the threshold of the channel injection layer. And
After removing the resist pattern 43, a silicon oxide film 5 having a thickness of about 4 to 7 nm is entirely formed by thermal oxidation.
Form 2 FIG. 12 is a cross-sectional view of the semiconductor device at the stage when this step has been completed. At this stage, channel injection layers are formed in the transistors in all the regions of the DRAM memory cell, the sense amplifier, and the logic circuit.
In the first embodiment, the sense amplifier is formed in the thick film portion, but may be formed in the thin film portion. Ion implantation for forming a channel implantation layer is performed simultaneously on portions where the gate oxide film thickness, the conductivity type of the channel implantation layer, and the impurity concentration of the channel implantation layer are the same. Next, nMOS contains impurities such as phosphorus and arsenic, and pMOS contains boron and boron fluoride in an amount of about 1 × 10 ²¹ / cm ^3.
A gate electrode 9 is formed by depositing a polysilicon layer 6 having a thickness of about 0 nm by a CVD method, forming a metal silicide layer 7 such as tungsten silicide by a CVD method or a sputtering method, and then patterning.

For nMOS, phosphorus, arsenic, pM
For OS, boron or boron fluoride is 3 × 10 ¹³ / c
m ² , ion implantation at about ²⁰ to 40 keV
Drain regions 10 to 15 are formed, and a silicon oxide film is deposited to a thickness of about 50 to 100 nm by a low pressure CVD method and etched back to form a sidewall 8. FIG. 13 is a cross-sectional view showing the semiconductor device at the stage when this step has been completed. When the source / drain regions 12 to 15 have an LDD structure, the region where the memory cell is to be formed is covered with a mask, and arsenic (nMOS), boron or boron fluoride (pMOS) is further added to the substrate. ^{15 ~5} × 10
^A source / drain region is formed together with an impurity region having an impurity concentration of about 1 × 10 ²⁰ / cm ³ formed by implanting about ¹⁵ / cm ² (not shown). Thereafter, an interlayer insulating film 61 having a thickness of about 200 nm to 600 nm is deposited by a low pressure CVD method, and a contact hole 16 reaching the source / drain region 12 is formed to a thickness of 0.1 μm to
Open with a diameter of μm. Then, add phosphorus to 1 × 10 ^{20 to} 5 × 1
Polycrystalline silicon containing about 0 ²⁰ / cm ³ by CVD
After depositing a thickness of about 150 nm, tungsten silicide (WSi) is deposited to a thickness of 50 to 150 nm by a CVD method and then patterned to form a wiring 17. FIG. 14 is a cross-sectional view showing the semiconductor device at the stage when this step has been completed.

Further, after forming an interlayer insulating film (not shown), a contact hole (not shown) is formed.
By burying a wiring material in the contact hole, a wiring (bit line) connected to the source / drain region 10 and a wiring connected to the source / drain regions 13 to 15 are formed (not shown). Any of the wirings connected to the source / drain regions 10 and 12 to 15 may be formed first according to the convenience of the circuit configuration. Then, after forming an interlayer insulating film 62 and forming a contact hole 23, an impurity such as phosphorus is
^The storage node 18 is formed by depositing polycrystalline silicon containing about ^{20 to} 5 × 10 ²⁰ / cm ^{3 on the} entire surface of about 600 to 1000 nm, patterning and disposing it only in a predetermined region. Then, a silicon nitride oxide film serving as the capacitor insulating film 19 is deposited to a thickness of about 5 to 10 nm by the CVD method, and further an impurity such as phosphorus serving as the cell plate 20 is added at 1 × 10 ^{20 to} 5 × 10 ²⁰ / cm ^3. The capacitor 22 is formed by depositing polycrystalline silicon containing about 50 to 100 nm and patterning it.
As described above, the semiconductor device shown in FIG. 1 is formed.

The source / drain regions 10 to 1
5 is formed, the impurity regions having the same conductivity type as the source / drain regions exposed in the contact holes are formed in the SAC (Self).
Aligned Contact) may be formed by injection. In such an impurity region, phosphorus is added in a range of 50 to 150 in a memory cell.
KeV is implanted at about 1 × 10 ¹³ to 1 × 10 ¹⁴ / cm ² to form an impurity region having an impurity concentration of about 1 × 10 ¹⁸ / cm ^3.
The electric field at the pn junction due to the impurity concentration peak in the drain region can be reduced, and the leakage current from the capacitor 22 to the semiconductor substrate 1 (well) is suppressed, so that the refresh characteristics are good and the reliability of the semiconductor device is improved. . In addition, in the portion other than the memory cell, if the nMOS is used, phosphorus, p
In the case of MOS, boron or boron fluoride is 20 to 50 keV,
By implanting ions at about 5 × 10 ¹³ to 30 × 10 ¹³ / cm ² to form an impurity region having an impurity concentration of about 5 × 10 ¹⁸ / cm ³ , the wiring and the source / drain buried in the contact holes are formed. The contact resistance of the region can be reduced, and the driving capability can be improved. In the first embodiment, a semiconductor device in which a logic circuit, a memory cell of a DRAM, and a sense amplifier are formed has been described. However, the present invention is not limited to this.

According to this method of manufacturing a semiconductor device, in the step of forming a plurality of gate oxide films having different thicknesses in one chip, the number of times the silicon oxide film formed on the surface of the active region is removed Since the conditions are almost the same, the silicon oxide film 4 in the portion along the edge of the groove 2 does not fall. Therefore, even if gate oxide films having different thicknesses are formed on the surface, the shape of the portion where the active region is in contact with the trench isolation can be substantially the same, so that the transistor characteristics are not affected by the shape of the active region. It works. This reduces the leakage current due to the thick gate oxide, improves the refresh characteristics, reduces power consumption and improves the reliability of the DRAM memory cell, and improves the driving capability due to the thin gate oxide. In addition, the threshold voltage can be suppressed by suppressing the reverse narrow channel effect, a logic circuit with high speed and improved reliability can be built in one chip, and the characteristics of the semiconductor device can be improved. It is possible to obtain a miniaturized method for manufacturing a semiconductor device while maintaining the same. Further, the surface of silicon oxide film 4 is etched at a portion adjacent to the active region where the thick gate oxide film is formed and at a portion adjacent to the active region where the thin gate oxide film is formed. Since the number of times and the conditions are the same, there is no variation in the height of the surface of the silicon oxide film 4 in a portion where the width of the groove 2 is equal. As a result, a margin for the depth of focus can be secured in the photolithography process at the time of gate electrode patterning, and when etching the gate electrode material deposited on the surface of the silicon oxide film 4, a short circuit due to the remaining gate electrode material occurs. There is no. Conversely, in order not to leave the gate electrode material, too much etching does not penetrate the gate oxide film, which is an etching stopper, and does not cut down to the surface of the semiconductor substrate.
It is possible to obtain a semiconductor device with improved reliability without a risk of generating a leak current due to the surface roughness of the semiconductor substrate.

In FIG. 15, reference numeral 212 denotes a polysilicon film. After forming a trench isolation on the surface of the semiconductor substrate, a silicon oxide film 32 is formed on the surface.
Further, FIG. 15 shows a cross section of the semiconductor device at a stage where the process of forming the polysilicon film 212 on the surface is completed. This is formed instead of the silicon nitride film 211 which is a mask for etching the silicon oxide film 32. The order of removing the silicon oxide film 32 by using a plurality of resist patterns is as follows. This is similar to the case of the silicon nitride film 211. The removal of the polysilicon film is performed by isotropic dry etching. When the silicon oxide film 32 is dry-etched, the selectivity of the silicon nitride film is about 3 to 20, while the selectivity of the polysilicon film can be secured to 50 or more. Etching can be performed, which is effective for miniaturization of a semiconductor device.

Embodiment 2 FIG. 16 to 18 are cross-sectional views showing one process of a method for manufacturing a semiconductor device according to the second embodiment of the present invention, which is another method for manufacturing the semiconductor device shown in the first embodiment. According to this manufacturing method, FIG.
Is manufactured. First, Embodiment 1
In the same manner as described above, a trench isolation composed of the trench 2 and the silicon oxide films 3 and 4 is formed on the surface of the semiconductor substrate 1. Then, in the same manner as in the first embodiment, a silicon oxide film 32 is formed, a mask for opening an nMOS portion is formed, boron or boron fluoride is ion-implanted, and a mask for opening a pMOS portion is formed. By ion-implanting impurities such as phosphorus and arsenic, a well (not shown) excluding the channel implantation layer is formed in the memory cell and other portions. The steps so far are the same as those in the first embodiment. In FIG. 16, reference numeral 44 denotes a resist pattern. After forming a silicon nitride film 211 having a thickness of 5 to 30 nm on the silicon oxide film 32 in the same manner as in the first embodiment, a resist pattern 44 covering the thin film portion is formed. The silicon nitride film 211 on the surface of the semiconductor substrate 1 is removed. FIG. 16 is a cross-sectional view showing the semiconductor device at the stage when this step has been completed. Embodiment 1
In the above, the silicon nitride film 211 was removed and the channel injection layer was formed for each of the portions having the same gate oxide film thickness, such as the memory cells and the sense amplifiers, having different threshold values. In the form 2,
The silicon nitride film 211 is removed for each portion having the same gate oxide film thickness.

Next, after removing the resist pattern 44, a resist pattern 41 for opening the active region of the memory cell is formed, and boron or boron fluoride is ion-implanted to form a channel implantation layer (not shown) of the memory cell. ) Is formed. FIG. 17 is a cross-sectional view of the semiconductor device after this step has been completed. Then, after removing the resist pattern 41, a resist pattern 42 for opening the active region of the sense amplifier is formed, and a channel injection layer (not shown) of the sense amplifier is formed by ion implantation. FIG. 18 is a cross-sectional view of the semiconductor device at the stage when this step has been completed.
As in the first embodiment, when there is a transistor having a different threshold value in the thick film portion, the formation of the resist pattern and the ion implantation may be repeated in the same manner. Next, in the same manner as in the first embodiment, after removing the resist pattern 42, using the silicon nitride film 211 as a mask, the silicon oxide film 32 on the surface of the thick semiconductor substrate is removed, and then thermal oxidation is performed again. Thus, a silicon oxide film 53 is formed. Then, after removing the silicon oxide film 32 remaining on the semiconductor substrate surface of the logic circuit portion in the same manner as in the first embodiment, the entire surface is removed by thermal oxidation.
A silicon oxide film 52 having a thickness of about 7 nm is formed. Thereafter, similarly to the first embodiment, the gate electrode 9, the source / drain regions 10 to 13, the sidewalls 8, the interlayer insulating film 61, the wiring 17, the interlayer insulating film 62,
And a capacitor 22 is formed. As described above, the semiconductor device shown in FIG. 1 is formed.

According to this method of manufacturing a semiconductor device, in the step of forming a plurality of gate oxide films having different thicknesses in one chip, the number of times the silicon oxide film formed on the surface of the active region is removed Since the conditions are almost the same, the silicon oxide film 4 in the portion along the edge of the groove 2 does not fall. Therefore, even if gate oxide films having different thicknesses are formed on the surface, the shape of the portion where the active region is in contact with the trench isolation can be substantially the same, so that the transistor characteristics are not affected by the shape of the active region. It works. This reduces the leakage current due to the thick gate oxide, improves the refresh characteristics, reduces power consumption and improves the reliability of the DRAM memory cell, and improves the driving capability due to the thin gate oxide. In addition, the threshold voltage can be suppressed by suppressing the reverse narrow channel effect, a logic circuit with high speed and improved reliability can be built in one chip, and the characteristics of the semiconductor device can be improved. It is possible to obtain a miniaturized method for manufacturing a semiconductor device while maintaining the same. Further, the surface of silicon oxide film 4 is etched at a portion adjacent to the active region where the thick gate oxide film is formed and at a portion adjacent to the active region where the thin gate oxide film is formed. Since the number of times and the conditions are the same, there is no variation in the height of the surface of the silicon oxide film 4 in a portion where the width of the groove 2 is equal. As a result, a margin for the depth of focus can be secured in the photolithography process at the time of gate electrode patterning, and when etching the gate electrode material deposited on the surface of the silicon oxide film 4, a short circuit due to the remaining gate electrode material occurs. There is no. Conversely, in order not to leave the gate electrode material, too much etching does not penetrate the gate oxide film, which is an etching stopper, and does not cut down to the surface of the semiconductor substrate.
A semiconductor device with improved reliability can be obtained without a risk of generating a leak current due to the surface roughness of the semiconductor substrate.

Further, according to the method of manufacturing a semiconductor device shown in the first embodiment, as shown in FIG. 19, when forming a resist pattern 42 opening on the sense amplifier, The end portion of the silicon nitride film 211 may be covered on the trench isolation therebetween, and the silicon nitride film 211 may remain without being etched at this portion. If the silicon nitride film 211 remains, the silicon oxide film 32 thereunder is not etched and the gate oxide film 53 is not formed even if thermal oxidation is performed. However, the silicon oxide film 32 may undergo gate oxide film destruction due to deterioration of the film quality through various processes such as ion implantation for well formation. On the other hand, according to the method of manufacturing the semiconductor device according to the second embodiment, when removing the silicon nitride film 211 used as a mask for determining the thickness of the gate oxide films 51 and 52, first, After the silicon nitride film 211 of the entire thick film portion is removed by the resist pattern 44, necessary processing such as channel implantation is performed, and the remaining silicon nitride film 211 is selectively removed by hot phosphoric acid or the like. In such a method, the silicon nitride film 211 is not left behind due to the shift of the resist pattern, so that the margin of the resist pattern can be secured and the yield can be improved.

As in the first embodiment, when a polysilicon film is used instead of the silicon nitride film 211, the selectivity of the polysilicon film is high when the silicon oxide film 32 is dry-etched. The silicon oxide film 32 can be efficiently etched, which is effective for miniaturization of a semiconductor device.

[0038]

Since the present invention is configured as described above, it has the following effects. According to the present invention, a silicon oxide film buried in a trench for trench isolation has a structure in which a gate oxide film having a different thickness is formed on the surface of a plurality of active regions in one chip. The shape of the edge of the active region at the portion in contact with the trench isolation is formed substantially the same without dropping at the portion along the edge. Therefore, for example, a transistor having a large gate oxide film thickness and a suppressed leakage current is formed in a memory cell portion, and a transistor having a thin gate oxide film having a high driving capability and capable of high-speed operation is formed in a logic portion. This has the effect of reducing the size of the chip while maintaining good characteristics of the elements formed in each of the thick-film portion and the thin-film portion of the film.

Further, in a portion where the width of the groove is equal, the height of the silicon oxide film buried in the groove is the same, and the depth of focus in the photoengraving process when patterning the gate electrode passing over this surface. Margin can be secured. Thus, when the gate electrode material deposited on the surface of the silicon oxide film is etched, a short circuit due to the remaining gate electrode material does not occur. On the other hand, in order to prevent the gate electrode material from being left behind, excessive etching is performed, so that the gate oxide film serving as an etching stopper does not penetrate and cut to the surface of the semiconductor substrate. There is no possibility of generating a current, and the reliability of the semiconductor device is improved.

Also, a DRAM memory cell which has a reduced gate current to improve a refresh characteristic by suppressing a leak current due to a thick gate oxide film, and has a reduced power consumption and an improved reliability, and a driving capability due to a thin gate oxide film. As a result, a logic circuit with high speed and high reliability can be built in one chip, and the characteristics of the semiconductor device can be reduced. The size of the chip can be reduced while maintaining good conditions.

Even if gate oxide films having different thicknesses are formed on the surfaces of a plurality of active regions in one chip, the silicon oxide film buried inside the trench for trench isolation is formed along the edge of the trench. Don't be depressed. Therefore, even if gate oxide films having different thicknesses are formed on the surface, the shape of the end of the active region where the active region is in contact with the trench isolation can be formed substantially the same. Therefore, for example, a transistor having a large gate oxide film thickness and a suppressed leakage current is formed in a memory cell portion, and a transistor having a thin gate oxide film having a high driving capability and capable of high-speed operation is formed in a logic portion. A method of manufacturing a semiconductor device in which a chip is downsized can be obtained while maintaining good characteristics of elements formed in each of a thick film portion and a thin film portion of a film.

Further, a polysilicon film is used as a mask for etching the second silicon oxide film,
Since the polysilicon film can secure a selectivity of 50 or more when dry-etching the silicon oxide film, the silicon oxide film can be etched with more controllability and a method for manufacturing a miniaturized semiconductor device can be obtained. it can.

Even if transistors having different gate oxide films are formed in one chip, the shape of the edge of the active region can be made uniform. This reduces the leakage current due to the thick gate oxide, improves the refresh characteristics, reduces power consumption and improves the reliability of the DRAM memory cell, and improves the driving capability due to the thin gate oxide. In addition, the threshold voltage can be suppressed by suppressing the reverse narrow channel effect, a logic circuit with high speed and improved reliability can be built in one chip, and the characteristics of the semiconductor device can be improved. It is possible to obtain a miniaturized method for manufacturing a semiconductor device while maintaining the same.

In addition, since the channel implantation of each element is performed through the second silicon oxide film, and the second silicon oxide film is removed and the gate oxide film is newly formed, the surface of the semiconductor substrate is protected. Thus, it is possible to obtain a method of manufacturing a semiconductor device in which gate oxide film breakdown is suppressed and reliability is improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 15 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 16 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 17 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 18 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 19 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 20 is a cross-sectional view showing a conventional semiconductor device.

FIG. 21 is a cross-sectional view showing a conventional semiconductor device.

FIG. 22 is a cross-sectional view showing one step of a conventional method for manufacturing a semiconductor device.

FIG. 23 is a cross-sectional view showing one step of a conventional method for manufacturing a semiconductor device.

FIG. 24 is a cross-sectional view showing one step of a conventional method for manufacturing a semiconductor device.

FIG. 25 is a cross-sectional view showing one step of a conventional method for manufacturing a semiconductor device.

FIG. 26 is a cross-sectional view showing one step of a conventional method for manufacturing a semiconductor device.

FIG. 27 is a cross-sectional view showing one step of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1 semiconductor substrate, 2 groove, 4 silicon oxide film,
51 gate oxide film, 52 gate oxide film, 53 gate oxide film, 211 silicon nitride film, 212 polysilicon film, 32 silicon oxide film, 41 resist pattern, 42 resist pattern, 43 resist pattern, 45 resist pattern

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Yasetsu Ito 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Katsuyuki Hotta 2-2-2 Marunouchi, Chiyoda-ku, Tokyo F term in Mitsubishi Electric Corporation (reference) NA01 NA08 PR38 PR44 PR48 ZA07

Claims (7)

[Claims] A groove formed in a main surface of a semiconductor substrate; a silicon oxide film embedded in the groove; and a first portion of the main surface of the semiconductor substrate surrounded by the groove. A first active region, a first field effect element having a first gate oxide film formed on a main surface of the first active region, and a second portion of the main surface of the semiconductor substrate A second active region disposed around the groove and having the same end shape as the first active region; a second active region formed on a main surface of the second active region; A second field effect element having a second gate oxide film having a thickness different from that of the first gate oxide film. 2. The semiconductor device according to claim 1, wherein the width of the groove surrounding the first active region and the second active region is the same, and the height from the bottom surface of the groove to the surface of the silicon oxide film is the same. Semiconductor device. 3. An interlayer insulating film formed on a surface of the first field-effect element and having an opening reaching the first field-effect field effect element; 3. The semiconductor device according to claim 1, further comprising a capacitor to be connected, wherein the first gate oxide film is thicker than the second gate oxide film. 4. A step of forming a groove surrounding the first and second active regions provided on the main surface of the semiconductor substrate; a step of forming a first silicon oxide film filling the groove; Forming a second silicon oxide film covering the first and second active regions; forming a first mask having an opening on the main surface of the first active region on the surface of the second silicon oxide film; Etching a second silicon oxide film on the first active region main surface; forming a first gate oxide film on the first active region main surface; Removing the mask, and forming a second mask having an opening on the main surface of the second active region, and etching a second silicon oxide film on the main surface of the second active region. Removing the second mask; First and forming a second gate oxide film on the second active region major surface, the first and second to the first and second active regions main surface
Forming a field-effect element. 5. The method according to claim 4, wherein the first mask is a polysilicon film. 6. A step of forming an interlayer insulating film, a step of forming an opening in the interlayer insulating film to reach a first field effect element, and reaching the first field effect element through the opening. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of forming a capacitor. 7. After the first mask is formed, before the second silicon oxide film on the main surface of the first active region is etched, channel implantation of the first field effect element into the first active region is performed. Performing a channel implantation of the second field effect element into the second active region before forming the second silicon oxide film on the main surface of the second active region after forming the second mask. 7. The method according to claim 6, further comprising the steps of: