CN100423212C - Component of metal oxide semiconductor transistor in high voltage, and fabricating method - Google Patents
Component of metal oxide semiconductor transistor in high voltage, and fabricating method Download PDFInfo
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- CN100423212C CN100423212C CNB2005100747896A CN200510074789A CN100423212C CN 100423212 C CN100423212 C CN 100423212C CN B2005100747896 A CNB2005100747896 A CN B2005100747896A CN 200510074789 A CN200510074789 A CN 200510074789A CN 100423212 C CN100423212 C CN 100423212C
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- grid
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- oxide semiconductor
- metal oxide
- gate dielectric
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Abstract
The present invention provides a technique of a semiconductor element which has high voltage and is made from metal oxide. The technique comprises the following steps that a semiconductor base is provided; a grid dielectric layer is formed on the semiconductor base; a polycrystalline silicon layer is deposited on the grid dielectric layer, and a mask pattern for grid light is formed on the polycrystalline silicon layer. The polycrystalline silicon layer and a part of the grid dielectric layer, which are not covered by the mask pattern for grid light, are etched to form a grid. A light mask pattern baffled by metal silicide is formed on the grid and is covered on the grid and the grid dielectric layer which extends from both sides of the grid in the offset distance d. The grid dielectric layer which is not covered by the light mask pattern baffled by metal silicide is etched and is exposed out of the semiconductor base. Thereby, ear parts baffled by metal silicide are formed at both sides of the grid and extend outwards for the offset distance d. A metal layer is deposited on the semiconductor base, and the metal layer reacts with the exposed semiconductor base to form a metal silicide layer.
Description
Technical field
The present invention relates to the making of semiconductor integrated circuit, particularly relate to a kind of high voltage device manufacture method of improvement, metal silicide technology can be integrated in the technology of high voltage device, reduce the resistance of component of metal oxide semiconductor transistor in high voltage by this.
Background technology
Known to the sector person, with high voltage device and low voltage component, as high/low pressure metal-oxide semiconductor (MOS) (MOS) transistor, the integrated circuit technique of integration and making is existing skill simultaneously.For example, use low voltage component to come the production control circuit, but use high voltage device make electric programming read-only memory (ElectricallyProgrammable Read-Only-Memory, EPROM) or the drive circuit of LCD or the like.
Yet existing high-pressure process is reducing on the resistance of grid, source electrode and drain electrode, still can't be because consider hot carrier's effect with traditional metal silicide, and titanium silicon metal (TiSi for example
2) or cobalt silicon metal (CoSi
2) or the like, the resistance of grid, source electrode and the drain electrode of high voltage device is reduced, what make high voltage device connects the dough sheet too high in resistance.
Hence one can see that, and the conventional semiconductor high-pressure process still has the space of further improvement.
Summary of the invention
Main purpose of the present invention is providing a kind of high voltage device technology of improvement, can be effectively the resistance of grid, source electrode and the drain electrode of high voltage device be reduced.
According to a preferred embodiment of the invention, the invention provides a kind of high-voltage metal oxide semiconductor element technology, include following steps:
The semiconductor substrate is provided;
Form a gate dielectric on this semiconductor-based end, thickness is t
1
Deposition one polysilicon layer on this gate dielectric;
On this polysilicon layer, form a grid optical mask pattern;
This polysilicon layer and this a part of gate dielectric that etching is not covered by this grid optical mask pattern are to form a grid;
Remove this grid optical mask pattern;
Form a metal silication and stop optical mask pattern on this grid, it covers this gate dielectric of this grid and this grid both sides extension offset distance d;
Etching is not stopped this gate dielectric that optical mask pattern covers by this metal silication, and exposes this semiconductor-based end, stops ear with the metal silication that forms the offset distance d that stretches out in these grid both sides, and its thickness is t
2, t wherein
2Less than t
1
Deposition one metal level on this semiconductor-based end; And
Carry out a thermal process, the reaction of the semiconductor-based end that this metal level and this are exposed forms a metal silicide layer, and the distance of this metal silicide layer and this grid is about d.
In order further to understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet appended graphic only for reference and aid illustration usefulness is not to be used for the present invention is limited.
Description of drawings
Fig. 1 to Fig. 9 is the generalized section of the integrating semiconductor high and low pressure element technology that illustrates according to the preferred embodiment of the present invention.
The simple symbol explanation
10 insulation systems of the semiconductor-based ends 12
22 low pressure grid oxic horizons, 24 high pressure grid oxic horizons
24a oxide layer ear 30 polysilicon layers
32 grids, 34 grids
42 photoresist masks, 44 photoresist masks
52 photoresist masks, 54 photoresist masks
64 sidewalls, 72 drain/sources
74 drain/sources, 80 metal levels
82a metal silicide layer 82b metal silicide layer
84a metal silicide layer 84b metal silicide layer
Embodiment
See also Fig. 1 to Fig. 9, it illustrates is generalized section according to the semiconductor high and low pressure element technology of the preferred embodiment of the present invention.High voltage device comprises and operates in 18 volts or high voltage person more, and low voltage component comprises and operates in 5 volts, 3.3 volts or low-voltage person more.At first, as shown in Figure 1, provide semiconductor substrate 10, include low voltage component zone 102 and high voltage device zone 104.In low voltage component zone 102 and high voltage device zone 104, be pre-formed insulation system 12, shallow groove insulation configuration for example, and define the active region on surface, the semiconductor-based ends 10.
As shown in Figure 2, then form low pressure grid oxic horizon 22 and high pressure grid oxic horizon 24 respectively at the semiconductor-based end 10 in low voltage component zone 102 and high voltage device zone 104, the thickness of its mesolow grid oxic horizon 22 is generally less than 200 dusts, and the thickness of high pressure grid oxic horizon 24 is then greater than 400 dusts.According to the preferred embodiment of the present invention, the thickness of low pressure grid oxic horizon 22 is less than or equal to 100 dusts, and the thickness of high pressure grid oxic horizon 24 is then at least more than or equal to 600 dusts.The technology that forms the grid oxic horizon of different-thickness on the semiconductor-based end is existing skill, therefore seldom gives unnecessary details.
As shown in Figure 3, then deposit a polysilicon layer 30 on low pressure grid oxic horizon 22 in low voltage component zone 102 and high voltage device zone 104 and the high pressure grid oxic horizon 24.Then, on polysilicon layer 30, form photoresist mask 42 and photoresist mask 44, the gate pattern of the low voltage component in the photoresist mask 42 definition low voltage components zone 102 wherein, and the gate pattern of the high voltage device in the photoresist mask 44 definition high voltage devices zones 104.
As shown in Figure 4, then carry out a plasma dry etching process, with polysilicon layer 30 ablations of not covered by photoresist mask 42 and photoresist mask 44, form the grid 32 of low voltage component and the grid 34 of high voltage device, continue etching low pressure grid oxic horizon 22 simultaneously, till the semiconductor-based end 10 in low voltage component zone 102, be exposed, at this moment, high pressure grid oxic horizon 24 is only fallen the thickness of a part by ablation, and high voltage device zone 104 is still covered in by remaining high pressure grid oxic horizon 24.
As shown in Figure 5, on the semiconductor-based end 10, be coated with a photoresist layer subsequently, utilize photoetching technique that the photoresist layer is defined as photoresist mask 52 and photoresist mask 54 then, wherein photoresist mask 52 covers in low voltage component zone 102, and photoresist mask 54 only covers the grid 34 of the high voltage device in the high voltage device zone 104, and the outstanding grid 34 both sides offset distances of a part are the high pressure grid oxic horizon 24 of d, and wherein offset distance d is the rough distance that equals between in subsequent step formed source electrode or drain electrode and the grid.
As shown in Figure 6, then carry out a plasma dry etching process, with high pressure grid oxic horizon 24 ablations that do not covered by photoresist mask 54.Then, again photoresist mask 52 and photoresist mask 54 are removed, stay the high pressure grid oxic horizon 24 that is positioned at grid 34 belows, comprise that its thickness is about 100 to the 600 Izod right sides by the stretch out 24a of oxide layer ear (lug) of offset distance d of grid 24 both sides.According to a preferred embodiment of the invention, offset distance d is approximately between 20 dust to 500 dusts.
As shown in Figure 7, follow the sub-dielectric layer 60 of deposited sidewalls, for example silicon nitride on the semiconductor-based end 10.Subsequently, as shown in Figure 8, carry out the anisortopicpiston dry ecthing, the sub-dielectric layer 60 of etching sidewall is to form sidewall 62 and sidewall 64 respectively on the sidewall of grid 32 and grid 34.Then, carry out ion implantation technology, utilize grid 32 and grid 34 and its sidewall, in the semiconductor-based end 10, inject the drain/source 72 of low voltage component and the drain/source 74 of high voltage device respectively as injecting mask.Then, carry out so-called metal silicide technology, at first deposition one metal level 80, for example titanium or cobalt metal on the semiconductor-based end 10.Wherein, the 24a of oxide layer ear plays the part of metal silication block (salicide block) in metal silicide technology, makes a bit of between the drain/source 74 of high voltage device and its grid 34 not touch with metal level 80 apart from d.
At last, as shown in Figure 9, after carrying out thermal process, metal level 80 forms metal silicide layer 82a and 84a respectively with drain/source 72 that touches and 74 reactions, and metal level 80 forms metal silicide layer 82b and 84b respectively with polysilicon gate 32 that touches and 34 reactions.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (7)
1. the manufacture method of a high-voltage metal oxide semiconductor element includes following steps:
The semiconductor substrate is provided;
Form a gate dielectric on this semiconductor-based end, thickness is t
1
Deposition one polysilicon layer on this gate dielectric;
On this polysilicon layer, form a grid optical mask pattern;
This polysilicon layer that etching is not covered by this grid optical mask pattern and this gate dielectric of a part of thickness are to form a grid;
Remove this grid optical mask pattern;
On this grid, form a metal silication and stop optical mask pattern, this gate dielectric that it covers this grid and extends offset distance d to these grid both sides;
Etching is not stopped this gate dielectric that optical mask pattern covers by this metal silication, and exposes this semiconductor-based end, stops ear with the metal silication that forms the offset distance d that stretches out in these grid both sides, and its thickness is t
2, t wherein
2Less than t
1
Deposition one metal level on this semiconductor-based end; And
Carry out a thermal process, the reaction of the semiconductor-based end that this metal level and this are exposed forms a metal silicide layer, and the distance of this metal silicide layer and this grid is d.
2. the manufacture method of high-voltage metal oxide semiconductor element as claimed in claim 1, the wherein thickness t of this gate dielectric
1Greater than 400 dusts.
3. the manufacture method of high-voltage metal oxide semiconductor element as claimed in claim 1, wherein this metal silication stops the thickness t of ear
2Greater than 100 dusts.
4. the manufacture method of high-voltage metal oxide semiconductor element as claimed in claim 1, wherein this offset distance d is between 20 dust to 500 dusts.
5. the manufacture method of high-voltage metal oxide semiconductor element as claimed in claim 1, wherein this metal level comprises and boring and titanium.
6. the manufacture method of high-voltage metal oxide semiconductor element as claimed in claim 1, wherein the operating voltage of this high-voltage metal oxide semiconductor element is more than or equal to 18 volts.
7. high-voltage metal oxide semiconductor element includes:
The semiconductor substrate;
One gate dielectric was formed on this semiconductor-based end, and thickness is t
1, t
1Greater than 400 dusts;
One grid is located on this gate dielectric;
One metal silication stops ear, and its thickness is t
2, t
2Greater than 100 dusts, wherein this metal silication stops that ear and this gate dielectric are adjacent, and is by these grid both sides stretch out offset distance d, wherein t
2Less than t
1
One drain/source is located at this metal silication and is stopped that ear is in this other semiconductor-based end; And
One metal silicide layer is formed on this drain/source, and the distance of this metal silicide layer and this grid is d, and d is between 20 dust to 500 dusts;
Wherein the operating voltage of this high-voltage metal oxide semiconductor element is more than or equal to 18 volts.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100747896A CN100423212C (en) | 2005-06-03 | 2005-06-03 | Component of metal oxide semiconductor transistor in high voltage, and fabricating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100747896A CN100423212C (en) | 2005-06-03 | 2005-06-03 | Component of metal oxide semiconductor transistor in high voltage, and fabricating method |
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| Publication Number | Publication Date |
|---|---|
| CN1873930A CN1873930A (en) | 2006-12-06 |
| CN100423212C true CN100423212C (en) | 2008-10-01 |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101866841B (en) * | 2009-04-16 | 2012-04-18 | 上海华虹Nec电子有限公司 | Method for forming self-aligned metal silicide at source/drain region of device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000195969A (en) * | 1998-12-28 | 2000-07-14 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| US6268633B1 (en) * | 1997-12-31 | 2001-07-31 | Stmicroelectronics S.R.L. | Electronic structure comprising high and low voltage transistors, and a corresponding fabrication method |
| US20020068406A1 (en) * | 2000-12-05 | 2002-06-06 | Kazutoshi Ishii | Semiconductor device and method of manufacturing the same |
| US20020125512A1 (en) * | 2001-02-16 | 2002-09-12 | Yoshinori Hino | Semiconductor device and manufacturing method thereof |
| US6777283B2 (en) * | 2000-10-31 | 2004-08-17 | Renesas Technology Corp. | Semiconductor device and method of manufacturing same |
-
2005
- 2005-06-03 CN CNB2005100747896A patent/CN100423212C/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6268633B1 (en) * | 1997-12-31 | 2001-07-31 | Stmicroelectronics S.R.L. | Electronic structure comprising high and low voltage transistors, and a corresponding fabrication method |
| JP2000195969A (en) * | 1998-12-28 | 2000-07-14 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| US6777283B2 (en) * | 2000-10-31 | 2004-08-17 | Renesas Technology Corp. | Semiconductor device and method of manufacturing same |
| US20020068406A1 (en) * | 2000-12-05 | 2002-06-06 | Kazutoshi Ishii | Semiconductor device and method of manufacturing the same |
| US20020125512A1 (en) * | 2001-02-16 | 2002-09-12 | Yoshinori Hino | Semiconductor device and manufacturing method thereof |
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|---|---|
| CN1873930A (en) | 2006-12-06 |
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