JP2007157859A - Ceramic/package, aggregate substrate, and electronic device - Google Patents

Ceramic/package, aggregate substrate, and electronic device Download PDF

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Publication number
JP2007157859A
JP2007157859A JP2005348574A JP2005348574A JP2007157859A JP 2007157859 A JP2007157859 A JP 2007157859A JP 2005348574 A JP2005348574 A JP 2005348574A JP 2005348574 A JP2005348574 A JP 2005348574A JP 2007157859 A JP2007157859 A JP 2007157859A
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Prior art keywords
ceramic
electrode
cavity
sealing
sealing electrode
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Masaki Hongo
政紀 本郷
Natsuyo Nagano
奈津代 長野
Takashi Ogura
隆 小倉
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ceramic/package of which reduction of the area of a sealing electrode as well as occurrence of rough on the surface of the sealing electrode are suppressed compared with a conventional technology, even if reduced in size and weight for improved air-tight sealing property of electronic circuit components housed in a cavity. <P>SOLUTION: A ceramic/package comprises a cavity for housing electronic circuit components, with a plurality of ceramic layers being laminated. On the surface of any one of ceramic layers, a sealing electrode is formed from a conductive material which air-tight seals the electronic circuit components by bonding a cap. A cavity inside wall conductive layer of conductive material is formed at least at a part of the cavity inside wall of the ceramic layer where the sealing electrode is formed. The sealing electrode is grounded through the cavity inside wall conductive layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、複数のセラミック層を積層してなるセラミック・パッケージ、複数のセラミック・パッケージが互いの側面の一部又は全部を介してマトリックス状に連結している集合基板、及び前記セラミック・パッケージに１以上の電子回路部品を搭載した電子デバイスに関するものである。   The present invention relates to a ceramic package formed by laminating a plurality of ceramic layers, a collective substrate in which a plurality of ceramic packages are connected in a matrix through part or all of the side surfaces of each other, and the ceramic package. The present invention relates to an electronic device on which one or more electronic circuit components are mounted.

携帯電話機等の移動体端末に装備されるアンテナ共用器１は、図８に示すように、複数のセラミック層からなりキャビティCvを具備したセラミック・パッケージ２と、弾性表面波素子からなる送信用フィルタ部及び受信用フィルタ部とを備えたSAWフィルタチップ３と、キャビティCv内に収容された前記SAWフィルタチップ３を気密封止するためのキャップ４とを備えている (特許文献１参照)。   As shown in FIG. 8, an antenna duplexer 1 equipped in a mobile terminal such as a cellular phone includes a ceramic package 2 made of a plurality of ceramic layers and having a cavity Cv, and a transmission filter made of a surface acoustic wave element. And a receiving filter unit, and a cap 4 for hermetically sealing the SAW filter chip 3 accommodated in the cavity Cv (see Patent Document 1).

セラミック・パッケージ２は、図７に示す如く、アンテナが接続されるべきアンテナ端子ＡＮＴと、送信回路が接続されるべき送信側信号端子Ｔｘと、受信回路が接続されるべき受信側信号端子Ｒｘとを具え、アンテナ端子ＡＮＴは、送信用フィルタ部31を経て送信側信号端子Ｔｘに繋がると共に、受信用フィルタ部32を経て受信側信号端子Ｒｘに繋がっている。   As shown in FIG. 7, the ceramic package 2 includes an antenna terminal ANT to which an antenna is connected, a transmission side signal terminal Tx to which a transmission circuit is connected, and a reception side signal terminal Rx to which a reception circuit is connected. The antenna terminal ANT is connected to the transmission side signal terminal Tx through the transmission filter unit 31 and is connected to the reception side signal terminal Rx through the reception filter unit 32.

又、アンテナ端子ＡＮＴと受信用フィルタ部32との間には、位相を回転させるための位相整合用ストリップラインSLが介在し、送信用フィルタ部31と受信用フィルタ部32の間の位相の整合を図っている。   Further, a phase matching stripline SL for rotating the phase is interposed between the antenna terminal ANT and the reception filter unit 32, and the phase matching between the transmission filter unit 31 and the reception filter unit 32 is performed. I am trying.

図９に従来のアンテナ共用器１の断面図を示す。セラミック・パッケージ２は５つのセラミック層L1、L2、L3、L4、L5を積層したものである。第１、第２、第３のセラミック層L1、L2、L3によりパッケージ基部2Aが構成され、第４、第５のセラミック層L4、L5によりパッケージ枠部2Bが構成されている。   FIG. 9 shows a cross-sectional view of a conventional antenna duplexer 1. The ceramic package 2 is a laminate of five ceramic layers L1, L2, L3, L4, and L5. The first, second, and third ceramic layers L1, L2, and L3 constitute a package base 2A, and the fourth and fifth ceramic layers L4 and L5 constitute a package frame 2B.

セラミック・パッケージ２の底面、即ち、第１のセラミック層L1の一方の表面には、前記アンテナ端子ＡＮＴ、送信側信号端子Ｔｘ、受信側信号端子Ｒｘ、ＧＮＤ端子等の外部電極21が形成されている。該外部電極21は、アンテナ共用器１が実装されるべきマザー回路基板の所定のランドと半田等により接合される。   On the bottom surface of the ceramic package 2, that is, one surface of the first ceramic layer L1, external electrodes 21 such as the antenna terminal ANT, the transmission side signal terminal Tx, the reception side signal terminal Rx, and the GND terminal are formed. Yes. The external electrode 21 is joined to a predetermined land of the mother circuit board on which the antenna duplexer 1 is to be mounted by solder or the like.

パッケージ基部2AにはストリップラインSLが具備されており、第３のセラミック層L3の表面のうちキャビティCvの底面として露出している領域には複数の金パッド28が形成されている。又、送信用フィルタ部（図示せず）及び受信用フィルタ部（図示せず）を具備したSAWフィルタチップ３の外部電極（図示せず）には金バンプ33が設けられている。セラミック・パッケージ２の金パッド28とSAWフィルタチップ３の外部電極（図示せず）とを金バンプ33を介して接合することにより、ＳＡＷフィルタチップ３をセラミック・パッケージ２にフリップチップ実装している。   The package base 2A is provided with a strip line SL, and a plurality of gold pads 28 are formed in a region exposed as the bottom surface of the cavity Cv in the surface of the third ceramic layer L3. Further, gold bumps 33 are provided on the external electrodes (not shown) of the SAW filter chip 3 provided with a transmitting filter part (not shown) and a receiving filter part (not shown). The SAW filter chip 3 is flip-chip mounted on the ceramic package 2 by bonding the gold pad 28 of the ceramic package 2 and the external electrode (not shown) of the SAW filter chip 3 via the gold bump 33. .

パッケージ枠部2Bには略矩形状の窓部が設けられ、キャビティCvを形成している。又、セラミック・パッケージ２の天面、即ち第５のセラミック層L5の表面にはキャップ４を接合するための封止用電極27が形成されている。   The package frame portion 2B is provided with a substantially rectangular window portion to form a cavity Cv. Further, a sealing electrode 27 for joining the cap 4 is formed on the top surface of the ceramic package 2, that is, the surface of the fifth ceramic layer L5.

セラミック・パッケージ２の側面には、横断面が半円状の側面電極用凹部をセラミック層の積層方向に設け、更に該側面電極用凹部に導電材層を被着してなる側面電極22が設けられており、対応する側面電極22、金パッド28、外部電極21は、配線パターン（図示せず）や導電材料が充填されたVIAホール（図示せず）を介して接続されている。   The side surface of the ceramic package 2 is provided with a side electrode recess having a semicircular cross section in the laminating direction of the ceramic layer, and further provided with a side electrode 22 formed by depositing a conductive material layer on the side electrode recess. The corresponding side electrode 22, gold pad 28, and external electrode 21 are connected through a VIA hole (not shown) filled with a wiring pattern (not shown) or a conductive material.

図９において、側面電極22、22はＧＮＤ電極である。外部電極21は、導電材からなる側面電極22を介して封止用電極27と接続している。即ち、封止用電極27は側面電極22と直接接続されて接地していることとなる。   In FIG. 9, side electrodes 22 and 22 are GND electrodes. The external electrode 21 is connected to the sealing electrode 27 via a side electrode 22 made of a conductive material. That is, the sealing electrode 27 is directly connected to the side electrode 22 and grounded.

又、封止用電極27にはＡｇ−Ｓｎ系合金の接合材（図示せず）等を介してキャップ４が固着され、キャビティCv内のSAWフィルタチップ３を気密封止している。尚、キャップ４は金属材、又は少なくとも封止用電極27との対抗面に金属層が被着されたセラミック材等からなり、側面電極用凹部を覆わないような大きさとなっている。
特開２００３−１５２０１６号公報 図１ The cap 4 is fixed to the sealing electrode 27 via an Ag—Sn alloy bonding material (not shown) or the like, and the SAW filter chip 3 in the cavity Cv is hermetically sealed. The cap 4 is made of a metal material, or a ceramic material having a metal layer deposited on at least the surface facing the sealing electrode 27, and has a size that does not cover the side electrode recess.
Japanese Patent Laid-Open No. 2003-152016 FIG.

近年、携帯電話機等の移動体端末の小型・軽量化が市場で求められ、それに伴ってアンテナ共用器の小型・軽量化、即ちセラミック・パッケージの小型・軽量化も進んでいる。   In recent years, mobile terminals such as mobile phones have been required to be reduced in size and weight, and along with this, antenna duplexers have been reduced in size and weight, that is, ceramic packages have been reduced in size and weight.

セラミック・パッケージが小型化されることにより封止用電極の面積も小さくなってきている。封止用電極とキャップとの気密封止性を保つため、封止用電極の平面度を小さくすることが望ましく、封止用電極表面に突起・陥没や傾き等の凹凸があると気密封止性が損なわれてしまう。   As the ceramic package is miniaturized, the area of the sealing electrode is also reduced. In order to maintain the hermetic sealing performance between the sealing electrode and the cap, it is desirable to reduce the flatness of the sealing electrode. If the sealing electrode surface has irregularities such as protrusions, depressions, and inclinations, hermetic sealing is performed. Sexuality will be impaired.

小型化されたアンテナ共用器における封止用電極の接地法として以下の手法１乃至３が考えられる。尚、以下の説明で使われる図１１は第５のセラミック層L5の平面図であり、斜線部は封止用電極27を示している。   The following methods 1 to 3 are conceivable as grounding methods for the sealing electrode in the miniaturized antenna duplexer. 11 used in the following description is a plan view of the fifth ceramic layer L5, and the hatched portion indicates the sealing electrode 27. FIG.

手法１のセラミック・パッケージでは、セラミック・パッケージ２の側面に横断面が半円状の側面電極用凹部をセラミック層の積層方向に設け、該側面電極用凹部に導電材を充填して横断面が半円状の充填型側面電極を形成し、該充填型側面電極と封止用電極とを接続した。又、キャップは封止用電極との接合面積を大きくするために、その縦・横寸法は第５のセラミック層L5の縦・横寸法と略同じとなっている。即ち、キャップは充填型側面電極をも覆うように構成されている。   In the ceramic package of method 1, a side electrode recess having a semicircular cross section is provided on the side surface of the ceramic package 2 in the laminating direction of the ceramic layer, and the side electrode recess is filled with a conductive material to form a cross section. A semicircular filling side electrode was formed, and the filling side electrode and the sealing electrode were connected. Further, in order to increase the bonding area of the cap with the sealing electrode, the vertical and horizontal dimensions are substantially the same as the vertical and horizontal dimensions of the fifth ceramic layer L5. That is, the cap is configured to cover the filling side electrode.

手法１の場合には、焼成によって充填型側面電極が収縮するため、図１１（ａ）に示すように充填型側面電極の位置に対応する封止用電極の領域に凹部271が発生してしまう。   In the case of Method 1, the filling side electrode contracts due to firing, so that a recess 271 is generated in the sealing electrode region corresponding to the position of the filling side electrode as shown in FIG. .

手法２として、導電材を充填したVIAホールをセラミック・パッケージの側面から離間した中心部側に設け、該VIAホールと封止用電極とを接続させる手法が挙げられる。尚、キャップは封止用電極との接合面積を大きくするために、その縦・横寸法は第５のセラミック層L5の縦・横寸法と略同じとなっている。   Method 2 includes a method in which a VIA hole filled with a conductive material is provided on the center side separated from the side surface of the ceramic package, and the VIA hole and the sealing electrode are connected. Note that the vertical and horizontal dimensions of the cap are substantially the same as the vertical and horizontal dimensions of the fifth ceramic layer L5 in order to increase the bonding area with the sealing electrode.

図１０に手法２によるアンテナ共用器の断面図を示す。第３のセラミック層L3の表面には配線パターン23が形成されており、側面電極22と接続している。又、第４及び第５のセラミック層L4、L5を貫通し、その内部に導電材が充填されたVIAホール24が設けられ、配線パターン23と封止用電極27とを接続している。手法２の場合も、焼成によってVIAホールが収縮するため、図１１（ｂ）に示すようにVIAホールの位置に対応する封止用電極の領域に凹部272が発生してしまう。   FIG. 10 shows a cross-sectional view of the antenna duplexer according to method 2. A wiring pattern 23 is formed on the surface of the third ceramic layer L3 and is connected to the side electrode 22. Further, a VIA hole 24 penetrating through the fourth and fifth ceramic layers L4 and L5 and filled with a conductive material is provided, and the wiring pattern 23 and the sealing electrode 27 are connected. In the case of method 2 as well, since the VIA hole contracts due to firing, a recess 272 is generated in the region of the sealing electrode corresponding to the position of the VIA hole as shown in FIG.

手法３のセラミック・パッケージでは、セラミック・パッケージ２の側面に横断面が半円状の側面電極用凹部をセラミック層の積層方向に設け、更に該側面電極用凹部に導電材層を被着してなるスルーホール型側面電極を設け、該スルーホール型側面電極と封止用電極を接続している。更に、前記封止用電極に、封止用電極との接合面積を大きくするためにその縦・横寸法が第５のセラミック層L5の縦・横寸法と略同じとなっているキャップを固着している。手法３の場合には、図１１（ｃ）に示すように側面電極用凹部273には封止用電極は形成できず、封止用電極の面積が減少してしまう。   In the ceramic package of Method 3, a side electrode recess having a semicircular cross section is provided on the side surface of the ceramic package 2 in the stacking direction of the ceramic layer, and a conductive material layer is further applied to the side electrode recess. A through-hole type side electrode is provided, and the through-hole type side electrode and the sealing electrode are connected. Further, a cap whose vertical and horizontal dimensions are substantially the same as the vertical and horizontal dimensions of the fifth ceramic layer L5 is fixed to the sealing electrode in order to increase the bonding area with the sealing electrode. ing. In the case of the method 3, as shown in FIG. 11C, the sealing electrode cannot be formed in the side electrode recess 273, and the area of the sealing electrode is reduced.

従って、上記した手法１乃至３のいずれをもってしても封止用電極とキャップとの気密封止性は悪いものとなっていた。   Therefore, even with any of the above-described methods 1 to 3, the hermetic sealing property between the sealing electrode and the cap is poor.

そこで、本発明は、小型・軽量化されても、従来技術と比較して封止用電極の面積の減少や封止用電極表面の凹凸の発生を抑えることができ、よってキャビティ内に収容すべき電子回路部品の気密封止性が向上したセラミック・パッケージを提供することを目的とする。更に、前記セラミック・パッケージがマトリック状に連結した集合基板、及び前記セラミック・パッケージを具備した電子デバイスを提供することも目的とする。   Therefore, even if the present invention is reduced in size and weight, it is possible to suppress the reduction in the area of the sealing electrode and the generation of irregularities on the surface of the sealing electrode as compared with the prior art, and thus the housing is accommodated in the cavity. It is an object of the present invention to provide a ceramic package having improved hermetic sealing performance of electronic circuit components. It is another object of the present invention to provide a collective substrate in which the ceramic packages are connected in a matrix, and an electronic device including the ceramic package.

第１の発明は、複数のセラミック層を積層してなると共に、電子回路部品を収容するためのキャビティを有するセラミック・パッケージであって、いずれかのセラミック層の表面には、キャップを固着することにより前記電子回路部品を気密封止することができる封止用電極が導電材により形成され、前記封止用電極が形成されたセラミック層のキャビティ内壁の少なくとも一部には導電材からなるキャビティ内壁導電層が形成され、前記封止用電極は前記キャビティ内壁導電層を介して接地されていることを特徴とするセラミック・パッケージである。   A first invention is a ceramic package comprising a plurality of ceramic layers laminated and a cavity for accommodating an electronic circuit component, wherein a cap is fixed to the surface of any ceramic layer A sealing electrode capable of hermetically sealing the electronic circuit component is formed of a conductive material, and at least a part of the cavity inner wall of the ceramic layer on which the sealing electrode is formed has a cavity inner wall made of the conductive material. The ceramic package is characterized in that a conductive layer is formed, and the sealing electrode is grounded through the cavity inner wall conductive layer.

キャビティ内壁を構成するすべてのセラミック層には、それぞれのキャビティ内壁部の少なくとも一部に導電材からなるキャビティ内壁導電層が形成されていることが好ましい。   It is preferable that all ceramic layers constituting the cavity inner wall have a cavity inner wall conductive layer made of a conductive material formed on at least a part of each cavity inner wall.

第２の発明は、第１の発明の複数のセラミック・パッケージが互いの側面の一部又は全部を介してマトリックス状に連結していることを特徴とする集合基板である。   A second invention is a collective substrate characterized in that the plurality of ceramic packages of the first invention are connected in a matrix through part or all of the side surfaces of each other.

第３の発明は、第１の発明のセラミック・パッケージのキャビティ内に１つ又は複数の電子回路部品を収容し、前記セラミック・パッケージの封止用電極にキャップを固着して前記電子回路部品を気密封止したことを特徴とする電子デバイスである。   According to a third aspect of the invention, one or more electronic circuit components are accommodated in the cavity of the ceramic package of the first invention, and a cap is fixed to the sealing electrode of the ceramic package to mount the electronic circuit component. An electronic device characterized by being hermetically sealed.

セラミック・パッケージが小型・軽量化されても、従来技術と比較して封止用電極の面積の減少を抑えることができ、かつ封止用電極の凹凸の発生を回避することができる。よってセラミック・パッケージのキャビティ内に収容した電子回路部品の気密封止性が向上する。   Even if the ceramic package is reduced in size and weight, a reduction in the area of the sealing electrode can be suppressed as compared with the conventional technique, and the occurrence of unevenness in the sealing electrode can be avoided. Therefore, the hermetic sealing performance of the electronic circuit components housed in the cavity of the ceramic package is improved.

以下、本発明の実施の形態につき、図面に沿って具体的に説明する。   Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.

本発明に係る第1の実施例のアンテナ共用器の概略分解斜視図を図２に示す。図２を見ると分かるように、アンテナ共用器１は、複数のセラミック層からなりキャビティCvを具備したセラミック・パッケージ２と、弾性表面波素子からなる送信用フィルタ部及び受信用フィルタ部とを備えたSAWフィルタチップ３と、キャビティCv内に収容された前記SAWフィルタチップ３を気密封止するためのキャップ４とを備えている。   FIG. 2 is a schematic exploded perspective view of the antenna duplexer according to the first embodiment of the present invention. As can be seen from FIG. 2, the antenna duplexer 1 includes a ceramic package 2 made of a plurality of ceramic layers and having a cavity Cv, and a transmission filter part and a reception filter part made of a surface acoustic wave element. A SAW filter chip 3 and a cap 4 for hermetically sealing the SAW filter chip 3 accommodated in the cavity Cv.

セラミック・パッケージ２は、図７に示す如く、アンテナが接続されるべきアンテナ端子ＡＮＴと、送信回路が接続されるべき送信側信号端子Ｔｘと、受信回路が接続されるべき受信側信号端子Ｒｘとを具え、アンテナ端子ＡＮＴは、送信用フィルタ部31を経て送信側信号端子Ｔｘに繋がると共に、受信用フィルタ部32を経て受信側信号端子Ｒｘに繋がっている。   As shown in FIG. 7, the ceramic package 2 includes an antenna terminal ANT to which an antenna is connected, a transmission side signal terminal Tx to which a transmission circuit is connected, and a reception side signal terminal Rx to which a reception circuit is connected. The antenna terminal ANT is connected to the transmission side signal terminal Tx through the transmission filter unit 31 and is connected to the reception side signal terminal Rx through the reception filter unit 32.

又、アンテナ端子ＡＮＴと受信用フィルタ部32との間には、位相を回転させるための位相整合用ストリップラインSLが介在し、送信用フィルタ部31と受信用フィルタ部32の間の位相の整合を図っている。   Further, a phase matching stripline SL for rotating the phase is interposed between the antenna terminal ANT and the reception filter unit 32, and the phase matching between the transmission filter unit 31 and the reception filter unit 32 is performed. I am trying.

図１に本発明に係るアンテナ共用器１の断面図を示す。セラミック・パッケージ２は５つのセラミック層L1、L2、L3、L4、L5を積層したものである。第１、第２、第３のセラミック層L1、L2、L3によりパッケージ基部2Aが構成され、第４、第５のセラミック層L4、L5によりパッケージ枠部2Bが構成されている。   FIG. 1 shows a cross-sectional view of an antenna duplexer 1 according to the present invention. The ceramic package 2 is a laminate of five ceramic layers L1, L2, L3, L4, and L5. The first, second, and third ceramic layers L1, L2, and L3 constitute a package base 2A, and the fourth and fifth ceramic layers L4 and L5 constitute a package frame 2B.

セラミック・パッケージ２の底面、即ち、第１のセラミック層L1の一方の表面には、前記アンテナ端子ＡＮＴ、送信側信号端子Ｔｘ、受信側信号端子Ｒｘ、ＧＮＤ端子等の外部電極21が形成されている。該外部電極21は、アンテナ共用器１が実装されるべきマザー回路基板の所定のランドと半田等により接合される。   On the bottom surface of the ceramic package 2, that is, one surface of the first ceramic layer L1, external electrodes 21 such as the antenna terminal ANT, the transmission side signal terminal Tx, the reception side signal terminal Rx, and the GND terminal are formed. Yes. The external electrode 21 is joined to a predetermined land of the mother circuit board on which the antenna duplexer 1 is to be mounted by solder or the like.

パッケージ基部2AにはストリップラインSLが具備されており、第３のセラミック層L3の表面のうちキャビティCvの底面として露出している領域には複数の金パッド28が形成されている。又、送信用フィルタ部（図示せず）及び受信用フィルタ部（図示せず）を具備したSAWフィルタチップ３の外部電極（図示せず）には金バンプ33が設けられている。セラミック・パッケージ２の金パッド28とSAWフィルタチップ３の外部電極（図示せず）とを金バンプ33を介して接合することにより、ＳＡＷフィルタチップ３をセラミック・パッケージ２にフリップチップ実装している。   The package base 2A is provided with a strip line SL, and a plurality of gold pads 28 are formed in a region exposed as the bottom surface of the cavity Cv in the surface of the third ceramic layer L3. Further, gold bumps 33 are provided on the external electrodes (not shown) of the SAW filter chip 3 provided with a transmitting filter part (not shown) and a receiving filter part (not shown). The SAW filter chip 3 is flip-chip mounted on the ceramic package 2 by bonding the gold pad 28 of the ceramic package 2 and the external electrode (not shown) of the SAW filter chip 3 via the gold bump 33. .

パッケージ枠部2Bには略矩形状の窓部が設けられ、キャビティCvを形成している。又、セラミック・パッケージ２の天面、即ち第５のセラミック層L5の表面にはキャップ４を接合するための封止用電極27が形成されている。   The package frame portion 2B is provided with a substantially rectangular window portion to form a cavity Cv. Further, a sealing electrode 27 for joining the cap 4 is formed on the top surface of the ceramic package 2, that is, the surface of the fifth ceramic layer L5.

パッケージ基部2Bの側面には、横断面が半円状の側面電極用凹部をセラミック層の積層方向に設け、更に該側面電極用凹部に導電材層を被着してなる側面電極22が設けられており、対応する側面電極22、金パッド28、外部電極21は、配線パターン（図示せず）や導電材料が充填されたVIAホール（図示せず）を介して接続している。   The side surface of the package base 2B is provided with a side electrode recess having a semicircular cross section in the laminating direction of the ceramic layer, and further, a side electrode 22 formed by depositing a conductive material layer on the side electrode recess. The corresponding side electrode 22, gold pad 28, and external electrode 21 are connected via a VIA hole (not shown) filled with a wiring pattern (not shown) or a conductive material.

図１において、側面電極22、22はＧＮＤ電極である。第３のセラミック層L3の表面には第１の配線パターン23が設けられ、第４のセラミック層L4の表面には第２の配線パターン25が設けられている。又、第４のセラミック層L4にはVIAホール24が設けられている。   In FIG. 1, side electrodes 22 and 22 are GND electrodes. A first wiring pattern 23 is provided on the surface of the third ceramic layer L3, and a second wiring pattern 25 is provided on the surface of the fourth ceramic layer L4. A VIA hole 24 is provided in the fourth ceramic layer L4.

キャビティCvを構成する第５のセラミック層L5の４つの内壁には導電材が被着されてなるキャビティ内壁導電層26が設けられている。従って、外部電極21は、それぞれ導電材からなる側面電極22、第１の配線パターン23、スルーホール24、第２の配線パターン25、キャビティ内壁導電層26を介して封止用電極27と接続している。即ち、封止用電極27は側面電極22ではなくキャビティ内壁部のキャビティ内壁導電層26と直接接続されて接地していることとなる。   On the four inner walls of the fifth ceramic layer L5 constituting the cavity Cv, a cavity inner wall conductive layer 26 formed by applying a conductive material is provided. Accordingly, the external electrode 21 is connected to the sealing electrode 27 via the side electrode 22 made of a conductive material, the first wiring pattern 23, the through hole 24, the second wiring pattern 25, and the cavity inner wall conductive layer 26, respectively. ing. That is, the sealing electrode 27 is not directly connected to the side wall electrode 22 but to the cavity inner wall conductive layer 26 of the cavity inner wall, and is grounded.

又、封止用電極27にはＡｇ−Ｓｎ系合金の接合材（図示せず）等を介してキャップ４が固着され、キャビティCv内のSAWフィルタチップ３を気密封止している。尚、キャップ４は金属材、又は少なくとも封止用電極27との対抗面に金属層が被着されたセラミック材等からなり、その縦・横寸法は第５のセラミック層L5の縦・横寸法と略同じである。   The cap 4 is fixed to the sealing electrode 27 via an Ag—Sn alloy bonding material (not shown) or the like, and the SAW filter chip 3 in the cavity Cv is hermetically sealed. The cap 4 is made of a metal material, or at least a ceramic material having a metal layer deposited on the surface facing the sealing electrode 27, and the vertical and horizontal dimensions thereof are the vertical and horizontal dimensions of the fifth ceramic layer L5. Is almost the same.

図３（ａ）に第５のセラミック層L5の平面図を示す。又、同図（ｂ）に封止用電極27を取り除いた第５のセラミック層L5の平面図を示す。第５のセラミック層L5は窓部L5wを有する窓枠状をしており、窓部L5wを構成する４つの内壁にはキャビティ内壁導電層26（斜線部）が形成されている。   FIG. 3A shows a plan view of the fifth ceramic layer L5. FIG. 2B is a plan view of the fifth ceramic layer L5 from which the sealing electrode 27 is removed. The fifth ceramic layer L5 has a window frame shape having a window portion L5w, and cavity inner wall conductive layers 26 (shaded portions) are formed on four inner walls constituting the window portion L5w.

第５のセラミック層L5の外周部には側面電極が設けられていないので、図１１（ｃ）のものと比較して封止用電極27（斜線部）を大きくすることができる。更に、図１１（ａ）（ｂ）のものと異なり、側面電極やVIAホールを介して接地していないため側面電極やVIAホールによる凹凸が発生しない。従って、封止用電極27とキャップ4による気密封止性の低減を防止することができる。尚、キャビティ内壁導電層はその厚さが約２０μmと薄いため気密封止性に影響は及ぼさない。   Since the side electrode is not provided on the outer peripheral portion of the fifth ceramic layer L5, the sealing electrode 27 (shaded portion) can be made larger than that in FIG. Further, unlike those shown in FIGS. 11 (a) and 11 (b), there is no unevenness due to the side electrodes and VIA holes because they are not grounded via the side electrodes and VIA holes. Therefore, it is possible to prevent the hermetic sealing performance from being reduced by the sealing electrode 27 and the cap 4. The cavity inner wall conductive layer has a thin thickness of about 20 μm and does not affect the hermetic sealing performance.

本発明に係る第２の実施例のアンテナ共用器からキャップ及び封止用電極を取り除いたものの平面図を図４に示す。又、線E-O-Eに沿って切断した断面図（キャップ及び封止用電極を取り除かず）を図５に示す。アンテナ共用器１は、実施例１と異なりセラミック・パッケージ２にSAWフィルタチップ３をフリップチップ実装ではなく、ワイヤボンディング実装している。以下に構成を具体的に説明するが、実施例１と同じ部分・部品については実施例１と同じ参照番号を付し、説明は省略する。   FIG. 4 shows a plan view of the antenna duplexer of the second embodiment according to the present invention from which the cap and the sealing electrode are removed. FIG. 5 shows a cross-sectional view taken along line E-O-E (without removing the cap and the sealing electrode). The antenna duplexer 1 is different from the first embodiment in that the SAW filter chip 3 is mounted on the ceramic package 2 by wire bonding instead of flip chip mounting. Although the configuration will be specifically described below, the same parts and parts as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and the description thereof is omitted.

第４のセラミック層L4の表面はキャビティCvに露出している２つの露出面28を有している。前記２つの露出面28上には複数のワイヤボンディング用パッド29が設けられ、該ワイヤボンディング用パッド29とSAWフィルタチップ３の接続電極（図示せず）とがボンディングワイヤ５を介して接続されている。   The surface of the fourth ceramic layer L4 has two exposed surfaces 28 exposed to the cavity Cv. A plurality of wire bonding pads 29 are provided on the two exposed surfaces 28, and the wire bonding pads 29 and the connection electrodes (not shown) of the SAW filter chip 3 are connected via the bonding wires 5. Yes.

第５のセラミック層L5の内壁のうち露出面28に沿う内壁2C2、2C2にはキャビティ内壁導電層26は設けられておらず、露出面28に沿っていない内壁2C1、2C1にのみキャビティ内壁導電層26は設けられている。これは、内壁2C2にキャビティ内壁導電層26を設けると、ワイヤボンディング用パッド29と接続してしまいショート不良が発生するからである。実施例２では２つの内壁2C1のみで封止用電極27を接地していることとなるが電気的性能には何ら問題はない。   Of the inner walls of the fifth ceramic layer L5, the inner walls 2C2 and 2C2 along the exposed surface 28 are not provided with the cavity inner wall conductive layer 26, and only the inner walls 2C1 and 2C1 not along the exposed surface 28 have the cavity inner wall conductive layer. 26 is provided. This is because if the cavity inner wall conductive layer 26 is provided on the inner wall 2C2, it is connected to the wire bonding pad 29 and a short circuit defect occurs. In the second embodiment, the sealing electrode 27 is grounded only by the two inner walls 2C1, but there is no problem in electrical performance.

尚、実施例２の構成のキャビティ内壁導電層26を形成する方法としては、例えば図６に示すように第５のセラミック層となるべきグリーンシートの内壁にキャビティ内壁導電層となるべき導電体を塗布すれば良い。   As a method of forming the cavity inner wall conductive layer 26 having the configuration of Example 2, for example, as shown in FIG. 6, a conductor to be the cavity inner wall conductive layer is formed on the inner wall of the green sheet to be the fifth ceramic layer. What is necessary is just to apply.

まず、図６（ａ）に示すように第５のセラミック層L５となるべきグリーンシートGSを準備し、略矩形状の貫通穴GH1を開設する。次いで同図（ｂ）に示すように前記貫通穴GH1の４つの内壁全面に導電材をスルーホール印刷により塗布して貫通穴内壁導電層GCを形成する。尚、スクリーン印刷により貫通穴内壁導電層GCとグリーンシートGS表面への配線パターン等を同時に塗布しても構わない。次に、同図（ｃ）に示すように穿孔装置を用いて斜線部で示す領域を打ち抜くと、同図（ｄ）に示すように貫通穴内壁導電層GCは分断されて２つの貫通穴内壁導電層GC1、GC1が形成される。該貫通穴内壁導電層GC1、GC1はその後の周知の工程を完了するとキャビティ内壁導電層26となる。   First, as shown in FIG. 6A, a green sheet GS to be the fifth ceramic layer L5 is prepared, and a substantially rectangular through hole GH1 is opened. Next, as shown in FIG. 2B, a conductive material is applied to the entire inner surfaces of the four inner walls of the through hole GH1 by through hole printing to form the through hole inner wall conductive layer GC. The through hole inner wall conductive layer GC and the wiring pattern on the green sheet GS surface may be applied simultaneously by screen printing. Next, when a region indicated by hatching is punched out using a perforating apparatus as shown in FIG. 4C, the through hole inner wall conductive layer GC is divided as shown in FIG. Conductive layers GC1 and GC1 are formed. The through-hole inner wall conductive layers GC1 and GC1 become the cavity inner wall conductive layer 26 when the subsequent well-known steps are completed.

本発明は上述の実施例に限定されるものではなく、その要旨を変更しない範囲において適宜変更して実施することが可能である。   The present invention is not limited to the above-described embodiments, and can be implemented with appropriate modifications without departing from the scope of the invention.

例えば、実施例１ではキャビティ内壁のうち上半部、即ち第５のセラミック層L5のみにキャビティ内壁導電層を設けたが、これに限定されない。第３のセラミック層L3上に形成された入出力電極とのショートの虞がなければ、キャビティ内壁の上半部及び下半部、即ち第４及び第５のセラミック層L4、L5にキャビティ内壁導電層を設けても良い。封止用電極が設けられたセラミック層のキャビティ内壁部のうちの少なくとも一部にキャビティ内壁導電層が設けられていれば本発明の効果を得ることができる。   For example, in Example 1, the cavity inner wall conductive layer is provided only in the upper half of the cavity inner wall, that is, the fifth ceramic layer L5. However, the present invention is not limited to this. If there is no risk of short-circuiting with the input / output electrode formed on the third ceramic layer L3, the cavity inner wall is electrically connected to the upper and lower halves of the cavity inner wall, that is, the fourth and fifth ceramic layers L4 and L5. A layer may be provided. If the cavity inner wall conductive layer is provided on at least a part of the cavity inner wall of the ceramic layer provided with the sealing electrode, the effect of the present invention can be obtained.

キャップは平板型に限定されず、有底筒型のものでも良い。   The cap is not limited to a flat plate type, and may be a bottomed cylindrical type.

又、ダイサー、押し切りカッター等により個々に分断されることにより前記セラミック・パッケージは完成するが、分断されずに複数の本発明によるセラミック・パッケージが互いの側面の一部又は全部を介してマトリックス状に連結している集合基板も本発明の技術的範囲に含まれる。   Further, the ceramic package is completed by being individually divided by a dicer, a push cutter, or the like, but a plurality of ceramic packages according to the present invention are formed in a matrix form through part or all of the side surfaces of each other without being divided. The collective substrate connected to is also included in the technical scope of the present invention.

実施例及び従来例としてアンテナ共用器を説明したが、アンテナ共用器に限定されない。電子回路部品としてSAWフィルタチップ以外のものを搭載した他の電子デバイスにも広く適用することができる。   Although the antenna duplexer has been described as an example and a conventional example, it is not limited to the antenna duplexer. The present invention can be widely applied to other electronic devices having electronic circuit components other than SAW filter chips.

本発明の実施例１に係るアンテナ共用器の断面図である。It is sectional drawing of the antenna sharing device which concerns on Example 1 of this invention. 本発明の実施例１に係るアンテナ共用器の概略分解斜視図である。It is a general | schematic disassembled perspective view of the antenna sharing device which concerns on Example 1 of this invention. 本発明の実施例１に係るセラミック・パッケージの第５のセラミック層を説明する図である。It is a figure explaining the 5th ceramic layer of the ceramic package which concerns on Example 1 of this invention. 本発明の実施例２に係るアンテナ共用器からキャップ及び封止用電極を取り除いたものの平面図である。It is a top view of what removed the cap and the electrode for sealing from the antenna sharing device which concerns on Example 2 of this invention. 本発明の実施例２に係るアンテナ共用器の断面図である。It is sectional drawing of the antenna sharing device which concerns on Example 2 of this invention. 本発明の実施例２に係るキャビティ内壁導電層の部分工程図である。It is a partial process figure of the cavity inner wall conductive layer which concerns on Example 2 of this invention. 実施例及び従来のアンテナ共用器のブロック図である。It is a block diagram of an Example and the conventional antenna sharing device. 従来のアンテナ共用器の概略分解斜視図である。It is a schematic exploded perspective view of the conventional antenna sharing device. 従来のアンテナ共用器の断面図である。It is sectional drawing of the conventional antenna sharing device. 従来の手法２によるアンテナ共用器の断面図である。It is sectional drawing of the antenna sharing device by the conventional method 2. FIG. 従来の手法１乃至３による第５のセラミック層を説明する図である。It is a figure explaining the 5th ceramic layer by the conventional methods 1 thru | or 3.

符号の説明Explanation of symbols

１ アンテナ共用器
２ セラミック・パッケージ
２Ａ パッケージ基部
２Ｂ パッケージ枠部
２１ 外部電極
２２ 側面電極
２３ 第１の配線パターン
２４ スルーホール
２５ 第２の配線パターン
２６ キャビティ内壁導電層
２７ 封止用電極
３ ＳＡＷフィルタチップ
４ キャップ
Ｃｖ キャビティ DESCRIPTION OF SYMBOLS 1 Antenna sharing device 2 Ceramic package 2A Package base 2B Package frame part 21 External electrode 22 Side electrode 23 First wiring pattern 24 Through hole 25 Second wiring pattern 26 Cavity inner wall conductive layer 27 Sealing electrode 3 SAW filter chip 4 Cap Cv Cavity

Claims (4)

複数のセラミック層を積層してなると共に、電子回路部品を収容するためのキャビティを有するセラミック・パッケージであって、
いずれかのセラミック層の表面には、キャップを固着することにより前記電子回路部品を気密封止することができる封止用電極が導電材により形成され、前記封止用電極が形成されたセラミック層のキャビティ内壁の少なくとも一部には導電材からなるキャビティ内壁導電層が形成され、前記封止用電極は前記キャビティ内壁導電層を介して接地されていることを特徴とするセラミック・パッケージ。 A ceramic package having a plurality of ceramic layers laminated and having a cavity for accommodating an electronic circuit component,
On the surface of any ceramic layer, a sealing electrode capable of hermetically sealing the electronic circuit component by fixing a cap is formed of a conductive material, and the ceramic layer on which the sealing electrode is formed A ceramic package, wherein a cavity inner wall conductive layer made of a conductive material is formed on at least a part of the cavity inner wall, and the sealing electrode is grounded via the cavity inner wall conductive layer. キャビティ内壁を構成するすべてのセラミック層は、それぞれのキャビティ内壁部の少なくとも一部に導電材からなるキャビティ内壁導電層が形成されていることを特徴とする請求項１に記載のセラミック・パッケージ。   2. The ceramic package according to claim 1, wherein all of the ceramic layers constituting the cavity inner wall are formed with a cavity inner wall conductive layer made of a conductive material on at least a part of each cavity inner wall portion. 請求項１乃至２に記載の複数のセラミック・パッケージが互いの側面の一部又は全部を介してマトリックス状に連結していることを特徴とする集合基板。   3. A collective substrate, wherein the plurality of ceramic packages according to claim 1 are connected in a matrix form through part or all of the side surfaces of each other. 請求項１又は２に記載のセラミック・パッケージのキャビティ内に１つ又は複数の電子回路部品を収容し、前記セラミック・パッケージの封止用電極にキャップを固着して前記電子回路部品を気密封止したことを特徴とする電子デバイス。
3. One or more electronic circuit components are accommodated in the cavity of the ceramic package according to claim 1 or 2, and a cap is fixed to the sealing electrode of the ceramic package to hermetically seal the electronic circuit component. An electronic device characterized by that.
JP2005348574A 2005-12-02 2005-12-02 Ceramic/package, aggregate substrate, and electronic device Pending JP2007157859A (en)

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KR20160123938A (en) * 2015-04-17 2016-10-26 삼성전기주식회사 Electronic component package and method of manufacturing the same
KR20170107318A (en) * 2016-03-15 2017-09-25 삼성전기주식회사 Electronic component package and manufacturing method for the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160123938A (en) * 2015-04-17 2016-10-26 삼성전기주식회사 Electronic component package and method of manufacturing the same
KR102065943B1 (en) * 2015-04-17 2020-01-14 삼성전자주식회사 Fan-out semiconductor package and method of manufacturing the same
KR20170107318A (en) * 2016-03-15 2017-09-25 삼성전기주식회사 Electronic component package and manufacturing method for the same
US10388614B2 (en) 2016-03-15 2019-08-20 Samsung Electronics Co., Ltd. Fan-out semiconductor package and method of manufacturing same
KR102015335B1 (en) * 2016-03-15 2019-08-28 삼성전자주식회사 Electronic component package and manufacturing method for the same

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