JP2007157805A - Led package, method of manufacturing light-emitting device and led package - Google Patents

Led package, method of manufacturing light-emitting device and led package Download PDF

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JP2007157805A
JP2007157805A JP2005347443A JP2005347443A JP2007157805A JP 2007157805 A JP2007157805 A JP 2007157805A JP 2005347443 A JP2005347443 A JP 2005347443A JP 2005347443 A JP2005347443 A JP 2005347443A JP 2007157805 A JP2007157805 A JP 2007157805A
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horn
led package
silicon substrate
oxide film
led
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Yoshiaki Yasuda
喜昭 安田
Yoshio Sato
喜郎 佐藤
Yoshihiro Nakamura
吉博 中村
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Stanley Electric Co Ltd
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Stanley Electric Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture an LED package having light distribution characteristics without any dark lines originating from a ridgeline formed by a (111) plane of a sloped side of a horn. <P>SOLUTION: Anisotropic etching depending on orientation is performed to a silicon substrate whose surface is a (100) plane, thus forming the horn with the (100) plane as a bottom surface and four (111) planes as sloped sides. Irregularities are formed on the sloped sides of the formed horn. An LED chip is packaged on the bottom surface of the horn. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、LEDパッケージ、発光装置及びLEDパッケージの製造方法に関し、特にシリコン基板に形成されたホーンにLEDチップを実装するLEDパッケージ、発光装置及びLEDパッケージの製造方法に関する。   The present invention relates to an LED package, a light emitting device, and an LED package manufacturing method, and more particularly to an LED package in which an LED chip is mounted on a horn formed on a silicon substrate, a light emitting device, and an LED package manufacturing method.

近年、LEDパッケージとして、例えば下記の特許文献1に開示の構成を有するものが知られている。特許文献1では、シリコン基板を異方性エッチングして(100)底面と(111)傾斜側面とを有するホーンと呼ばれる窪みを形成し、ホーン底面に青色LEDチップを配置する。ホーン斜面には反射膜を形成し、外部光取り出し効率を向上させている。   In recent years, LED packages having a configuration disclosed in, for example, Patent Document 1 below are known. In Patent Document 1, a silicon substrate is anisotropically etched to form a depression called a horn having a (100) bottom surface and a (111) inclined side surface, and a blue LED chip is disposed on the horn bottom surface. A reflective film is formed on the horn slope to improve external light extraction efficiency.

特開2004−356213号公報JP 2004-356213 A

特許文献1によるLEDパッケージでは、ホーン斜面の面と面との境界に稜線が存在し、発光の際、稜線の影が生じるという問題があった。   In the LED package according to Patent Document 1, there is a ridge line at the boundary between the surfaces of the horn slope, and there is a problem that a shadow of the ridge line is generated during light emission.

本発明の目的は、稜線の影を無くし、配光特性を向上させたLEDパッケージ及びLEDパッケージ製造方法を提供することである。   The objective of this invention is providing the LED package which eliminated the shadow of the ridgeline, and improved the light distribution characteristic, and an LED package manufacturing method.

本発明の一観点によれば、表面が(100)面のシリコン基板に対して面方位に依存する異方性エッチングを施して、(100)面を底面とし、4つの(111)面を傾斜側面とするホーンを形成する工程と、前記ホーンの傾斜側面に凹凸を形成する工程と、前記ホーン底面上にLEDチップを実装する工程とを含むLEDパッケージの製造方法が提供される。   According to one aspect of the present invention, a silicon substrate having a (100) plane surface is subjected to anisotropic etching depending on the plane orientation, and the (100) plane is a bottom surface and four (111) planes are inclined. There is provided an LED package manufacturing method including a step of forming a horn as a side surface, a step of forming irregularities on an inclined side surface of the horn, and a step of mounting an LED chip on the bottom surface of the horn.

本発明の他の観点によれば、異方性エッチングにより、(100)面の底面と、4つの(111)面の傾斜側面からなるホーンを形成し、さらに4つの(111)面に凹凸を形成したシリコン基板と、前記ホーン底面上に実装されたLEDチップとを含むLEDパッケージが提供される。   According to another aspect of the present invention, a horn composed of a bottom surface of the (100) plane and four inclined sides of the (111) plane is formed by anisotropic etching, and irregularities are formed on the four (111) planes. An LED package including the formed silicon substrate and an LED chip mounted on the bottom surface of the horn is provided.

ホーン内に実装されたLEDチップに外部電源から電圧が印加され、LEDが発光し、ホーン外部に光が取り出される。従来はホーンの傾斜側面の面と面の境界に存在する稜線由来のダークラインが見られたが、本願の発明ではホーンの傾斜側面を凹凸のある拡散反射面とすることにより稜線由来のダークラインのない発光を得ることができる。   A voltage is applied from an external power source to the LED chip mounted in the horn, the LED emits light, and light is extracted outside the horn. Conventionally, a dark line derived from a ridge line existing at the boundary between the surfaces of the inclined side surface of the horn was seen. Luminescence without light can be obtained.

図1、図2を参照して、本願の実施例によるLEDパッケージの製造方法について説明する。   With reference to FIG. 1 and FIG. 2, the manufacturing method of the LED package by the Example of this application is demonstrated.

図1に、LEDパッケージの製造工程の一部を示す。LEDチップを実装するための基体として、厚さ525μmの単結晶シリコン基板11を用いる。単結晶シリコン基板11の表面は光学研磨処理によって平坦化されている。   FIG. 1 shows a part of the manufacturing process of the LED package. A single crystal silicon substrate 11 having a thickness of 525 μm is used as a base for mounting the LED chip. The surface of the single crystal silicon substrate 11 is flattened by an optical polishing process.

まず、図1(A)に示すように、(100)面のシリコン基板11の表面に例えば拡散炉を用いた熱酸化により厚さ500nmの酸化シリコン膜21を形成する。   First, as shown in FIG. 1A, a silicon oxide film 21 having a thickness of 500 nm is formed on the surface of the (100) silicon substrate 11 by thermal oxidation using, for example, a diffusion furnace.

次に、図1(B)に示すように、フォトリソグラフィー技術によって酸化シリコン膜21上に[110]方向の辺を有する矩形のレジストパターン22を形成し、その後バッファードフッ酸(BHF)によって酸化シリコン膜21を部分的にエッチング除去し、開口Hが設けられた酸化シリコン膜のパターン21aを形成する。   Next, as shown in FIG. 1B, a rectangular resist pattern 22 having sides in the [110] direction is formed on the silicon oxide film 21 by photolithography, and then oxidized by buffered hydrofluoric acid (BHF). The silicon film 21 is partially etched away to form a silicon oxide film pattern 21a provided with openings H.

その後、図1(C−1)に示すように、レジストパターン22を除去し、酸化シリコン膜パターン21aをマスクにして、シリコン基板11に対して例えば25%水酸化テトラメチルアンモニウム(以下TMAH)溶液により異方性エッチングを施す。本実施例ではシリコン基板11の表面は(100)面であり、異方性エッチングを施すことにより、シリコン基板11中にホーン11aが形成される。ホーン11aは、垂直断面が台形で、水平断面が四角形となる。すなわち、(100)面である底面と、4つの(111)面である傾斜側面からなる。(111)面である傾斜側面は、(100)面である底面に対して54.7°の傾斜角を取ることになる。   Thereafter, as shown in FIG. 1C-1, the resist pattern 22 is removed, and a 25% tetramethylammonium hydroxide (hereinafter, TMAH) solution is applied to the silicon substrate 11 using the silicon oxide film pattern 21 a as a mask. To perform anisotropic etching. In this embodiment, the surface of the silicon substrate 11 is a (100) plane, and a horn 11a is formed in the silicon substrate 11 by performing anisotropic etching. The horn 11a has a trapezoidal vertical cross section and a quadrangular horizontal cross section. That is, it consists of a bottom surface that is the (100) plane and four inclined side surfaces that are the (111) plane. The inclined side surface that is the (111) plane has an inclination angle of 54.7 ° with respect to the bottom surface that is the (100) plane.

この時点で、ホーン11aには、図1(C−2)の平面図に示すように、4つの傾斜側面の面と面の境界において稜線が存在する。   At this time, as shown in the plan view of FIG. 1C-2, the horn 11a has ridge lines at the boundaries between the four inclined side surfaces.

次に、図1(D)に示すように、一旦酸化シリコン膜21及び酸化シリコン膜パターン21aを除去し、再び熱酸化によりシリコン基板11の表面全体に酸化シリコン膜23を形成する。   Next, as shown in FIG. 1D, the silicon oxide film 21 and the silicon oxide film pattern 21a are once removed, and a silicon oxide film 23 is formed on the entire surface of the silicon substrate 11 by thermal oxidation again.

その後、図1(E)に示すように、(100)面にレジストパターン24を形成する。レジストパターン24の形成は、まず、ホーンのように段差が数百μmある立体形状においても、通常のフォトリソグラフィプロセスとほぼ同様の均一な厚みのレジストを塗布できるレジストスプレーコーティングによって一旦酸化シリコン膜23の上全体にレジストを塗布する。そして、マスクアライナにてパターン露光し、現像処理によってホーン傾斜側面のレジストを除去することによって形成される。   Thereafter, as shown in FIG. 1E, a resist pattern 24 is formed on the (100) plane. First, the resist pattern 24 is formed once by a resist spray coating that can apply a resist having a uniform thickness almost the same as that of a normal photolithography process even in a three-dimensional shape having a step of several hundred μm like a horn. Apply resist over the entire surface. Then, pattern exposure is performed with a mask aligner, and the resist on the horn inclined side surface is removed by development processing.

次に、バッファードフッ酸(以下BHF)溶液を用いて上にレジストパターン24が形成されてない部分の酸化シリコン膜23bを除去する。そして、レジストパターン24をリムーバー液により除去すると、図1(F)に示すように、シリコン基板11の(100)面に、酸化シリコン膜23aのハードマスクが残る。なお、この後行う異方性エッチングのオーバエッチを考慮して底面近傍の傾斜側面に酸化シリコン膜を残しておく。   Next, a portion of the silicon oxide film 23b where the resist pattern 24 is not formed is removed using a buffered hydrofluoric acid (hereinafter referred to as BHF) solution. Then, when the resist pattern 24 is removed by the remover liquid, the hard mask of the silicon oxide film 23a remains on the (100) surface of the silicon substrate 11 as shown in FIG. Note that the silicon oxide film is left on the inclined side surface in the vicinity of the bottom surface in consideration of the overetching of the anisotropic etching performed thereafter.

次に、ホーン11aの傾斜側面に対して加工を施し、傾斜側面を凹凸のある拡散反射面にする工程を行う。この工程には2通りの方法があるので、ここで順に説明する。   Next, a process is performed on the inclined side surface of the horn 11a to make the inclined side surface an uneven diffuse reflection surface. There are two methods for this process, which will be described in order here.

第1の方法として、酸化シリコン膜23aをハードマスクとして、ホーン11aの形成で行った異方性エッチングとは条件の異なる、例えばエッチャントに5%TMAH溶液を用いる等した異方性エッチングを行う方法がある。この方法により、図1(G−1)に示すように傾斜側面がディンプル形状からなる凹凸面となるホーン11bが形成される。ここで、ディンプルとは滑らかな曲線で構成された凹凸の集まりのことである。凹凸面の表面粗さはエッチング条件によって調整可能であり、通常0.1〜1μmに設定される。形成された凹凸により、ホーン11bの傾斜側面は拡散反射面となる。   As a first method, anisotropic etching using, for example, a 5% TMAH solution as an etchant is performed under different conditions from the anisotropic etching performed by forming the horn 11a using the silicon oxide film 23a as a hard mask. There is. By this method, as shown in FIG. 1 (G-1), the horn 11b having an inclined side surface that is an uneven surface having a dimple shape is formed. Here, the dimple is a group of irregularities formed by a smooth curve. The surface roughness of the concavo-convex surface can be adjusted by etching conditions, and is usually set to 0.1 to 1 μm. Due to the formed irregularities, the inclined side surface of the horn 11b becomes a diffuse reflection surface.

第2の方法として、(100)面を酸化シリコン膜23aの上にさらにパターニングした厚膜レジストで保護した状態で、サンドブラストやドライアイスブラスト等のブラスト加工を施す方法がある。この方法により、ホーン傾斜側面に荒れた凹凸を形成する。荒れた凹凸は、第1の方法で形成されるディンプル形状の凹凸面と比べると表面の荒れ方が違うが、効果としては同様の拡散反射面となる。   As a second method, there is a method of performing blasting such as sand blasting or dry ice blasting in a state where the (100) surface is protected by a thick film resist further patterned on the silicon oxide film 23a. By this method, rough irregularities are formed on the inclined side surface of the horn. The rough uneven surface is different in surface roughness from the dimple-shaped uneven surface formed by the first method, but the effect is the same diffuse reflection surface.

上記のような方法で形成されたホーン11bに、LEDチップを実装する。その工程を図2に示す。図2(A)に示すように、一旦、全ての酸化シリコン膜(上記第2の方法の場合は厚膜レジストを含む)を除去した後、再び熱酸化によりシリコン基板11の表面に酸化シリコン膜24を形成する。   An LED chip is mounted on the horn 11b formed by the above method. The process is shown in FIG. As shown in FIG. 2A, after all the silicon oxide film (including the thick film resist in the case of the second method) is once removed, the silicon oxide film is again formed on the surface of the silicon substrate 11 by thermal oxidation. 24 is formed.

次に、図2(B)に示すように、シリコン基板11の表面上の酸化シリコン膜24の上に、スパッタ法等の成膜法よってTi、Cu、Ni、Pt等かならなるバリア層25を成膜する。   Next, as shown in FIG. 2B, a barrier layer 25 made of Ti, Cu, Ni, Pt or the like is formed on the silicon oxide film 24 on the surface of the silicon substrate 11 by a film forming method such as sputtering. Is deposited.

続いて、バリア層25の上に、Ag、Au、Al等の反射膜を成膜する。さらに、ストライプ状のスリットを有するレジストパターン27を反射膜の上に成膜する。このレジストパターン27をマスクとして金属層であるバリア層25と反射膜の選択エッチングを行うことにより、図2(C)に示すように、パターニングされたバリア層25a、25b及び反射膜兼電極26a、26bが形成される。   Subsequently, a reflective film such as Ag, Au, or Al is formed on the barrier layer 25. Further, a resist pattern 27 having stripe-shaped slits is formed on the reflective film. By performing selective etching of the barrier layer 25, which is a metal layer, and the reflective film using the resist pattern 27 as a mask, as shown in FIG. 2C, the patterned barrier layers 25a and 25b and the reflective film / electrode 26a are formed. 26b is formed.

なお、パターンニングの手法として、酸化シリコン膜24の上に、レジストパターンを形成しておき、その上にバリア層、反射膜を成膜し、最後にレジストの上に積層されたバリア層、反射膜をレジストパターン共に除去してバリア層、反射膜のパターンニングを行う「リフトオフ」という手法を用いてもよい。   As a patterning method, a resist pattern is formed on the silicon oxide film 24, a barrier layer and a reflective film are formed thereon, and finally a barrier layer and a reflective layer laminated on the resist are formed. A technique called “lift-off” may be used in which the film is removed together with the resist pattern and the barrier layer and the reflective film are patterned.

次に、図2(D)に示すように、ホーンの底面上に画定された反射膜兼電極26aのチップ実装部26cに、LEDチップ31の下部電極をダイボンドする。LEDチップ31は、赤(R)、緑(G)又は青(B)の発光色を有する単色LEDである。例えば、赤色の場合、半導体層にアルミガリウム砒素(AlGaAs)を用いる。緑色の場合はガリウムリン(GaP)、青色の場合はガリウムナイトライド(GaN)等が用いられる。その構成は、赤色の場合、例えば、図3に示すように、ガリウム砒素(GaAs)基板31bに半導体層31c(p型半導体層31d、発光層31e、n型半導体層31fの順に積層)を積層し、最下部と最上部に金属電極31a、31gを設けている。緑色の場合は、例えば基板にGaP等を用い、赤色の場合と同じように、GaP基板の上に半導体層を積層し、最下部と最上部に金属電極を設ける。青色の場合は、例えば特願2005−167319号公報中の図1および段落[0017]〜[0023]に記載の構成からなっている。そのような構成のLEDチップ31の下部電極をダイボンディングすると、Au−Sn共晶結合により、反射膜兼電極26aとLEDチップ31は電気的機械的に接合される。   Next, as shown in FIG. 2D, the lower electrode of the LED chip 31 is die-bonded to the chip mounting portion 26c of the reflective film / electrode 26a defined on the bottom surface of the horn. The LED chip 31 is a single color LED having an emission color of red (R), green (G), or blue (B). For example, in the case of red, aluminum gallium arsenide (AlGaAs) is used for the semiconductor layer. Gallium phosphorus (GaP) is used for green, and gallium nitride (GaN) is used for blue. In the case of red, for example, as shown in FIG. 3, a semiconductor layer 31c (a p-type semiconductor layer 31d, a light-emitting layer 31e, and an n-type semiconductor layer 31f are stacked in this order) is stacked on a gallium arsenide (GaAs) substrate 31b. The metal electrodes 31a and 31g are provided at the bottom and top. In the case of green, for example, GaP or the like is used for the substrate, and as in the case of red, a semiconductor layer is stacked on the GaP substrate, and metal electrodes are provided at the bottom and top. In the case of blue, for example, it has the structure described in FIG. 1 and paragraphs [0017] to [0023] in Japanese Patent Application No. 2005-167319. When the lower electrode of the LED chip 31 having such a configuration is die-bonded, the reflective film cum electrode 26a and the LED chip 31 are electrically and mechanically bonded by Au—Sn eutectic bonding.

さらに、LEDチップ31の上部電極と反射膜兼電極26bの接続部26dとをAu等のボンディングワイヤ31wでワイヤボンディングして電気的に接合する。反射膜兼電極26a、26bはホーン11b底部から傾斜側面を介してシリコン基板11表面まで延びている。   Further, the upper electrode of the LED chip 31 and the connecting portion 26d of the reflective film / electrode 26b are wire-bonded by a bonding wire 31w such as Au and are electrically joined. The reflective film and electrodes 26a and 26b extend from the bottom of the horn 11b to the surface of the silicon substrate 11 via the inclined side surface.

次に、図2(E−1)に示すように、ホーン11b内部を透明樹脂40でモールドする。こうして、LEDパッケージが完成する。上から見ると図2(E−2)のようになる。また、樹脂が硬化する前に、予め用意したホーン開口部を内包する大きさの光学レンズをホーン上部に配置することにより、光学レンズつきのLEDパッケージを作成することもできる。   Next, as shown in FIG. 2E-1, the inside of the horn 11 b is molded with a transparent resin 40. Thus, the LED package is completed. When viewed from above, it is as shown in FIG. Moreover, an LED package with an optical lens can also be created by placing an optical lens of a size that encloses a horn opening prepared in advance on the top of the horn before the resin is cured.

完成したLEDパッケージに給電して発せられる光の配光パターンを評価すると、ホーン11bの傾斜側面が拡散反射面になっているので、稜線に由来するダークラインは観測されず、配光特性が従来よりも均一に近付く。   When evaluating the light distribution pattern of the light emitted by feeding the completed LED package, since the inclined side surface of the horn 11b is a diffuse reflection surface, the dark line derived from the ridge line is not observed, and the light distribution characteristic is conventional. More uniform.

また、拡散反射面を形成する際、ホーン底面に酸化シリコン膜23aや厚膜レジストなどの保護膜を設けて底面を保護することによって底面の凹凸の差が±10nm以下のフラットな状態に保持し、Au−Sn共晶結合を十分な接合強度で実施することができる。保護膜がない場合、底面の凹凸の差は±数μm以上になり、Au−Sn共晶結合の信頼性が著しく低下する。   In addition, when forming the diffuse reflection surface, a protective film such as a silicon oxide film 23a or a thick film resist is provided on the bottom surface of the horn to protect the bottom surface, thereby maintaining a flat state in which the difference in unevenness on the bottom surface is ± 10 nm or less. , Au—Sn eutectic bonding can be performed with sufficient bonding strength. When there is no protective film, the difference in the irregularities on the bottom surface becomes ± several μm or more, and the reliability of the Au—Sn eutectic bond is remarkably lowered.

図4、図5を参照して、LEDパッケージの他の構成例について説明する。   With reference to FIGS. 4 and 5, another configuration example of the LED package will be described.

上記の実施例において、RGB3種の発光色を持ったLEDチップを実装するLEDパッケージの形態がある。ホーンを上記の実施例と同様に形成し、反射膜兼電極を3つのLEDチップが実装されるようにパターニングする形態である。   In the above-described embodiment, there is a form of an LED package on which LED chips having three types of RGB emission colors are mounted. The horn is formed in the same manner as in the above embodiment, and the reflective film and electrode are patterned so that three LED chips are mounted.

3種のLEDチップ32a、32b、32cの配列方法として、図4(A)に示すように、反射膜兼電極を27a〜27dのように4つに分割し、27a、27b、27cの底部にLEDチップ32a、32b、32cを一つずつマウントし、直列接続となるように実装する方法がある。すなわち、LEDチップ32a、32b、32cの下部電極を反射膜兼電極27a、27b、27cの底部にそれぞれダイボンディングし、電気的機械的に接合する。次に、LEDチップ32a、32b、32cの上部電極を反射膜兼電極27b、27c、27dの底部にそれぞれワイヤボンディングして電気的に接続する。反射膜兼電極27aと27dを外部電源に接続し、LEDチップ32a、32b、32cに順バイアスが印加されるように回路を形成する。第1または第2の実施例と同様に、LEDチップが実装されたホーンに樹脂をモールドしてLEDパッケージが完成する。   As an arrangement method of the three types of LED chips 32a, 32b, 32c, as shown in FIG. 4 (A), the reflective film / electrode is divided into four as 27a-27d, and the bottom of 27a, 27b, 27c is formed. There is a method of mounting the LED chips 32a, 32b, and 32c one by one and mounting them in series. That is, the lower electrodes of the LED chips 32a, 32b, and 32c are die-bonded to the bottoms of the reflective film and electrodes 27a, 27b, and 27c, respectively, and are electrically and mechanically bonded. Next, the upper electrodes of the LED chips 32a, 32b, and 32c are electrically connected by wire bonding to the bottoms of the reflective film and electrodes 27b, 27c, and 27d, respectively. The reflective film and electrodes 27a and 27d are connected to an external power source, and a circuit is formed so that a forward bias is applied to the LED chips 32a, 32b, and 32c. Similar to the first or second embodiment, a resin is molded into a horn on which an LED chip is mounted to complete an LED package.

3つのLEDチップ32a、32b、32cに同時に給電することにより、RGB発光の混色としての白色発光が得られる。波長変換材料による吸収や散乱のロスが少ない、高外部光取り出し効率の白色LED発光装置を供給することができる。   By simultaneously supplying power to the three LED chips 32a, 32b, and 32c, white light emission as a mixed color of RGB light emission can be obtained. It is possible to supply a white LED light-emitting device with high external light extraction efficiency with little loss of absorption and scattering due to the wavelength conversion material.

3種のLEDチップの他の配列方法として、図4(B)に示すように、4つに分割した反射膜兼電極28a〜28dのうち一つの反射膜兼電極28aをアースに接続した上で、ホーン底面上の反射膜兼電極28aにLEDチップ33a、33b、33cを3つ配置し、LEDチップ33a、33b、33cのそれぞれの底面にある電極と反射膜兼電極28aとをダイボンド等で機械的電気的に接続する。   As another arrangement method of the three types of LED chips, as shown in FIG. 4B, one of the reflective film / electrodes 28a to 28d divided into four is connected to the ground. Three LED chips 33a, 33b, 33c are arranged on the reflective film / electrode 28a on the bottom surface of the horn, and the electrodes on the bottom surfaces of the LED chips 33a, 33b, 33c and the reflective film / electrode 28a are machined by die bonding or the like. Connect electrically.

3つのLEDチップ33a、33b、33cのそれぞれの上部にある電極を反射膜兼電極28b、28c、28dにワイヤボンディングにより接続する。第1または第2の実施例と同様に、LEDチップが実装されたホーンに樹脂をモールドしてLEDパッケージが完成する。   The electrodes on the upper portions of the three LED chips 33a, 33b, and 33c are connected to the reflective film and electrodes 28b, 28c, and 28d by wire bonding. Similar to the first or second embodiment, a resin is molded into a horn on which an LED chip is mounted to complete an LED package.

反射膜兼電極28b、28c、28dにはそれぞれ、V、V、Vの電圧が印加されており、動作電圧の違う3つのLEDチップ33a、33b、33cに対してそれぞれに給電することができる。このようなLEDチップの実装形態でも、波長変換材料による吸収や散乱のロスが少ない、RGB発光の混色としての高外部光取り出し効率の白色発光が得られる。また、RGB各々に独立に電圧を印加できることから、これらのLEDの組み合わせによって種々の発光色の選択発光が可能である。 Voltages V 1 , V 2 , and V 3 are applied to the reflective film / electrodes 28b, 28c, and 28d, respectively, and power is supplied to the three LED chips 33a, 33b, and 33c having different operating voltages. Can do. Even in such LED chip mounting form, white light emission with high external light extraction efficiency as a mixed color of RGB light emission with little loss of absorption and scattering by the wavelength conversion material can be obtained. In addition, since voltage can be applied to each of RGB independently, selective emission of various emission colors is possible by combining these LEDs.

図5に、LEDチップの他の実装例を表した断面図を示す。先述の実施例と同様の構成の部分には同一の符号を付し、説明は省略する。サファイア等の絶縁性基板上にGaN系LEDを形成した場合等にはLEDチップの底面に一方の電極を形成することは容易ではない。そこで、図5(A)に示すように、シリコン基板11のホーン11bの底面上に、LEDチップ34をマウントする。LEDチップ34は、基板34a上に、n型半導体層34b、発光層34c、p型半導体層34dが順次積層されてなるGaN系半導体を構成要素に備え、さらにp型半導体層34d表面にp型電極34fを有すると共に、p型半導体層34d側からn型半導体層34bの一部が露出するように露出面が形成されており、該露出面にn型電極35eを有している。   FIG. 5 is a cross-sectional view showing another mounting example of the LED chip. The same components as those in the previous embodiment are denoted by the same reference numerals, and description thereof is omitted. When a GaN-based LED is formed on an insulating substrate such as sapphire, it is not easy to form one electrode on the bottom surface of the LED chip. Therefore, as shown in FIG. 5A, the LED chip 34 is mounted on the bottom surface of the horn 11b of the silicon substrate 11. The LED chip 34 includes a GaN-based semiconductor in which an n-type semiconductor layer 34b, a light-emitting layer 34c, and a p-type semiconductor layer 34d are sequentially stacked on a substrate 34a, and a p-type semiconductor layer 34d on the surface thereof. In addition to the electrode 34f, an exposed surface is formed so that a part of the n-type semiconductor layer 34b is exposed from the p-type semiconductor layer 34d side, and an n-type electrode 35e is provided on the exposed surface.

このLEDチップ34は、n型半導体層34bと酸化シリコン膜24で覆われたシリコン基板11との間に透光性基板34aが介在するようにシリコン基板11に固着されている。さらに、ホーン11bの傾斜側面からシリコン基板11の上面にかけて形成された反射膜兼電極26a、26bとp型電極34f、n型電極34eがそれぞれボンディングワイヤ34wによって電気的に接続されている。なお、ワイヤボンディングの箇所はホーン11bの傾斜側面であっても良い。   The LED chip 34 is fixed to the silicon substrate 11 so that the translucent substrate 34 a is interposed between the n-type semiconductor layer 34 b and the silicon substrate 11 covered with the silicon oxide film 24. Further, the reflective film and electrodes 26a, 26b, the p-type electrode 34f, and the n-type electrode 34e formed from the inclined side surface of the horn 11b to the upper surface of the silicon substrate 11 are electrically connected by bonding wires 34w. The wire bonding portion may be the inclined side surface of the horn 11b.

図5(B)に、LEDチップのさらに他の実装例を表した断面図を示す。図5(A)に示した実装例と同様、先述の実施例と同じ構成の部分には同一の符号を付し、説明を省略する。図5(B)に示したLEDパッケージは、ホーン11bの底面上で、反射膜兼電極26a、26bが互いに間隔をあけて突き合わせられたチップ実装部26c、26eを備えるように形成されている。これらのチップ実装部部26c、26eの上に、所謂フリップチップタイプのLEDチップ35が、その下面の両側縁に設けられた電極部を載置するようにマウントされ、電気的に接続される。   FIG. 5B is a cross-sectional view illustrating still another mounting example of the LED chip. Similar to the mounting example shown in FIG. 5A, the same reference numerals are given to the same components as those in the previous embodiment, and the description thereof is omitted. The LED package shown in FIG. 5B is formed so as to include chip mounting portions 26c and 26e on the bottom surface of the horn 11b, in which the reflective film and electrodes 26a and 26b are abutted with each other with a gap therebetween. On these chip mounting portions 26c and 26e, a so-called flip chip type LED chip 35 is mounted and electrically connected so as to place electrode portions provided on both side edges of the lower surface thereof.

図5に示したようなLEDパッケージにおいても、先述の実施例と同様の効果を得ることができる。   Also in the LED package as shown in FIG. 5, the same effects as those of the above-described embodiment can be obtained.

上述のように、(100)底面と4つの(111)傾斜側面からなるホーンを有したシリコン基板11の(111)面を凹凸のある拡散反射面とすることにより、稜線由来のダークラインのない発光を得ることができる。   As described above, the (111) plane of the silicon substrate 11 having the horn composed of the (100) bottom surface and the four (111) inclined side surfaces is a diffusive reflective surface having irregularities, so that there is no dark line derived from the ridge line. Luminescence can be obtained.

このような方法で作製したLEDパッケージは、種々の発光装置として用いることができ、例えば図6のように使用できる。LED発光体51に作製したLEDパッケージが使用され、スイッチ52でLEDパッケージへの給電を制御する。柄53を持ってLED発光体51を所望の方向に向けることができる。   The LED package manufactured by such a method can be used as various light emitting devices, for example, as shown in FIG. The LED package produced for the LED light emitter 51 is used, and the power supply to the LED package is controlled by the switch 52. The LED emitter 51 can be directed in a desired direction with the handle 53.

以上実施例に沿って本発明を説明したが、本発明はこれらに制限されるものではない。   Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto.

例えば、ホーン11aを形成するための異方性エッチングのエッチャントに水酸化カリウム溶液等を用いてもよい。   For example, a potassium hydroxide solution or the like may be used as an etchant for anisotropic etching for forming the horn 11a.

また、LEDパッケージの形態として、図7に示すように、反射膜兼電極26a、26bがシリコン基板裏面まで延長していても良い。この延長された反射膜兼電極26a、26bが電極パッドとなり、電子回路等に実装される。   As a form of the LED package, as shown in FIG. 7, the reflective film and electrodes 26a and 26b may extend to the back surface of the silicon substrate. The extended reflection film and electrodes 26a and 26b serve as electrode pads and are mounted on an electronic circuit or the like.

その他、種々の変更、改良、組み合わせ等が可能なことは当業者に自明であろう。   It will be apparent to those skilled in the art that other various modifications, improvements, combinations, and the like can be made.

(A)〜(G−2)は、シリコン基板に稜線のないホーンを形成する製造工程を示す断面図及び平面図である。(A)-(G-2) are sectional drawing and top view which show the manufacturing process which forms a horn without a ridgeline in a silicon substrate. (A)〜(E−2)は、稜線のないホーンが形成された単結晶シリコン基板にLEDチップを実装したLEDパッケージの製造工程を示す断面図及び平面図である。(A)-(E-2) are sectional drawing and top view which show the manufacturing process of the LED package which mounted the LED chip on the single crystal silicon substrate in which the horn without a ridgeline was formed. LEDチップの構成例を示した断面図である。It is sectional drawing which showed the structural example of the LED chip. (A)、(B)は、3種のLEDを実装したLEDパッケージの例を示した平面図である。(A), (B) is the top view which showed the example of the LED package which mounted 3 types of LED. (A)、(B)は、LEDチップの他の実装例を表した断面図である。(A), (B) is sectional drawing showing the other mounting example of the LED chip. 本願の実施例により作製したLEDパッケージを用いた発光装置である。It is the light-emitting device using the LED package produced by the Example of this application. LEDパッケージの構成例を示した断面図である。It is sectional drawing which showed the structural example of the LED package.

符号の説明Explanation of symbols

11 シリコン基板
11a、11b ホーン
21、21a、23、23a、23b、24 酸化シリコン膜
22、24、27 レジストパターン
25、25a、25b バリア層
26 反射膜
26a、26b、27a、27b、27c、27d、28a、28b、28c、28d 反射膜兼電極
26c、26e チップ実装部
26d 接続部
31、32a、32b、32c、33a、33b、33c、34、35 LEDチップ
31a、31g 金属電極
31b、34a 基板
31c 半導体層
31d、34d p型半導体層
31e、34c 発光層
31f、34b n型半導体層
31w、34w ボンディングワイヤ
34e n型電極
34f p型電極
40 透明樹脂
51 LED発光体
52 スイッチ
53 柄
11 Silicon substrate 11a, 11b Horn 21, 21a, 23, 23a, 23b, 24 Silicon oxide film 22, 24, 27 Resist pattern 25, 25a, 25b Barrier layer 26 Reflective film 26a, 26b, 27a, 27b, 27c, 27d, 28a, 28b, 28c, 28d Reflective film and electrode 26c, 26e Chip mounting part 26d Connection part 31, 32a, 32b, 32c, 33a, 33b, 33c, 34, 35 LED chip 31a, 31g Metal electrode 31b, 34a Substrate 31c Semiconductor Layers 31d, 34d p-type semiconductor layers 31e, 34c light-emitting layers 31f, 34b n-type semiconductor layers 31w, 34w bonding wires 34e n-type electrodes 34f p-type electrodes 40 transparent resin 51 LED light emitters 52 switches 53

Claims (12)

(a)表面が(100)面のシリコン基板に対して面方位に依存する異方性エッチングを施して、(100)面を底面とし、4つの(111)面を傾斜側面とするホーンを形成する工程と、
(b)前記ホーンの傾斜側面に凹凸を形成する工程と、
(c)前記ホーン底面上にLEDチップを実装する工程と
を含むLEDパッケージの製造方法。
(A) A silicon substrate whose surface is a (100) plane is subjected to anisotropic etching depending on the plane orientation to form a horn having a (100) plane as a bottom surface and four (111) planes as inclined side surfaces. And a process of
(B) forming irregularities on the inclined side surface of the horn;
(C) A method of manufacturing an LED package, including a step of mounting an LED chip on the bottom surface of the horn.
前記工程(b)は、
(b−1)前記ホーンを含むシリコン基板の表面に酸化膜を形成する工程と、
(b−2)表面に酸化膜が形成されたシリコン基板の(100)面上にレジストパターンを形成する工程と、
(b−3)バッファードフッ酸溶液により該ホーンの傾斜側面の酸化膜を除去し、該ホーンを含むシリコン基板の(100)面に酸化膜を残す工程と
(b−4)前記(100)に残された酸化膜をマスクとし、前記ホーンの(111)面に前記工程(a)で施した異方性エッチングとは条件の異なる異方性エッチングを施して該(111)面に滑らかな曲線で構成されたディンプル形状の凹凸を形成する工程と
を含む請求項1に記載のLEDパッケージの製造方法。
The step (b)
(B-1) forming an oxide film on the surface of the silicon substrate including the horn;
(B-2) forming a resist pattern on the (100) surface of the silicon substrate having an oxide film formed on the surface;
(B-3) removing the oxide film on the inclined side surface of the horn with a buffered hydrofluoric acid solution and leaving the oxide film on the (100) surface of the silicon substrate containing the horn; and (b-4) the above (100) Using the remaining oxide film as a mask, the (111) surface of the horn is subjected to anisotropic etching under different conditions from the anisotropic etching performed in the step (a) to make the (111) surface smooth. A method for manufacturing an LED package according to claim 1, further comprising a step of forming dimple-shaped irregularities configured by curves.
前記工程(b)は、
(b−1)前記ホーンを含むシリコン基板の表面に酸化膜を形成する工程と、
(b−2)表面に酸化膜が形成されたシリコン基板の(100)面上にレジストパターンを形成する工程と、
(b−3)バッファードフッ酸溶液により該ホーンの傾斜側面の酸化膜を除去し、該ホーンを含むシリコン基板の(100)面に酸化膜を残す工程と
(b−4)前記(100)に残された酸化膜をマスクとし、前記ホーンの(111)面にブラスト加工を施して、該(111)面に荒れた凹凸のある拡散反射面を形成する工程と
を含む請求項1に記載のLEDパッケージの製造方法。
The step (b)
(B-1) forming an oxide film on the surface of the silicon substrate including the horn;
(B-2) forming a resist pattern on the (100) surface of the silicon substrate having an oxide film formed on the surface;
(B-3) removing the oxide film on the inclined side surface of the horn with a buffered hydrofluoric acid solution and leaving the oxide film on the (100) surface of the silicon substrate containing the horn; and (b-4) the above (100) And a blasting process is performed on the (111) surface of the horn to form a rough diffused reflection surface on the (111) surface, using the remaining oxide film as a mask. LED package manufacturing method.
前記工程(c)は、
(c−1)前記底面と前記傾斜側面を含むホーン内面に絶縁膜を形成する工程と、
(c−2)前記絶縁膜上に、反射膜を兼ね、少なくとも2つの領域に分割された電極を形成する工程と、
(c−3)前記電極の少なくとも1つの上に少なくとも1つのLEDチップの一方の端子を電気的及び機械的に接続し、さらに該電極とは別の電極と該LEDチップの他方の端子とを接続する工程と
を含む請求項1から3のいずれかに記載のLEDパッケージの製造方法。
The step (c)
(C-1) forming an insulating film on the inner surface of the horn including the bottom surface and the inclined side surface;
(C-2) forming an electrode that also serves as a reflective film and is divided into at least two regions on the insulating film;
(C-3) electrically and mechanically connecting one terminal of at least one LED chip on at least one of the electrodes, and further connecting an electrode different from the electrode and the other terminal of the LED chip The manufacturing method of the LED package in any one of Claim 1 to 3 including the process to connect.
前記工程(c)の後に、
前記ホーン内に樹脂材料を充填して樹脂モールドを形成する工程
を含む請求項1から4のいずれかに記載のLEDパッケージの製造方法。
After step (c)
The manufacturing method of the LED package in any one of Claim 1 to 4 including the process of filling the resin material in the said horn and forming a resin mold.
異方性エッチングにより、(100)面の底面と、4つの(111)面の傾斜側面からなるホーンを形成し、さらに4つの(111)面に凹凸を形成したシリコン基板と、
前記ホーン底面上に実装されたLEDチップと
を含むLEDパッケージ。
By anisotropic etching, a horn composed of a bottom surface of (100) plane and four (111) plane inclined side surfaces is formed, and further, a silicon substrate having irregularities formed on four (111) planes;
An LED package including an LED chip mounted on the bottom surface of the horn;
前記凹凸は、
前記(111)面に前記異方性エッチングとは条件の異なる異方性エッチングを施して形成された、滑らかな曲線で構成されたディンプル形状の凹凸である請求項6に記載のLEDパッケージ。
The unevenness is
7. The LED package according to claim 6, wherein the LED package is a dimple-shaped concavo-convex having a smooth curve formed by subjecting the (111) plane to anisotropic etching under conditions different from those of the anisotropic etching.
前記凹凸は、
前記(111)面にブラスト加工を施して形成された、荒れた凹凸のある拡散反射面である請求項6に記載のLEDパッケージ。
The unevenness is
The LED package according to claim 6, wherein the LED package is a diffuse reflection surface having rough irregularities formed by blasting the (111) surface.
前記底面と前記傾斜側面とを含むホーン内面に形成される絶縁膜と、
前記絶縁膜上に形成され、反射膜を兼ねた少なくとも2つの領域に分割された電極と、
前記電極の少なくとも1つの上に一方の端子を電気的機械的に接続され、さらに該電極とは別の電極に他方の端子を接続されたLEDチップと
を含む請求項6から8のいずれかに記載のLEDパッケージ。
An insulating film formed on the inner surface of the horn including the bottom surface and the inclined side surface;
An electrode formed on the insulating film and divided into at least two regions serving also as a reflective film;
The LED chip according to any one of claims 6 to 8, further comprising: an LED chip having one terminal electrically and mechanically connected to at least one of the electrodes, and the other terminal connected to another electrode. The described LED package.
前記電極が前記シリコン基板裏面側まで延長していることを特徴とする請求項9に記載のLEDパッケージ。   The LED package according to claim 9, wherein the electrode extends to the back side of the silicon substrate. さらに、
前記ホーン内に樹脂材料を充填して形成した樹脂モールド
を含む請求項6から10のいずれかに記載のLEDパッケージ。
further,
The LED package according to claim 6, further comprising a resin mold formed by filling the horn with a resin material.
請求項6から11のいずれかに記載のLEDパッケージを用いた発光装置。   A light emitting device using the LED package according to claim 6.
JP2005347443A 2005-12-01 2005-12-01 Led package, method of manufacturing light-emitting device and led package Pending JP2007157805A (en)

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