JP2007150775A - Method and system for detecting erroneous connection of differential signal line - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily detect in a short period of time an erroneous connection of a differential signal circuit by using a circuit based on the SDH system of an ITU-T standard especially when differentially transmitting SDH (synchronous digital hierarchy) signals or the like. <P>SOLUTION: The method is for detecting the erroneous connection of a differential signal line between a transmission side circuit 1 and a reception side circuit 2. When the frame synchronization of signals transmitted from the transmission side circuit 1 to the reception side circuit 2 can not be made, after inserting the inverted value of a frame synchronization byte to signals to be transmitted by an OH insertion part 102 of the transmission side circuit 1, conversion to differential signals is performed by a single-balance conversion driver 104. In the reception side circuit 2, the differential signals are converted to single line signals by a balance-single conversion receiver 201, and when an LOF alarm 217 is not detected and the frame synchronization of signals is attained by a frame synchronization part 203, the erroneous connection of the differential signal line is judged. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to detection of erroneous connection of a differential signal line, and in particular, an interface between circuits such as an ITU-T standard SDH (Synchronous Digital Hierarchy) device or an ANSI standard SONET (Synchronous Optical NETwork) device. The present invention relates to a method and a system for detecting an erroneous connection of a line for transmitting a differential signal when conforming to SONET.

  Wiring of printed boards between circuits such as LSIs and wiring of cables is not a single wire but a wiring by a differential as the device speed increases in recent years. When the transmission format between circuits such as LSI complies with the SDH / SONET standard, an identification code is inserted into the overhead for each line and an identification code different from the line is received as a method of detecting an erroneous connection of the line. A method has been proposed in which it is determined that the connection is incorrect (see, for example, Patent Document 1).

JP 2003-008533 A

  However, the method of inserting an identification code into the overhead and detecting the incorrect connection between the lines by comparing with the expected value can detect the erroneous connection between the lines, but the polarity is reversed due to the erroneous connection of the differential signal. Then, since frame loss occurs, there is a problem that the overhead, that is, the identification code cannot be recognized and verified, and the erroneous connection of the differential signal line cannot be detected.

  In addition, when a transmission monitoring alarm occurs due to an incorrect connection of a differential signal line, it is difficult to identify the cause of the error from the error phenomenon because the cause of the error is diverse, such as incorrect connection, failure, disconnection between connections, deterioration, etc. There was a problem that it took a long time to investigate the cause.

  Therefore, the present invention has been made in view of the above-described problems in the prior art, and easily detects an erroneous connection of a differential signal line when an interface between circuits conforms to SDH / SONET. It is an object to provide a method and system capable of doing so.

  In order to achieve the above object, the present invention is a method for detecting a misconnection of a differential signal line between a transmission side circuit and a reception side circuit, which is transmitted from the transmission side circuit to the reception side circuit. When the frame synchronization of the signal cannot be achieved, the transmission side circuit inserts the inverted value of the frame synchronization byte into the signal to be transmitted and converts it to a differential signal, and the reception side circuit converts the differential signal to the differential signal. When the signal is converted into a single-line signal and the frame synchronization of the signal is established, it is determined that the differential signal line is erroneously connected.

  According to the present invention, if there is an erroneous connection of the differential signal line, it is usually impossible to achieve frame synchronization. However, in the transmission side circuit, after the inverted value of the frame synchronization byte is inserted, it is converted into a differential signal. However, since the polarity of the data is inverted when the differential signal is converted into a single-line signal in the receiving side circuit, frame synchronization can be obtained. Therefore, when such a phenomenon occurs before and after inserting the inverted value of the frame synchronization byte, it can be specified that the differential signal line is erroneously connected.

  In the present invention, since an erroneous connection can be detected by inserting an inverted value of the frame synchronization byte, an erroneous connection of the differential signal line can be detected without replacing the cable, and the detection work is facilitated. This can be done in a short time.

  In the differential signal line misconnection detection method, the differential signal line can transmit an SDH differential signal, is outside the scramble range, and supports insertion from the user in the ITU-T standard. Insertion control from the CPU with respect to the J0 / Z0 byte and the LOF alarm can be monitored on the CPU side, so that it is possible to determine an incorrect connection. Therefore, the software conforms to the ITU-T standard without hardware modification. False detection can be performed by software.

  In addition, the present invention is a system for detecting an erroneous connection of a differential signal line between a transmission side circuit and a reception side circuit, and is provided in the transmission side circuit. An overhead insertion unit for inserting an inverted value, a driver for single-to-differential conversion of a signal to be transmitted, a receiver for differential-to-single line conversion of a signal to be transmitted, and a frame loss alarm And a frame synchronization unit for detection.

  With this configuration, after the frame synchronization of the signal transmitted from the transmission side circuit to the reception side circuit cannot be achieved, the overhead insertion unit of the transmission side circuit inserts the inverted value of the frame synchronization byte into the transmitted signal. A single line-differential conversion is performed by a driver, a signal transmitted from a transmission side circuit is differential-single line converted by a receiver of the reception side circuit, and a differential signal is detected when a frame loss alarm is detected by a frame synchronization unit. It can be identified as a line misconnection. Accordingly, it is possible to detect an erroneous connection of the differential signal line without replacing the cable, and the detection operation can be performed easily and in a short time.

  In the erroneous connection detection system of the differential signal line, the differential signal line can transmit an SDH differential signal, and as described above, the hardware in a circuit conforming to the ITU-T standard. False detection can be performed by software without modification.

  As described above, according to the present invention, it is possible to easily detect an erroneous connection of a differential signal line when an interface between circuits conforms to SDH / SONET.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows an embodiment of a differential signal line misconnection detection system according to the present invention. This system detects a differential signal line misconnection between a circuit 1 and a circuit 2.

  The circuit 1 includes a main signal processing unit 101 that processes the main signal, an OH (overhead) insertion unit 102 that inserts overhead into the data 106 output from the main signal processing unit 101, and a scramble process for the data 107. A scramble unit 103 to perform, a single-balance conversion driver 104 that converts data 108 into a differential signal in order to transmit an output SDH signal, and a CPU interface unit 105 that controls the OH insertion unit 102 via the CPU bus 301. Composed.

  The circuit 2 extracts a clock from the balance-single conversion receiver 201 that converts an input SDH signal from a differential signal to a single-line signal, and received data 211, and an LOS (loss of signal) alarm 216 when there is no input signal. A frame that detects a frame synchronization byte for received data 212, detects frame synchronization, and detects a LOF (loss of frame) alarm 217 when no frame synchronization byte is detected. A synchronization unit 203, a descrambling unit 204 that performs descrambling processing on the data 213, an OH termination unit 205 that terminates overhead, a main signal processing unit 206 that processes a main signal, and a detected alarm by the CPU bus 301 And a CPU interface unit 207 that notifies the CPU 3 via . For the connection between the circuit 1 and the circuit 2, cable wiring such as coaxial is mainly used.

  Next, the operation of the apparatus shown in FIG. 1 will be described with reference to the chart.

  In the circuit 1 shown in FIG. 1, after the main signal is processed by the main signal processing unit 101, the overhead value 111 is inserted into the data 106 by the OH insertion unit 102. This overhead includes A1 byte and A2 byte which are frame synchronization bytes, B1 byte for monitoring transmission path errors, and overhead bytes which can be inserted by the user in accordance with ITU-T. Insert.

  In the present embodiment, values are inserted by setting from the CPU 3 into the J0 byte and the Z0 byte that are outside the scramble range and can be set by the user. After that, the scramble unit 103 performs scramble processing on the portion (see FIG. 3) excluding the first section overhead line (A1 byte, A2 byte, J0 byte, Z0 byte). The scrambled data 108 is converted into a differential signal by the single-balance conversion driver 104 and output as a data output P_109 and a data output N_110.

  After the cable transmission, the circuit 2 converts the received differential signal between the data input P_209 and the data input N_210 into a single line signal by the balance-single conversion receiver 201. The clock recovery unit 202 extracts the clock for the single-line data 211 and performs retiming. If there is no input signal, the LOS alarm 216 is detected.

  Thereafter, the frame synchronization unit 203 searches for a total of 32 bits of the two values F6 (h) and two values 28 (h) in FIG. 2 which are SDH synchronization detection conditions, and performs synchronization pull-in. When the synchronization byte is not detected, the LOF alarm 217 is detected. Thereafter, the descrambling unit 204 performs descrambling processing on the portion excluding the first row of section overhead (A1 byte, A2 byte, J0 byte, Z0 byte), and restores the signal before scrambling.

  Thereafter, the overhead 219 conforming to ITU-T is terminated by the OH termination unit 205, and the main signal is processed by the main signal processing unit 206. The detected LOS alarm 216, LOF alarm 217, B1 error alarm 218, and terminated overhead value 208 are notified from the CPU interface unit 207 to the CPU 3 via the CPU bus 301.

  The J0 / Z0 byte is an overhead that can be inserted by the user, and an arbitrary value can be inserted. Usually, however, the STM identification number, 0 value, 1 value, and the STM-64 or higher are basic. Therefore, since AAh (CCh in the ANSI standard) is inserted, the values (09, 09, D7, D7) in this embodiment are not inserted. If event 1 is wired normally, neither LOS alarm 216 nor LOF alarm 217 is detected in circuit 2.

  Here, Table 1 shows the relationship between events and alarm states. When the LOS alarm 216 and the LOF alarm 217 are detected, various factors can be considered as shown in Table 1. As shown in the table, if the event 2 cable pair is erroneously connected, the LOS alarm 216 is not detected and the LOF alarm 217 is detected. According to the table, it is difficult to separate the erroneous connection in the pair from other factors, so it takes time to investigate the cause.

  Next, the operation when detecting the miswiring of the differential signal line by the method according to the present invention will be described.

  In a normal use example, that is, when the J0 / Z0 byte is a value other than the value of the present invention and there is no detection by the LOS alarm 216 and there is detection by the LOF alarm 217, the OH insertion unit 102 of the circuit 1 is separated as a separation. 4, the value 09 (h) obtained by inverting the value F6 (h) is inverted to the J0 byte and the Z0 byte # 1, and the value 28 (h) is inverted to the Z0 byte # 2 and # 3. The value D7 (h) is inserted according to the setting from the CPU 3. In the scramble unit 103, since the J0 byte and the Z0 byte are out of the scramble range, the values are output as they are, and are transmitted as a differential signal by the single-balance conversion driver 104 via a cable.

  In the circuit 2, the differential signal is converted into a single line by the balance-single conversion receiver 201, and when the differential signal line is erroneously connected in the frame synchronization unit 203, the previously inserted J0 byte and Z0 byte are As a result of the inversion, the value 09 (h) is captured as the value F6 (h) and the value D7 (h) is captured as the value 28 (h). Therefore, frame synchronization can be achieved. Table 2 shows a relationship between an event and an alarm state when the method according to the present invention is employed.

  Comparing Table 1 and Table 2, since the presence or absence of an alarm is different only when Event 2 is erroneously connected, it is possible to identify an erroneous connection. This method allows software detection from the CPU, facilitates factor identification, and reduces work time.

  Next, another embodiment of the present invention will be described with reference to FIGS. The basic configuration of this embodiment is the same as that described above, but in this embodiment, detection is possible for all combinations of adjacent erroneous connections.

  As shown in FIG. 5, in this system, when a plurality of SDH frames are input / output between the circuit 1 and the circuit 2, the circuit 1 outputs the main signal processing unit 101 for processing the main signal and the main signal processing unit 101 for output. An OH insertion unit 102 for inserting overhead into the data 106, a scramble unit 103 for performing a scramble process, a single-balance conversion driver 104 for converting an SDH signal to be output, and a CPU bus And a CPU interface unit 105 that controls the OH insertion unit 102 via 301.

  Circuit 2 is a balanced-single conversion receiver 201 that converts an input SDH signal from a differential signal to a single-line signal, and extracts a clock from received data, and detects a LOS (loss of signal) alarm when there is no input signal. A frame recovery unit 202 that detects a frame synchronization byte for received data, performs frame synchronization, and detects a LOF (loss of frame) alarm when no frame synchronization byte is detected, , A descrambling unit 204 that performs descrambling processing, an OH termination unit 205 that terminates overhead, a main signal processing unit 206 that processes main signals, and a CPU interface unit that notifies the CPU 3 of detected alarms via the CPU bus 301 207. For the connection between the circuit 1 and the circuit 2, cable wiring such as coaxial is mainly used.

  Next, the operation of the system in each of the events 1-5 shown in FIG. 6 will be described.

(1) Event 1 (normal connection)
The signal output P109 (n) is normally connected to the signal input P209 (n), and the signal output N110 (n) is normally connected to the signal input N210 (n). As shown in Table 1 above, the LOS alarm 216 or the LOF alarm 217 is detected for a failure or break.

(2) Event 2 (Incorrect connection within pair)
The signal output P109 (n) shows a signal input N210 (n), and the signal output N110 (n) shows a case where the signal input P209 (n) is erroneously connected to the signal input P209 (n) by crossing within the cable pair. The event 2 can be identified by the difference between Table 1 and Table 2 by the operation of the apparatus shown in FIG.

(3) Event 3 (adjacent signal polarity is incorrect)
The signal output N110 (n-1) is erroneously connected to the signal input P209 (n), and the signal output P109 (n) is erroneously connected to the signal input N210 (n-1) by crossing only one polarity of the adjacent signal. Show the case. The data n−1 cannot be normally converted by the balance-single conversion receiver 201 because the input source is both P. Therefore, the LOS alarm 216 is detected by the clock recovery unit 202, or the LOF alarm is detected by the subsequent frame synchronization unit. Similarly for the data n, the LOS alarm 216 or the LOF alarm 217 is detected.

(4) Event 4 (adjacent signals with the same polarity are incorrectly connected)
The signal output N110 (n-1) is erroneously connected to the signal input N210 (n), and the signal output N110 (n) is erroneously connected to the signal input N210 (n-1) by crossing only one polarity of the adjacent signal. Show the case. Since the input sources of data n−1 are P and N, the balanced-single conversion receiver 201 can normally convert the data n−1 if the wirings are of equal length. Neither LOS alarm 216 nor LOF alarm 217 is detected. Similarly, the LOS alarm 216 or the LOF alarm 217 is not detected for the data n.

  Next, both B1 errors are monitored so that they can be distinguished from normal connections. While neither B1 error is detected at the time of normal connection, in this event, even if there is frame synchronization, the values in the data are different, so a B1 error always occurs in both.

  On the other hand, if the wirings are not the same length, both are specified by occurrence of the LOS alarm 216 or the LOF alarm 217 as in the event 3.

(5) Event 5 (adjacent signal misconnection)
The signal output P109 (n-1) is sent to the signal input P209 (n), the signal output N110 (n-1) is sent to the signal input N210 (n), and the signal output P109 (n) is sent to the signal input P209 (n- To 1), the signal output N110 (n) is erroneously connected to the signal input N210 (n-1) in both polarities and sets of adjacent signals.

  In this case, neither the data n-1 nor the data n detects the LOS alarm 216, the LOF alarm 217, or the B1 error alarm 218. If a method of inserting an identification code is used, an erroneous connection can be specified.

  Next, an example of an erroneous connection detection procedure flow using event 1-5 will be described with reference to FIG.

  First, in step S1, if there is a LOS alarm or LOF alarm in data n, it is determined in step S2 whether there is a LOS alarm or LOF alarm in data n-1 or data n + 1. And when at least one exists, it determines with it being the event 3 or the event 4. On the other hand, if no alarm exists, the process proceeds to step S3.

  In step S3, the value of FIG. 4 is inserted into data n, and it is determined whether or not there is a LOS alarm or a LOF alarm in data n. And when at least one exists, it determines with it being the event 1. On the other hand, if no alarm is present, it is determined that the event 2 has occurred.

  Next, if there is no LOS alarm or LOF alarm in data n in step S1, it is determined in step S4 whether a B1 alarm exists in data n. If the B1 alarm exists, the process proceeds to step S5. On the other hand, if there is no B1 alarm, the process proceeds to step S6.

  In step S5, it is determined whether or not the B1 alarm exists in the data n-1 or n + 1. If the B1 alarm exists, it is determined that the event 4 is present. On the other hand, when the B1 alarm does not exist, it is determined that the event is one.

  On the other hand, in step S6, the data n is collated with the identification code to check whether or not they match. On the other hand, if they do not match, the event 5 is determined.

It is a block diagram which shows the structure of one Embodiment of the misconnection detection system of the differential signal line | wire concerning this invention. It is a figure which shows the synchronous byte and detection condition of an SDH signal in the misconnection detection system of the differential signal line concerning this invention. It is a figure which shows the overhead insertion location of the SDH signal in the erroneous connection detection system of the differential signal line | wire concerning this invention. It is a figure which shows the overhead insertion location and insertion value in the misconnection detection system of the differential signal line | wire concerning this invention. It is a block diagram which shows the structure which utilized the misconnection detection system of the differential signal line | wire concerning this invention. It is a figure which shows the combination of the misconnection of the adjacent signal which can apply the misconnection detection method and system of the differential signal line concerning this invention. It is a figure which shows an example of the implementation flow of the misconnection detection method of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Circuit 101 Main signal processing part 102 OH insertion part 103 Scramble part 104 Single-balance conversion driver 105 CPU interface part 106-108 Data 109, 110 Data output (differential)
111 Overhead value 2 Circuit 201 Balance-single conversion receiver 202 Clock recovery unit 203 Frame synchronization unit 204 Descramble unit 205 OH termination unit 206 Main signal processing unit 207 CPU interface unit 208 Overhead values 209 and 210 Data input (differential)
211 to 215 Data 216 LOS alarm 217 LOF alarm 218 B1 error alarm 3 CPU
301 CPU bus

Claims (4)

A method of detecting an erroneous connection of a differential signal line between a transmission side circuit and a reception side circuit,
When frame synchronization of the signal transmitted from the transmission side circuit to the reception side circuit cannot be obtained, the transmission side circuit inserts an inverted value of the frame synchronization byte into the transmitted signal and converts it to a differential signal. In the receiving circuit, the differential signal is converted into a single-line signal, and the differential signal line is determined to be erroneously connected when frame synchronization of the signal is established. Signal line misconnection detection method.   The differential signal line misconnection detection method according to claim 1, wherein the differential signal line transmits an SDH differential signal. A system for detecting a misconnection of a differential signal line between a transmission side circuit and a reception side circuit,
An overhead insertion unit that is provided in the transmission-side circuit and inserts an inverted value of a frame synchronization byte into a signal to be transmitted; and a driver that performs single-line to differential conversion on the signal to be transmitted;
A differential signal line misconnection detection system, comprising: a receiver that is provided in the receiving side circuit and that performs differential-single line conversion on a signal to be transmitted; and a frame synchronization unit that detects a frame loss alarm.   The differential signal line misconnection detection system according to claim 3, wherein the differential signal line transmits an SDH differential signal.

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