JP2007150046A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To miniaturize the size of a semiconductor chip equipped with a semiconductor element while securing the latch up immunity of the semiconductor element. <P>SOLUTION: The semiconductor chip has a logic 20 in which a semiconductor element is formed in the surface side of a p-type silicon substrate 1 and an input protection 10 equipped with an n<SP>+</SP>-type region 11 and a p<SP>+</SP>-type region 12 formed in the surface side of the p-type silicon substrate 1. The n<SP>+</SP>-type region 11 is connected to an input terminal 13 in the input protection portion 10, and at the same time, the P<SP>+</SP>region 12 is connected to a ground 14, and a surge input to the input terminal 13 is removed to the ground 14 through the n<SP>+</SP>-type region 11 and the p<SP>+</SP>-type region 12. A trench 2 is formed in a position facing at least the n<SP>+</SP>-type region 11 among the backside of the p-type silicon substrate 1, the electrode 3 is formed in the bottom of the trench 2, and this electrode 3 is connected to the ground 14. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which latch-up of a transistor caused by an externally input surge is prevented.

  2. Description of the Related Art Conventionally, in a semiconductor chip in which a semiconductor element such as a CMOS transistor is formed, a parasitic bipolar transistor is formed by a well, an n + diffusion layer, a p + diffusion layer, etc. that constitute the CMOS transistor in accordance with the structure of the CMOS transistor. When a surge is input from the outside to such a semiconductor chip, this surge becomes a trigger and the parasitic bipolar transistor is turned on. That is, a latch-up phenomenon in which a through current flows through the parasitic bipolar transistor occurs. If this through current continues to flow, heat is generated in the semiconductor chip, causing a problem that the CMOS transistor is destroyed due to, for example, melting of the silicon substrate constituting the CMOS transistor.

A semiconductor chip structure that solves this problem is proposed in Patent Document 1. Specifically, in Patent Document 1, a surge absorption layer (cut well) is provided between an input terminal of a semiconductor chip and a CMOS transistor in order to prevent a surge input to the semiconductor chip from reaching the CMOS transistor. A structure has been proposed in which the surge input from the input terminal is absorbed by the surge absorbing layer to improve the latch-up resistance of the CMOS transistor.
Japanese Patent Laid-Open No. 7-111315

  However, in the above conventional technique, the width of the surge absorption layer (the length of the surge absorption layer in the direction in which the surge flows from the input terminal to the CMOS transistor) is required to ensure the surge withstand capability. It has become difficult to reduce the size. That is, if the width of the surge absorption layer is wide, the surge can be sufficiently absorbed, but if the width of the surge absorption layer is reduced to reduce the size of the semiconductor chip, the surge absorption layer cannot absorb the surge, There is a possibility that the CMOS transistor is latched up.

  Specifically, if the semiconductor chip is reduced in size and the width of the surge absorption layer is reduced, when a surge is input to a diode that is an input protection element as an input terminal, a part of the surge is absorbed by the diode itself. However, the surge that is not absorbed by the diode propagates to the substrate constituting the semiconductor chip. The surge propagated to the substrate is absorbed by the surge absorption layer, but the surge not absorbed by the surge absorption layer propagates to the CMOS transistor and causes latch-up of the CMOS transistor.

  In addition, when using a semiconductor chip for on-vehicle use, for example, reduction in chip size is desired. Therefore, it is not preferable to provide the surge absorbing layer.

  An object of the present invention is to provide a semiconductor device that can secure a latch-up resistance against a semiconductor element and can reduce the size of a chip including the semiconductor element.

  In order to achieve the above object, in the present invention, at least the first conductivity type region (11) of the back surface of the semiconductor substrate (1) provided with the input protection unit (10) provided with the input terminal (13). Electrodes (3, 6) are formed at opposing positions, and the electrodes are connected to a ground (14).

  Thus, an electrode is provided on the back surface of the semiconductor substrate, and this electrode is connected to the ground. As a result, when the surge input from the input terminal is not absorbed by the diode composed of the first conductivity type region and the second conductivity type region, the surge flowing into the semiconductor substrate is absorbed by the back electrode. It can be removed to the ground, and the latch-up resistance can be ensured.

  Therefore, it is possible to ensure the latch-up resistance without forming a surge absorbing layer for absorbing surges, to reduce the size of the semiconductor substrate, and to downsize the semiconductor device.

  In the present invention, the recess (2) is formed at least on the back surface of the semiconductor substrate at a position facing the first conductivity type region, and the back electrode is formed at least on the bottom of the recess. .

  As described above, the concave portion is provided on the back surface of the semiconductor substrate, and the distance between the front surface and the back surface of the semiconductor substrate is reduced in the portion where the first conductivity type region is formed on the semiconductor substrate. Thereby, the distance between the region of the first conductivity type and the back electrode can be reduced, and the surge can be more easily absorbed by the electrode. In this way, the latch-up resistance can be further improved.

  In the present invention, a recess (5) is formed in the input protection portion of the surface of the semiconductor substrate, and a first conductivity type region and a second conductivity type region are formed in the surface portion of the semiconductor substrate corresponding to the recess. In the back surface of the semiconductor substrate, an electrode is formed at a position facing at least the first conductivity type region.

  Thus, a recess is provided on the surface of the semiconductor substrate, and the first conductivity type region and the second conductivity type region are formed on the surface portion of the semiconductor substrate corresponding to the recess. An electrode is formed on the back surface of the semiconductor substrate facing the first conductivity type region. Accordingly, the distance between the first conductivity type region and the back electrode can be reduced, and the electrode can easily absorb the surge. In this way, the latch-up resistance can be further improved.

  In the present invention, the back electrode is formed on the entire back surface of the semiconductor substrate. Thus, an electrode is provided on the entire back surface of the semiconductor substrate. Thereby, when the surge input to the input protection unit flows in the direction of the semiconductor device unit, the surge can be absorbed by the electrode and removed to the ground before reaching the semiconductor device. Therefore, the latch-up resistance can be improved.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. The semiconductor device shown in this embodiment can be applied to a semiconductor chip in which a semiconductor element is formed, in which the semiconductor element may be latched up. For example, it can be used by being mounted on an in-vehicle ECU.

  FIG. 1 is a schematic cross-sectional view of a semiconductor chip as a semiconductor device according to the first embodiment of the present invention. As shown in this figure, the P-type silicon substrate 1 is provided with an input protection unit 10 and a logic unit 20. In FIG. 1, a portion formed on the surface of the P-type silicon substrate 1 is omitted. The P-type silicon substrate 1 corresponds to the semiconductor substrate of the present invention, and the Logic portion corresponds to the semiconductor device portion of the present invention.

  In the input protection unit 10, an N + type region 11 and a P + type region 12 are formed on the surface side of the P type silicon substrate 1, and a diode is configured by the N + type region 11 and the P + type region 12. Yes. That is, the N + type region 11 corresponds to the anode of the diode, and the P + type region 12 corresponds to the cathode of the diode. The N + type region 11 corresponds to a first conductivity type region of the present invention, and the P + type region 12 corresponds to a second conductivity type region of the present invention.

  An input terminal 13 is connected to the N + type region 11, and a ground 14 is connected to the P + type region 12. That is, the diode constituted by the N + type region 11 and the P + type region 12 has its input terminal 13 connected to an external circuit, and removes a surge input from the external circuit to the ground 14, so that the Logic unit 20 Serves to protect against surges.

  In the Logic portion 20, an N-type well 21 is formed on the surface portion of the P-type silicon substrate 1, and a P-type well 22 is formed on the surface portion inside the N-type well 21. In the surface layer portion of the P-type well 22, N + regions 23 and 24 are formed apart from each other, and a P + region 25 is formed separately from the N + region 24. These N + type regions 23 and 24 correspond to the source region and the drain region, and the P + type region 25 corresponds to the well region.

  Further, the surface side portion of the P-type well 22 located between the N + -type regions 23 and 24 is used as a channel region, and a gate electrode 27 is formed on the channel region via a gate insulating film 26. ing. In this way, an nMOS transistor is formed in the P-type well 22.

  Further, in the surface portion of the N-type well 21 where the P-type well 22 is not formed, P + -type regions 28 and 29 are formed apart from each other. N + type region 30 is formed between the two. The P + type regions 28 and 29 correspond to the source region and the drain region, and the N + type region 30 corresponds to the well region.

  Then, the surface side portion of the N-type well 21 located between the P + -type regions 28 and 29 is used as a channel region, and the gate electrode 32 is formed on the channel region via the gate insulating film 31. Yes. In this way, a pMOS transistor is formed in the N-type well 21.

  Therefore, in the logic unit 20, a CMOS transistor is configured by the nMOS transistor and the pMOS transistor.

  In the semiconductor chip having the above configuration, a groove 2 having a recessed back surface is formed on the back surface side of the P-type silicon substrate 1 in the input protection unit 10. An electrode 3 is formed at the bottom of the groove 2, and the electrode 3 is connected to the ground 14.

  Such a groove 2 can be partially formed on the back side of the P-type silicon substrate 1 by, for example, etching, and the depth thereof is, for example, 30 μm. The electrode 3 is formed, for example, by metal sputtering, and Al (aluminum), for example, is adopted as the material of the electrode 3. In addition, the groove | channel 2 is corresponded to the recessed part of this invention.

  In the present embodiment, the groove 2 is formed on the P-type silicon substrate 1 at a position facing the diode constituted by the N + type region 11 and the P + type region 12. As shown in FIG. 1, the distance between the front surface and the back surface of the P-type silicon substrate 1 is reduced by the groove 2. That is, the P-type silicon substrate 1 is thinned (thinned). In other words, the distance between each region 11, 12 in which the diode is formed, more specifically, the N + type region 11 and the bottom of the trench 2 is reduced.

  Since the surge is input from the input terminal 13 to the N + type region 11, the groove 2 may be formed at least in a position facing the N + type region 11 on the back surface of the semiconductor substrate.

  Next, a method for manufacturing the semiconductor chip will be described. First, a P-type silicon substrate 1 is prepared, and an N + -type region 11 and a P + -type region 12 are formed by ion implantation and thermal diffusion in a predetermined region of the P-type silicon substrate 1 serving as the input protection unit 10 using a mask or the like. Form from time to time. Similarly, nMOS transistors and pMOS transistors are formed by performing ion implantation and thermal diffusion in a predetermined region of the P-type silicon substrate 1 serving as the logic portion 20 to form gate insulating films 26 and 31, gate electrodes 27 and 32, and the like. Form. Then, wiring electrodes or the like (not shown) are formed on the surface of the P-type silicon substrate 1, the N + type region 11 of the input protection unit 10 is connected to the input terminal 13, and the P + type region 12 is connected to the ground 14. In addition, a source electrode, a drain electrode, and the like (not shown) are formed for each transistor of the logic unit 20.

  Thereafter, the groove 2 is formed on the back surface side of the P-type silicon substrate 1 on the side opposite to the diode constituted by the N + type region 11 and the P + type region 12 in the input protection unit 10. Specifically, after a mask is formed on the back surface of the P-type silicon substrate 1, the mask is patterned by, for example, photolithography, and a portion corresponding to the groove 2 is opened. Then, a groove 2 having a desired depth is formed by anisotropic dry etching using a patterned mask. Further, an electrode 3 is formed at least on the bottom of the groove 2 by sputtering, and the electrode 3 is connected to the ground 14. As described above, the semiconductor chip shown in FIG. 1 is completed.

  Next, in the semiconductor chip illustrated in FIG. 1, a surge path when a surge is input to the input terminal 13 of the input protection unit 10 will be described. First, when a surge is input to the input terminal 13, the surge is input to the N + type region 11 and flows to the ground 14 via the P + type region 12 that constitutes a diode together with the N + type region 11.

  When a higher surge is input to the input terminal 13, the surge cannot be absorbed by the diode of the input protection unit 10, and the surge flows from the N + type region 11 to the P-type silicon substrate 1. Specifically, the surge flows in the thickness direction of the P-type silicon substrate 1 (in the direction of the hatched arrow in FIG. 1). This surge flows between the thinned portion of the P-type silicon substrate 1, that is, between the P-type silicon substrate 1 and the bottom of the groove 2, is absorbed by the electrode 3 formed at the bottom of the groove 2, and is removed by the ground 14. Is done.

  As described above, since the electrode 3 is formed on the back surface of the P-type silicon substrate 1, a surge that flows in the thickness direction of the P-type silicon substrate 1 from the diode of the input protection unit 10 can be absorbed by the electrode 3. it can. Further, since the groove 2 is formed on the back surface of the P-type silicon substrate 1 and the distance between the diode of the input protection unit 10 and the electrode 3 is reduced, the surge can be efficiently removed to the ground 14. .

  Here, the inventors performed a simulation on the latch-up resistance of the semiconductor chip depending on the thickness of the P-type silicon substrate 1. FIG. 2 is a schematic cross-sectional view of a semiconductor chip targeted for simulation.

  In the present embodiment, the CMOS transistor structure of the semiconductor chip is only the structure necessary for latch-up to occur in the CMOS transistor when the latch-up tolerance simulation is performed. Specifically, as shown in FIG. 2, in the nMOS transistor, only the N + type region 24 and the P + type region 25 are formed in the P type well 22, and in the pMOS transistor, only the N + type region 30 and the P + type region 29 are formed. Is formed.

  That is, whether or not a through current flows between the P + type region 29 of the pMOS transistor and the N + type region 24 of the nMOS transistor by the surge that has passed through the inside of the P type silicon substrate 1 flowing into the N type well 21. judge. As a result, a simulation is performed to determine whether latch-up has occurred in the CMOS transistor.

  In this simulation, the width of the P-type silicon substrate 1 passing through the input protection unit 10 and the Logic unit 20 (the length in the direction passing through the input protection unit 10 and the Logic unit 20) is 70 μm, and the P-type silicon substrate 1 It is assumed that the electrode 4 is formed on the entire back surface of the substrate. Then, the latch-up resistance was simulated by changing the substrate thickness of the P-type silicon substrate 1 in the range of 20 to 100 μm. In this simulation, a negative voltage surge is input to the input terminal 13 of the input protection unit 10 shown in FIG. 2, and the surge voltage immediately before the current flows through the CMOS transistor is defined as a latch-up withstand capability.

  FIG. 3 is a diagram showing the correlation between the substrate thickness and the latch-up tolerance by simulation. Note that since a negative voltage surge is input, the unit of the latch-up resistance is -kV.

  As shown in this figure, it can be seen that the smaller the thickness of the P-type silicon substrate 1, the greater the latch-up resistance. That is, since the thickness of the P-type silicon substrate 1 is not small, the distance between the N + type region 11 of the input protection unit 10 and the electrode 4 is reduced, and the surge is easily absorbed by the electrode 4. This is because the latch-up resistance is improved.

  Therefore, as apparent from the above simulation, the groove 2 is provided on the opposite side of the N + type region 11 formed in the P type silicon substrate 1 in the input protection part 10 of the semiconductor chip shown in FIG. By reducing the thickness of the input protection portion 10 in the silicon substrate 1, it is possible to easily absorb the surge input to the input terminal 13 into the electrode 3, and to improve the latch-up resistance of the semiconductor chip. . Further, since it is not necessary to form a surge absorbing layer for absorbing surges in the P-type silicon substrate 1 as in the prior art, the distance between the input protection unit 10 and the logic unit 20 can be reduced, and the semiconductor chip The chip size can be reduced. Thereby, a semiconductor chip can be reduced in size.

  As described above, this embodiment is characterized in that the electrode 3 is provided in the groove 2 formed on the back surface of the P-type silicon substrate 1 and this electrode 3 is connected to the ground 14. Thus, when the surge input from the input terminal 13 is not absorbed by the diode constituted by the N + type region 11 and the P + type region 12, the surge flowing into the P type silicon substrate 1 is absorbed by the electrode 3. It can be removed to the ground 14, and latch-up resistance can be secured.

  Therefore, by providing the electrode 3, it is possible to ensure the latch-up resistance without forming a surge absorbing layer for absorbing the surge, and to reduce the size of the P-type silicon substrate 1, and to reduce the size of the semiconductor chip. Can be

  Moreover, the groove | channel 2 is provided in the back surface of the P-type silicon substrate 1, and the distance of the front surface of the P-type silicon substrate 1 and a back surface is made small. Thereby, the distance between the N + type region 11 and the electrode 3 can be reduced, and the surge can be more easily absorbed by the electrode 3. In this way, the latch-up resistance can be further improved.

(Second Embodiment)
In the present embodiment, only parts different from the first embodiment will be described. This embodiment is characterized in that a groove is formed on the surface of the P-type silicon substrate 1.

  FIG. 4 is a schematic cross-sectional view of a semiconductor chip according to the second embodiment of the present invention. As shown in this figure, of the input protection unit 10 and the logic unit 20 provided on the P-type silicon substrate 1, the groove 5 is formed on the surface of the P-type silicon substrate 1 in the input protection unit 10. . Thereby, in the input protection part 10, the distance of the bottom of the groove | channel 5 and the back surface of the P-type silicon substrate 1 is made small.

  In the P-type silicon substrate 1, an N + type region 11 and a P + type region 12 are formed on the surface portion corresponding to the groove 5. As in the first embodiment, the N + type region 11 has an input terminal 13. The P + region 12 is connected to the ground 14. In addition, the groove | channel 5 is corresponded to the recessed part of this invention.

  In the present embodiment, the electrode 6 is formed on the entire back surface of the P-type silicon substrate 1. As a result, the electrode 6 is formed on at least a portion corresponding to the groove 5 on the back surface of the P-type silicon substrate 1.

  When a surge is input from the input terminal 13 to the semiconductor chip having the above configuration, the surge is absorbed by the diode configured by the N + type region 11 and the P + type region 12 as in the first embodiment. However, when a surge that has not been absorbed by the diode flows into the P-type silicon substrate 1, it is absorbed by the electrode 6 formed in the portion corresponding to the groove 5 on the back surface of the P-type silicon substrate 1 and removed to the ground 14. Is done.

  Here, in this embodiment, the electrode 6 is formed on the entire back surface of the P-type silicon substrate 1. For this reason, even if a surge flows out from the input protection unit 10 toward the logic unit 20, the surge can be absorbed by the electrode 6 before the surge reaches the logic unit 20. Therefore, a higher latch-up capability can be ensured.

  As described above, the grooves 5 may be provided on the surface of the P-type silicon substrate 1 so as to reduce the thickness of the P-type silicon substrate 1 in the input protection unit 10.

(Other embodiments)
In the above embodiments, the grooves 2 and 5 may have any shape. Alternatively, the grooves 2 and 5 may not be formed in the P-type silicon substrate 1, but only the electrodes 3 and 6 may be formed. That is, since the electrodes 3 and 6 are provided, the latch-up resistance can be secured only by the electrodes 3 and 6. However, by providing the grooves 2 and 5 and making the P-type silicon substrate 1 thin, the latch-up resistance can be further increased. Can be improved. This is made clear from the simulation in the first embodiment.

  In the first embodiment, the electrode 3 is formed at least on the bottom of the groove 2. However, the electrode 3 may also be formed on the wall of the groove 2. Further, similarly to the second embodiment, the electrode 3 may be formed not only on the wall surface of the groove 2 but also on the entire back surface of the P-type silicon substrate 1.

  In the second embodiment, the electrode 6 is formed on the entire input protection portion 10 and the Logic portion 20 in the back surface of the P-type silicon substrate 1, but corresponds to the groove 5 in the back surface of the P-type silicon substrate 1. You may make it form the electrode 6 only in the part. Alternatively, the electrode 6 formed in the portion corresponding to the groove 5 may be extended to the logic portion 20 and the electrode 6 may be formed only between the input protection portion 10 and the logic portion 20.

  In each of the above embodiments, the CMOS transistor is formed in the Logic unit 20. However, the semiconductor element formed in the Logic unit 20 is not limited to the CMOS transistor, and other semiconductor devices in which latch-up occurs. May be formed.

  In each of the above embodiments, the grooves 2 and 5 are formed to reduce the thickness of the input protection unit 10, but the thickness of the entire P-type silicon substrate 1 is reduced to reduce the thickness of the entire substrate. It doesn't matter.

1 is a schematic cross-sectional view of a semiconductor chip as a semiconductor device according to a first embodiment of the present invention. It is a schematic sectional drawing of the semiconductor chip made into object when performing simulation. It is the figure which showed the correlation of the board | substrate thickness by a simulation, and latchup tolerance. It is a schematic sectional drawing of the semiconductor chip which concerns on 2nd Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... P-type silicon substrate, 2, 5 ... Groove 3, 4, 6 ... Electrode, 10 ... Input protection part, 11 ... N + type | mold area | region, 12 ... P + type | mold area | region, 13 ... Input terminal, 14 ... Ground, 20 ... Logic part.

Claims (4)

A semiconductor device part (20) in which a semiconductor element is formed on the surface side of the semiconductor substrate (1), and a first conductivity type region (11) and a second conductivity type region ( And 12) an input protection unit (10).
In the input protection unit, the first conductivity type region is connected to the input terminal (13), the second conductivity type region is connected to the ground (14), and the surge input to the input terminal is In the semiconductor device removed to the ground via the first conductivity type region and the second conductivity type region,
Electrodes (3, 6) are formed at least on the back surface of the semiconductor substrate so as to face the first conductivity type region, and the electrodes are connected to the ground. apparatus. A recess (2) is formed at least in a position facing the first conductivity type region on the back surface of the semiconductor substrate, and the electrode is formed at least at the bottom of the recess. Item 14. The semiconductor device according to Item 1. A recess (5) is formed in the input protection portion of the surface of the semiconductor substrate, and the first conductivity type region and the second conductivity type region are formed in the surface portion of the semiconductor substrate corresponding to the recess. Has been
2. The semiconductor device according to claim 1, wherein the electrode is formed at a position facing at least the first conductivity type region on the back surface of the semiconductor substrate. 4. The semiconductor device according to claim 1, wherein the electrode is formed on the entire back surface of the semiconductor substrate.

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