JP2007149953A - Manufacturing method of semiconductor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the manufacturing method of semiconductor which is capable of contriving the reduction and the microfabrication of an interlevel membrane capacitance and a capacitance between wirings of a semiconductor device, and which is capable of reducing the manufacturing man-hour of the semiconductor. <P>SOLUTION: The manufacturing method of semiconductor comprises a process for forming a via-hole pattern 7 by a first resist, a process for forming a first interlevel membrane 6a so as to fill at least a part of circumference of the via-hole pattern 7, a process for forming a wiring pattern 8 on the via-hole pattern 7 and the first interlevel membrane 6a by a second resist, a process for forming a second interlevel membrane 6b so as to fill at least a part of the circumference of the wiring pattern 8, a process for forming a dual damascene wiring groove by selectively removing the wiring pattern and the via-hole pattern, and a process for filling the dual damascene wiring groove by a metal layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor manufacturing method including a multilayer wiring using, for example, a low dielectric constant interlayer film.

  With the miniaturization and speeding up of semiconductor devices, low dielectric constant interlayer films have been introduced as interlayer insulating films for multilayer wiring (see, for example, Patent Document 1).

  In general, such a semiconductor device is formed as follows, for example. First, a cap layer / stopper layer is formed on a lower wiring formed on a semiconductor substrate, and a low dielectric constant interlayer film and a resist film are sequentially formed thereon. Then, a resist is patterned, and using this as a mask, via holes are formed by dry etching, and then filled with a low resistance metal to form vias. Then, a cap layer / stopper layer is formed on the low dielectric constant interlayer film in which the via is formed, and a low dielectric constant interlayer film and a resist film are formed thereon. Then, a resist is patterned, and using this as a mask, a wiring groove reaching the via is formed in the low dielectric constant interlayer film by dry etching, and then buried with a low resistance metal to form a wiring layer.

In recent years, in such a semiconductor device, there is a demand for further reduction in the interlayer film capacitance and inter-wiring capacitance and miniaturization. There is also a demand for reduction in manufacturing man-hours from the viewpoint of reducing defects.
JP 2004-221498 A

  An object of the present invention is to provide a semiconductor manufacturing method capable of reducing and miniaturizing the interlayer film capacitance and inter-wiring capacitance of a semiconductor device having a multilayer wiring and reducing the number of manufacturing steps. .

  According to one aspect of the present invention, a step of forming a via pattern with a first resist, a step of forming a first interlayer film so as to fill at least part of the via pattern, and the via Forming a wiring pattern with a second resist on the pattern and the first interlayer film, and forming a second interlayer film so as to fill at least part of the wiring pattern; There is provided a semiconductor manufacturing method comprising: a step of selectively removing the wiring pattern and the via pattern to form a dual damascene wiring groove; and a step of filling the dual damascene wiring groove with a metal layer. The

  According to one embodiment of the present invention, it is possible to reduce and miniaturize the interlayer film capacity and inter-wiring capacity of a semiconductor device having multilayer wiring, and to reduce the number of manufacturing steps.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 shows a multilayer wiring structure of a semiconductor device formed by the semiconductor manufacturing method of this embodiment. As shown in the figure, a cap layer / stopper layer 3 is formed on an interlayer film 1 and a lower wiring layer 2 formed on a semiconductor substrate (not shown). Via 4 is formed so as to be connected to. A wiring layer 5 is formed on the via 4 so as to be connected to the via 4. The via 4 and the wiring layer 5 are separated by interlayer films 6a and 6b made of two low dielectric constant films.

  Such a semiconductor device is formed as follows. First, as shown in FIG. 2, a cap layer / stopper layer 3 made of, for example, a SiN film is formed on an interlayer film 1 and a lower wiring layer 2 formed on a semiconductor substrate (not shown). Then, a negative resist is applied on the cap layer / stopper layer 3, and a via pattern (dummy pattern) 7 made of the negative resist is formed by a normal exposure / development technique. At this time, it is possible to make the pattern finer by forming a larger mask pattern and performing development processing by isotropic etching.

  Next, as shown in FIG. 3, a low dielectric constant film material such as, for example, a methyl group-containing silicon oxide film (MSQ: Methyl Silses Quioxane film) is applied to the entire surface so as to cover the via pattern 7 by a coating method (SOD: Spin On A film is formed using the Dielectrics method), and the film quality is changed by baking or EB (Electron Beam) to change the film quality, thereby forming an interlayer film 6 a that fills and covers the via pattern 7.

  Then, as shown in FIG. 4, a negative resist is applied on the interlayer film 6a, and a wiring pattern (dummy pattern) 8 made of resist is formed by a normal exposure / development technique.

  Next, as shown in FIG. 5, a coating type low dielectric constant film is applied to the entire surface so as to cover the wiring pattern 8, and the film quality is changed by baking or EB curing, so that the space between the wiring patterns 9 is changed. An interlayer film 6b to be filled and covered is formed.

Then, as shown in FIG. 6, the entire surface is etched back by O ₂ RIE (Reactive Ion Etching), so that only the surface of the interlayer film 6b containing Si is made of SiO _{2 and} a high selectivity to the resist (wiring pattern 8) is obtained. Therefore, the resist (wiring pattern 8) is selectively removed and the wiring groove 9 is formed.

Subsequently, as shown in FIG. 7, the entire surface is similarly etched back by O ₂ RIE, so that the surface of the interlayer film 6a containing Si can also be made of SiO ₂ and have a high selectivity with the resist (via pattern 7). Therefore, the resist (via pattern 7) is selectively removed to form a via hole 10 that reaches the cap layer / stopper layer 3.

Then, as shown in FIG. 6, by etching back the entire surface with N ₂ / H ₂ asher simultaneously with UV irradiation, a highly selective film can be formed only on the surface of the interlayer film 6 b containing Si. The wiring pattern 8) is selectively removed to form a wiring groove 9.

Subsequently, as shown in FIG. 7, similarly, the entire surface is etched back by N ₂ / H ₂ asher simultaneously with UV irradiation, so that the surface of the interlayer film 6a containing Si is also made _high as a resist (via pattern 7) as SiO _2. Since the selectivity can be obtained, the resist (via pattern 7) is selectively removed to form the via hole 10 reaching the cap layer / stopper layer 3.

Then, as shown in FIG. 8, the cap layer / stopper layer 3 at the bottom of the via hole 10 is selectively removed by RIE containing gas species such as CF ₄ and CHF _3, and the bottom of the via hole becomes the lower layer wiring 2. To reach.

  Further, as shown in FIG. 9, after a barrier metal / Cu layer (not shown) is formed on the entire surface by sputtering, a Cu film 11 is formed on the entire surface including the via hole 10 and the wiring trench 9 by plating. To do. Then, by removing the Cu film on the surface by CMP (Chemical Mechanical Polishing), a multilayer wiring structure having dual damascene wiring as shown in FIG. 1 is formed.

  In the present embodiment, by leaving the via pattern and the wiring pattern as a pattern (dummy pattern), the via pattern and the wiring pattern can be formed without using a dry etching process, and at the interface position between the via and the wiring layer. Dual damascene wiring can be formed in an interlayer film having a low dielectric constant without forming a cap layer / stopper layer.

  Therefore, it is possible to reduce costs and defects by reducing the number of steps. Further, since the cap layer / stopper layer is not interposed in the low dielectric constant interlayer film, it is possible to reduce the interlayer film capacitance and the inter-wiring capacitance. In addition, since the resist itself becomes an object to be aligned, it is possible to improve the alignment accuracy and improve the fine processing accuracy.

  Furthermore, in this embodiment, as the interlayer films 6a and 6b, a coating type low dielectric constant film formed by a coating method is used. However, by using a coating type low dielectric constant film, the interlayer tension is increased by surface tension. The film can be highly planarized, and the alignment accuracy can be improved when forming a wiring pattern formed in an upper layer.

  In the present embodiment, the interlayer films 6a and 6b are formed so as to cover the dummy pattern (via pattern 7, wiring layer pattern 8), but the dummy pattern is not necessarily covered with the interlayer film. As shown in FIG. 10, even if a part (upper end) of the via pattern 7 ′ is exposed from the interlayer film 6a ′, the wiring pattern 8 ′ is formed in the upper layer as shown in FIG. Dual damascene wiring can be formed.

  In this embodiment, a negative resist is used when forming a dummy pattern, but it is also possible to form a pattern using a positive resist. However, in the exposure technique using a positive resist, there is a limit of miniaturization due to a hole resolution limit. On the other hand, by using a negative resist, a dummy pattern can be miniaturized by development processing by isotropic etching. Therefore, it is preferable to use a negative resist.

Also, in this embodiment, when forming the wiring trench and via hole, etch back is performed by O ₂ RIE, but ashing is performed while protecting the low dielectric constant interlayer film by N ₂ / H ₂ asher. May be.

In this embodiment, when the wiring trench and via hole are formed, the etch back is performed by the N2 / H2 asher. However, even when the low dielectric constant interlayer film is protected by O ₂ RIE, the etching is performed. good.

  A desired dual damascene wiring shape can be formed by appropriately optimizing the film thicknesses of the dummy pattern and the interlayer film according to the etching selectivity between the resist and the interlayer film in RIE.

  In addition, this invention is not limited to embodiment mentioned above. Various other modifications can be made without departing from the scope of the invention.

FIG. 6 illustrates a multilayer wiring structure of a semiconductor device formed by a semiconductor manufacturing method according to one embodiment of the present invention. FIG. 6 illustrates a semiconductor manufacturing process in one embodiment of the present invention. FIG. 6 illustrates a semiconductor manufacturing process in one embodiment of the present invention. FIG. 6 illustrates a semiconductor manufacturing process in one embodiment of the present invention. FIG. 6 illustrates a semiconductor manufacturing process in one embodiment of the present invention. FIG. 6 illustrates a semiconductor manufacturing process in one embodiment of the present invention. FIG. 6 illustrates a semiconductor manufacturing process in one embodiment of the present invention. FIG. 6 illustrates a semiconductor manufacturing process in one embodiment of the present invention. FIG. 6 illustrates a semiconductor manufacturing process in one embodiment of the present invention. FIG. 6 illustrates a semiconductor manufacturing process in one embodiment of the present invention. FIG. 6 illustrates a semiconductor manufacturing process in one embodiment of the present invention.

Explanation of symbols

1, 6a, 6a ', 6b Interlayer film 2 Lower wiring layer 3 Cap layer / stopper layer 4 Via 5 Wiring layer 7, 7' Via pattern 8, 8 'Wiring pattern 9 Wiring groove 10 Via hole 11 Cu film

Claims (5)

Forming a via pattern with a first resist;
Forming a first interlayer film so as to fill at least part of the via pattern; and
Forming a wiring pattern with a second resist on the via pattern and the first interlayer film;
Forming a second interlayer film so as to fill at least part of the periphery of the wiring pattern;
Selectively removing the wiring pattern and the via pattern to form a dual damascene wiring groove;
A semiconductor manufacturing method comprising a step of filling the dual damascene wiring trench with a metal layer.   The semiconductor manufacturing method according to claim 1, wherein the first resist is a negative resist.   The semiconductor manufacturing method according to claim 1, wherein the first interlayer film and the second interlayer film are low dielectric constant films.   4. The semiconductor manufacturing method according to claim 1, wherein, in the step of forming the first interlayer film, the via pattern is covered with the first interlayer film.   4. The semiconductor manufacturing method according to claim 1, wherein in the step of forming the first interlayer film, at least a part of the via pattern is exposed from the first interlayer film. 5. .

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