JP2007144051A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine of convenience in which a game player is capable of counting the number of tokens they obtained without leaving the game machine. <P>SOLUTION: The game machine 1 is provided with a token counting unit 300 comprising a receiving port 301 for receiving the tokens to be counted, a token counting part 310 for counting the tokens received, and a discharge port 302 for discharging the tokens counted to a token receiving plate 16. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a gaming machine.

  Conventionally, a plurality of reels in which a plurality of symbols are drawn on each peripheral surface, and a plurality of reels corresponding to each of these reels are provided, and some of the plurality of symbols drawn on the peripheral surface of each reel A symbol display window for displaying symbols, a stepping motor that individually rotates and drives each reel, an operation by a player to insert medals, coins, and the like into a slot, and an operation of a BET button (hereinafter referred to as “throwing operation”). And a medal sensor or BET switch that outputs a signal designating the number of medals or coins to be inserted in a unit game, and a start lever operation by the player (hereinafter referred to as “ Based on the “start operation”), a plurality of start switches for outputting a signal for instructing the start of rotation of all reels and a plurality of switches corresponding to the respective reels are provided. Based on the operation of the up button (hereinafter referred to as “stop operation”), a stop switch that outputs a signal to stop rotation of each reel and the operation of the stepping motor are controlled, and rotation and stop of all reels are controlled. As a result, there is known a gaming machine (so-called “pachi-slot”) including a control unit that determines a game result (that is, a player's winning or losing) by a combination of symbols displayed on the active line of the symbol display window. ing.

  Such a gaming machine pays out a game value such as a medal to a player according to a game result. The player can exchange medals and prizes according to the number of medals paid out. However, in order for a player to count the number of medals paid out, it is necessary to carry medals to a predetermined place where a medal counting device is installed. Until the time of exchange, the number of medals was not counted, and the number of medals held during the game was not grasped.

Under such circumstances, there is known a gaming machine including medal counting means for stacking medals and counting the number of medals in the vicinity of a receiving tray for storing paid-out medals (for example, Patent Document 1). According to the gaming machine, the number of medals can be easily counted without carrying the medals to a predetermined place where the medal counting device is installed.
JP-A-2005-80966

  However, in the above-described gaming machine, the number of medals that can be counted is limited to a small amount, and the practicality is low as a means for counting the number of medals, and may not be convenient.

  The present invention has been made in view of the above problems, and provides a convenient gaming machine that allows a player to count the number of gaming values such as medals acquired by the player without leaving the gaming machine. The purpose is to do.

  In order to solve the above-described problems, a gaming machine according to the present invention includes a housing (for example, a cabinet 1a described later) having an opening on the front side, and a door (for example, a front surface described later) that opens and closes the opening. The game value (for example, medal) according to the combination of the door 1b), a symbol display portion (for example, symbol display windows 4L, 4C, 4R described later) and a symbol displayed on the symbol display portion. A game value paying unit (for example, a hopper 40 and a hopper driving circuit 41 described later), a tray for storing the game value paid out by the game value paying unit (for example, a medal tray 16 described later), A game value counting unit (for example, a medal counting unit 300 described later) for counting the number of game values paid out, and the game value counting unit receives the game value to be counted. A receiving entrance (for example, a receiving port 301 described later), a gaming value counting unit (for example, a medal counting unit 310 described later) for counting the received gaming value, and a drain for discharging the counted gaming value to the receiving tray. And an outlet (for example, an outlet 302 described later).

  With this configuration, the gaming machine of the present invention counts the gaming value received from the receiving port in the gaming value counting unit, and discharges the counted gaming value from the outlet to the tray.

  According to the gaming machine of the present invention, the player can count the number of gaming values acquired by the player without leaving the gaming machine. That is, the gaming machine of the present invention can improve the convenience for the player.

  In addition, in the gaming machine according to the present invention, the saucer includes a first saucer (eg, a later-described later plate) having a bottom plate (eg, a later-described bottom plate 161) and both side plates (eg, a later-described left-side plate 162, a right-side plate 163). A medal receiving portion main body 160), a front plate (for example, a front plate 174 described later), a bottom plate (for example, a bottom plate 171 described later), and both side plates (for example, a left plate 172 and a right plate 173 described later), And a second tray (for example, a later-described drawer plate 170) provided to the first tray so as to be capable of being pulled out along the bottom plate and both side plates of the first tray. Gaming machine.

  With this configuration, the gaming machine of the present invention can pull out the second tray having the front plate, the bottom plate, and both side plates along the first tray having the bottom plate and both side plates.

  According to the gaming machine of the present invention, the player can pull out the second saucer and store more game value in the saucer. Therefore, when the game value is counted by the game value counting unit, The game value can be counted at once. In other words, the gaming machine of the present invention can reduce the number of times that the player transfers the game value from the tray to the box containing the game value, and can improve the convenience of the player.

  Therefore, according to the gaming machine of the present invention, the player can count the number of game values acquired by the player without leaving the gaming machine. That is, the gaming machine of the present invention can improve the convenience for the player.

  The gaming machine of the present invention will be specifically described below with reference to the drawings. In the following embodiment, as a gaming machine of the present invention, a gaming machine having three rotating reels that variably display symbols, in addition to coins, medals, tokens, etc., a card given to a player A description will be given using a game machine capable of playing using a game medium such as a so-called pachislot machine. In the following embodiments, a pachislot gaming machine will be described as an example. However, the gaming machine of the present invention is not limited and may be a pachinko machine or a slot machine.

  First, an overview of the gaming machine according to the present embodiment will be described with reference to FIGS. 1 is a perspective view of the gaming machine 1 according to the present embodiment, and FIG. 2 is a side view of the gaming machine 1 according to the present embodiment.

  As shown in FIG. 1, the gaming machine 1 includes a cabinet 1a that houses reels 3L, 3C, and 3R, a main control circuit 60 (see FIG. 5) that will be described later, and the like, and a front surface that can be opened and closed with respect to the cabinet 1a. And a door 1b. In addition, the cabinet 1a of this embodiment comprises the housing | casing of this invention, and the front door 1b comprises the door of this invention.

  A panel display portion 2a and a liquid crystal display portion 2b are formed as substantially vertical surfaces on the front surface of the central portion of the cabinet 1a. Three reels 3L, 3C, and 3R are rotatably provided in a horizontal row inside the front of the central portion of the cabinet 1a (the back of the liquid crystal display portion 2b). On the three reels 3L, 3C, 3R, a symbol row composed of a plurality of types of symbols is drawn on each outer peripheral surface. The symbols of the reels 3L, 3C, and 3R can be seen through the symbol display windows 4L, 4C, and 4R. Each reel 3L, 3C, 3R is controlled by a main control circuit 60 (see FIG. 5), which will be described later, so as to rotate at a constant speed (for example, 80 revolutions / minute), and within the symbol display windows 4L, 4C, 4R. The symbols drawn on the reels 3L, 3C, 3R vary as the reels rotate. In addition, the symbol display windows 4L, 4C, and 4R of the present embodiment constitute a symbol display unit of the present invention.

  In addition, the gaming machine 1 receives a winning that serves as a reference for determining success or failure of winning based on the symbols displayed on the symbol display windows 4L, 4C, and 4R when the rotation of the reels 3L, 3C, and 3R is stopped. A line is provided. As the winning lines, a top line 8b, a center line 8c and a bottom line 8d are provided in the horizontal direction, and a cross-up line 8a and a cross-down line 8e are provided in the oblique direction.

  The five winning lines 8a to 8e are basically operated by operating a 1-BET button 11, a 2-BET button 12, and a maximum BET button 13, which will be described later, or by inserting medals into the medal slot 22. Each one, three, and five are activated (hereinafter, the activated winning line is referred to as an activated line). Which winning line is activated is displayed by lighting of BET lamps 9a, 9b, 9c, which will be described later. The determination of the display combination, which will be described later, is performed based on the combination of symbols displayed along this effective line.

  A substantially horizontal pedestal 10 is formed below the panel display 2a and the liquid crystal display 2b. On the left side of the pedestal 10, a 1-BET button 11, a 2-BET button 12, and a maximum BET button 13 for betting credited medals by a push button operation are provided. The 1-BET button 11 is inserted with one of the credited medals by a single pressing operation. The 2-BET button 12 is inserted with two of the credited medals by a single pressing operation. The maximum BET button 13 is a single push operation, and three of the credited medals {that is, the maximum number that can be inserted in a unit game (hereinafter referred to as “maximum number of inserted sheets”)} Is inserted. By operating these BET buttons 11, 12, and 13, the above-described winning line is activated.

  On the right side of the pedestal portion 10, a medal slot 22 is provided. The above-described winning line is activated according to the medal inserted into the medal slot 22.

  A C / P button 14 is provided on the left side of the front surface of the pedestal 10 to switch between credit (Credit) / payout (Pay) of medals acquired by the player in the game. The payout mode or the credit mode is switched by the player's operation on the C / P button 14. In the credit mode, when a winning is established, medals for the number of payouts corresponding to the winning are credited. In the payout mode, when a winning is established, medals corresponding to the payout are paid out from the medal payout opening 15 at the lower front, and the medals paid out from the medal payout opening 15 are stored in the medal tray 16.

  The medal tray 16 is provided at the lowermost portion of the front door 1b and stores medals paid out from the payout opening 15. The medal tray 16 includes a medal receiving portion main body 160 and a drawer tray 170. The medal tray body 160 includes a bottom plate 161 (see FIG. 2), a left side plate 162, and a right side plate 163, and is provided on the front door 1b. On the other hand, the drawer tray 170 is slidably provided on the outside of the medal tray main body 160, and includes a bottom plate 171 (see FIG. 2), a left side plate 172, a right side plate 173, and a front plate 174. . Further, grooves 164 are formed on the outer surfaces of the side plates 162 and 163 of the medal tray body 160 along the pulling direction of the drawer plate 170, and the pulling direction is formed on the inner surfaces of the side plates 172 and 173 of the drawer plate 170. A protrusion 175 that engages with the groove 164 is formed. Thereby, the drawer tray 170 can be pulled out to the near side with respect to the medal tray main body 160. In addition, the medal tray 16 of this embodiment comprises the saucer of this invention, and the medal receiving part main body 160 and the drawer tray 170 comprise a 1st saucer and a 2nd saucer, respectively.

  A clear button 200 is provided on the right side of the front surface of the pedestal 10. By the player's operation on the clear button 200, the medal counting unit 300, which will be described later, counts and the number of medals accumulated and displayed by the liquid crystal display device 5 is cleared to zero.

  Speakers 21 </ b> L and 21 </ b> R are provided on the left and right above the medal tray 16. The speakers 21L and 21R output game sounds such as performance sounds and notification sounds according to the game situation.

  A medal counting unit 300 is provided below the pedestal 10 and above the speakers 21L and 21R. As shown in FIG. 2, the medal counting unit 300 counts the number of medals M inserted from the receiving port 301 by the player at the medal counting unit 310, and the medal M that has been counted is received from the outlet 302 as a medal tray. 16 to discharge. The counted number of medals M is displayed by the liquid crystal display device 5. The medal counting unit 300 can be stored in the front door 1b. Further, the medal counting unit 300 of the present embodiment constitutes a gaming value counting unit of the present invention, the receiving port 301 constitutes a receiving port of the present invention, and the medal counting unit 310 is a gaming value counting unit of the present invention. The discharge port 302 forms the discharge port of the present invention. Details of the medal counting unit 310 will be described later.

  A start lever 6 is provided on the right side of the C / P button 14. The start lever 6 rotates the reels 3L, 3C, and 3R by a player's start operation, and starts changing the symbols displayed in the symbol display windows 4L, 4C, and 4R.

  Three stop buttons 7L, 7C, and 7R for stopping the rotation of the three reels 3L, 3C, and 3R by the player's stop operation are located on the right side of the start lever 6 at the center of the front surface of the pedestal 10, respectively. Is provided. Here, when the three reels 3L, 3C, and 3R are rotating, the first stop of the rotation of the reels is referred to as a first stop, which is performed after the first stop and the two reels are rotated. The second stop of the rotation of the reel that is performed when the operation is performed is referred to as the second stop, which is performed after the second stop, and is performed last when the rotation of the remaining one reel is performed. Stopping the rotation of the reel is referred to as a third stop.

  An LED 101 and a lamp 102 are provided on the upper portion of the front door 1b. The LED 101 and the lamp 102 emit light in a light emission pattern according to the game situation, and effects and notifications are performed.

  The panel display unit 2 a includes a WIN lamp 17, BET lamps 9 a to 9 c, a payout number display unit 18, and a credit display unit 19.

  The WIN lamp 17 notifies the player that the combination of symbols related to the operation of the bonus can be displayed (for example, a carryover state described later) by lighting. The 1-BET lamp 9a, the 2-BET lamp 9b, and the maximum BET lamp 9c are unit games (for example, one game from the start of reel rotation until the reel rotation stops and a game result is obtained). The lighting is performed according to the number of medals inserted to perform (that is, the number of inserted medals). The 1-BET lamp 9a is turned on when the number of inserted sheets is one and one winning line 8c is activated. The 2-BET lamp 9b is turned on when the number of inserted coins is two and the three pay lines 8b, 8c, 8d are activated. The maximum BET lamp 9c is turned on when the number of inserted coins is three and all winning lines 8a to 8e are activated.

  The payout number display unit 18 and the credit display unit 19 are each composed of a 7-segment LED, and display the payout number of medals at the time of winning and the number of stored medals.

  The liquid crystal display unit 2b is disposed on the front side of the reels 3L, 3C, and 3R when viewed from the front side, and displays an image and is displayed on the reels 3L, 3C, and 3R on the symbol display windows 4L, 4C, and 4R. The displayed design is displayed transparently. Further, the liquid crystal display unit 2 b displays various images displayed by the liquid crystal display device 5.

  The liquid crystal display unit 2b has an effect display area 23, a frame image having a predetermined shape so as to surround the symbol display windows 4L, 4C, and 4R, and a background image constituting a predetermined image or a background in the image at the time of the effect. Display images that contain. The medal number display area 24 of the effect display area 23 displays the number of medals counted by the medal counting unit 300.

  Next, the medal counting unit 310 will be described with reference to FIG. FIG. 3A is a plan view of the medal counting unit 310 according to the present embodiment, and FIG. 3B is a view taken along the line bb in FIG.

  The medal counting unit 310 is provided inside the medal counting unit 300. The medal counting unit 310 includes a rotating disk 311 arranged horizontally, a lead-out port 312 provided near the outer periphery of the disk, a conveyance path including guide members 313 and 314, and a counting sensor. 315. The conveyance path includes guide members 313 and 314 for aligning medals M in a row, and a conveyance belt 316 for moving the medals M in contact with the upper surfaces of the aligned medals M, and a lead-out port 312 connected to one end thereof. The medals M discharged from are conveyed to a counting sensor 315 provided at the other end.

  Accordingly, when the medal M is inserted into the receiving port 301 of the medal counting unit 300, the medal M moves radially outward on the rotating disk 311 by centrifugal force, and moves one by one from the outlet 312 to the conveyance path. Sent out. The medal M sent to the conveyance path is conveyed between the guide members 313 and 314 by the conveyance belt 316, passes through the counting sensor 315, and is discharged from the discharge port 302 to the medal tray 16. Here, the count sensor 315 outputs a count-up signal to the image control microcomputer 72 every time the medal M passes.

  Next, with reference to FIG. 4, the symbol sequence arranged on the reels 3L, 3C, 3R will be described. FIG. 4 is a diagram showing an arrangement of symbols drawn on the reels 3L, 3C, and 3R of the gaming machine 1 according to the present embodiment.

  A reel sheet is mounted on the outer peripheral surface of each reel 3L, 3C, 3R, and a symbol row in which 21 types of symbols are arranged on the reel sheet is drawn. Specifically, a symbol row composed of symbols of white 7, cherry, watermelon, bell, replay and blank is drawn.

  For each symbol, a code number “00 to 20” for specifying the position of each symbol is determined in advance and stored as a data table in the ROM 32 of the main control circuit 60 described later with reference to FIG. .

  Next, the circuit configuration of the gaming machine 1 including a peripheral device (actuator) electrically connected to the main control circuit 60, the sub control circuit 61, the main control circuit 60, or the sub control circuit 61 will be described with reference to FIG. To do. FIG. 5 is a diagram showing a circuit configuration of the gaming machine 1.

  The main control circuit 60 includes a microcomputer 30 disposed on a circuit board as a main component, and is added to a circuit for random number sampling. The microcomputer 30 includes a main CPU 31 and ROM 32 and RAM 33 which are storage means.

  The main CPU 31 is connected to a clock pulse generation circuit 34, a frequency divider 35, a random number generator 36, and a sampling circuit 37. The clock pulse generation circuit 34 and the frequency divider 35 generate a reference clock pulse.

  The random number generator 36 generates random numbers within a certain range. The sampling circuit 37 extracts (samples) one random number value from the random number generated by the random number generator 36. Further, in the gaming machine 1, the random value extracted in the unit game is stored in a random value storage area of the RAM 33 described later. Then, by using a random value stored in the random value storage area of the RAM 33 for each unit game, an internal lottery process described later is performed to determine an internal winning combination.

  In addition, as a means for random number sampling, you may make it the structure which performs random number sampling within the microcomputer 30, ie, on the operation program of the main CPU31. In that case, the random number generator 36 and the sampling circuit 37 can be omitted, or can be left as a backup for the random number sampling operation.

  The ROM 32 of the microcomputer 30 stores a program (for example, see FIGS. 13 to 20 described later), various tables (for example, see FIG. 4 and FIGS. 7 to 11 described later), bonus check data (for example, see FIG. Various control commands (commands) to be transmitted to the sub-control circuit 61 are stored.

  Various information obtained by the processing of the main CPU 31 is set in the RAM 33. For example, information for specifying the extracted random number value, gaming state, payout number, etc. is set. These pieces of information are transmitted to the sub-control circuit 61 by the aforementioned command.

  In the circuit of FIG. 5, the main actuators whose operation is controlled by a control signal from the microcomputer 30 are BET lamps 9a, 9b, 9c, a WIN lamp 17, a payout number display unit 18, a credit display unit 19, and a hopper 40. There are stepping motors 49L, 49C, 49R and the like. The exchange of signals between these actuators and the main CPU 31 is performed via the I / O port 38.

  In addition, each circuit for controlling the operation of each actuator described above is connected to the output unit of the microcomputer 30 in response to a control signal output from the main CPU 31. Each circuit includes a motor drive circuit 39, a lamp drive circuit 45, a display unit drive circuit 48, and a hopper drive circuit 41.

  The lamp driving circuit 45 controls the drive of the BET lamps 9a, 9b, 9c and the WIN lamp 17. Thereby, the BET lamps 9a, 9b, 9c and the WIN lamp 17 are turned on and off.

  The display unit drive circuit 48 drives and controls the payout number display unit 18 and the credit display unit 19. As a result, various information (such as the number of credits) is displayed on the payout number display unit 18 and the credit display unit 19.

  The hopper drive circuit 41 drives and controls the hopper 40. Thereby, the medal accommodated in the hopper 40 is paid out. Note that the hopper drive circuit 41 and the hopper 40 of the present embodiment constitute a game value payout unit of the present invention.

  The motor drive circuit 39 drives and controls the stepping motors 49L, 49C, 49R. As a result, the reels 3L, 3C, and 3R are rotated and stopped.

  Also, each switch and each circuit for generating an input signal that triggers outputting a control signal to each circuit and each actuator described above are connected to the input section of the microcomputer 30. Each switch and circuit includes a start switch 6S, stop switches 7LS, 7CS, 7RS, 1-BET switch 11S, 2-BET switch 12S, maximum BET switch 13S, C / P switch 14S, medal sensor 22S, reel position detection. There are a circuit 50 and a payout completion signal circuit 51.

  The start switch 6S detects a player's start operation with respect to the start lever 6, and outputs a start signal instructing the start of the unit game to the microcomputer 30. At this time, in order to perform automatic stop, the microcomputer 30 sets an automatic stop timer based on the input start signal and measures a predetermined time (for example, 40 seconds).

  This automatic stop means that when a stop signal from the stop switch 7LS, 7CS, 7RS is not detected within a predetermined time counted based on the input start signal, the microcomputer 30 This means that the reels 3L, 3C, and 3R are controlled to stop by outputting a control signal to the motor drive control circuit 39 without being based on the player's stop operation. Further, when the microcomputer 30 performs this automatic stop, the reels 3L, 3C, 3R are arranged so that the combination of symbols stopped on the active line is the most unfavorable aspect for the player, that is, loses. Command to stop the rotation of.

  The stop switches 7LS, 7CS, and 7RS detect the player's stop operation on the stop buttons 7L, 7C, and 7R, respectively, and stop the rotation of the reels 3L, 3C, and 3R corresponding to the detected stop buttons 7L, 7C, and 7R. A stop signal to be commanded is output to the microcomputer 30.

  The BET switches 11S to 13S detect a player's insertion operation for each BET button, and output a signal instructing insertion of one, two, or three medals from the credited medals to the microcomputer 30. .

  The C / P switch 14S detects a player's switching operation on the C / P button 14, and outputs a signal for switching the credit mode or the payout mode to the microcomputer 30. When the credit mode is switched to the payout mode, a signal for instructing the payout of medals credited to the gaming machine 1 is output to the microcomputer 30.

  The medal sensor 22S detects medals inserted into the medal insertion slot 22 by the player's insertion operation, and outputs a signal indicating that a medal has been inserted to the microcomputer 30.

  The reel detection circuit 50 detects a pulse signal from the reel rotation sensor and generates a signal for detecting the position of the symbol on each reel 3L, 3C, 3R.

  The payout completion signal circuit 51 indicates that the payout of medals is completed when the number of medals detected by the medal detection unit 40S (that is, the number of medals paid out from the hopper 40) reaches the designated number. For generating a signal.

  The sub-control circuit 61 performs various processes such as determination and execution of effect contents based on various commands output from the main control circuit 60 such as a start command described later. The sub control circuit 61 does not input commands, information, or the like to the main control circuit 60, and communication is performed in one direction from the main control circuit 60 to the sub control circuit 61.

  The main actuators whose operation is controlled by a control signal from the sub control circuit 61 include the liquid crystal display device 5, the speakers 21L and 21R, the LED 101, the lamp 102, and the motor 300. The sub-control circuit 61 determines and displays an image displayed on the liquid crystal display device 5 based on the determined content of the effect, determines and outputs the lighting pattern of the LED 101 and the lamp 102, and the effect sound output from the speakers 21L and 21R. Control of sound and sound effects and output.

  In the present embodiment, the sub control circuit 61 is connected to the clear button 200 and the medal counting unit 310 of the medal counting unit 300. Details of the configuration of the sub control circuit 61 in the present embodiment will be described later.

  In the gaming machine 1, when a signal for starting a unit game is output from the start switch 6S by a player's operation on the start lever 6 on condition that a medal is inserted, a control signal is output to the motor drive circuit 39, and stepping is performed. The rotation of the reels 3L, 3C, 3R is started by drive control of the motors 49L, 49C, 49R (for example, excitation to each phase). At this time, the number of pulses output to the stepping motors 49L, 49C, 49R is counted, and the counted value is set in a predetermined area of the RAM 33 as a pulse counter. In the gaming machine 1, when the “16” pulse is output, the reels 3L, 3C, and 3R move by one symbol. The number of symbols moved is counted, and the counted value is set in a predetermined area of the RAM 33 as a symbol counter. That is, every time the pulse counter counts “16”, the symbol counter is updated by “1”.

  A reel index is obtained from the reels 3L, 3C, and 3R for each rotation and is output to the main CPU 31 via the reel position detection circuit 50. With the output of the reel index, the pulse counter and the symbol counter set in the RAM 33 are cleared to “0”. In this way, the symbol position within one rotation range is specified for each reel 3L, 3C, 3R.

  Here, in the ROM 32, a symbol arrangement table (see FIG. 4) is stored in the ROM 32 in order to associate the rotational positions of the reels 3L, 3C, and 3R with the symbols drawn on the outer peripheral surface of the reel. ing. In this symbol arrangement table, the code numbers from “00” to “20”, which are sequentially given for each fixed rotation pitch of each of the reels 3L, 3C, and 3R, with the position where the reel index is output as a reference, A symbol code for identifying the type of symbol provided corresponding to each code number is associated.

  When a start signal is output from the start switch 6S, a random number value is extracted by the random number generator 36 and the sampling circuit 37. In the gaming machine 1, when the random value is extracted, it is stored in the random value storage area of the RAM 33. Then, an internal lottery process, which will be described later, is performed based on the random number value stored in the random value storage area, and an internal winning combination is determined.

  After the reels 3L, 3C, and 3R have reached constant speed rotation, when a stop signal is output from the stop switches 7LS, 7CS, and 7RS by a stop operation, based on the output stop signal and the determined internal winning combination, A control signal for stopping and controlling the reels 3L, 3C, 3R is output to the motor drive circuit 39. The motor drive circuit 39 drives and controls the stepping motors 49L, 49C, 49R, and stops the rotation of the reels 3L, 3C, 3R.

  In addition, when the predetermined time has elapsed after the reels 3L, 3C, and 3R have reached constant speed rotation and the automatic stop timer becomes “0”, the automatic stop is performed. Therefore, the reels 3L, 3L, A control signal for stopping and controlling 3C and 3R is output to the motor drive circuit 39.

  When the reels 3L, 3C, and 3R are controlled to stop, a table that determines the stop positions of the reels 3L, 3C, and 3R that are selected by the stop operation for each gaming state and for each internal winning combination (hereinafter referred to as a table). The stop position determination table is stored in the ROM 32. The control signal for controlling the stop of the reels 3L, 3C, 3R is selected based on the gaming state and the determined internal winning combination, and the stop position determination table is selected and the selected stop position determination table and the stop operation are selected. Based on this, a predetermined symbol of each reel 3L, 3C, 3R is output to the motor drive circuit 39 so as to be displayed in the symbol display windows 4L, 4C, 4R. However, as described above, when the automatic stop is performed, the control signal for controlling the stop of the reels 3L, 3C, and 3R indicates that the combination of symbols stopped on the effective line is the most disadvantageous to the player. As shown in FIG.

  When the rotation of all the reels 3L, 3C, 3R is stopped, the display combination retrieval process is performed based on the combination of symbols displayed at a predetermined position (for example, the center line 8c). The display combination is searched based on a symbol combination table (see FIG. 7 described later) stored in the ROM 32. In this symbol combination table, a symbol combination related to a display combination and a corresponding payout are set.

  When it is determined by the display combination search that a combination of symbols related to winning is displayed, a control signal is output to the hopper driving circuit 41 and the hopper 40 is driven to pay out medals. At this time, the medal detection unit 40S counts the number of medals to be paid out from the hopper 40, and when the count value reaches the designated number, the payout completion signal circuit 51 outputs a signal indicating completion of the medal payout. The Thereby, a control signal is output to the hopper drive circuit 41, and the drive of the hopper 40 is stopped.

  When the credit mode is switched by the C / P switch 14S, if it is determined that the winning symbol combination is displayed, the payout amount corresponding to the winning symbol combination is stored in the credit of the RAM 33. Add to the number counter. Further, a control signal is output to the display unit driving circuit 48 and the value of the credit number counter is displayed on the credit display unit 19. Here, there is a case where a medal payout or a credit performed when a combination of symbols related to winning is displayed is simply referred to as “payout”.

  Next, the circuit configuration of the sub-control circuit 61 will be described with reference to FIG. FIG. 6 is a diagram showing a circuit configuration of the sub control circuit of the gaming machine 1.

  As shown in FIG. 6, the sub control circuit 61 includes an image control circuit 70 and a sound / lamp control circuit 90. The image control circuit 70 controls the liquid crystal display device 5. The sound / lamp control circuit 90 controls sound output from the speakers 21L and 21R and lighting of the LED 101 and the lamp 102.

  The image control circuit 70 includes a serial port 71, an image control microcomputer 72, a program ROM 73, a work RAM 74, a calendar IC 75, an image control IC 76, an image ROM 79, and a video RAM 80.

  The serial port 71 receives a command output from the main control circuit 60. The serial port 71 outputs a command generated by the image control microcomputer 72 to the sound / lamp control circuit 90.

  The image control microcomputer 72 performs display control of the liquid crystal display device 5 based on a program stored in the program ROM 73. Specifically, the image control microcomputer 72 receives a command indicating a gaming state, a winning combination, and the like from the main control circuit 60, and data related to date and time (hereinafter referred to as “date and time data”) from the calendar IC 75. Acquired and stored in the work RAM 74. The image control microcomputer 72 executes the program while referring to the game state identifier, winning combination identifier, date / time data, and the like stored in the work RAM 74, whereby the liquid crystal display device 5, the speakers 21L and 21R, the LED 101, the lamp 102, and the like. The effect identifier and the effect data for defining the contents of the effect are determined.

  Further, the image control microcomputer 72 outputs a control command to the sound / lamp control circuit 90 via the serial port 71 based on the determined effect identifier and effect data.

  Further, in the present embodiment, the clear button 200 and the medal counting unit 310 of the medal counting unit 300 are connected to the image control microcomputer 72. The image control microcomputer 72 receives the count-up signal output from the medal counting unit 310 by executing the program stored in the program ROM 73 and performs display control of the number of medals displayed by the liquid crystal display device 5. .

  The program ROM 73 stores programs such as an image control program executed by the image control microcomputer 72 (for example, see FIGS. 21 to 23 and 25 to 31 described later) and various tables.

  The work RAM 74 is used as temporary work storage means when the image control microcomputer 72 executes each program. For example, the work RAM 74 stores information such as commands transmitted from the main control circuit 60, gaming identifiers, effect identifiers, gaming state identifiers, carryover combination identifiers, winning combination identifiers, medal counting counters, and the like.

  The calendar IC 75 stores date / time data input from an operation unit (not shown) of the gaming machine. The image control microcomputer 72 executes various effects using the date / time data. Note that the data stored in the aforementioned work RAM 74 and calendar IC 75 is data to be backed up.

  An image control IC 76 (hereinafter also referred to as VDP) includes a control RAM 77 that stores image data, date / time data, and the like transmitted from the image control microcomputer 72, and a D / A converter 78 that converts the image data into an image signal. It is equipped with.

  The image control IC 76 performs display control for the liquid crystal display device 5. When receiving an image display command or the like from the image control microcomputer 72, the image control IC 76 reads image data stored in the image ROM 79 or the work RAM 74 in order to display an image on the liquid crystal display device 5.

  The image control IC 76 sequentially superimposes the image data read from the image ROM 79 or the work RAM 74 from the background image located at the rear to the image located at the front, and stores the data in a video RAM 80 described later, thereby synthesizing the image data. Is supplied to the D / A converter 78 at the timing of The D / A converter 78 converts the image data into an image signal and supplies it to the liquid crystal display device 5. As a result, an image is displayed on the liquid crystal display device 5.

  The control RAM 77 is used as temporary storage means when the image control microcomputer 72 executes an image control program. Various variables such as a VDP counter are assigned to the control RAM 77 of the present embodiment. This VDP counter is incremented based on a clock signal transmitted from the image control IC 76 to the image control microcomputer 72, and from the timing when the bank control instruction described later is sent from the image control microcomputer 72 to the image control IC 76 last time. Used to determine whether 1/30 seconds or more have elapsed.

  The image ROM 79 stores image data constituting an image displayed on the liquid crystal display device 5.

  The video RAM 80 is used as a temporary storage unit when the image control IC 76 generates a display image from the image data. The video RAM 80 is composed of two frame buffers, a write image data area for storing image data transferred from the image control IC 76 and a display image data area for storing image data displayed on the liquid crystal display device 5. Yes. These frame buffers are alternately switched by the image control IC 76 (that is, the banks are switched), whereby image data is sequentially supplied to the liquid crystal display device 5.

  The sound / lamp control circuit 90 includes a serial port 91, a sound / lamp control microcomputer 92, a work RAM 93, a program ROM 94, a sound source IC 95, a power amplifier 96, and a sound source ROM 97.

  The serial port 91 receives a command generated by the image control microcomputer 72 via the serial port 71.

  The sound / lamp control microcomputer 92 controls the lighting of the LED 101 and the lamp 102 and the output sound of the speakers 21L and 21R based on the program stored in the program ROM 94. Specifically, the sound / lamp control microcomputer 92 receives a command from the image control circuit 70 and stores it in the work RAM 93. The sound / lamp control microcomputer 92 executes the program (see FIG. 24) stored in the program ROM 94 based on the information stored in the work RAM 93, and controls the sound source IC 95 and the lighting of the LED 101 and the lamp 102. I do.

  The sound source IC 95 reads the sound data stored in the sound source ROM 97 and amplifies the read sound data using the power amplifier 96 in accordance with control by the sound / lamp control microcomputer 92.

  Next, with reference to FIG. 7, the display combination corresponding to the displayed symbol combination and its payout will be described. FIG. 7 is a diagram showing an example of the symbol combination table of the gaming machine 1 of the present embodiment.

  The symbol combination table defines the display combination corresponding to the combination of symbols displayed on the active line and the number of payouts for the display combination for each inserted number of medals. Cherry, bell, watermelon, replay, and BB (so-called “big bonus”) are set as the display combination of the gaming machine 1. Here, cherry, bell, and watermelon are collectively referred to as “small role”.

  As shown in FIG. 7, the cherry is established when the cherry symbol is on the effective line and displayed on the left symbol display window 4 </ b> L. As a result, the cherry is won. When the number of inserted medals is 3, 4 medals are paid out.

  The bell is established by displaying three bell symbols side by side along the active line. As a result, Bell wins. When the number of inserted medals is 3, 10 medals are paid out.

  A watermelon is established by displaying three watermelon symbols along the active line. This is a watermelon prize. When the number of inserted medals is 3, eight medals are paid out.

  Replay is established when three replay symbols are displayed side by side along the active line. Thereby, the re-game is performed in the next unit game. That is, the same number of medals as the number of coins inserted in the unit game in which replay is established are automatically inserted in the next unit game without being based on the player's insertion operation. Thereby, the player can perform the next unit game without consuming medals. Here, the above-mentioned medal payout and re-game are examples of giving a game medium.

  BB is established when three white 7 symbols are displayed side by side along the active line, and thereafter, the gaming state of the gaming machine 1 becomes the BB operating state. When the gaming state of the gaming machine 1 becomes the BB operation state, the RB gaming state continuously operates until the number of medals paid out exceeds 350. In the RB gaming state, there is a high probability that an internal winning combination (that is, a bell) having a larger number of payouts than other internal winning combinations is determined. Further, the RB gaming state is ended when the number of unit games performed in the RB gaming state reaches 12 times or when the number of winnings reaches 8 times. However, even before the termination condition is satisfied, if the BB operation state is terminated because the number of paid-out medals exceeds 350, the RB gaming state is also terminated accordingly.

  Further, when a symbol combination other than the symbol combinations related to cherry, bell, watermelon, replay, and BB is displayed, a loss is established.

  Next, a lottery count determination table used when determining an internal winning combination in an internal lottery process (see FIG. 15) described later will be described with reference to FIG. FIG. 8 is a diagram illustrating an example of a lottery count determination table of the gaming machine 1 according to the present embodiment.

  The lottery count determination table defines the number of lotteries corresponding to each gaming state. Specifically, the lottery count determination table defines “5” as the number of lotteries when the gaming state is the general gaming state, and “3” as the number of lotteries when the gaming state is the RB gaming state. Is prescribed. However, in the case of the BB carryover state described later, the number of lotteries is updated to “4” in the process of step S33 of the internal lottery process. Note that the number of lotteries is the number of times that a lottery value (to be described later) is subtracted from a random value stored in the random value storage area of the RAM 33 in the internal lottery process (step S36).

  Next, an internal lottery table used when determining an internal winning combination in an internal lottery process (see FIG. 15) described later will be described with reference to FIG. FIG. 9 (1) is a diagram showing an example of an internal lottery table for a general gaming state of the gaming machine 1 of the present embodiment. FIG. 9 (2) is a diagram showing an example of an internal lottery table for RB gaming state of the gaming machine 1 of the present embodiment.

  The internal lottery table includes an internal lottery table for a general gaming state that is used when the gaming state is a general gaming state, and an internal lottery table for an RB gaming state that is used when the gaming state is an RB gaming state. is there. The internal lottery table defines lottery values determined based on the winning number and the number of medals inserted. For example, in the internal lottery table for general gaming state, when the winning number is “5” and the number of inserted medals is 3, the lottery value is defined as “250”.

  Here, the winning number is a number having a value of “0 to 5” used when determining the internal winning combination. The values “0 to 5” correspond to lose, cherry, bell, watermelon, replay, and BB, respectively, as shown in an internal winning combination determination table (see FIG. 10) described later. The gaming machine 1 determines the internal winning combination by determining the winning number in the internal lottery process. The lottery value is a value that is subtracted from the random number value stored in the RAM 33 when determining the internal winning combination in the process of step S36 of the internal lottery process.

  In the present embodiment, the RB gaming state internal lottery table is set to have one medal inserted per unit game in the RB gaming state, so the number of inserted medals is two or three. It does not stipulate in some cases.

  Next, an internal winning combination determination table used when determining an internal winning combination in an internal lottery process (see FIG. 15) described later will be described with reference to FIG. FIG. 10 is a diagram illustrating an example of the internal winning combination determination table of the gaming machine 1 according to the present embodiment.

  The internal winning combination determination table defines an internal winning combination corresponding to the winning number and a bit pattern indicating the internal winning combination. For example, when the winning number is “5”, the internal winning combination determination table defines BB as the internal winning combination and “00010000” as the bit pattern of the internal winning combination.

  Next, referring to FIG. 11, the BB operation state and the RB gaming state are ended in the BB operation process (see step S92 in FIG. 18) and the RB operation process (see step S53 in FIG. 14) described later. The bonus operation time table used when setting the conditions to be performed will be described. FIG. 11 is a diagram showing an example of the bonus operation time table of the gaming machine 1 of the present embodiment.

  The bonus operation time table defines the value of the bonus end number counter that is a condition for ending the BB operation state, and also defines the value of the possible number of games and the number of possible winnings that are conditions for ending the RB gaming state. Specifically, in the bonus operation time table, “350” is defined as the value of the bonus end number counter which is a condition for ending the BB operation state, and the possible number of games and the number of possible winnings are the conditions for ending the RB gaming state. The values of “12” and “8” are respectively defined as the values of. That is, the BB operation state is ended when the number of paid-out medals exceeds 350, and the RB game state is ended when the number of games reaches 12 times or the number of wins reaches 8.

  Next, with reference to FIG. 12A, bonus check data used to determine whether or not the internal winning combination is BB in the internal lottery process (see FIG. 15) described later will be described. FIG. 12 (1) is a diagram showing an example of bonus check data for the gaming machine 1 of the present embodiment.

  The bonus check data is an 8-bit bit pattern, where “bit 0 to bit 3” and “bit 5 to bit 7” are composed of “0”, and “bit 4” is composed of “1”. In other words, the bonus check data has the same bit pattern as the BB bit pattern “00010000” defined in the internal winning combination determination table.

  Next, with reference to FIG. 12 (2), an internal winning combination storing area for storing internal winning combination information will be described. FIG. 12 (2) is a diagram showing an example of the internal winning combination storing area of the gaming machine 1 of the present embodiment.

  The internal winning combination storing area is an 8-bit data area allocated on the RAM 33. The internal winning combination storage area indicates which combination is an internal winning combination by storing data of “0” or “1” in the “bit 0 to bit 4” area. For example, when the bit pattern of the internal winning combination storing area is “00000010”, it indicates that the bell is an internal winning combination.

  Next, a carryover combination storage area for storing carryover combination information will be described with reference to FIG. FIG. 12 (3) is a diagram showing an example of the carryover combination storage area of the gaming machine 1 of the present embodiment.

  The carryover combination storage area is an 8-bit data area allocated on the RAM 33. The carryover combination storage area indicates whether it is in the BB carryover state by storing “0” or “1” data in the “bit 4” area. That is, when the bit pattern of the carryover combination storage area is “00010000”, it indicates that the BB carryover state is set. Here, the BB carryover state refers to the BB until the white 7 symbols are displayed side by side along the active line when the internal winning combination is determined to be BB during the general gaming state. A state in which the internal winning state continues.

  Next, the control operation of the main CPU 31 of the main control circuit 60 will be described with reference to the flowcharts shown in FIGS.

  First, with reference to FIG. 13, the reset interrupt process by the main CPU 31 of the main control circuit 60 will be described. FIG. 13 is a diagram illustrating a flowchart of reset interrupt processing by the main CPU 31 performed by the main control circuit 60 of the present embodiment. Further, the main CPU 31 generates a reset interrupt when power is turned on and a voltage is applied to the reset terminal, and the reset interrupt process stored in the ROM 32 is sequentially performed based on the occurrence of the interrupt. It is configured as follows.

  First, when the power is turned on, the main CPU 31 performs initialization (step S1).

  Next, the main CPU 31 clears the designated RAM area at the end of the game (step S2). Specifically, the main CPU 31 erases data in the writable area in the RAM 33 used for the previous unit game, writes parameters necessary for the current unit game in the writable area in the RAM 33, Specify the start address to the sequence program.

  Next, the main CPU 31 performs a bonus operation monitoring process which will be described later with reference to FIG. 14 (step S3). This bonus operation monitoring process is a process for generating an RB gaming state when the BB operating state is not the RB gaming state.

  Next, the main CPU 31 performs medal insertion / start check processing (step S4). First, in the medal insertion check process, the main CPU 31 determines whether the medal sensor 22S has detected passage of a medal, whether the BET switches 11S, 12S, 13S are turned on, or based on the replay operating flag. It is determined whether or not a replay has been established in the unit game, and the insertion number counter set in the RAM 33 is updated based on each determination result. Here, the replay operating flag is information for identifying whether or not replay is established. The inserted number counter is information for specifying the inserted number in the current unit game. Next, the main CPU 31 validates the winning line according to the value of the inserted number counter. For example, if the inserted number counter is “3”, the main CPU 31 performs a display combination search process described later based on the combination of symbols displayed on all winning lines. In the start check process, the main CPU 31 starts on the condition that a medal is inserted, for example, on the condition that the inserted number counter is “1” or more or the inserted number counter is the maximum value “3”. Processing for determining whether or not the start switch 6S is turned on by the operation is performed.

  Next, when determining that the start switch 6S is turned on, the main CPU 31 extracts a random number value for determining an internal winning combination (step S5). Specifically, the main CPU 31 extracts one random value from the range of “0 to 65535” by the random number generator 36 and the sampling circuit 37 and stores the extracted random value in the random value storage area of the RAM 33 described above. .

  Next, the main CPU 31 performs a gaming state monitoring process (step S6). In this gaming state monitoring process, the main CPU 31 sets a gaming state identifier for identifying the gaming state in the current unit game in the RAM 33 based on the RB operating flag. Specifically, the main CPU 31 sets the RB gaming state if the RB operating flag is on, and sets the general gaming state if it does not correspond to this.

  Next, the main CPU 31 performs an internal lottery process which will be described later with reference to FIG. 15 (step S7). In this internal lottery process, the main CPU 31 determines, based on the gaming state, the aforementioned lottery count determination table (see FIG. 8), the internal lottery table (see FIGS. 9 (1) and 9 (2)), An internal winning combination is determined with reference to a combination determination table (see FIG. 10).

  Next, the main CPU 31 transmits a start command to the sub control circuit 61 (step S8). The start command includes, for example, information such as a gaming state, a winning combination, and a random value.

  Next, the main CPU 31 determines whether 4.1 seconds have elapsed since the start of the previous rotation of the reels 3L, 3C, 3R (step S9). When determining that 4.1 seconds have not elapsed, the main CPU 31 performs a wait process (step S10). In this wait process, the main CPU 31 performs a standby process without performing subsequent processes until 4.1 seconds have elapsed since the start of rotation of the reels 3L, 3C, and 3R.

  The main CPU 31 sets a game monitoring timer in the RAM 33 when it is determined that 4.1 seconds have elapsed in the process of step S9 or when a wait process is performed in the process of step S10 (step S10). S11). The main CPU 31 counts the above-mentioned 4.1 seconds by the set game monitoring timer, sets the automatic stop timer in order to perform the above-mentioned automatic stop, and sets a predetermined time (for example, 40 seconds). Start timing.

  Next, the main CPU 31 requests the start of rotation of all reels (step S12). For example, the main CPU 31 performs processing such as turning on a rotation start request flag set in the RAM 33. When the start of rotation of all reels is requested, rotation start processing and acceleration control processing of the reels 3L, 3C, and 3R are performed.

  Next, the main CPU 31 performs a reel stop control process which will be described later with reference to FIG. 16 (step S13). In the reel stop control process, the main CPU 31 stops the display of symbols on the reels 3L, 3C, and 3R based on a stop signal output from the stop switches 7LS, 7CS, and 7RS by the stop operation of the player.

  Next, when the symbols of the reels 3L, 3C, and 3R are stopped, the main CPU 31 performs a display combination search process based on the combination of the symbols for which the display has been stopped (step S14). In this display combination search process, the main CPU 31 identifies a display combination based on the code number of the symbols displayed side by side on the active line and the symbol combination table (see FIG. 7). Further, the main CPU 31 sets a display combination flag for identifying the display combination and information on the number of payouts corresponding to the display combination in the RAM 33. For example, when watermelons are displayed side by side on the center line 8c, the main CPU 31 stores the display combination flag for identifying that the display combination is a watermelon and payout number information for specifying that the number of payouts is 8 in the RAM 33. Set to.

  Next, the main CPU 31 transmits a display combination command to the sub control circuit 61 (step S15). The display combination command includes information on a display combination flag that identifies a display combination established on the active line, such as a replay display combination.

  Next, the main CPU 31 performs medal payout processing (step S16). In this medal payout process, the main CPU 31 updates the credit counter set in the RAM 33 based on the payout number information in the credit mode. When the credit counter is updated, the credit counter 19 displays the value of the credit counter. In the payout mode, the main CPU 31 drives and controls the hopper 40 by the hopper drive circuit 41 based on the payout number information to pay out medals. Further, if the display combination is replay, the main CPU 31 turns on the replay operating flag.

  Next, when the BB operating flag set in the RAM 33 is ON, the main CPU 31 subtracts the number of medals paid out in the process of step S16 from the bonus end number counter (step S17).

  Next, the main CPU 31 determines whether or not the BB operating flag or the RB operating flag set in the RAM 33 is on (step S18). At this time, when the main CPU 31 determines that the BB operating flag or the RB operating flag is not ON, that is, when it is determined that both the BB operating flag and the RB operating flag are OFF, FIG. The process proceeds to a bonus operation check process (step S20) described with reference to FIG.

  On the other hand, when the main CPU 31 determines in the process of step S18 that the BB operating flag or the RB operating flag is on, it performs a bonus end check process (step S19) described later with reference to FIG. . In this bonus end check process, the main CPU 31 ends the RB when the RB end condition is satisfied, and when the BB operation state end condition is satisfied, the main CPU 31 determines the BB operation state and the RB game. End the state.

  Next, when the main CPU 31 determines in the process of step S18 that the BB operating flag or the RB operating flag is not on, or performs a bonus end check process in the process of step S19, the main CPU 31 performs a bonus operation check. Processing is performed (step S20). This bonus operation check process is a process for generating a BB operation state when the display combination is BB. When this process ends, the main CPU 31 proceeds to the process of step S2.

  As described above, the main CPU 31 executes the process from step S2 to step S20 as the process in the unit game. When the process in step S20 is completed, the main CPU 31 proceeds to the process in step S2 to execute the process in the next unit game. .

  Next, the bonus operation monitoring process will be described with reference to FIG. FIG. 14 is a flowchart of the bonus operation monitoring process performed in the main control circuit 60 of the present embodiment. The bonus operation monitoring process is a process for generating an RB gaming state when the BB operating state is not the RB gaming state.

  First, the main CPU 31 determines whether or not the BB operating flag is on (step S51). At this time, when the main CPU 31 determines that the BB operating flag is not on, the main CPU 31 ends the bonus operation monitoring process. On the other hand, in the process of step S51, when the main CPU 31 determines that the BB operating flag is on, it then determines whether or not the RB operating flag is on (step S52). At this time, when the main CPU 31 determines that the RB operating flag is on, the main CPU 31 ends the bonus operation monitoring process.

  On the other hand, when the main CPU 31 determines in the process of step S52 that the RB operating flag is not on, the main CPU 31 then refers to the bonus operating table (see FIG. 11) and performs the RB operating process (step S53). Specifically, the main CPU 31 refers to the bonus operating time table, sets “12” as the number of possible games, sets “8” as the number of possible winnings, and turns on the RB operating flag. After completing this process, the main CPU 31 ends the bonus operation monitoring process.

  That is, the main CPU 31 always generates the RB gaming state in the BB operating state by the bonus operation monitoring process. For example, in the previous unit game, either the number of possible games or the number of possible winnings is “0”, and even if the RB gaming state is finished, the main CPU 31 again performs the RB A game state is generated. When the main CPU 31 ends the bonus operation monitoring process, the main CPU 31 proceeds to the process of step S4 in FIG.

  Next, an internal lottery process will be described with reference to FIG. FIG. 15 is a diagram showing a flowchart of an internal lottery process performed by the main control circuit 60 of the present embodiment. The internal lottery process is a process for determining an internal symbol combination and setting an internal symbol combination storage area and a carryover combination storage area.

  First, the main CPU 31 refers to the lottery count determination table (see FIG. 8) and determines the lottery count based on the gaming state (step S31). Specifically, when the main CPU 31 determines that it is the general gaming state based on the gaming state identifier for identifying the gaming state, it determines “5” as the number of lotteries and determines that it is the RB gaming state. When it is done, “3” is determined as the number of lotteries.

  Next, the main CPU 31 determines whether or not the carryover combination storage area is “00000000” (step S32). Specifically, the main CPU 31 determines whether or not it is in the BB carryover state. When the main CPU 31 determines that the carryover combination storage area is “00000000”, that is, determines that the carryover combination storage area is not in the BB carryover state, the main CPU 31 proceeds to the processing of step S34.

  On the other hand, when the main CPU 31 determines in the process of step S32 that the carryover combination storage area is not “00000000”, that is, is in the BB carryover state, the main CPU 31 changes the number of lotteries to “4” (step S33). By changing the number of lotteries to “4”, the main CPU 31 avoids determining the BB as the internal winning combination again in the subsequent processing despite the BB carryover state. When this process ends, the main CPU 31 proceeds to the process of step S34.

  Next, the main CPU 31 sets the same value as the number of lotteries in the winning number (step S34). Next, the main CPU 31 refers to the internal lottery table (see FIG. 9), and acquires a lottery value based on the winning number and the inserted number counter (step S35). For example, when the gaming state is the general gaming state, the main CPU 31 acquires “250” as the lottery value when the winning number is “5” and the inserted number counter is “3”.

  Next, the main CPU 31 subtracts the lottery value acquired in the process of step S35 from the random number value stored in the RAM 33 (step S36), and then, when the subtraction process is performed, whether a digit has been performed. It is determined whether or not (step S37). Specifically, the main CPU 31 determines whether or not the result of subtracting the lottery value from the random number value has become negative. When the main CPU 31 determines that a digit has been taken, the main CPU 31 proceeds to the process of step S41.

  On the other hand, when the main CPU 31 determines in the process of step S37 that no digit has been made, it subtracts "1" from the winning number (step S38), and then subtracts "1" from the number of lotteries (step S38). S39). That is, the main CPU 31 sets the same number for the number of lotteries and the winning number in the process of step S34, and subtracts “1” by one in the processes of step S38 and step S39, thereby making the winning number and the number of lotteries the same. maintain. When the main CPU 31 ends this process, the process proceeds to the process of step S40.

  Next, the main CPU 31 determines whether or not the number of lotteries is “0” (step S40). When the main CPU 31 determines that the number of lotteries is “0”, the main CPU 31 proceeds to the process of step S41.

  On the other hand, when the main CPU 31 determines in the process of step S40 that the number of lotteries is not “0”, the main CPU 31 proceeds to the process of step S35. After that, the main CPU 31 performs the processing from step S35 to step S40, until the result of the processing for subtracting the lottery value from the random number value (step S36), until the digit is performed or the number of lotteries becomes “0”. repeat. Note that the main CPU 31 subtracts the lottery value from the previous subtraction result when performing the processing of step S36 in the repetitive processing.

  Next, when the main CPU 31 determines that a digit has been made in the process of step S37, or determines that the number of lotteries is “0” in the process of step S40, the main winning combination determination table ( With reference to FIG. 10, the internal winning combination is determined based on the winning number. (Step S41). For example, when the winning number is “2”, the main CPU 31 determines the bell as an internal winning combination.

  In addition, when the main CPU 31 ends the above-described repetitive processing from step S35 to step S40 due to a digit being performed, the main CPU 31 corresponds to the winning number “1-5” at that time, cherry, bell, One of watermelon, replay, and BB is determined as an internal winning combination. On the other hand, when the main CPU 31 ends the repetitive processing because the number of lotteries has reached “0”, the main CPU 31 determines that the result of the internal lottery is lost based on the winning number “0” at that time.

  Next, the main CPU 31 refers to the internal winning combination determination table, takes the logical product of the 8-bit bit pattern corresponding to the internal winning combination and bonus check data (see FIG. 12 (1)), and this bit pattern. And the carryover combination storage area are stored in the carryover combination storage area (step S42). For example, when the internal winning combination is BB and the carryover combination storing area is “00000000”, the main CPU 31 sets a bit pattern “00010000” corresponding to the internal winning combination BB and bonus check data “00010000”. And “00010000”, which is the logical sum of this and the carryover combination storage area “00000000”, is stored in the carryover combination storage area.

  Next, the main CPU 31 stores the logical sum of the 8-bit bit pattern corresponding to the internal winning combination and the carryover combination storing area in the internal winning combination storing area (step S43). For example, when the internal winning combination is a bell and the carryover combination storing area is “00010000”, the main CPU 31 has a bit pattern “00000010” corresponding to the bell that is an internal winning combination and a carryover combination storing area “00010000”. Is stored in the internal winning combination storing area. When this process ends, the main CPU 31 ends the internal lottery process and proceeds to the process of step S8 in FIG.

  Next, the reel stop control process will be described with reference to FIG. FIG. 16 is a diagram showing a flowchart of the reel stop control process performed by the main control circuit 60 of the present embodiment. The reel stop control process is a process for stopping display of symbols on the reels 3L, 3C, and 3R based on a stop signal output from the stop switches 7LS, 7CS, and 7RS based on a stop operation by the player. It is.

  First, the main CPU 31 determines whether or not a valid stop switch is turned on (step S101). Specifically, the main CPU 31 determines whether stop switches 7LS, 7CS, and 7RS corresponding to the rotating reels 3L, 3C, and 3R are turned on based on a stop operation by the player. At this time, when the main CPU 31 determines that the effective stop switch is not turned on, the main CPU 31 repeats the process of step S101 until it is determined that the effective stop switch is turned on.

  On the other hand, when the main CPU 31 determines in the process of step S101 that the effective stop switch is turned on, it is based on the internal winning combination determined in the process of step S41 of the internal lottery process described with reference to FIG. The number of sliding frames is determined (step S102).

  Next, the main CPU 31 determines the planned stop positions of the reels 3L, 3C, 3R based on the number of sliding symbols determined in the process of step S102 and the current symbol position (step S103).

  Next, the main CPU 31 transmits a reel stop command to the sub control circuit 61 (step S104).

  Next, the main CPU 31 determines whether or not all reels have been stopped (step S105). At this time, when determining that all the reels are not stopped, the main CPU 31 repeats the processing from step S101 to step S104 until it is determined that all the reels are stopped.

  On the other hand, when the main CPU 31 determines in the process of step S105 that all the reels have stopped, the main CPU 31 ends the reel stop control process and proceeds to the process of step S14 in FIG.

  Next, the bonus end check process will be described with reference to FIG. FIG. 17 is a view showing a flowchart of the bonus end check process performed in the main control circuit 60 of the present embodiment. Further, this bonus end check process is a process of updating the RB game possible number and the winning possible number, BB end time process, and RB end time process.

  First, the main CPU 31 determines whether or not a winning is achieved (step S81). At this time, when the main CPU 31 determines that no winning has been established, the main CPU 31 proceeds to the processing of step S87. Here, winning means that a medal is paid out by displaying a combination of symbols related to small roles such as cherry, bell, and watermelon.

  On the other hand, when the main CPU 31 determines in the process of step S81 that a winning has been established, the main CPU 31 determines whether or not the bonus end number counter is “0” (step S82). At this time, when the main CPU 31 determines that the bonus end number counter is not “0”, the main CPU 31 proceeds to the process of step S85.

  On the other hand, when the main CPU 31 determines in the process of step S82 that the bonus end number counter is “0”, the main CPU 31 performs the RB end process (step S83). Specifically, the main CPU 31 turns off the RB operating flag and performs processing such as setting a command indicating the end of the RB gaming state.

  Next, the main CPU 31 performs processing at the end of BB (step S84). Specifically, the main CPU 31 performs processing such as turning off the BB operating flag. When this process ends, the main CPU 31 ends the bonus end check process and proceeds to the process of step S20 in FIG.

  On the other hand, when the main CPU 31 determines in the process of step S82 that the bonus end number counter is not “0”, the main CPU 31 subtracts “1” from the winning possible number counter (step S85).

  Next, the main CPU 31 determines whether or not the winning possible number counter obtained by subtracting “1” in the process of step S85 is “0” (step S86). At this time, when the main CPU 31 determines that the winning possible number counter is “0”, the main CPU 31 proceeds to the process of step S89. On the other hand, when the main CPU 31 determines that the winning possible number counter is not “0”, the main CPU 31 proceeds to the process of step S87.

  Next, when the main CPU 31 determines that a winning is not established in the process of step S81, or when it is determined that the winning possible number counter is not “0” in the process of step S86, the possible game number counter Then, “1” is subtracted from (Step S87).

  Next, the main CPU 31 determines whether or not the possible game number counter obtained by subtracting “1” in the process of step S87 is “0” (step S88). At this time, when the main CPU 31 determines that the possible game number counter is not “0”, the main CPU 31 ends the bonus end check process and proceeds to the process of step S20 in FIG. On the other hand, when the main CPU 31 determines that the possible game number counter is “0”, the main CPU 31 proceeds to the process of step S89.

  Next, when the main CPU 31 determines in the process of step S86 that the possible winning number counter is “0”, or in the process of step S88, determines that the possible game number counter is “0”. , RB end processing is performed (step S89). Specifically, the main CPU 31 turns off the RB operating flag and performs a predetermined process such as setting a command indicating the end of the RB gaming state. When this process ends, the main CPU 31 ends the bonus end check process and proceeds to the process of step S20 in FIG.

  Next, the bonus operation check process will be described with reference to FIG. FIG. 18 is a flowchart of the bonus operation check process performed in the main control circuit 60 of the present embodiment. The bonus operation check process is a process for generating a BB operation state when the display combination is BB.

  First, the main CPU 31 determines whether or not the display combination is BB (step S91). At this time, if the main CPU 31 determines that the display combination is not BB, the main CPU 31 ends the bonus operation check process and proceeds to the process of step S2 in FIG.

  On the other hand, when the main CPU 31 determines in step S91 that the display combination is BB, the main CPU 31 performs BB operation processing based on the BB operation table (step S92). Specifically, the main CPU 31 refers to the bonus operating time table, sets “350” in the bonus end number counter, and turns on the BB operating flag.

  Next, the main CPU 31 clears the carryover combination storage area (step S93). When this process ends, the main CPU 31 ends the bonus operation check process and proceeds to the process of step S2 in FIG.

  Next, with reference to FIG. 19, the interrupt process by the control of the main CPU will be described. FIG. 19 is a diagram showing a flowchart of the interrupt process under the control of the main CPU performed by the main control circuit 60 of the present embodiment. Further, the interrupt process under the control of the main CPU is an interrupt process that occurs every predetermined period (for example, 1.1173 milliseconds).

  First, the main CPU 31 interrupts the program being executed before calling the interrupt process under the control of the main CPU, and saves the address indicating the interrupted position and the values of various registers in a predetermined area of the RAM 33. (Step S401). This is because when the interrupt process under the control of the main CPU is completed, the address indicating the interrupted position of the saved program and the values of various registers are restored, and the program is continuously executed from the point of interruption. It is.

  Next, the main CPU 31 performs input port check processing for checking the I / O port 38 (step S402), and then adds "1" to the interrupt counter (step S403).

  Next, the main CPU 31 determines whether or not the value of the interrupt counter is an even number (step S404). At this time, when the main CPU 31 determines that the value of the interrupt counter is an even number, the main CPU 31 proceeds to the processing of step S411.

  On the other hand, when the main CPU 31 determines in step S404 that the value of the interrupt counter is not an even number, the main CPU 31 sets an identifier indicating the left reel to the rotation control reel identifier for determining the target reel for rotation control (step S404). S405). The main CPU 31 performs reel rotation control based on the rotation control reel identifier in a reel control process described later.

  Next, the main CPU 31 performs a reel control process described later with reference to FIG. 20 based on the rotation control reel identifier set in the process of step S405 (step S406).

  Next, the main CPU 31 sets an identifier indicating a middle reel as a rotation control reel identifier for determining a target reel for rotation control (step S407).

  Next, the main CPU 31 performs a reel control process described later with reference to FIG. 20 based on the rotation control reel identifier set in the process of step S407 (step S408).

  Next, the main CPU 31 sets an identifier indicating the right reel as a rotation control reel identifier for determining a target reel for rotation control (step S409).

  Next, the main CPU 31 performs a reel control process described later with reference to FIG. 20 based on the rotation control reel identifier set in the process of step S409 (step S410).

  Next, when the main CPU 31 determines that the value of the interrupt counter is an even number in the process of step S404, or when the reel control process is performed in step S410, the main CPU 31 performs a lamp / 7SEG drive control process ( Step S411). Specifically, the main CPU 31 drives and controls the BET lamps 9 a, 9 b, 9 c and the WIN lamp 17 via the lamp driving circuit 45. Thereby, the BET lamps 9a, 9b, 9c and the WIN lamp 17 are turned on and off. Further, the main CPU 31 drives and controls the payout number display unit 18 and the credit display unit 19 via the display unit drive circuit 48. As a result, various information (such as the number of credits) is displayed on the payout number display unit 18 and the credit display unit 19.

  Next, the main CPU 31 refers to the value saved in the RAM 33 in the process of step S401 and restores the register (step S412). When this process ends, the interrupt process under the control of the main CPU is ended, and the program interrupted by the occurrence of the interrupt process under the control of the main CPU is continuously executed.

  Next, the reel control process will be described with reference to FIG. FIG. 20 is a diagram illustrating a flowchart of the reel control process performed by the main control circuit 60 of the present embodiment.

  First, the main CPU 31 refers to the rotation control reel identifier set in step S405, step S407, and step S409 of the interrupt process (see FIG. 19) under the control of the main CPU described above, and the corresponding reel is in rotation control. It is determined whether or not (step S421). At this time, when the main CPU 31 determines that the corresponding reel is not under rotation control, the main CPU 31 ends the reel control process.

  On the other hand, when the main CPU 31 determines in the process of step S421 that the corresponding reel is under rotation control, the main CPU 31 determines whether or not the reel is in a waiting state for a planned stop position (step S422). Here, the waiting state for the planned stop position refers to a state of waiting for the corresponding rotating reel to reach the planned position for stopping the rotation. In this state, the rotation of the reel is maintained at a constant speed. When the main CPU 31 determines that the corresponding reel is not waiting for the scheduled stop position, the main CPU 31 proceeds to the process of step S425.

  Next, when the main CPU 31 determines in the process of step S422 that the corresponding reel is waiting for the planned stop position, the main CPU 31 determines whether or not the reel has reached the planned stop position (step S423). When the main CPU 31 determines that the corresponding reel has not reached the scheduled stop position, the main CPU 31 proceeds to the process of step S425.

  On the other hand, when the main CPU 31 determines in step S423 that the corresponding reel has reached the scheduled stop position, the main CPU 31 shifts the control state of the reel to the deceleration control state (step S424).

  Next, when the main CPU 31 determines in the process of step S422 that the corresponding reel is not waiting for the planned stop position, the main CPU 31 determines in the process of step S423 that the corresponding reel has not reached the planned stop position. Alternatively, when the control state of the corresponding reel is shifted to the deceleration control state in the process of step S424, the reel rotation acceleration control, constant speed control, deceleration control, or stop is performed according to the reel control state. Control is performed (step S425). The main CPU 31 ends the reel control process after completing the process of step S425.

  Next, control operations of the image control microcomputer 72 and the sound / lamp control microcomputer 92 of the sub-control circuit 61 will be described with reference to flowcharts shown in FIGS.

  First, the reset interrupt process by the image control microcomputer 72 will be described with reference to FIG. FIG. 21 is a diagram showing a flowchart of reset interrupt processing by the image control microcomputer 72 of this embodiment. Further, the image control microcomputer 72 generates a reset interrupt when the power is turned on and a voltage is applied to the reset terminal, and the reset interrupt process stored in the program ROM 73 based on the occurrence of the interrupt. Are sequentially performed.

  First, the image control microcomputer 72 performs initialization when power is turned on (step S201). Specifically, the image control microcomputer 72 performs initial setting of a storage area such as a work RAM 74 provided in the image control circuit.

  Next, the image control microcomputer 72 performs input monitoring processing for the command transmitted from the main control circuit 60 (step S202). Specifically, in the input monitoring process, the image control microcomputer 72 determines whether various commands such as a start command and a display combination command are received.

  Next, the image control microcomputer 72 performs a command input process which will be described later with reference to FIG. 26 (step S203). Specifically, in the command input process, when various commands are received, the image control microcomputer 72 performs a predetermined process based on the received commands.

  Next, the image control microcomputer 72 performs image drawing processing (step S204). Specifically, the image control microcomputer 72 reads image data from the work RAM 74 and transmits the read image data and information related to the display position and size of the image data to the image control IC 76. Further, the image control microcomputer 72 acquires a corresponding numeric display image from the image ROM 79 based on the value of the medal count counter stored in the work RAM 74 and transmits it to the image control IC 76 together with information related to the display position and size. . Further, the image control IC 76 stores the received image data in one frame buffer area provided in the video RAM 80. The value of the medal count counter is set in a medal count interrupt process described later with reference to FIG.

  Next, the image control microcomputer 72 determines whether or not the VDP counter is “2” (step S205). At this time, if the image control microcomputer 72 determines that the VDP counter is “2”, the process proceeds to step S206. On the other hand, when the image control microcomputer 72 determines that the VDP counter is not “2”, it proceeds to the process of step S205 again, and repeats the process of step S205 until the VDP counter becomes “2”. The VDP counter is counted up when a periodic signal reception process from the image control IC 76 described later occurs at a predetermined cycle (every 1/60 seconds). Thereby, in this embodiment, a display image will be switched every 1/30 second.

  Next, when the image control microcomputer 72 determines that the VDP counter has reached “2” in the process of step S205, the image control microcomputer 72 sets “0” to the VDP counter (step S206). A bank switching command is transmitted, and the display image data area and the writing image data area are switched (step S207). That is, the bank switching process is performed. In addition, the image control IC 97 receives the bank switching command to output the image data written in the write image data area to the liquid crystal display device 5 and replace the display image data area with the write image data area. Then, image data to be displayed next is written. When this process ends, the image control microcomputer 72 proceeds to the process of step S202.

  Next, the periodic signal reception process from the image control IC 76 will be described with reference to FIG. FIG. 22 is a diagram showing a flowchart of the regular signal reception process from the image control IC 76 of the present embodiment. The regular signal reception process from the image control IC 76 is an interrupt process that occurs every predetermined period (for example, 1/60 seconds).

  In this periodic signal reception process, the image control microcomputer 72 interrupts the program being executed before calling the periodic signal reception process, and stores the address indicating the interrupted position and the values of various registers in a predetermined area of the work RAM 74. Evacuate to. In addition, when the periodic signal reception process is completed, the image control microcomputer 72 restores the address indicating the position where the saved program is interrupted and the values of various registers, and continues to execute the program from the point of interruption. To do.

  In the regular signal reception process, the image control microcomputer 72 adds “1” to the VDP counter (step S321). When this process ends, the image control microcomputer 72 ends the regular signal reception process and continues the reset interrupt process interrupted by the occurrence of the regular signal reception process.

  Next, a command signal reception interrupt process performed by the image control microcomputer 72 when a command transmitted from the main control circuit 60 is received will be described with reference to FIG. FIG. 23 is a flowchart of command signal reception interrupt processing from the main control circuit 60 of the present embodiment. The command signal reception interrupt process by the image control microcomputer 72 is an interrupt process that is called when a command transmitted from the main control circuit 60 is received.

  Similar to the periodic signal reception processing from the image control IC 76, the image control microcomputer 72 interrupts the program being executed before calling the command signal reception interrupt processing, and addresses indicating the interrupted position and various registers The value is saved in a predetermined area of the work RAM 74. Further, when the command signal reception interrupt process is completed, the image control microcomputer 72 restores the address indicating the interrupted position of the saved program and the values of various registers, and continues the program from the point of interruption. And execute.

  When receiving the command signal from the main control circuit 60, the image control microcomputer 72 interrupts the reset interrupt process, and then stores the data corresponding to the received command in the work RAM 74 as an unprocessed command (step S331). The command reception interrupt process is terminated, and the reset interrupt process interrupted by the occurrence of the command signal reception interrupt process is continued.

  Next, the periodic interruption process by the sound / lamp control microcomputer 92 will be described with reference to FIG. FIG. 24 is a diagram showing a flowchart of periodic interruption processing by the sound / lamp control microcomputer 92 of the present embodiment. In addition, this periodic interrupt process is an interrupt process that occurs every predetermined period (for example, 2 milliseconds).

  Similar to the periodic signal reception process from the image control IC 76, the sound / lamp control microcomputer 92 interrupts the program being executed before the periodic interrupt process is executed, The register value is saved in a predetermined area of the work RAM 93. In addition, when the periodic interrupt process ends, the sound / lamp control microcomputer 92 restores the address indicating the interrupted position of the saved program and the values of various registers, and continues the program from the point of interruption. And execute.

  First, the sound / lamp control microcomputer 92 performs a sound output control process based on the effect data (step S341). Specifically, in the sound output control process, the sound / lamp control microcomputer 92 causes the sound source IC 95 to generate a sound signal corresponding to the effect data, and outputs the sound signal from the speakers 21L and 21R at a predetermined timing.

  Next, the sound / lamp control microcomputer 92 performs lamp lighting control processing based on the effect data (step S342). Specifically, in the lamp lighting control process, the sound / lamp control microcomputer 92 controls the lighting of the LED 101 and the lamp 102 so as to perform a lighting mode corresponding to the effect data. When this process ends, the sound / lamp control microcomputer 92 ends the periodic interrupt process and continues to execute the program interrupted by the occurrence of the periodic interrupt process.

  Next, with reference to FIG. 25, the medal counting interrupt process will be described. FIG. 25 is a diagram illustrating a flowchart of the medal counting interrupt process according to the present embodiment. The medal counting interrupt process is an interrupt process that occurs every predetermined period (for example, 2 milliseconds).

  In this medal counting interrupt process, the image control microcomputer 72 interrupts the program being executed before calling the medal counting interrupt process, and assigns the address indicating the interrupted position and the values of various registers to a predetermined value in the work RAM 74. Evacuate to the area. In addition, when the medal counting interrupt process is completed, the image control microcomputer 72 restores the address indicating the interrupted position of the saved program and the values of various registers, and continues the program from the point of interruption. Execute.

  First, the image control microcomputer 72 determines whether or not the clear button 200 has been operated (step S351). When the image control microcomputer 72 determines that the clear button 200 has not been operated, the process proceeds to step S353. On the other hand, when determining that the clear button 200 has been operated, the image control microcomputer 72 sets “0” to the medal count counter (step S352). Here, the medal count counter is a counter assigned to a predetermined area of the work RAM 74, and the image control microcomputer 72 causes the liquid crystal display device 5 to display the value of the medal count counter.

  Next, the image control microcomputer 72 determines that the clear button 200 has not been operated in the process of step S351, or after setting “0” to the medal count counter in the process of step S352, It is determined whether or not a count-up signal has been received from unit 310 (step S353). When the image control microcomputer 72 determines that the count-up signal is not received from the medal counting unit 310, the image control microcomputer 72 ends the medal count interrupt process, and performs the reset interrupt process interrupted by the occurrence of the medal count interrupt process. Continue.

  On the other hand, when the image control microcomputer 72 determines in step S353 that the count-up signal has been received from the medal counting unit 310, the image control microcomputer 72 adds “1” to the medal count counter (step S354). After completing the process of step S354, the image control microcomputer 72 ends the medal count interrupt process and continues the reset interrupt process interrupted by the occurrence of the medal count interrupt process.

  Next, command input processing by the image control microcomputer 72 will be described with reference to FIG. FIG. 26 is a diagram showing a flowchart of command input processing by the image control microcomputer 72 of this embodiment. The command input process is a process for determining whether or not a command has been received and performing predetermined control based on the command.

  First, the image control microcomputer 72 determines whether or not the command transmitted from the main control circuit 60 has been received (step S211). When the image control microcomputer 72 determines that the command transmitted from the main control circuit 60 has not been received, the image control microcomputer 72 ends the command input process and proceeds to the process of step S204 in FIG.

  On the other hand, when determining that the command transmitted from the main control circuit 60 has been received in the process of step S211, the image control microcomputer 72 performs a command corresponding execution process described later with reference to FIG. 27 (step S212). Specifically, the image control microcomputer 72 performs medal insertion processing, game start processing, reel stop processing, and display processing based on the received command type.

  Next, the image control microcomputer 72 sets the unprocessed command for which the command corresponding execution process has been performed to be processed (step S213). Specifically, the image control microcomputer 72 clears an unprocessed command stored in the work RAM 74 in the command signal reception interrupt process. When this process ends, the image control microcomputer 72 ends the command input process and proceeds to the process of step S204 in FIG.

  Next, a command response execution process by the image control microcomputer 72 will be described with reference to FIG. FIG. 27 is a diagram showing a flowchart of command response execution processing by the image control microcomputer 72 of this embodiment. In the command corresponding execution process, a predetermined process is performed based on the type of the received command.

  First, the image control microcomputer 72 determines whether or not the received command is a medal insertion command (step S221). When determining that the received command is a medal insertion command, the image control microcomputer 72 performs a medal insertion process described later with reference to FIG. 28 (step S222). Specifically, in the medal insertion process, the image control microcomputer 72 sets an in-game identifier. When this process ends, the image control microcomputer 72 ends the command corresponding execution process, sets the unprocessed command to “processed” in the command input process (see FIG. 26) (step S213), and performs the process of step S204 in FIG. Migrate to

  Next, when the image control microcomputer 72 determines in step S221 that the received command is not a medal insertion command, it determines whether or not the received command is a start command (step S223). When determining that the received command is a start command, the image control microcomputer 72 performs a game start process which will be described later with reference to FIG. 29 (step S224). Specifically, in the game start process, the image control microcomputer 72 determines an effect identifier and sets start effect data. When this process ends, the image control microcomputer 72 ends the command corresponding execution process, sets the unprocessed command to “processed” in the command input process (see FIG. 26) (step S213), and performs the process of step S204 in FIG. Migrate to

  Next, when determining in step S223 that the received command is not a start command, the image control microcomputer 72 determines whether or not the received command is a reel stop command (step S225). When determining that the received command is a reel stop command, the image control microcomputer 72 performs a reel stop process which will be described later with reference to FIG. 30 (step S226). Specifically, in the reel stop process, the image control microcomputer 72 sets the first stop effect data, the second stop effect data, the third stop effect data, and the like. When this process ends, the image control microcomputer 72 ends the command corresponding execution process, sets the unprocessed command to “processed” in the command input process (see FIG. 26) (step S213), and performs the process of step S204 in FIG. Migrate to

  Next, when the image control microcomputer 72 determines in step S225 that the received command is not a reel stop command, whether the received command is a display combination command having information of a display combination flag for specifying a display combination. It is determined whether or not (step S227). When determining that the received command is a display combination command, the image control microcomputer 72 performs a display process described later with reference to FIG. 31 (step S228). Specifically, in the display process, display effect data is set. When this process ends, the image control microcomputer 72 ends the command corresponding execution process, sets the unprocessed command as processed in the command input process (see FIG. 26) (step S213), and performs step S204 in FIG. Move on to processing.

  Next, when the image control microcomputer 72 determines in step S227 that the received command is not a display combination command, the image control microcomputer 72 determines effect data corresponding to the received command (step S229). When this process ends, the image control microcomputer 72 ends the command corresponding execution process, sets the unprocessed command to “processed” in the command input process (see FIG. 26) (step S213), and performs the process of step S204 in FIG. Migrate to

  Next, with reference to FIG. 28, a medal insertion process by the image control microcomputer 72 will be described. FIG. 28 is a diagram showing a flowchart of medal insertion processing by the image control microcomputer 72 of the present embodiment. The medal insertion process is a process that is executed when a medal insertion command is received.

  First, the image control microcomputer 72 extracts a medal insertion command stored in the work RAM 74 as an unprocessed command (step S251).

  Next, the image control microcomputer 72 determines whether or not the in-game identifier of the work RAM 74 is “0” (step S252). When determining that the in-game identifier is not “0”, the image control microcomputer 72 ends the medal insertion process.

  On the other hand, when the image control microcomputer 72 determines that the in-game identifier is “0” in the process of step S252, it sets “1” in the in-game identifier (step S253). The image control microcomputer 72 ends the medal insertion process when this process ends.

  When the medal insertion process is completed, the image control microcomputer 72 returns to the command input process of FIG. 26 through the command corresponding execution process of FIG. 27, sets the unprocessed command to “processed” (step S213), and the process shown in FIG. The process proceeds to step S204.

  Next, with reference to FIG. 29, the game start process by the image control microcomputer 72 will be described. FIG. 29 is a diagram showing a flowchart of the game start process by the image control microcomputer 72 of this embodiment. The game start process is a process that is executed when a start command is received.

  First, the image control microcomputer 72 extracts a start command stored in the work RAM 74 as an unprocessed command, and sets a game state identifier, a winning combination identifier, a carryover combination identifier, etc. included in the start command in the work RAM 74. (Step S261).

  Next, the image control microcomputer 72 refers to an effect identifier determination table (not shown) and determines an effect identifier based on the winning combination identifier (step S262).

  Next, the image control microcomputer 72 refers to an effect data determination table (not shown), and determines start effect data based on the effect identifier determined in the process of step S262 (step S263). The gaming machine 1 performs an effect at the start of the game using the liquid crystal display device 5, the LED 101, the lamp, the speakers 21L, 21R, and the like based on the start effect data.

  Next, the image control microcomputer 72 clears the stop reel number counter (step S264). When this process ends, the image control microcomputer 72 ends the game start process, returns to the command input process of FIG. 26 via the command corresponding execution process of FIG. 27, and sets the unprocessed command to processed (step). S213), the process proceeds to step S204 in FIG.

  Next, the reel stop process by the image control microcomputer 72 will be described with reference to FIG. FIG. 30 is a diagram showing a flowchart of reel stop processing by the image control microcomputer 72 of the present embodiment. The reel stop process is a process that is executed when a reel stop command is received.

  First, the image control microcomputer 72 extracts a reel stop command stored in the work RAM 74 as an unprocessed command, and sets a stop reel identifier and a stop symbol identification number included in the reel stop command in the work RAM 74 (steps). S271).

  Next, the image control microcomputer 72 determines whether or not the reel 3 to be stopped is the first stop based on the stop reel identifier (step S272). When determining that the reel 3 to be stopped is the first stop, the image control microcomputer 72 refers to the effect data determination table (not shown) and sets the first stop effect data based on the effect identifier ( Step S273). The gaming machine 1 performs an effect at the time of the first stop using the liquid crystal display device 5, the LED 101, the lamp, the speakers 21L, 21R, and the like based on the first stop effect data. When this process ends, the image control microcomputer 72 ends the reel stop process.

  On the other hand, when the image control microcomputer 72 determines in the process of step S272 that the reel 3 to be stopped is not the first stop, it determines whether or not the reel 3 to be stopped is the second stop based on the stop reel identifier. (Step S274). When it is determined that the reel 3 to be stopped is the second stop, the image control microcomputer 72 refers to the effect data determination table and sets the second stop effect data based on the effect identifier (step S275). Based on the second stop effect data, the gaming machine 1 uses the liquid crystal display device 5, the LED 101, the lamp, the speakers 21L, 21R, etc. to perform the effect at the second stop time. When this process ends, the image control microcomputer 72 ends the reel stop process.

  On the other hand, when determining that the reel 3 to be stopped is not the second stop in the process of step S274, the image control microcomputer 72 refers to the effect data determination table and determines the third stop effect data based on the effect identifier. Set (step S276). The gaming machine 1 performs an effect at the time of the third stop using the liquid crystal display device 5, the LED 101, the lamp, the speakers 21L, 21R, etc. based on the third stop effect data. Next, the image control microcomputer 72 adds “1” to the stop reel number counter (step S277), and ends the reel stop process.

  When the reel control process ends, the image control microcomputer 72 returns to the command input process of FIG. 26 via the command corresponding execution process of FIG. 27, sets the unprocessed command as processed (step S213), and FIG. The process proceeds to step S204.

  Next, display processing by the image control microcomputer 72 will be described with reference to FIG. FIG. 31 is a diagram showing a flowchart of display processing by the image control microcomputer 72 of the present embodiment. The display process is a process that is executed when a display combination command is received.

  First, the image control microcomputer 72 extracts the display combination command stored in the work RAM 74 as an unprocessed command, and sets the display combination identifier included in the display combination command in the work RAM 74 (step S281).

  Next, the image control microcomputer 72 refers to an effect data determination table (not shown), and sets display effect data based on the effect identifier (step S282). Based on the display effect data, the gaming machine 1 uses the liquid crystal display device 5, the LED 101, the lamp, the speakers 21 </ b> L, 21 </ b> R, etc. to perform an effect at the time of symbol stop display on the reel 3.

  Next, the image control microcomputer 72 sets “0” in the in-game identifier (step S283). When this process ends, the image control microcomputer 72 ends the display process, returns to the command input process of FIG. 26 via the command corresponding execution process of FIG. 27, and sets the unprocessed command to processed (step S213). ), The process proceeds to step S204 in FIG.

  As described above, according to this embodiment, the player can count the number of medals acquired by the player without leaving the gaming machine 1. That is, the gaming machine 1 can improve the convenience of the player.

  In addition, according to the present embodiment, the player can pull out the drawer tray 170 and store more medals in the medal tray 16, so that when the medal counting unit 300 counts medals, You can count medals at once. That is, the gaming machine 1 can reduce the number of times that the player transfers medals from the medal tray 16 to the medal storage box, and can improve the convenience of the player.

  In addition, although illustrated as a pachislot gaming machine in this embodiment, it is not limited to this, The present invention can be applied to other gaming machines.

It is a perspective view which shows the game machine in one Embodiment which concerns on this invention. It is a side view of the gaming machine in one embodiment. FIG. 3A is a plan view of a medal counting unit in one embodiment, and FIG. 3B is a view taken along the line bb in FIG. It is a figure which shows the example of the arrangement | positioning table of the symbol on the reel of the game machine in one Embodiment. It is a figure which shows the structure of the internal circuit of the game machine in one Embodiment. It is a figure which shows the structure of the sub control circuit of the game machine in one Embodiment. It is a figure which shows the example of the symbol combination table of the game machine of one Embodiment. It is a figure which shows the example of the lottery frequency determination table of the game machine of one Embodiment. It is a figure which shows the example of the internal lottery table of the game machine of one Embodiment. It is a figure which shows the example of the internal winning combination determination table of the gaming machine of one embodiment. It is a figure which shows the example of the table at the time of the bonus action | operation of the gaming machine of one Embodiment. It is a figure which shows the example of the bonus check data of the gaming machine of one Embodiment, an internal winning combination storing area, and a carryover combination storing area. It is a figure which shows the flowchart of the reset interruption process by the main CPU performed by the main control circuit of one Embodiment. It is a figure which shows the flowchart of the bonus operation | movement monitoring process performed with the main control circuit of one Embodiment. It is a figure which shows the flowchart of the internal lottery process performed with the main control circuit of one Embodiment. It is a figure which shows the flowchart of the reel stop control process performed with the main control circuit of one Embodiment. It is a figure which shows the flowchart of the bonus completion | finish check process performed in the main control circuit of one Embodiment. It is a figure which shows the flowchart of the bonus operation | movement check process performed with the main control circuit of one Embodiment. It is a figure which shows the flowchart of the interruption process by control of the main CPU performed by the main control circuit of one Embodiment. It is a figure which shows the flowchart of the reel control process performed with the main control circuit of one Embodiment. It is a figure which shows the flowchart of the reset interruption process by the image control microcomputer performed by the sub control circuit of one Embodiment. It is a figure which shows the flowchart of the regular signal reception process from the image control IC performed with the sub control circuit of one Embodiment. It is a figure which shows the flowchart of the command signal reception interruption process performed with the sub control circuit of one Embodiment. It is a figure which shows the flowchart of the regular interruption process performed with the sub control circuit of one Embodiment. It is a figure which shows the flowchart of the medal count interruption process performed with the sub-control circuit of one Embodiment. It is a figure which shows the flowchart of the command input process performed with the sub-control circuit of one Embodiment. It is a figure which shows the flowchart of the command corresponding | compatible execution process performed with the sub control circuit of one Embodiment. It is a figure which shows the flowchart of the medal insertion process performed with the sub control circuit of one Embodiment. It is a figure which shows the flowchart of the game start process performed with the sub-control circuit of one Embodiment. It is a figure which shows the flowchart of the reel stop process performed with the sub control circuit of one Embodiment. It is a figure which shows the flowchart of the display process performed in the sub control circuit of one Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Game machine 3L, 3C, 3R ... Reel 4L, 4C, 4R ... Symbol display window 6S ... Start switch 7LS, 7CS, 7CR ... Stop switch 16 ... Medal tray 21L, 21R ... Speaker 30 ... Microcomputer 31 ... Main CPU
32 ... ROM
33 ... RAM
60 ... Main control circuit 61 ... Sub control circuit 101 ... Lamp 102 ... LED
160 ... Medal receiving unit main body 170 ... Drawer plate 200 ... Clear button 300 ... Medal counting unit 301 ... Receiving port 302 ... Ejecting port 310 ... Medal counting unit

Claims (2)

A housing having an opening on the front side;
A door that opens and closes the opening;
A symbol display section for displaying a plurality of symbols;
A game value payout unit for paying out a game value according to a combination of symbols displayed on the symbol display unit;
A tray for storing the game value paid out by the game value payout unit;
A game value counting unit for counting the number of game values paid out;
With
The gaming value counting unit has a receiving port for receiving the gaming value to be counted, a gaming value counting unit for counting the received gaming value, and an outlet for discharging the counted gaming value to the tray. A featured gaming machine. In the gaming machine according to claim 1,
The saucer is
A first saucer having a bottom plate and side plates;
A second saucer that has a front plate, a bottom plate, and both side plates, and is provided to the first saucer so that it can be pulled out along the bottom plate and both side plates of the first saucer;
A gaming machine characterized by comprising:

Images