JP2007141101A - Personal digital assistant - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform efficient data communication between a host controller 1 which generates image data and control data and an LCD controller 2N. <P>SOLUTION: The LCD controller 2N connected to the host controller 1 through two data communication lines 50 and 51 comprises a VRAM access part 23 writing image data inputted through the data communication line 51 to a VRAM 24, an image data output part 25 outputting image data within the VRAM 24 to an LCD display device 3, a peripheral equipment control part 29 performing signal input and output with peripheral equipment detachably connected with the personal digital assistant, and a register group 27 storing writing control data for regulating operation of the VRAM access part 23 and peripheral equipment control data for regulating operation of the peripheral equipment control part 29. Both the writing control data and the peripheral equipment control data are inputted from the host controller 1 through the data communication line 50. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a portable information terminal such as a cellular phone, and more particularly to an improvement of a portable information terminal in which a display controller is interposed between a display device that displays an image and a host controller that generates image data.

  Generally, a liquid crystal display (LCD) is adopted as a display device of a portable information terminal such as a mobile phone. This type of liquid crystal display is provided as a pre-moduleized LCD display device including a liquid crystal display panel and a driver circuit, and is used with an LCD controller (display controller) interposed between it and a host controller that generates image data. Is done. The LCD controller has a built-in video RAM for storing the image data generated by the host controller, reads the image data in the video RAM at a predetermined timing, and outputs it to the LCD display device 3.

  Further, in recent mobile phones, a display processor is introduced in addition to the host processor in the host controller in order to cope with an increase in size and definition of the liquid crystal display and an increase in the drawing update speed. The display processor is a circuit dedicated to display processing that executes image data generation and transfer at a high speed, which was conventionally performed by the host processor, and reduces the processing load on the display system by the host processor. Has improved.

  FIG. 11 is a block diagram showing an example of the configuration of the main part of a conventional portable information terminal. The host controller 1, LCD controller 2, LCD display device 3, I / O (Input / Output) controller 4, and data storage are shown in FIG. Parts 12 and 13 are shown. The parallel communication line 51 is the only data communication line connecting the host controller 1 and the LCD controller 2, and all data communication between these controllers is performed via the parallel communication line 51. .

  The host controller 1 includes a host processor 10 and a display processor 11. The display processor 11 generates image data to be displayed on the liquid crystal display panel 33 based on an instruction from the host processor 10 and transfers the image data to the LCD controller 2 through the parallel communication line 51 at a high speed. Also, the control data of the LCD controller 2 and the LCD display device 3 generated by the host processor 10 is once transmitted from the host processor 10 to the display processor 11 and then output to the LCD controller 2 via the parallel communication line 51. Is done.

  The LCD controller 2 includes a video RAM (VRAM) 24 that stores image data and a register group 27 that stores control data. Image data transferred from the display processor 11 is received by the communication unit 20 and written to the video RAM 24 by the VRAM access unit 23. Further, the image data held in the video RAM 24 is read out by the image data output unit 25 at a predetermined timing and output to the LCD display device 3. On the other hand, control data output from the display processor 11 is received by the communication unit 20 and written to the register group 27 by the register access unit 26. In the register group 27, write control data, output control data, and LCD control data are held as control data.

  The write control data is control data that defines the operation of the VRAM access unit 23 and includes, for example, information such as a pixel position at which writing is started, a writing range, and a writing direction. The VRAM access unit 23 automatically generates an address of the video RAM 24 based on the write control data, and writes the image data continuously input from the display processor 11 to the video RAM 24. Therefore, the write control data is generated by the display processor 11 and output to the LCD controller 2 prior to the transfer of a series of image data.

  The output control data is control data that defines the operation of the image data output unit 25. The image data output unit 25 adjusts the timing for outputting the image data in the video RAM 24 to the LCD display device 3 based on the output control data.

  The LCD control data is control data that defines the operation of the communication unit 31 and the driver circuit 32 in the LCD display device 3, and is transmitted to the LCD display device 3 by the control data output unit 28. The output control data and the LCD control data are generated by the host processor 10 and input to the LCD controller 2 via the display processor 11.

The I / O controller 4 is connected to the host processor 10 via the serial communication line 50, and performs signal input / output and control for peripheral devices not shown based on peripheral device control data output from the host processor 10. Yes. The peripheral device includes not only an external device that is detachably attached to the mobile phone, such as a USB device or an SD card, but also an internal device that is built in the mobile phone in advance.
JP 2002-221958 A

  As described above, recent mobile phones have introduced a display processor in the host controller to cope with an increase in the size and definition of the liquid crystal display. With such changes, the display processor 11 changes to the LCD controller. The amount of image data to be transferred to 2 is also increasing. For this reason, it is required to increase the transfer speed of image data between the host controller 1 and the LCD controller 2.

  However, in the conventional mobile phone, since the parallel communication line 51 is the only data communication line connecting the host controller 1 and the LCD controller 2, not only image data but also control is performed using the same parallel communication line 51. Data transfer also has to be performed, and there has been a problem that the transfer rate of image data decreases due to the transfer of control data.

  Also, in the conventional portable information terminal, a method suitable for image data transfer is adopted for communication using the parallel communication line 51, and high-speed image data transfer is realized using a small number of signal lines. That is, when transferring a series of image data, the VRAM access unit 23 generates an address of the video RAM 24, thereby realizing writing to the video RAM 24 without transmitting a write destination address for each image data. Unlike the general memory interface, the parallel communication line 51 does not have an address line.

  However, since the control data write operation to the register group 27 is not a write operation to a continuous storage area like image data write to the video RAM 24, it is necessary to transmit both the write destination address and data. The parallel communication line 51 is not suitable for transfer of control data, and there is a problem that the efficiency of data transfer is poor. Further, when reading the register group 27 from the parallel communication line 51, it is necessary to specify the address of the register to be read in advance and then read the data, and the procedure between the host controller 1 and the LCD controller 2 is necessary. It was a factor that lowered the data transfer efficiency.

  Further, if the time required for writing data once (write cycle) is different between the video RAM 24 and the register group 27, is the write cycle performed via the parallel communication line 51 adopted the slower one? Alternatively, it is necessary to change the write cycle according to the write destination. However, when two data output timings are properly used for one parallel communication line 51, there is a problem that the control procedure or circuit configuration of the display processor 11 becomes complicated.

  Further, even the control data generated by the host processor 10 must be transferred from the display processor 11, which causes a problem that the performance of the display processor 11 is lowered.

  The present invention has been made in view of the above circumstances, and provides a portable information terminal capable of performing efficient data communication between a display controller and a host controller that generates image data and control data. The purpose is to do. In particular, transfer of image data from the host controller to the display controller can be speeded up without complicating the circuit configuration of the host controller and without increasing the number of data signal lines connected to the host controller. An object is to provide a portable information terminal.

  A portable information terminal according to the present invention includes a display device that displays an image, a host controller that generates image data, a display controller that is interposed between the display device and the host controller, and the host controller and the display. The controller is connected by the first data communication line and the second data communication line and has the following characteristics.

  In the portable information terminal according to the first aspect of the present invention, the display controller is input via the second data communication line together with the video RAM for storing the image data input via the first data communication line. A register group that stores write control data and peripheral device control data; a VRAM access unit that generates an address of the video RAM as a write destination when writing the image data based on the write control data; Based on the peripheral device control data, it is configured to include a peripheral device controller that performs signal input / output with a peripheral device that is detachably connected to the portable information terminal.

  The image data generated by the host controller is transferred to the display controller via the first data communication line, and the write control data and peripheral device control data generated by the host controller are displayed via the second data communication line. Transferred to the controller. The address on the video RAM where the image data is written is generated in the display controller based on the write control data. Therefore, there is no need to transfer the video RAM address and write control data via the first data communication line. Therefore, it is possible to speed up the transfer of image data performed via the first data communication line without complicating the control procedure and circuit configuration of the host controller. In addition, a peripheral device control unit is provided in the display controller, and write control data is also transferred using the second data communication line used for transferring peripheral device control data, so the number of data communication lines is increased. Therefore, the transfer of image data can be speeded up.

  The LCD display device 3 to be described later is an example of the display device, the LCD controller 2N is an example of the display controller, and the present invention is not limited to a mobile phone having an LCD display device.

  In the portable information terminal according to the second aspect of the present invention, the host controller transmits write control data defining a storage area of the series of image data on the video RAM prior to transmission of the series of image data. The VRAM access unit is configured to generate an address of the video RAM based on the write control data when each image data is written to the video RAM.

  In the portable information terminal according to the third aspect of the present invention, the first data communication line includes a communication line for performing parallel communication, and the second data communication line includes a communication line for performing serial communication. The bit rate of the first data communication line is configured to be higher than that of the second data communication line.

  ADVANTAGE OF THE INVENTION According to this invention, the portable information terminal which can perform efficient data communication between the host controller which produces | generates image data and control data, and a display controller can be provided. In particular, it is possible to provide a portable information terminal capable of simultaneously transferring image data and control data from the host controller to the display controller without reducing the image data transfer speed.

  Further, it does not complicate the control procedure and circuit configuration of the host controller, and speeds up the transfer of image data from the host controller to the display controller without increasing the number of data signal lines connected to the host controller. A portable information terminal can be provided.

  Furthermore, since only the image data is transferred from the first data communication line, if the host controller is constituted by the display processor and the host processor, the display processor can be used during the period when the image data is not transferred. A portable information terminal capable of stopping the function and reducing the power consumption of the host controller can be provided.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a schematic configuration example of a portable information terminal according to Embodiment 1 of the present invention. Here, a cellular phone is shown as an example of the portable information terminal. The host controller 1 operates based on a program held in the program storage unit 13 and controls each block constituting the mobile phone. The wireless communication unit 14 performs wireless communication with a base station (not shown), and the user can talk using the handset 17. Such call processing and outgoing / incoming processing are controlled by the host controller 1. When the user performs a key operation, the host controller 1 executes a predetermined process based on an operation signal from the key operation unit 16. The image data captured by the camera unit 15 is temporarily stored in the image data storage unit 12 by the host controller 1 and compressed according to an existing image compression method such as the JPEG format, and then stored in a nonvolatile memory such as a flash memory or an SD card. Stored in sex memory.

  Further, image data displayed on the screen of the LCD display device 3 is also generated by the host controller 1. For example, image data to be displayed on the screen is generated by the host controller 1 reading out image data held in an SDRAM, flash memory, SD card or the like and processing the image data. The image data generated in this way is temporarily stored in the LCD controller 2N and output to the LCD display device 3 at a predetermined timing. The LCD controller 2N also performs signal input / output and control for peripheral devices based on instructions from the host controller 1.

  FIG. 2 is a block diagram showing in more detail the main part of the mobile phone shown in FIG. 1, and shows each block related to screen display, that is, host controller 1, LCD controller 2N, LCD display device 3, and image data storage unit. 12 and a program storage unit 13 are shown. That is, it is a block diagram showing an example of the configuration of the display system built in the mobile phone of FIG.

  The LCD controller 2N in the figure is a semiconductor device in which the functions of the conventional LCD controller 2 and the I / O controller 4 are integrated. The LCD controller 2N is provided as a semiconductor device different from the host controller 1, and is disposed so as to be interposed between the host controller 1 and the LCD display device 3 and also between the host controller 1 and peripheral devices (not shown). Has been. The host controller 1 and the LCD controller 2N are connected by two data communication lines, that is, a serial communication line 50 and a parallel communication line 51. Note that the semiconductor device in this specification means circuit elements that are formed on a single semiconductor substrate and are independent from each other until they are fixed onto a printed circuit board.

  The serial communication line 50 is a data communication line for performing serial communication between the host processor 10 and the LCD controller 2N. Here, it is composed of a clock signal line SCL (Serial Clock Line) for transmitting a clock signal from the host processor 10 and a data signal line SDA (Serial Data line) for transmitting and receiving a data signal. It is assumed that I2C (registered trademark) is adopted.

  The parallel communication line 51 is a data communication line for performing parallel communication between the display processor 11 and the LCD controller 2N. Here, a chip select signal line CS indicating access to the LCD controller 2N, a write signal line WRB indicating data writing, a read signal line RDB indicating data reading, and a plurality of data signal lines D0 to D7 are used. It is assumed that 8-bit data can be transmitted and received at the same time, but the address lines are omitted.

  The image data storage unit 12 is a storage device that holds image data. For example, an SDRAM (Synchronous Dynamic RAM) that operates in synchronization with a clock signal of the host controller 1 is used. This image data is read by the host processor 10 or the display processor 11, and desired image processing is performed in the display processor 11, whereby image data that can be stored in the LCD controller 2N is generated. Note that the image data is pixel data or vector data defining a still image or an operation image, or a collection of these.

  The program storage unit 13 is a storage device that holds programs and data. For example, a flash memory that is an electrically rewritable nonvolatile semiconductor memory is used. The host processor 10 sequentially executes the program read from the program storage unit 13. Further, after initializing the display processor 11, the host processor 10 reads a program or microcode for the display processor 11 from the program storage unit 13 and writes it in the memory in the display processor 11.

  The host controller 1 includes a host processor 10, a display processor 11, and a timing control unit 18. The host processor 10, the display processor 11, and the timing control unit 18 can be configured as different semiconductor devices, but can also be configured as one semiconductor device.

  The display processor 11 generates image data to be displayed on the screen based on the image data read from the image data storage unit 12. For example, MPEG4, H.264. Decoding processing that expands moving image data encoded in a format such as H.263 into image data for each frame, enlargement processing, reduction processing, rotation processing, inversion processing, format conversion processing, color space correction processing, superposition of image data Processing is performed. The image data generated in this way is transferred to the LCD controller 2N at high speed via the parallel communication line 51. At this time, prior to the transfer of a series of image data by the display processor 11, write control data defining the operation of the VRAM access unit 23 is output from the host processor 10 to the LCD controller 2N.

  The host processor 10 outputs control data to the LCD controller 2N via the serial communication line 50, and performs various controls on the LCD controller 2N and the LCD display device 3 except for the processing performed by the display processor 11. Here, for the LCD controller 2N, write control data defining the operation of the VRAM access unit 23, output control data defining the operation of the image data output unit 25, LCD control data defining the operation of the LCD display device 3, Peripheral device control data defining the operation of the peripheral device control unit 29 is output.

  The timing control unit 18 controls access timing to the LCD controller 2N by the host processor 10 and the display processor 11. Here, the operation timing of both is adjusted so that the image data is transferred by the display processor 11 after the transfer of the write control data by the host processor 10 is completed.

  The LCD controller 2N includes a display communication unit 21, a control communication unit 22, a VRAM access unit 23, a video RAM 24, an image data output unit 25, a register access unit 26, a register group 27, a control data output unit 28, and a peripheral device control unit. 29.

  The display communication unit 21 is connected to the parallel communication line 51 and performs image data transmission / reception processing with the display processor 11. The display communication unit 21 outputs the image data received via the parallel communication line 51 to the VRAM access unit 23 and sends the image data input from the VRAM access unit 23 to the parallel communication line 51.

  The control communication unit 22 is connected to the serial communication line 50 and performs reception processing of write control data, output control data, LCD control data, and peripheral device control data sent from the host processor 10. These data are output from the control communication unit 22 to the register access unit 26.

  The VRAM access unit 23 writes the image data received by the display communication unit 21 to the video RAM 24 and outputs the image data read from the video RAM 24 to the display communication unit 21. The image data is written by sequentially writing a series of image data into the video RAM 24 based on the write control data in the register group 27. Since a series of image data transferred from the display processor 11 has a continuous pixel position, the VRAM access unit 23 uses an address on the video RAM 24 as a write destination based on the write control data. Is generated and high-speed writing of image data is performed. The write control data includes, for example, information such as the format of the image data, the pixel position where writing to the video RAM 24 is started, the writing direction, the writing range, and writing prohibition permission.

  The video RAM 24 is a semiconductor storage device that stores image data in a rewritable manner, and stores the image data received by the display communication unit 21 in association with the pixel position designated by the VRAM access unit 23. The image data stored in the video RAM 24 is read by the image data output unit 25 and output to the LCD display device 3. Note that the video RAM is provided with an input buffer for reducing overhead during writing, and the average writing speed is faster than that of the register group 27.

  The image data output unit 25 is connected to the LCD display device 3 through the data communication line 53, processes the image data read from the video RAM 24 based on the output control data in the register group 27, and registers The processed image data is output to the data communication line 53 at a timing based on the output control data in the group 27. This output control data includes, for example, information such as the color palette of image data, transfer speed, format, horizontal / vertical signal output timing, and pixel data output timing. Further, the transmission of image data through the data communication line 53 employs RGB666 parallel communication or LVDS (Low Voltage Differential Signaling) system, for example, image data is transmitted at a frame rate of 60 frames per second. Transferred.

  The register group 27 is a rewritable semiconductor memory device including a plurality of registers that hold control data. The register access unit 26 writes the control data received by the control communication unit 22 to the register group 27. The control data read from the register group 27 is output to the control communication unit 22. That is, write control data, output control data, LCD control data, and peripheral device control data input from the host processor 10 via the serial communication line 50 are sent to any register in the register group 27 by the register access unit 26. Is written to.

  The control data output unit 28 is connected to the LCD display device 3 via the data communication line 52 and outputs the LCD control data in the register group 27 to the LCD display device 3. The LCD control data includes various control information except image data input to the LCD display device 3 via the data communication line 53. For example, it includes information such as image data transfer speed and format information, horizontal and vertical signal output timing, pixel data output timing, voltage control of the driver circuit 32 in the LCD display device 3, and gamma correction. These pieces of information are output to the LCD display device 3.

  The peripheral device control unit 29 performs signal input / output and control with respect to a peripheral device (not shown) based on the peripheral device control data, and has a function as, for example, a USB transceiver and a level shifter that converts a signal level. That is, it corresponds to the I / O controller 4 in the conventional mobile phone shown in FIG. The peripheral devices targeted by the peripheral device control unit 29 include not only external devices that are detachably attached, such as USB devices and SD cards, but also internal devices that are built in the mobile phone in advance. .

  The LCD display device 3 is a display device that displays the image data transferred from the video RAM 24 of the LCD controller 2N on the screen. The LCD display device 3 includes a communication unit 31 that receives image data via a data communication line 53, a driver circuit 32 that drives a liquid crystal display panel 33 based on the received image data, and a liquid crystal display panel having a display screen. 33. The communication unit 31 and the driver circuit 32 can be configured as different semiconductor devices, but can also be configured as a single semiconductor device.

  The communication unit 31 and the driver circuit 32 operate based on LCD control data input via the data communication line 52. If the image data cannot be correctly received from the LCD controller 2N, the communication unit 31 generates an interrupt signal (interrupt signal) as a control signal for notifying a reception error, and outputs the interrupt signal to the LCD controller 2N or the host controller 1. .

  FIG. 3 is a block diagram showing a more detailed configuration example of the register access unit 26 and the register group 27 of FIG.

  The register group 27 includes two or more registers 71 and an RA (Read Address) register 72, both of which are accessed from the host processor 10 via the serial communication line 50. The register 71 stores write control data, output control data, LCD control data, and peripheral device control data. On the other hand, the RA register 72 is a register in which an address (read address) of a register to be read is written in advance when the control data held in the register 71 is read.

  The register access unit 26 includes an input buffer 61, an address decoder 64, and a selector 65. The input buffer 61 temporarily stores a data write request from the control communication unit 22. The input buffer 61 includes an address storage unit 62 and a data storage unit 63, a register address as a write destination is stored in the address storage unit 62, and data to be written is stored in the data storage unit 63.

  The address decoder 64 decodes a register address that specifies a register in the register group 27. At the time of writing, the register address in the address storage unit 62 is decoded. The selector 65 selects one of the registers constituting the register group 27 based on the decoding result. Data in the data storage unit 63 is written to the register selected in this way.

  Steps S101 to S104 in FIG. 4 are flowcharts illustrating an example of the operation in the register access unit 26 in FIG. 3, and a processing procedure at the time of data writing (writing) to the register group 27 is shown. First, the input buffer 61 stores the register address and data input from the host processor 10 via the serial communication line 50 in the address storage unit 62 and the data storage unit 63, respectively. (Step S101).

  Next, the register address in the address storage unit 62 is output to the address decoder 64, and the data in the data storage unit 63 is output to the selector 65. The address decoder 64 decodes the register address and outputs the decoding result to the selector 65 (step S102). Based on the decoding result, the selector 65 selects a register as a write destination, and writes the data in the data storage unit 63 to the register (steps S103 and S104).

  Steps S201 to S204 in FIG. 5 are flowcharts illustrating an example of the operation in the register access unit 26 in FIG. 3, and a processing procedure at the time of data reading (reading) from the register group 27 is shown.

  First, the host controller 1 writes the address (read address) of the register to be read into the RA register 72 in the register group 27 (steps S201 and S202). Next, when a read request for the register group 27 is input from the host processor 11 to the control communication unit 22, the control data held in the register at the address specified by the RA register 72 is read (step S203). Then, the register address (read address) stored in the RA register 72 and the data read from the register are output to the host processor 10 via the serial communication line 50 (step S204).

  Steps S301 to S305 in FIG. 6 are flowcharts showing an example of the image data transmission operation in the host controller 1 in FIG. 2, and an example in which the operation timing of the display processor 11 is controlled by the host processor 10 is shown. It is shown.

  First, the host processor 10 sends write control data to the serial communication line 50 and writes it to the register group 27 of the LCD controller 2N (step S301). This write control data includes image data format information, write permission information for the video RAM 24, and information necessary for generating an address when writing the image data. When transmission of the write control data is completed, the host processor 10 notifies the timing controller 18 of permission to transmit image data, and the display processor 11 starts generating image data (step S302).

  Next, the display processor 11 sequentially sends the generated image data to the parallel communication line 51 and writes it in the video RAM 24 of the LCD controller 2N (step S303). At this time, the write destination address in the video RAM 24 is generated by the VRAM access unit 24 based on the write control data. The transmission of the image data is repeated until all the image data is transmitted (step S304).

  When the transmission of all the image data is completed, the timing control unit 18 notifies the host processor 10 of the completion of the image data transfer. Based on the transfer completion notification, the host processor 10 sends the write control data to the serial communication line 50 again and writes it to the register group 27 of the LCD controller 2N (step S305). This write control data includes information for prohibiting writing to the video RAM 24.

  FIG. 7 is a timing chart showing an example of data communication between the host controller 1 and the LCD controller 2N performed via the parallel communication line 51, and shows a state in which image data is transmitted from the host controller 1. Yes. The image data generated by the display processor 11 is sequentially output to the data signal lines D0 to D7 and transferred to the LCD controller 2N. The display communication unit 21 takes in the signal levels of the data signal lines D0 to D7 based on the chip select signal CS and the write signal WRB from the display processor 11, and sequentially receives the image data.

  FIG. 8 is a timing chart showing an example of data communication between the host controller 1 and the LCD controller 2N performed via the serial communication line 50. (A) in the figure shows the data write operation to the register group 27 by the host processor 10, and (b) in the figure shows the data read operation from the register group 27 by the host processor 10. Has been.

  In register writing, first, when the clock signal line SCL is at a high level, the host processor 10 changes the data signal line SDA from a high level to a low level and activates the serial communication line 50 (start condition). Next, by outputting a 7-bit slave address indicating register access to the data signal line SDA, the control communication unit 22 recognizes that access to the register group 27 has started. If the next data signal (eighth clock) following the slave address is at a low level, the control communication unit 22 recognizes that the access is a register write.

  If the control communication unit 22 outputs an ACK signal (acknowledge signal) at the subsequent 9th clock, the register address to be written and the data to be written are transferred by the host processor 10 to the data signal line SDA bit by bit. Output sequentially. In the control communication unit 22, the register address and data are received based on the clock signal line SCL and written to the register group 27 by the register access unit 26. The address and data are each input as 8-bit information. When the ACK signal is output from the control communication unit 22 at the ninth clock after the data is input and the clock signal line SCL is at the high level, the host processor 10 When the data signal line SDA is changed from the low level to the high level, the control communication unit 22 recognizes that the access to the register group 27 is finished (end condition), and the writing is finished.

  In the case of register read, the host processor 10 writes the address (read address) of the register to be read into the RA register 72 of the LCD controller 2N via the serial communication line 50 in accordance with the register write operation described above. Next, as in the case of register writing, if access to the register group 27 is started and the next data signal (eighth clock) following the 7-bit slave address is high, the control communication unit 22 Recognize that the access is a register read.

  At the subsequent ninth clock, the control communication unit 22 outputs an ACK signal (acknowledge signal), and then outputs the read address to the data signal line SDA as 8-bit information. If the host processor 10 outputs the ACK signal at the subsequent ninth clock, the data read from the register group 27 is output to the data signal line SDA by the control communication unit 22 based on the read address. When the non-ACK signal is output from the host processor 10 at the ninth clock after the 8-bit data is output and the clock signal line SCL is at the high level, the host processor 10 changes the data signal line SDA from the low level. When the level is changed to the high level, the control communication unit 22 recognizes that the access to the register group 27 is completed (end condition), and the reading is completed.

  According to the present embodiment, the image data generated by the host controller 1 is transferred to the LCD controller 2N via the parallel communication line 51, and the address on the video RAM 24 where the image data is written is the write control data. Is generated by the VRAM access unit 23 in the LCD controller 2N. On the other hand, the write control data and peripheral device control data generated by the host controller 1 are transferred to the LCD controller 2N via the serial communication line 50.

  Therefore, when transferring image data to the LCD controller 2N, it is not necessary to transfer the address of the video RAM 24 or the write control data via the parallel communication line 51, and the control procedure and circuit configuration of the display processor 11 are complicated. Without this, the transfer of image data performed via the parallel communication line 51 can be speeded up. In particular, in the LCD controller 2N, when the write cycle to the video RAM 24 is shorter than the write cycle to the register group 27, the transfer of image data from the display processor 11 to the video RAM 24 can be easily accelerated.

  Further, the peripheral device control unit 29 is provided in the LCD controller 2N, and the write communication data is transferred using the serial communication line 50 used for transferring the peripheral device control data. The transfer of image data can be speeded up without increasing the number of lines.

  In the present embodiment, image data is input to the LCD controller 2N via the parallel communication line 51, and control data for peripheral devices including the LCD display device 3 is input via the serial communication line 50. However, the present invention is not limited to this example. For example, the present invention can also be applied to a case where image data is input via the serial communication line 50 and control data is input via the parallel communication line 51. Also, the present invention can be applied to the case where the two data communication lines 50 and 51 are both parallel communication lines or both are serial communication lines.

  Furthermore, in the present embodiment, the timing processor 18 notifies the host processor 11 of the completion of image data transfer after the display processor 11 finishes transferring one frame of image data to the LCD controller 2N. It is not limited to. For example, a register including a bit indicating whether or not the display processor 11 is transmitting image data is provided in the timing control unit 18, and the host processor 10 polls the register to complete the image data transfer by the display processor 11. You may be the structure which confirms whether it did.

Embodiment 2. FIG.
In the first embodiment, an example in which the operation timing of the display processor 11 is controlled by the host processor 10 has been described. On the other hand, in the present embodiment, a case will be described in which the host processor 10 and the display processor 11 are operating at their own timing.

  FIG. 9 is a sequence diagram showing an example of an image data transmission operation in the host controller 1 of FIG. When outputting the write control data to the serial communication line 50, the host processor 10 outputs a write control data transmission request signal to the timing control unit 18. The timing control unit 18 determines whether or not write control data can be transmitted from the host processor 10 to the LCD controller 2N based on the access status of the display processor 11 to the LCD controller 2N.

  When the host processor 10 receives the transmission permission signal from the timing control unit 18, the host processor 10 transmits the write control data to the LCD controller 2N via the serial communication line 50. When the transmission of the write control data is completed, the host processor 10 outputs a transmission completion notification signal to the timing control unit 18. When the timing control unit 18 receives the transmission completion notification signal from the host processor 10, the timing control unit 18 returns an ACK signal (response signal) to the host controller, and a series of processing for transmitting the write control data to the LCD controller 2N is completed.

  On the other hand, the display processor 11 reads out image data in the image data storage unit 12 and generates image data to be written in the video RAM 24. The display processor 11 outputs an image data transmission request signal to the timing controller 18 when transmitting the generated image data to the LCD controller 2N. At this time, if transmission of the write control data by the host processor 10 is not completed, the timing control unit 18 returns a transmission rejection signal to the display processor 11 and does not permit transmission of the image data.

  If the display processor 11 outputs the image data transmission request signal after the transmission of the write control data is completed, the timing control unit 18 determines that the display processor 11 can transmit the image data to the LCD controller 2N, and the display processor 11 11, a transmission permission signal is returned. When the display processor 11 receives the transmission permission signal from the timing control unit 18, the display processor 11 starts transmission of image data to the LCD controller 2N via the parallel communication line 51. When the transmission of the image data is completed, the display processor 11 outputs a transmission completion notification signal to the timing control unit 18, and an ACK signal is returned to the display processor 11 from the timing control unit 18 that has received the transmission completion notification signal. A series of image data transmission processing to the LCD controller 2N is completed.

  According to the present embodiment, the timing control unit 18 controls the timing of transmission of write control data by the host processor 10 and transmission of image data by the display processor 11. For this reason, even when the host processor 10 and the display processor 11 are operating at independent timing, image data can be transmitted to the LCD controller 2N after transmission of the write control data is completed.

Embodiment 3 FIG.
In the first and second embodiments, an example has been described in which transmission / reception of image data between the host controller 1 and the LCD controller 2N is performed via the parallel communication line 51. In contrast, in the present embodiment, a case will be described in which the parallel communication line 51 is used for transmission of image data by the host controller 1 and the serial communication line 50 is used for reception of image data by the host controller 1.

  FIG. 10 is a block diagram showing a configuration example of the main part of the portable information terminal according to the second embodiment of the present invention. Compared with FIG. 2, the VRAM access unit 23 is displayed in the LCD controller 2N. It is different in that it is connected to the communication unit 21 for control and the communication unit 22 for control. Furthermore, when the two-wire communication standard I2C (registered trademark) is adopted for the serial communication line 50, the control communication unit 22 has a slave address for accessing the register group 27 and a slave address for accessing the VRAM 24. Whether the access to the register group 27 or the access to the VRAM 24 is made based on the slave address prepared and received from the host processor 10.

  In this portable information terminal, the image data is written by the host controller 1 through the parallel communication line 51 as in the case of the above embodiment, but the image data is read out through the serial communication line 50. Is called. That is, the image data in the video RAM 24 read by the VRAM access unit 23 is output to the control communication unit 22 and output to the host processor 10 via the serial communication line 50.

  When image display is performed using the LCD display device 3, image data is written from the host controller 1 to the video RAM 24, and it is not usually necessary for the host controller 1 to read image data in the video RAM 24. However, for example, when designing a portable information terminal, it may be necessary to read arbitrary image data in the video RAM 24 for debugging work. By reading such image data through the serial communication line 50, the parallel communication line 51 can be dedicated to writing image data to the LCD controller 2N. As a result, the control procedure and circuit configuration of the display processor 11 can be simplified, and the transfer of image data from the host controller 1 to the LCD controller 2N can be further accelerated.

  Also, when debugging, connecting an external device to the data communication line 50 or 51 between the host controller 1 and the LCD controller 2N and monitoring the transmission data is more compatible with the multi-master bus than the parallel communication line 51. When the serial communication line 50 such as the I2C interface is used, it is easier to connect the external device and read the VRAM 24 from the external device. Therefore, outputting image data read from the video RAM 24 to the serial communication line 50 is also suitable for debugging work.

1 is a block diagram illustrating a schematic configuration example of a mobile phone according to a first embodiment of the present invention. FIG. 2 is a block diagram illustrating in detail a main part of the mobile phone in FIG. 1. FIG. 3 is a block diagram showing a more detailed configuration example of a register access unit 26 and a register group 27 in FIG. 2. 4 is a flowchart showing an example of a data write operation in the register access unit 26 of FIG. 3. 4 is a flowchart showing an example of a data read operation in the register access unit 26 of FIG. 3. 3 is a flowchart showing an example of an image data transmission operation in the host controller 1 of FIG. 2. 3 is a timing chart showing an example of data communication performed via a parallel communication line 51. 4 is a timing chart showing an example of data communication performed via a serial communication line 50. FIG. 3 is a sequence diagram showing an example of an image data transmission operation in the host controller 1 of FIG. 2. It is the block diagram which showed one structural example about the principal part of the portable information terminal by Embodiment 3 of this invention. It is the block diagram which showed one structural example about the principal part of the conventional portable information terminal.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Host controller 2N LCD controller 3 LCD display device 10 Host processor 11 Display processor 12 Image data storage part 13 Program storage part 14 Wireless communication part 15 Camera part 16 Key operation part 17 Handset 18 Timing control part 19 Analog control part 21 For display Communication unit 22 Control communication unit 23 VRAM access unit 24 Video RAM
25 Image data output unit 26 Register access unit 27 Register group 28 Control data output unit 29 Peripheral device control unit 31 Communication unit 32 Driver circuit 33 Liquid crystal display panel 50 to 53 Data communication line 61 Input buffer 62 Address storage unit 63 Data storage unit 64 Address decoder 65 Selector 71 Register 72 RA register MCLK Internal clock signal CS Chip select signal line RSP Select signal line SCL Clock signal line SDA Data signal line WRB Write signal RDB Read signal

Claims (3)

In a portable information terminal comprising a display device for displaying an image, a host controller for generating image data, and a display controller interposed between the display device and the host controller.
The host controller and the display controller are connected by a first data communication line and a second data communication line,
A video RAM for storing image data input via the first data communication line by the display controller;
A register group for storing write control data and peripheral device control data both input via the second data communication line;
A VRAM access unit that generates an address of the video RAM as a writing destination when writing the image data based on the writing control data;
A portable information terminal comprising: a peripheral device control unit that performs signal input / output with a peripheral device that is detachably connected to the portable information terminal based on the peripheral device control data. Prior to transmission of a series of image data, the host controller transmits write control data defining a storage area of the series of image data on the video RAM,
The portable information terminal according to claim 1, wherein the VRAM access unit generates an address of the video RAM based on the write control data when each image data is written to the video RAM.   The first data communication line is a communication line for performing parallel communication, the second data communication line is a communication line for performing serial communication, and the bit rate of the first data communication line is second. The portable information terminal according to claim 1, wherein the portable information terminal is higher than a data communication line.

Images