JP2009032211A - Portable electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily achieve a synchronous serial bus connection between a control side circuit having only an existing parallel interface part and a controlled side circuit by suppressing increase of the mounting area on a substrate or costs. <P>SOLUTION: A host side circuit is provided with a parallel bus controller 100, and configured to perform serial communication with a device having a serial interface part 203. Parallel/serial converted data are output from a data bus (D0), and address data and a signal for selection for selecting data corresponding to the address data by the serial interface part 203 are output from an address bus (A0) to the serial interface part 203. The address and data are transmitted by serial communication bit by bit from the host side to the device side. Also, this portable electronic equipment is provided with a bit width conversion part for converting the data received by the data bus into data with predetermined bit width in order to achieve a bus width adjusting function. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention uses an asynchronous parallel interface in a central processing unit (hereinafter abbreviated as “CPU”) such as a central processing unit, so that serial communication can be performed with an asynchronous serial interface of a desired device. It relates to electronic equipment.

  As a bus interface between devices in an electronic apparatus, for example, a configuration in which a CPU having a parallel bus interface is connected to a target device by a parallel bus connection and the device is controlled is known. A configuration is also known in which a predetermined controller (SPI controller, USB controller, etc.) is interposed between a CPU having a parallel bus interface and a target device having a synchronous interface. For example, Patent Document 1 discloses an interface circuit in which a parallel / serial conversion circuit and a serial / parallel conversion circuit are provided on the host side and the target device side.

  FIG. 7 shows a host-side parallel bus controller 100 including a CPU and a device-side bus interface unit 200 as an example of a conventional parallel bus connection. In the parallel bus controller 100 and the bus interface unit 200, “A0 to A7” indicate address terminals, and “D0 to D7” indicate data terminals. “RD” indicates a read terminal, “WR” indicates a write terminal, and “CS” indicates a chip select terminal.

  The “A0 to A7” terminals of the parallel bus controller 100 are connected to the “A0 to A7” terminals of the bus interface unit 200 corresponding to these terminals. Similarly, the “D0 to D7” terminals of the parallel bus controller 100 are connected to these terminals. Are connected to each of the “D0 to D7” terminals of the bus interface unit 200 corresponding to. In the parallel bus controller 100 and the bus interface unit 200, the RD terminals are connected, the WR terminals are connected, and the CS terminals are connected.

  FIG. 8 schematically shows the main part of the circuit configuration in the bus interface unit 200. Address data from the “A0 to A7” terminals is stored in the address buffer 200a, and data from the “D0 to D7” terminals is stored in the write data buffer 200c via the switching unit 200b. Then, the data in the read data buffer 200d is sent to the “D0 to D7” terminals via the switching unit 200b. The switching unit 200b is controlled based on a signal from the decoder 200e, and the decoder 200e is supplied with signals from the RD terminal, the WR terminal, and the CS terminal. Further, predetermined internal processing is performed on the data in each buffer in a circuit unit (not shown).

  According to such a parallel bus connection method, there is an advantage that a desired device can be directly connected to the host-side parallel bus controller at a relatively high speed. On the other hand, there is a one-to-one correspondence between the terminals, and the number of wires increases, so the required area of the substrate and wiring increases, and the number of pins of the device increases and the package size increases. End up. And the bus width (number of bus lines) cannot be adjusted and only a fixed bus width can be used (for example, when the bus bandwidth in the system is low, the area required for the board and wiring cannot be reduced by narrowing the bus width. ).

  Next, the synchronous serial bus connection will be described with reference to FIGS.

  FIG. 9 shows, as an example of a synchronous serial bus connection, a parallel bus controller 100 on the host (for example, CPU) side, a serial bus interface unit 201 on the device side, and a parallel / serial interface arranged therebetween. The controller 300 is shown. The parallel bus controller 100 is as described above, and the bus interface unit 201 includes a data terminal indicated by “D0”, a clock terminal indicated by “CLK”, and a chip select terminal indicated by “CS”.

  For the controller 300, for example, a serial interface represented by SPI (Serial Peripheral Interface) is used, and “A0 to A7” indicate address terminals, and “D0 to D7” indicate data terminals. “RD” indicates a read terminal, “WR” indicates a write terminal, and “CS” indicates a chip select terminal. These terminals are connected to corresponding terminals in the parallel bus controller 100. The controller 300 includes a data terminal indicated by “D0”, a clock terminal indicated by “CLK”, and a chip select terminal indicated by “CS”, and these terminals are connected to corresponding terminals in the bus interface unit 201. .

  FIG. 10 shows another example of the synchronous serial bus connection, the parallel bus controller 100 on the host (for example, CPU) side, the serial bus interface unit 202 on the device side, and the USB (Universal Serial) arranged between the two. Bus) controller 301 is shown. The parallel bus controller 100 is as described above, and the bus interface unit 202 includes a “D +” terminal and a “D−” terminal.

  The USB controller 301 is provided with a PLL (phase locked loop) circuit 400, “A0 to A7” indicate address terminals, “D0 to D7” indicate data terminals, and “RD” indicates a read terminal. , “WR” indicates a write terminal, and “CS” indicates a chip select terminal. These terminals are connected to corresponding terminals in the parallel bus controller 100. The USB controller 301 includes a “D +” terminal and a “D−” terminal, and these terminals are connected to corresponding terminals in the bus interface unit 202.

In the synchronous serial bus connection method as described above, a moderate data transfer speed can be obtained, and the number of wirings between the controller 300 or 301 and the device-side bus interface unit 201 or 202 is small. The advantage is that the required area can be reduced. On the other hand, since the controllers 300 and 301, the PLL circuit 400, and the like are required, the cost increases and the number of parts becomes a problem.
JP 2005-142463 A

  As described above, the conventional parallel bus connection method has a problem that the number of pins on the device side, and hence the number of wires, is large, a large occupied area is required, and the bus width adjustment is not easy.

  Therefore, when the device controlled from the host side does not require a very high transmission rate, it is advantageous from the viewpoint of the mounting area on the board to adopt the serial connection method.

  However, in the conventional synchronous serial connection method, it is necessary to add a serial bus controller, a PLL circuit, and the like separately from the parallel bus controller on the host side, which increases the circuit scale and causes an increase in cost.

  Therefore, an object of the present invention is to easily realize an asynchronous serial bus connection between a control side circuit having only a parallel interface unit and a controlled side circuit while suppressing an increase in mounting area and cost on a substrate. There is.

  In order to solve the above problems, a portable electronic device according to the present invention includes a central processing unit that includes a parallel interface unit and performs conversion processing between parallel data and serial data therein, and a device including the serial interface unit. The central processing unit outputs data converted from parallel data to serial data via a data bus from the parallel interface unit to the serial interface unit, and the serial interface unit and the address data and the A selection signal for selecting data corresponding to address data is output from the parallel interface unit to the serial interface unit via an address bus, and the address data and the data corresponding to the address data are the most significant bit or the least significant bit. And transmits the serial communication one bit the device in order from.

  Further, when data of 2 bits or more is transmitted from the parallel interface unit to the serial interface unit via the data bus in the portable electronic device, the data received by the device on the data bus is determined in advance. It is preferable to provide a bit width conversion unit that converts the data into the data having the specified bit width.

  According to the present invention, it is possible to easily realize asynchronous serial bus connection between a control side circuit having only an existing parallel interface unit and a controlled side circuit.

  Embodiments of the present invention will be described below.

  FIG. 1 is an external perspective view of a mobile phone device as an example of a mobile electronic device according to the present invention. 1 shows a form of a so-called foldable mobile phone device, the form of the mobile phone device according to the present invention is not particularly limited to this. For example, a sliding type in which one casing is slid in one direction from a state in which both casings are overlapped, or a rotary type in which one casing is rotated around an axis along the overlapping direction ( Turn type), or a type (straight type) in which the operation unit and the display unit are arranged in one housing and does not have a connecting unit.

  The portable electronic device 1 includes an operation unit side housing unit 2 and a display unit side housing unit 3. The operation unit side body unit 2 includes an operation unit 11 and a microphone 12 to which a voice uttered by a user of the portable electronic device 1 is input on the surface unit 10. The operation unit 11 includes a function setting operation button 13 for operating various functions such as various settings, a telephone book function, and a mail function, and an input operation button 14 for inputting a telephone number and characters such as mail. , And a determination operation button 15 for performing determination and scrolling in various operations.

  Further, the display unit side body unit 3 includes, on the surface unit 20, an LCD (Liquid Crystal Display) display unit 21 for displaying various types of information, and a speaker 22 for outputting the voice of the other party of the call. It is configured.

  Further, the upper end of the operation unit side body 2 and the lower end of the display unit side body 3 are connected via a hinge mechanism 4. In addition, the portable electronic device 1 relatively rotates the operation unit side body 2 and the display unit side body 3 that are connected via the hinge mechanism 4, thereby operating the operation unit side body 2. The display unit side body 3 can be opened from each other, or the operation unit side body 2 and the display unit side body 3 can be folded.

  FIG. 2 is a functional block diagram showing functions of the mobile electronic device 1. The portable electronic device 1 includes an operation unit 11, a microphone 12, a main antenna 40, an RF circuit unit 41, an LCD control unit 42, an audio processing unit 43, a memory 44, a CPU 45, and a power supply unit 46 on the operation unit side, and an LCD display unit 21, a speaker 22, and a driver IC 23 are provided on the display unit side.

  The main antenna 40 communicates with an external device in a predetermined use frequency band (for example, 800 MHz). In the present embodiment, the predetermined use frequency band is 800 MHz, but other frequency bands may be used. Further, the main antenna 40 may have a so-called dual-band compatible configuration that can support other use frequency bands (for example, 2 GHz) in addition to a predetermined use frequency band.

  The RF circuit unit 41 demodulates the signal received by the main antenna 40, supplies the processed signal to the CPU 45, modulates the signal supplied from the CPU 45, and performs an external device (via the main antenna 40). To the base station).

  The LCD control unit 42 performs predetermined image processing in accordance with control by the CPU 45 and outputs the processed image data to the driver IC 23. The driver IC 23 stores the image data supplied from the LCD control unit 42 in the frame memory and outputs it to the LCD display unit 21 at a predetermined timing.

  The audio processing unit 43 performs predetermined audio processing on the signal supplied from the RF circuit unit 41 under the control of the CPU 45 and outputs the processed signal to the speaker 22. The speaker 22 outputs the signal supplied from the sound processing unit 43 to the outside.

  In addition, the sound processing unit 43 processes a signal input from the microphone 12 according to control by the CPU 45, and outputs the processed signal to the RF circuit unit 41. The RF circuit unit 41 performs a predetermined process on the signal supplied from the sound processing unit 43 and outputs the processed signal to the main antenna 40.

  The power supply unit 46 is provided to supply a necessary voltage to each circuit unit after receiving power supply from a secondary battery or a charging device (not shown) and converting it to a predetermined voltage. It is configured using.

  In the portable electronic device 1 according to the present invention, the host side including the CPU 45 has a parallel bus interface unit, which is connected to the serial bus interface unit on the target device side by serial communication. That is, the portable electronic device 1 includes a control-side circuit such as a CPU 45 and a controlled-side circuit having a serial interface unit. In the control-side circuit, conversion between parallel data and serial data is performed by software processing. Data after serial conversion is transmitted from the control side circuit to the controlled side circuit, and data received by the control side circuit from the controlled side circuit is serial / parallel converted. In addition, as a specific target device, an optical wireless data communication circuit using infrared rays such as a sound source IC constituting the audio processing unit 43, a UART (Universal Asynchronous Receiver Transmitter) circuit, or an IrDA (Infrared Data Association) module is used. Various signal processing units.

  FIG. 3 is a circuit block diagram showing the main part of the configuration example according to the first embodiment of the present invention. In this example, a form using a 1-bit data line and a 1-bit address line is shown.

  The parallel bus controller 100 constituting the parallel interface unit is as described above. That is, on the host side, the parallel interface unit has a plurality of data terminals (D0 to D7 in this example) and address terminals (A0 to A7), as well as a read (RD) terminal, a write (WR) terminal, and a chip select (CS) terminal. Then, one of a plurality of address terminals (A0 terminal in this example), one of a plurality of data terminals (D0 terminal in this example), an RD terminal, a WR terminal, and a CS terminal are used.

  The serial interface unit 203 on the device side includes an A terminal, a D terminal, a read (RD) terminal, a write (WR) terminal, and a chip select (CS) terminal. The A terminal is A0 of the parallel bus controller 100. The D terminal is connected to the D0 terminal of the parallel bus controller 100. Note that the RD terminal, the WR terminal, and the CS terminal are connected to terminals corresponding to these terminals in the parallel bus controller 100, respectively. The chip select signal is set to negative logic (when the signal is at the Low level, the device is validated).

  In the data transfer process, data (including address data and data corresponding thereto) converted in parallel / serial by the software process is transmitted from the parallel bus controller 100 to the serial interface unit 203 on the device side on the host side, and by its internal circuit Serial / parallel conversion is performed. On the contrary, the data parallel / serial converted by the internal circuit of the serial interface unit 203 is sent to the parallel bus controller 100, and the host side performs serial / parallel conversion on the received data by software processing.

  FIG. 4 is a circuit block diagram showing a main part of a configuration example of the serial interface unit 203 on the device side.

  The D terminal is connected to the first switching unit 203a, and a signal from the D terminal is sent to the serial / parallel conversion unit 203b via the first switching unit 203a. The serial / parallel converter 203b converts the serial signal received from the host side into a parallel signal, and outputs the parallel signal to the address buffer 203d or the write data buffer 203e via the second switching unit 203c.

  The data stored in the read data buffer 203f is sent to the parallel / serial conversion unit 203g, where conversion from parallel data to serial data is performed, and the converted signal is transferred to the D via the first switching unit 203a. Sent to the terminal.

  The decoder 203h receives signals from the A terminal, the WR terminal, the RD terminal, and the CS terminal, generates an output signal corresponding to the signal state, and changes the switching state between the first switching unit 203a and the second switching unit 203c. Control. That is, according to the first switching control signal sent from the decoder 203h to the first switching unit 203a, the first switching unit 203a outputs a signal to the serial / parallel conversion unit 203b or from the parallel / serial conversion unit 203g. Is input to the first switching unit 203a. Further, in response to a second switching control signal sent from the decoder 203h to the second switching unit 203c, the second switching unit 203c outputs a signal to the address buffer 203d or a signal to the write data buffer 203e. Is output.

  FIG. 5 is a timing chart for explaining an example of a signal sequence.

  In this example, 8-bit serial data indicated by “A7 to A0” is sequentially transmitted bit by bit as a signal of the D terminal (see “signal D”), and subsequently, 8 bits indicated by “D7 to D0”. Bit serial data is sequentially transmitted bit by bit. In this example, data is transmitted bit by bit in order from the most significant bit. However, the present invention is not limited to this, and data transmission may be performed bit by bit in order from the least significant bit.

  Further, the signal at the A terminal (see “signal A”) is not address data, but an address signal (control signal) for distinguishing between address data indicated by “A7 to A0” and data indicated by “D7 to D0”. It is. That is, this signal is a selection signal for selecting address data and data corresponding to the address data in the serial interface unit 203 on the device side. In this example, the binary level of the signal A is set to the high level during the transmission period of the address data, and is set to the low level during the transmission period of data following the address data.

  The chip select signal (see “signal CS”) is negative logic. In FIG. 5, the low level period is a pulse signal wider than the high level period. Further, the read strobe signal (see “signal RD”) and the write strobe signal (see “signal WR”) are synchronized with the chip select signal, and the Low level period is narrower than the Low level period of the chip select signal. It has.

  When writing data from the host side to the device side, the signal A, the signal WR, and the signal CS are sent to the decoder 203h, and the signal D is sent to the first switching unit 203a. The signal D is output to the serial / parallel converter 203b by the first switching control signal sent from the decoder 203h to the first switching unit 203a. Then, the address buffer 203d or the write data buffer 203e is selected by the second switching control signal sent from the decoder 203h to the second switching unit 203c. That is, the address buffer 203d is selected while the signal A is at the high level, and the address data (A7 to A0) is stored as parallel data in this period. Further, the write data buffer 203e is selected during the period when the signal A is at the low level, and data (D7 to D0) are stored therein as parallel data.

  At the time of reading the device side data from the host side, the signal A, the signal RD, and the signal CS are sent to the decoder 203h. The parallel data stored in the read data buffer 203f is sent to the parallel / serial conversion unit 203g and converted into serial data. The input signal from the parallel / serial conversion unit 203g is selected by the first switching control signal sent from the decoder 203h to the first switching unit 203a, and D0 of the parallel bus controller 100 on the host side is selected as a serial signal via the D terminal. It will be sent to the terminal.

  In the above interface, the binary state of the signal A changes during the transfer of address bits and the transfer of data bits. When switching from the reading operation to the writing operation or vice versa, the data transfer and the conversion process between the serial data and the parallel data are stopped, and the interruption sequence is used to stop the reading or writing. It has a function to recognize. It has a function of recognizing a restart sequence so that the operation starts normally again when writing of address data to the address buffer 203d starts after this interruption.

  In addition, when the address exceeds the specified number of bits, it is preferable to have a function of fetching data into the address buffer 203d after performing serial / parallel conversion again from the first bit of the address.

  In this interface, it is desirable to support the continuous read mode or continuous write mode. In the former mode, when data reading continues without address writing after the read operation, the internal address is incremented automatically. Can be read continuously. In the latter mode, when data writing continues without address writing after the data writing operation, data can be continuously written by automatically incrementing the internal address.

  The host side parallel bus controller 100 and the device side serial interface unit 203 can be connected via the above interface, and one of the plurality of data buses (D0 in this example) in the parallel bus controller 100 is transmitted as a serial data signal. Can be used to transmit addresses and data. Thus, the host side circuit including the CPU can perform serial communication with the device side circuit using only the existing parallel bus interface unit. That is, in the case of data transmission from the host-side circuit to the device-side circuit, data converted from parallel data to serial data by internal processing is output from the parallel bus controller 100 to the serial interface unit 203 via the data bus, and the serial interface unit 203 The selection signal (see “signal A” in FIG. 5) for selecting the address data and the data corresponding to the address data is output from the parallel bus controller 100 to the serial interface unit 203 via the address bus. Thereby, the address data and the data corresponding to the address data can be transmitted bit by bit to the device side circuit by serial communication. In the case of data transmission from the device side circuit to the host side circuit, the data converted from parallel data to serial data in the device side circuit is output from the serial interface unit 203 to the parallel bus controller 100 via the data bus. The host side circuit can receive this data bit by bit by serial communication.

  FIG. 6 is a circuit block diagram showing a main part of a configuration example according to the second embodiment of the present invention, and shows an example of the device-side bus interface unit 204 having a bus width adjustment function.

  In the configuration shown in FIG. 4, a 1-bit data bus of a plurality of data bits is used. However, in this configuration, the bus width can be freely changed by specifying the bit width. That is, there is an advantage that the bus width can be adjusted arbitrarily or dynamically in accordance with the design and specifications of the system.

  The bus interface unit 204 has data terminals indicated by “D0 to Dn−1” (for example, n = 8), and these are connected to the first switching unit 204a. However, not all of these terminals are always used, and the terminal to be used is selected according to the designated bit width. That is, a bit width designation terminal indicated by “BTWDTH” in the figure is provided, and this is connected to the bit width designation register 204i. The A terminal, WR terminal, RD terminal, and CS terminal are connected to the decoder 204h in the same manner as described above.

  The m-bit to n-bit data conversion unit 204b is a circuit unit that converts m-bit width serial data input from the first switching unit 204a into n-bit parallel data. The data is sent to the address buffer 204d or the write data buffer 204e via the switching unit 204c. Note that m and n are variables each having a natural number value, “n” is the maximum usable bit width (for example, “n = 8”), and “m” is a bit width determined by the bit width designation terminal “BTWDTH”. The bit width is set in the designated register 204i (that is, the relationship of “n ≧ m” is satisfied). For setting the bit width m, refer to the contents of the bit width designation register 204i (the default value is, for example, 1 bit, which is the same as the serial / parallel conversion unit 203b in FIG. 4). This is performed by the data conversion unit 204b.

  The n-bit to m-bit data conversion unit 204g is a circuit unit that converts n-bit parallel data input from the read data buffer 204f into m-bit width serial data. The data is output from the m data terminals to the host side via the switching unit 204a. Regarding the setting of the bit width m, refer to the contents of the bit width designation register 204i (the default value is, for example, 1 bit, which is the same as the parallel / serial conversion unit 203g in FIG. 4 in this case). This is performed by the data conversion unit 204g.

  The data conversion units 204b and 204g constitute a bit width conversion unit 204j. When data of 2 bits or more is transmitted from the parallel interface unit to the serial interface unit via the data bus, a data bus is provided on the device side. The data of the bit width m received in step 1 is converted into n-bit data determined in advance. Further, after the n-bit data is converted into data having a bit width m on the device side, data of 2 bits or more is transmitted from the serial interface unit to the parallel interface unit via the data bus.

  The decoder 204h receives each signal from the A terminal, the WR terminal, the RD terminal, and the CS terminal, generates an output signal corresponding to the signal state, and changes the switching state between the first switching unit 204a and the second switching unit 204c. Control. That is, in response to the first switching control signal sent from the decoder 204h to the first switching unit 203a, the first switching unit 204a outputs a signal to the data conversion unit 204b, or the signal from the data conversion unit 204g 1 is input to the switching unit 204a. Further, in response to a second switching control signal sent from the decoder 204h to the second switching unit 204c, the second switching unit 204c outputs a signal to the address buffer 204d or a signal to the write data buffer 204e. Is output.

  The data read operation and data write operation are performed in the same manner as in the first embodiment except that serial data transfer is performed with a bus width specified by m bits (thus, Detailed description is omitted).

  As described above, in the present configuration in which the bus width can be specified, for example, a circuit unit that performs conversion processing between serial data having a bit width m and parallel data having n bits is provided.

  In this example, the bit width designation terminal “BTWDTH” and the bit width designation register 204i that can be written from the host side are provided as external terminals. However, the present invention is not limited to this. For example, the signals at the terminals D0 to Dn−1 It may be configured to have a function of automatically recognizing the bus width by monitoring the above. That is, it recognizes how many bits are used among n terminals in the first switching unit 204a. For this purpose, for example, a circuit configuration having the following recognition function can be given.

  (1) Using a stable signal that does not malfunction due to noise at start-up, for example, a specific signal A having a sufficiently long width (indicating an address bit width), a bus width designation based on the signal on the device side Ability to receive commands.

  (2) A predetermined state of the signal D (D0 to Dn-1), for example, its inactive state (High level or Low level) is determined, and the negative logic chip select (CS) signal is at the Low level. A function of recognizing that the signal is valid when the signal D changes from the inactive state even once.

  In short, any method may be used as long as it can recognize how many bits are valid or how many bits are invalid among the maximum n bits transmitted from the host side to the target device side. In the case of “n = m”, it is an identity conversion and does not correspond to a substantial process. Therefore, this may be excluded, but such a conversion mode is temporarily used in a situation where high-speed processing is required. It is also useful to leave room for them to appear.

  As described above, according to the portable electronic device 1 according to the present invention, the number of wirings is smaller than that of the conventional parallel bus connection method (in the first embodiment, only five lines are required), and on the substrate necessary for wiring. Can be reduced. Further, it is not necessary to provide a parallel / serial conversion controller as in the conventional synchronous serial bus connection method for the host-side asynchronous parallel bus controller, which is advantageous for cost reduction and size reduction.

  In addition, the host side device can use an existing parallel bus controller, and conversion between parallel data and serial data can be entrusted to software processing. There is no complication of the configuration.

  As the target device, a sound source IC, an optical wireless data communication circuit using infrared rays, and the like are illustrated, but a power supply control IC in the power supply unit 46 may be used as the target device. In this case, the interface circuit of the serial / parallel conversion part is incorporated on a power supply control IC included in the power supply unit 46. By preparing such a power supply control IC for general use, no matter what the device-side interface to the CPU is, when developing multiple models with a common power supply unit designed, Can be connected only via the power supply control IC, and can be implemented simply by adjusting each other's control on the software, and the power supply control IC and the CPU, and between the power supply control IC and each device, of course, for power supply. Since power connection is required, they tend to be placed close to each other. For this reason, providing such a mediation interface in the power supply control IC of the power supply unit means that even if the power supply control IC mediates, the devices that are originally close to each other are close to each other. There is also an advantage that the distance is hardly increased. In addition, even when a PLL circuit is used, since the PLL circuit provided in the power supply unit is used, the wiring can be concentrated, which does not hinder high-density mounting.

  And by expanding the function by adjusting the bus bandwidth based on the bus width adjustment described in the second embodiment, the versatility is enhanced, and the constraints due to the area of the wiring and the board can be flexibly dealt with. Become. Further, by adjusting the bus width, for example, it is possible to respond to a request for instantaneously increasing or decreasing the data transfer rate (in IrDA module or the like, the processing speed can be reduced when the apparatus is started or terminated).

  In the above description, the mobile phone device which is an example of the mobile electronic device has been described. However, the present invention is not limited to this, and for example, a personal handy phone system (PHS), a personal digital assistant (PDA), and a portable device. The present invention can be widely applied to navigation devices, notebook computers, and the like.

It is a perspective view which shows the example of an external appearance of the portable electronic device which concerns on this invention. It is the block diagram which illustrated the circuit function of the portable electronic equipment concerning the present invention. 1 is a circuit block diagram showing a main part of a configuration example according to a first embodiment of the present invention. It is a circuit block diagram which shows the principal part about the structural example of the serial interface part by the side of the device which concerns on this invention. It is a timing chart for demonstrating an example of the signal sequence which concerns on this invention. It is a circuit block diagram which shows the principal part of the structural example which concerns on the 2nd Embodiment of this invention. It is a circuit block diagram for demonstrating the conventional parallel bus connection. It is a figure which shows schematically the principal part of the circuit structure in a bus interface part. It is a circuit block diagram for demonstrating synchronous serial bus connection. It is a circuit block diagram for demonstrating another example of a synchronous serial bus connection.

Explanation of symbols

1 Portable Electronic Device 45 Central Processing Unit 100 Parallel Interface Unit (Parallel Bus Controller)
203 serial interface unit 204j bit width conversion unit

Claims (2)

A central processing unit that has a parallel interface unit and performs conversion processing between parallel data and serial data therein, and a portable electronic device including a device having a serial interface unit,
The central processing unit outputs data converted from parallel data to serial data via a data bus from the parallel interface unit to the serial interface unit, and selects the address data and data corresponding to the address data in the serial interface unit The signal is output from the parallel interface unit to the serial interface unit via the address bus, and the address data and the data corresponding to the address data are sequentially transmitted to the device bit by bit from the most significant bit or the least significant bit in order. A portable electronic device characterized by that.   When data of 2 bits or more is transmitted from the parallel interface unit to the serial interface unit via the data bus, the data received by the device on the data bus is converted into data having a predetermined bit width. The portable electronic device according to claim 1, further comprising a bit width conversion unit for conversion.

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