CN117519807A

CN117519807A - Motor driving method and system and electronic equipment

Info

Publication number: CN117519807A
Application number: CN202311630682.XA
Authority: CN
Inventors: 杨东升
Original assignee: Shanghai Awinic Technology Co Ltd
Current assignee: Shanghai Awinic Technology Co Ltd
Priority date: 2023-11-30
Filing date: 2023-11-30
Publication date: 2024-02-06

Abstract

The application relates to the technical field of electronics, and discloses a motor driving method, a motor driving system and electronic equipment, which can drive double motors to vibrate by adopting one path of IIC bus, and can achieve a double-motor vibration effect while saving IIC resources of a main control module. The method comprises the following steps: determining that a first driving message to be sent corresponds to a first motor, and switching the slave address of the target IIC to the slave address of a first motor driving chip in the plurality of motor driving chips; and sending a first driving message to the first motor driving chip through the target IIC, wherein the first motor is connected with the first motor driving chip, and the first driving message is related to the action of the first motor. The method is particularly applicable to a scenario of dual motor vibration or multiple motor vibration.

Description

Motor driving method and system and electronic equipment

Technical Field

The present disclosure relates to the field of electronic technologies, and in particular, to a motor driving method, a system, and an electronic device.

Background

With the wide application of motors in electronic devices such as mobile phones, handles, tablet computers and smart watches, users demand that the electronic devices provide stronger and more stereoscopic vibration effects, so as to realize the effects of enemy step azimuth prompt, stereo music along with sound vibration and the like in games. Typically one motor requires one drive chip to drive, and then two drive chips are required to drive each. When the resources of the integrated circuit buses (inter integrated circuit, IIC) of the main control module in the electronic equipment are rich, two driving chips can be respectively mounted on the two IIC buses for respectively controlling, but often, because more IIC peripherals are arranged on one equipment or some peripherals monopolize one IIC bus, only one IIC remains on the platform for mounting the motor. Then, when the IIC bus resources are intense, two driving chips cannot be mounted at the same time to drive the dual motor to work.

Disclosure of Invention

The embodiment of the application provides a motor driving method, a motor driving system and electronic equipment, which can drive double motors to vibrate by adopting one path of IIC bus, and can realize the vibration sensing effect of the double motors while saving the IIC resources of a main control module.

In a first aspect, embodiments of the present application provide a motor driving method, including:

determining that a first driving message to be sent corresponds to a first motor, and switching the slave address of the target IIC to the slave address of a first motor driving chip in the plurality of motor driving chips;

and sending a first driving message to the first motor driving chip through the target IIC, wherein the first motor is connected with the first motor driving chip, and the first driving message is related to the action of the first motor.

It can be understood that, in the present application, one IIC bus in the main control module of the target IIC electronic device, the target IIC may be connected to a plurality of motor driving chips, so as to control a plurality of motors to vibrate through the one IIC bus. Wherein the first motor may be any one of a plurality of motors to be driven. In the application, different slave addresses are different in different motor driving chips in the plurality of motor driving chips, so that the slave addresses of the target IIC can be switched to communicate with the motor driving chips needing to send data, and a plurality of motors can be driven to vibrate through one IIC bus, such as driving double motors to vibrate. Therefore, one path of IIC bus is adopted to drive the double motors to vibrate, IIC resources of the main control module are saved, and meanwhile, the vibration effect of the double motors is achieved.

In one possible implementation manner of the first aspect, the first driving message is first vibration parameter information or a first instruction, where the first vibration parameter information is used to instruct the first motor driving chip to generate a first driving waveform signal for driving the first motor to vibrate, and the first instruction is used to trigger the first motor driving chip to output the first driving waveform signal to the first motor.

It can be understood that the present application may send the first vibration parameter or the first command to any one of the required first motor driving chips through an IIC bus to drive the corresponding first motor to vibrate.

In a possible implementation manner of the first aspect, the method further includes:

when the first driving message is the first vibration parameter information, determining that a second vibration parameter to be sent corresponds to a second motor, and switching the slave address of the target IIC to the slave address of a second motor driving chip in the plurality of motor driving chips;

transmitting second vibration parameter information to a second motor driving chip through a target IIC, wherein the second motor is connected with the second motor driving chip, and the second vibration parameter information is used for indicating the second motor driving chip to generate a second driving waveform signal for driving the second motor to vibrate;

Determining that a second instruction to be sent corresponds to a second motor, and sending a second instruction to a second motor driving chip through a target IIC, wherein the second instruction is used for triggering the second motor driving chip to output a second driving waveform signal to the second motor;

determining that a first instruction to be sent corresponds to a first motor, and switching the slave address of the target IIC to the slave address of the first motor driving chip;

and sending a first instruction to the first motor driving chip through the target IIC.

It can be understood that the configuration of the first motor driving chip and the second motor driving chip 2 can be completed in the present application, and then the second motor driving chip and the first motor driving chip are triggered to output driving waveform signals respectively, so as to reduce the vibration starting interval of the two motors as much as possible.

In a possible implementation manner of the first aspect, each of the plurality of motor driving chips has an IIC chip select pin, and input parameters of the IIC chip select pins of different motor driving chips are different, and the different input parameters correspond to different slave addresses. For example, the IIC chip select pin may be an AD pin (a type of chip pin) hereinafter.

In a possible implementation manner of the first aspect, the input parameter of the IIC chip select pin of the first motor driving chip is at a high level, and the input parameter of the IIC chip select pin of the second motor driving chip is at a low level. For example, hereinafter the AD pin 3211 of the motor drive chip 321 is pulled high, and the AD pin 3210 of the motor drive chip 322 is grounded.

In a possible implementation manner of the first aspect, the first vibration parameter information is used to instruct the first driving chip to configure the internal register to generate the first driving waveform signal; the second vibration parameter information is used for indicating the second driving chip to configure the internal register to generate a second driving waveform signal. I.e. the vibration parameter information may be provided in the respective motor driving chips so that the motor driving chips may transmit driving signals to the corresponding motors in real time.

In a possible implementation manner of the first aspect, the first vibration parameter information and the second vibration parameter information include at least the following information: waveform identification number (identity document, ID), gain value, frequency, intensity. Therefore, the vibration parameter information can be adjusted through the rhythm point so as to realize the effect of ringing along with vibration.

In a second aspect, embodiments of the present application provide a motor drive system, the system comprising: the system comprises a main control module, a plurality of motor driving chips connected with the main control module through a target integrated circuit IIC, and a plurality of motors connected with the motor driving chips one by one;

the main control module is used for determining that a first driving message to be sent corresponds to the first motor, and switching the slave address of the target IIC into the slave address of a first motor driving chip in the plurality of motor driving chips;

The main control module is used for sending a first driving message to the first motor driving chip through the target IIC, wherein the first motor is connected with the first motor driving chip, and the first driving message is related to the action of the first motor.

In one possible implementation manner of the second aspect, the first driving message is first vibration parameter information or a first instruction, where the first vibration parameter information is used to instruct the first motor driving chip to generate a first driving waveform signal for driving the first motor to vibrate, and the first instruction is used to trigger the first motor driving chip to output the first driving waveform signal to the first motor.

In one possible implementation manner of the second aspect, when the first driving message is the first vibration parameter information, the main control module is further configured to determine that the second vibration parameter information to be sent corresponds to the second motor, and switch the slave address of the target IIC to the slave address of the second motor driving chip in the plurality of motor driving chips;

the main control module is further used for sending second vibration parameter information to the second motor driving chip through the target IIC, wherein the second motor is connected with the second motor driving chip, and the second vibration parameter information is used for indicating the second motor driving chip to generate a second driving waveform signal for driving the second motor to vibrate;

The main control module is also used for determining that a second instruction to be sent corresponds to a second motor, sending the second instruction to the second motor driving chip through the target IIC, and the second instruction is used for triggering the second motor driving chip to output a second driving waveform signal to the second motor;

the main control module is also used for determining that a first instruction to be sent corresponds to the first motor and switching the slave address of the target IIC into the slave address of the first motor driving chip;

the main control module is also used for sending a first instruction to the first motor driving chip through the target IIC.

In a possible implementation manner of the second aspect, the plurality of motor driving chips each have an IIC chip select pin, and input parameters of the IIC chip select pins of different motor driving chips are different, and the different input parameters correspond to different slave addresses.

In one possible implementation manner of the second aspect, the input parameter of the IIC chip select pin of the first motor driving chip is at a high level, and the input parameter of the IIC chip select pin of the second motor driving chip is at a low level.

In a possible implementation manner of the second aspect, the first driving chip is configured to configure the internal register according to the first vibration parameter information to generate a first driving waveform signal, and output the first driving waveform signal to the first motor based on the received first instruction;

A first motor for generating vibration according to a first driving waveform signal;

the second driving chip is used for configuring an internal register according to the second vibration parameter information to generate a second driving waveform signal and outputting the second driving waveform signal to a second motor based on a received second instruction;

and a second motor for generating vibration according to the second driving waveform signal.

In a possible implementation manner of the second aspect, at least the first vibration parameter information and the second vibration parameter information include the following information: waveform identification number, gain value, frequency and intensity.

In a third aspect, an embodiment of the present application provides an electronic device, including: a motor drive system as in the second aspect and any one of its possible implementations. For example, the above-mentioned main control module may be implemented by a processor in an electronic device, and in addition, the electronic device may further include other devices or modules such as a memory.

Drawings

FIG. 1 is a system schematic diagram of a single motor vibration scheme provided by the related art;

FIG. 2 is a system schematic diagram of a dual motor vibration scheme provided in the related art;

FIG. 3 is a schematic diagram of a system frame of a dual motor vibration scheme provided in an embodiment of the present application;

Fig. 4 is a schematic structural diagram of a motor driving system according to an embodiment of the present disclosure;

fig. 5 is a schematic flow chart of a motor driving method according to an embodiment of the present application;

fig. 6 is a schematic flow chart of a motor driving method according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a mobile phone according to an embodiment of the present application;

fig. 8 is a block diagram of a system provided in an embodiment of the present application.

Detailed Description

Illustrative embodiments of the present application include, but are not limited to, motor drive methods, systems, and electronic devices.

In order to more clearly understand the schemes in the embodiments of the present application, some terms related to the embodiments of the present application will be explained first.

The integrated circuit bus (inter integrated circuit, IIC), also known as the I2C bus, is a simple, bi-directional two-wire synchronous serial bus. The IIC bus requires only two lines, namely a Data signal line (Serial Data, SDA) and a Serial clock line (Serial Clock Line, SCL) of the I2C bus to transfer information between devices connected to the bus.

The driving chip is located between the main circuit and the control circuit, and is used for amplifying the signal of the control circuit (namely, amplifying the signal of the control circuit to enable the driving of the power transistor). The driver chip amplifies the pulse width modulated (pulse width modulation, PWM) pulses output by the control circuit sufficiently to drive the power transistor-switching power amplification. The driving chip can be mainly divided into: motor/motor driving chip, display driving chip, lighting driving chip, voice coil motor driving chip, audio power amplifier chip, etc. The motor driving chip is mainly used for driving the motor to vibrate.

The motor driving method provided by the embodiment of the application can be applied to a motor driving system, and the motor driving system can be deployed in electronic equipment. Specifically, the motor driving system mainly comprises a main control module, a plurality of motor driving chips and a plurality of motors.

The main control module is connected with the motor driving chip through the IIC bus to control motor vibration, and one motor driving chip is only used for driving one motor.

As examples, electronic devices suitable for use in the present application include, but are not limited to: electronic devices such as mobile phones, handles, tablet computers, smart watches, and the like. In some embodiments, the electronic device of the present application has a processor for implementing the functions of the main control module, a motor, and a motor drive chip.

In one related art, an electronic device drives a motor to vibrate using a single motor vibration scheme. Referring to fig. 1, a system diagram of a single motor vibration scheme provided by the related art is shown. In the motor vibration system 10 shown in fig. 1, a main control module 11 is connected to a motor driving chip 13 through an IIC bus 12, and then is connected to and drives a motor 14 to vibrate through the motor driving chip 13. However, the single motor vibration scheme has a problem in that the vibration feeling is not strong enough and is not three-dimensional enough.

In another related art, the electronic device drives the motor to vibrate using a two-motor vibration scheme of a two-way IIC bus. Referring to fig. 2, a system diagram of a dual motor vibration scheme provided in the related art is shown. In fig. 2, a main control module 21 in the motor vibration system 20 is respectively connected to a motor driving chip 24 and a motor driving chip 25 through an IIC1 bus 22 and an IIC2 bus 23, and is respectively connected to and drives a motor 26 and a motor 27 to vibrate through the motor driving chip 24 and the motor driving chip 25. However, in this scheme, the dual motors are mounted on two IIC buses, and occupy IIC resources of the main control module. In addition, when IIC resources of the main control module are tense, the main control module cannot drive the double motors.

In order to solve the above-mentioned problems, the embodiment of the present application provides a motor driving method, in which IIC chip selection pins are set in a motor driving chip, and different input parameters are set for IIC chip selection pins of different motor driving chips, so that different motor driving chips have different IIC slave addresses based on corresponding input parameters, so as to implement driving of dual-motor vibration by adopting a dual-motor vibration scheme of one path IIC bus. Specifically, a main control module in the electronic equipment is switched to the slave addresses of different motor driving chips through one IIC bus to send vibration parameters of two motors to the two motor driving chips respectively, so that the two motors are driven to vibrate to generate a vibration effect, IIC resources of the main control module are saved, and meanwhile, the vibration effect of the two motors is realized.

Next, a method for driving the dual motors of the one IIC bus provided in the embodiment of the present application will be described in detail.

Referring to fig. 3, a schematic diagram of a system frame of a dual motor vibration scheme according to an embodiment of the present application is shown. The motor vibration system 30 in fig. 3 mainly includes: a main control module 31, a motor driving module 32 and a motor module 33.

The motor driving module 32 includes a motor driving chip 321 and a motor driving chip 322, and the motor module includes a motor 331 and a motor 332. The main control module 31 is connected to the motor driving chip 321 and the motor driving chip 322 through an IIC bus 34, and the motor driving chip 321 and the motor driving chip 322 are respectively used for driving the motor 331 and the motor 332 to vibrate.

Specifically, the main control module 31 respectively sends two vibration parameter information to the motor driving module 32 through one IIC bus. When the motor driving chip 32 receives the vibration parameter information, it generates a driving waveform and outputs the driving waveform to the motor module 33 to vibrate.

In some embodiments of the present application, the motor driver chip has a slave address configuration function, and the IIC address is configured using IIC address chip select pins. As an example, in the present application, the AD pin is used as the IIC address chip select pin of the motor driving chip, and pulling it high can change the default IIC address of the chip; for example, default address 0x5A, goes high and then becomes 0x5B. Then, when driving both motor driver chips, the motor driver chip in communication with the IIC bus will be selected by setting the motor driver chip to a default address or a pulled up address.

In some embodiments of the present application, when two motor driving chips in the motor driving system 30 are mounted on the same IIC bus 34 of the main control module 31, the motors will be connected to the output pins of the corresponding motor driving chips. Further, the IIC address chip select pin (i.e., the AD pin, which is a type of chip pin) of one motor driving chip is pulled up to change the IIC address, for example, the IIC address of the motor driving chip 321 is changed to 0x5B after the AD pin of the motor driving chip 321 is pulled up, and the default IIC address of 0x5A is maintained when the AD pin of the motor driving chip 32 is not pulled up.

Referring to fig. 4, a schematic structural diagram of a motor driving system according to an embodiment of the present application is shown in connection with the motor driving system shown in fig. 3.

As shown in fig. 4, the motor driving system 40 includes a main control module 31, a motor driving chip 321 and a motor 331 connected to each other, and a motor driving chip 322 and a motor 332 connected to each other. The main control module 31 controls the two motor driving chips through one IIC bus 34.

The master module 31 in fig. 4 has an SDA pin 311 and an SCL pin 312, and a VCC pin 313 and a GND pin 314. It will be appreciated that the communication line to which the two pins SDA pin 311 and SCL pin 312 are connected is an IIC bus, i.e., IIC bus 34.

The motor driving chip 321 in fig. 4 has an AD pin 3211, and pulling the AD pin 3211 high causes the IIC address of the motor driving chip 321 to become 0x5B. The SDA pin 3211 and SCL pin 3212 in the motor drive chip 321 are connected to the SDA pin 311 and SCL pin 312, respectively, via the IIC bus 34. An output pin (out 1) 3214 and an output pin (out 2) 3215 in the motor driving chip 321 are used to connect the motor 331. In addition, a VCC pin 3216 for connection to a power supply voltage and a GND pin 3217 for connection to ground (e.g., digital Ground (DGND) or Analog Ground (AGND)) are also included in the motor driving chip 321.

The motor driver chip 322 in fig. 4 has an AD pin 3221, and the AD pin 3221 is grounded such that the IIC address of the motor driver chip 322 is default 0x5A. The SDA pin 3221 and the SCL pin 3222 in the motor drive chip 322 are connected to the SDA pin 311 and the SCL pin 312, respectively, through the IIC bus 34. An output pin (out 1) 3224 and an output pin (out 2) 3225 in the motor drive chip 322 are used to connect to the motor 332. In addition, VCC pin 3226 is included in motor driver chip 322 for connection to a supply voltage, and GND pin 3227 is used for grounding (e.g., digital or analog ground).

In some embodiments, pulling AD pin 3211 high may be connecting AD pin 3211 high, i.e., the input parameter of AD pin 3211 is high. While AD pin 3221 is grounded, it may be that AD pin 3221 is connected to a low level, i.e., the input parameter of AD pin 3221 is low.

It will be appreciated that a high level, used to represent a state of high voltage, may be marked as 1 in a binary system in a digital logic circuit. In some examples, the high level may be generally specified to be any value between 3.5V and 5V, or may be set to other values, without limitation.

A low level, which is used to represent a state where the voltage is low, may be marked as 0 in binary in the digital logic circuit. In some examples, the low level may be generally specified to be any value between 0 and 0.25V, or may be set to other values, without limitation.

In other embodiments, AD pin 3211 is connected to a first input parameter, e.g., a value between 3.5V and 5V. AD pin 3221 may be pulled low to connect AD pin 3211 to a second input parameter, such as a value between 2.5V and 3.5V.

In some embodiments, the main control module 31 is configured to determine vibration parameter information of the motor driving chip 321 and the motor driving chip 322; and switching the IIC slave address connected to the IIC bus 334 to the slave address of the motor driving chip 321 and the slave address of the motor driving chip 322; and issuing vibration parameters to the corresponding motor driving chips.

In addition, in other embodiments, the chip selection pins of the motor driving chip provided in the present application may be other pins, or the chip selection pins may include a plurality of pins, which are not specifically described in the embodiments of the present application.

Accordingly, the motor driving chip 321 and the motor driving chip 322 can generate driving waveform signals and output the driving waveform signals to the motor 331 and the motor 332 according to the received corresponding vibration parameter information through the IIC bus 34. In some embodiments, the motor driving chip 321 and the motor driving chip 322 may configure the internal registers to generate and store the corresponding driving waveform signals according to the received corresponding vibration parameter information until receiving the go command from the main control module 31, and then output the driving waveform signals to the motor 331 and the motor 332.

Further, the motor 331 and the motor 332 drive internal vibrations according to the corresponding driving waveform signals to generate vibration feeling.

In some embodiments, the vibration parameter information provided by embodiments of the present application includes, but is not limited to, a waveform identification number (identity document, ID), a gain value, a frequency, an intensity, and the like. For example, the waveform ID may indicate a sine wave, a cosine wave, a saw tooth wave, or the like. The gain value is used to adjust the amplitude of the waveform.

Next, referring to fig. 5, a motor driving method according to an embodiment of the present application is shown in conjunction with the motor driving system 40 shown in fig. 4, and the main execution body of the method is mainly the main control module 31 in the motor driving system 40.

As shown in fig. 5, the method comprises the steps of:

s501: the main control module 31 determines vibration parameter information 1 issued to the motor 331 and determines vibration parameter information 2 issued to the motor 332.

For example, the vibration parameter information 1 and the vibration parameter information 2 may include parameters of waveform ID, gain value, frequency, intensity.

In some embodiments, vibration parameter information 1 and vibration parameter information 2 are different, for example, vibration parameter information 1 drives motor 331 to have a stronger vibration sensation and vibration parameter information 2 drives motor 332 to have a weaker vibration sensation, so as to achieve the effect of prompting the enemy step azimuth in the game in which the electronic device is running.

In other embodiments, the vibration parameter information 1 and the vibration parameter information 2 may be the same, for example, to achieve a stereo vibration effect when the electronic device plays music.

S502: the master control module 31 switches the IIC slave address to be accessed to the IIC slave address of the motor driving chip 321.

For example, the IIC slave address of the motor driver chip 321 is address 0x5B after the AD pin 3311 is pulled high.

S503: the main control module 31 issues the vibration parameter information 1 to the motor driving chip 321 through the IIC bus 34, and triggers the register configuration of the motor driving chip 321 to generate the driving waveform signal 1.

It is understood that the motor driving chip 321 may generate the driving waveform signal 1 according to the vibration parameter information 1 and save the driving waveform signal 1 into a register to complete the register configuration.

As an example, the main control module 31 may issue the vibration parameter information 1 to the motor driving chip 321 through the SDA line in the IIC bus 34.

S504: the master control module 31 switches the IIC slave address to be accessed to the IIC slave address of the motor driving chip 322.

For example, the IIC slave address of motor driver chip 322 is address 0x5A for AD pin default.

As an example, the main control module 31 may issue a go command to the motor driving chip 321 through the SDA line in the IIC bus 34.

S505: the main control module 31 issues the vibration parameter information 2 to the motor driving chip 322 through the IIC bus 34, and triggers the register configuration of the motor driving chip 322 to generate the driving waveform signal 2.

S506: the main control module 31 sends go command to the motor driving chip 322 through the IIC bus 34, and triggers the motor driving chip 322 to start outputting the driving waveform signal 2 to the motor 332.

In some embodiments, the motor driver chip 322 has a go register inside, which can be understood as a trigger vibration register, where the master control module 31 configures the register through the IIC bus 34, for example, to write 1, and triggers the motor driver chip 322 to start playing the waveform signal to trigger the motor 332 to start vibrating.

S507: the master control module 331 switches to the IIC slave address of the motor driving chip 322.

S508: the main control module 331 sends go command to the motor driving chip 321 through the IIC bus 34, and triggers the motor driving chip 321 to start outputting the driving waveform signal 1 to the motor 331.

It can be understood that the main control module 31 completes the configuration of the motor driving chip 321 and the motor driving chip 322, and then triggers the motor driving chip 321 and the motor driving chip 322 to output driving waveform signals respectively, so as to reduce the vibration starting interval of the two motors as much as possible.

In the embodiment of the application, the main control module can switch the motor driving chip to be accessed through one path of IIC bus through IIC address chip selection, and realizes driving double motors to vibrate through one path of IIC bus. Therefore, the motor vibration effect with strong vibration sense and good three-dimensional effect can be realized while IIC bus resources are saved.

Further, on the basis of the motor driving method shown in fig. 5, in combination with fig. 6, a motor driving method according to an embodiment of the present application is provided. The method shown in fig. 6 differs from fig. 5 only in that it is composed of the main control module 31, the motor driving chips 321 and 322, and the motors 31 and 332 in the motor driving system 40.

As shown in fig. 6, the method includes the steps of:

s601: the main control module 31 determines vibration parameter information 1 issued to the motor 331 and determines vibration parameter information 2 issued to the motor 332.

S602: the master control module 31 switches the IIC slave address to be accessed to the IIC slave address of the motor driving chip 321.

S603: the main control module 31 issues the vibration parameter information 1 to the motor driving chip 321 through the IIC bus 34.

The descriptions of S601-S603 are the same as S501-S503 in the embodiment shown in fig. 5, and will not be repeated here.

S604: the motor driving chip 321 performs register configuration according to the received vibration parameter information 1 to generate a driving waveform signal 1.

Wherein, the description of S604 is related to the description of S503 in the embodiment shown in fig. 5, and will not be described in detail here.

S605: the master control module 31 switches the IIC slave address to be accessed to the IIC slave address of the motor driving chip 322.

S606: the main control module 31 transmits the vibration parameter information 2 to the motor driving chip 322 through the IIC bus 34.

S607: the motor driving chip 322 performs register configuration according to the received vibration parameter information 2 to generate a driving waveform signal 2.

Wherein the descriptions of S605-S607 are related to the descriptions of S504-S505 in the embodiment shown in fig. 5, and are not described in detail herein.

S608: the main control module 31 sends go commands to the motor driving chip 322 through the IIC bus 34.

S609: the motor driving chip 322 outputs a driving waveform signal 2 to the motor 332.

S610: the motor 332 drives the internal structure to oscillate based on the received driving waveform signal 2 to generate vibration.

Wherein the descriptions of S608-S610 are related to the descriptions of S506 in the embodiment shown in fig. 5, and will not be described in detail herein.

S611: the master control module 331 switches to the IIC slave address of the motor driving chip 322.

S612: the main control module 331 sends go commands to the motor driving chip 321 through the IIC bus 34.

S613: the motor driving chip 321 outputs a driving waveform signal 1 to the motor 331.

S614: the motor 331 drives the internal structure to oscillate based on the received driving waveform signal 1 to generate vibration.

Wherein the descriptions of S611-S614 are related to the descriptions of S507-S508 in the embodiment shown in fig. 5, and are not described in detail herein.

Thus, each unit in the motor driving system 40 can interactively complete the scheme of driving the dual motors to vibrate by one IIC bus, thereby saving IIC bus resources.

In some embodiments, the motor control method provided in the embodiments of the present application is not limited to a dual-motor driving scenario, but may be applied to a multi-motor driving scenario, for example, a motor driving system includes M motor driving chips and M motors correspondingly connected. At this time, the motor driving chips may have one or more IIC address chip select pins, and different motor driving chips are controlled to have different IIC slave addresses by adjusting input signals of the IIC address chip select pins. And the main control module can switch the IIC slave addresses through N IIC buses and send out predetermined vibration parameter information to each motor driving chip so as to trigger the motor driving chips to complete register configuration. And then, the main control module switches the IIC slave addresses through fewer IIC buses, and issues go commands to each motor driving chip to trigger the motor driving chips to output driving waveform signals to the corresponding motors. Wherein N is less than M, and M and N are both positive integers.

According to an embodiment of the present application, an electronic device is provided. The electronic device may be a cell phone, tablet, wearable device, etc. with dual motors and two motor drive chips. A mobile phone will be described below as an example of an electronic device.

Fig. 7 is a schematic structural diagram of a mobile phone according to an embodiment of the present application. The motor drive system 40 shown in fig. 4 may then be implemented by the cell phone 100 shown in fig. 7.

Specifically, as shown in fig. 7, the mobile phone 100 may include a processor 110, a power module 140, a memory 180, a mobile communication module 130, a wireless communication module 120, a sensor module 190, an audio module 150, a camera 170, an interface module 160, keys 101, a display 102, motor driving chips 1 to M103, motors 1 to M104, and the like.

It should be understood that the structure illustrated in the embodiments of the present invention is not limited to the specific embodiment of the mobile phone 100. In other embodiments of the present application, the handset 100 may include more or fewer components than shown, or certain components may be combined, or certain components may be split, or different arrangements of components may be provided. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

The processor 110 may include one or more processing units, for example, processing modules or processing circuits that may include a central processing unit (central processing unit, CPU), an image processor (graphics processing unit, GPU), a digital signal processor DSP, a microprocessor (micro-programmed control unit, MCU), an artificial intelligence (artificial intelligence, AI) processor, a programmable logic device (Field Programmable Gate Array, FPGA), or the like. Wherein the different processing units may be separate devices or may be integrated in one or more processors. For example, the master control module 31 shown in fig. 4 may be implemented by the processor 110, such as by a DSP or other processing unit in the processor 110.

The controller can generate operation control signals according to the instruction operation codes and the time sequence signals to finish the control of instruction fetching and instruction execution.

A memory may also be provided in the processor 110 for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may hold instructions or data that the processor 110 has just used or recycled. If the processor 110 needs to reuse the instruction or data, it can be called directly from the memory. Repeated accesses are avoided and the latency of the processor 110 is reduced, thereby improving the efficiency of the system.

In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an I2C interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART) interface, a mobile industry processor interface (mobile industry processor interface, MIPI), a general-purpose input/output (GPIO) interface, a subscriber identity module (subscriber identity module, SIM) interface, and/or a universal serial bus (universal serial bus, USB) interface, among others.

The I2C interface is a bi-directional synchronous serial bus comprising a serial data line (SDA) and a Serial Clock Line (SCL). In some embodiments, the processor 110 may contain multiple sets of I2C buses. The processor 110 may be coupled to a charger, a flash, a camera 170, one or more motors 104, etc. through different I2C bus interfaces. For example: the processor 110 may be connected to two or more of the motor driving chips 1 to M103 through one I2C interface, so that the processor 110 communicates with the motor driving chips through an I2C bus interface, and the electronic device 100 may implement a function of driving two or more of the motors 1 to M104 through the motor driving chips.

It should be understood that the interfacing relationship between the modules illustrated in the embodiments of the present invention is only illustrative, and is not meant to limit the structure of the electronic device 100. In other embodiments of the present application, the electronic device 100 may also use different interfacing manners, or a combination of multiple interfacing manners in the foregoing embodiments.

The power module 140 may include a power source, a power management component, and the like. The power source may be a battery. The power management component is used for managing the charging of the power supply and the power supply supplying of the power supply to other modules. In some embodiments, the power management component includes a charge management module and a power management module. The charging management module is used for receiving charging input from the charger; the power management module is used for connecting a power supply, and the charging management module is connected with the processor 110. The power management module receives input from the power and/or charge management module and provides power to the processor 110, the display 102, the camera 170, the wireless communication module 120, and the like.

The mobile communication module 130 may include, but is not limited to, an antenna, a power amplifier, a filter, an LNA (Low noise amplify, low noise amplifier), etc. The mobile communication module 130 may provide a solution for wireless communication including 2G/3G/4G/5G, etc. applied to the handset 100. The mobile communication module 130 may receive electromagnetic waves from an antenna, perform processes such as filtering, amplifying, and the like on the received electromagnetic waves, and transmit the processed electromagnetic waves to a modem processor for demodulation. The mobile communication module 130 may amplify the signal modulated by the modem processor, and convert the signal into electromagnetic waves through the antenna to radiate. In some embodiments, at least some of the functional modules of the mobile communication module 130 may be disposed in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 130 may be disposed in the same device as at least some of the modules of the processor 110. The wireless communication technologies may include global system for mobile communications (global system for mobile communications, GSM), general packet radio service (general packet radio service, GPRS), code division multiple access (code divisionmultiple access, CDMA), wideband code division multiple access (wideband code division multiple access, WCDMA), time division code division multiple access (time-division code division multiple access, TD-SCDMA), long term evolution (long term evolution, LTE), bluetooth (BT), global navigation satellite system (global navigation satellite system, GNSS), wireless local area network (wireless local area networks, WLAN), near field wireless communication technology (near field communication, NFC), frequency modulation (frequency modulation, FM) and/or field communication, NFC), infrared (IR) technology, and the like. The GNSS may include a global satellite positioning system (global positioning system, GPS), a global navigation satellite system (globalnavigation satellite system, GLONASS), a beidou satellite navigation system (beidou navigationsatellite system, BDS), a quasi zenith satellite system (quasi-zenith satellite system, QZSS) and/or a satellite based augmentation system (satellite based augmentation systems, SBAS).

The wireless communication module 120 may include an antenna, and transmit and receive electromagnetic waves via the antenna. The wireless communication module 120 may provide solutions for wireless communication including wireless local area network (wireless localarea networks, WLAN) (e.g., wireless fidelity (wireless fidelity, wi-Fi) network), bluetooth (BT), global navigation satellite system (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), near field wireless communication technology (near field communication, NFC), infrared technology (IR), etc. applied to the handset 100. The handset 100 may communicate with a network and other devices via wireless communication technology.

In some embodiments, the mobile communication module 130 and the wireless communication module 120 of the handset 100 may also be located in the same module.

The display screen 102 is used for displaying human-computer interaction interfaces, images, videos, and the like. The display screen 102 includes a display panel. The display panel may employ a liquid crystal display (liquid crystal display, LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED) or an active-matrix organic light-emitting diode (matrix organic light emitting diode), a flexible light-emitting diode (flex), a mini, a Micro led, a Micro-OLED, a quantum dot light-emitting diode (quantum dot light emitting diodes, QLED), or the like.

The sensor module 190 may include a proximity light sensor, a pressure sensor, a gyroscope sensor, a barometric sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, and the like.

The audio module 150 is used to convert digital audio information into an analog audio signal output, or to convert an analog audio input into a digital audio signal. The audio module 150 may also be used to encode and decode audio signals. In some embodiments, the audio module 150 may be disposed in the processor 110, or some functional modules of the audio module 150 may be disposed in the processor 110. In some embodiments, the audio module 150 may include a speaker, an earpiece, a microphone, and an earphone interface.

The camera 170 is used to capture still images or video. The object generates an optical image through the lens and projects the optical image onto the photosensitive element. The photosensitive element converts the optical signal into an electrical signal, which is then passed to image signal processing (image signal processing, ISP) for conversion into a digital image signal. The cell phone 100 may implement a photographing function through an ISP, a camera 170, a video codec, a graphic processor (graphic processing unit, GPU), a display screen 102, an application processor, and the like.

The interface module 160 includes an external memory interface, a universal serial bus (universal serial bus, USB) interface, a subscriber identity module (subscriber identification module, SIM) card interface, and the like. Wherein the external memory interface may be used to connect an external memory card, such as a Micro SD card, to extend the memory capabilities of the handset 100. The external memory card communicates with the processor 110 through an external memory interface to implement data storage functions. The universal serial bus interface is used for communication between the handset 100 and other electronic devices. The subscriber identity module card interface is used to communicate with a SIM card mounted to the handset 10010, for example, by reading a telephone number stored in the SIM card or by writing a telephone number to the SIM card.

The motor driving chips 1 to M103 are used for driving the motors 1 to M104 to vibrate. In some embodiments, the electronic device 100 may include 1 or M motor drive chips 103, M being a positive integer greater than 1. For example, the motor is used to generate a vibration effect on the mobile phone 100, such as when the mobile phone 100 of the user is called, so as to prompt the user to answer an incoming call of the mobile phone 100.

In some embodiments, the handset 100 also includes keys 101, indicators, and the like. The key 101 may include a volume key, an on/off key, and the like. The indicators may include laser indicators, radio frequency indicators, LED indicators, and the like. In addition, it is understood that in other embodiments, the electronic device 100 may further include other driving chips, such as a display driving chip, an illumination driving chip, a voice coil motor driving chip, an audio power amplifier chip, and the like, to drive the corresponding peripheral devices to operate.

Referring now to fig. 8, shown is a block diagram of a system 1400 in accordance with one embodiment of the present application. Fig. 8 schematically illustrates an example system 1400 in accordance with various embodiments. In one embodiment, the system 1400 may include one or more processors 1404, system control logic 1408 coupled to at least one of the processors 1404, a system memory 1412 coupled to the system control logic 1408, a non-volatile memory (NVM) 1416 coupled to the system control logic 1408, and a network interface 1420 coupled to the system control logic 1408.

In some embodiments, the processor 1404 may include one or more single-core or multi-core processors. In some embodiments, the processor 1404 may include any combination of general-purpose processors and special-purpose processors (e.g., graphics processors, application processors, baseband processors, etc.). In embodiments where the system 1400 employs an enhanced Node B (eNB) 101 or a radio access network (Radio Access Network, RAN) controller 102, the processor 1404 may be configured to perform various conforming embodiments, such as the embodiments shown in fig. 5 or 6.

In some embodiments, the system control logic 1408 may include any suitable interface controller to provide any suitable interface to at least one of the processors 1404 and/or any suitable device or component in communication with the system control logic 1408.

In some embodiments, the system control logic 1408 may include one or more memory controllers to provide an interface to the system memory 1412. The system memory 1412 may be used for loading and storing data and/or instructions. The memory 1412 of the system 1400 may include any suitable volatile memory in some embodiments, such as suitable dynamic random access memory (dynamic random access memory, DRAM).

NVM/memory 1416 may include one or more tangible, non-transitory computer-readable media for storing data and/or instructions. In some embodiments, NVM/memory 1416 may include any suitable nonvolatile memory, such as flash memory, and/or any suitable nonvolatile storage device, such as at least one of a Hard Disk Drive (HDD), compact disc drive (CD) drive, digital versatile disc (digital versatiledisc, DVD) drive.

The NVM/memory 1416 may include a portion of the storage resources on the device mounting the system 1400 or it may be accessed by, but not necessarily part of, the apparatus. For example, NVM/storage 1416 may be accessed over a network via network interface 1420.

In particular, the system memory 1412 and NVM/storage 1416 may include: a temporary copy and a permanent copy of instructions 1424. The instructions 1424 may include: instructions that, when executed by at least one of the processors 1404, cause the system 1400 to implement a method as shown in fig. 5 or 6. In some embodiments, instructions 1424, hardware, firmware, and/or software components thereof may additionally/alternatively be disposed in system control logic 1408, network interface 1420, and/or processor 1404.

Network interface 1420 may include a transceiver to provide a radio interface for system 1400 to communicate over one or more networks to any other suitable devices (e.g., front end modules, antennas, etc.). In some embodiments, the network interface 1420 may be integrated with other components of the system 1400. For example, the network interface 1420 may be integrated with at least one of the processor 1404, the system memory 1412, the nvm/storage 1416, and a firmware device (not shown) having instructions which, when executed by at least one of the processor 1404, the system 1400 implements the methods as shown in fig. 5 or 6.

The network interface 1420 may further include any suitable hardware and/or firmware to provide a multiple-input multiple-output radio interface. For example, network interface 1420 may be a network adapter, a wireless network adapter, a telephone modem, and/or a wireless modem.

In one embodiment, at least one of the processors 1404 may be packaged together with logic for one or more controllers of the system control logic 1408 to form a System In Package (SiP). In one embodiment, at least one of the processors 1404 may be integrated on the same die with logic for one or more controllers of the system control logic 1408 to form a system on a chip (SoC).

The system 1400 may further include: input/output (I/O) devices 1432. The I/O device 1432 may include a user interface to enable a user to interact with the system 1400; the design of the peripheral component interface enables peripheral components to also interact with the system 1400. In some embodiments, system 1400 further includes a sensor for determining at least one of environmental conditions and location information associated with system 1400.

In some embodiments, the user interface may include, but is not limited to, a display (e.g., a liquid crystal display, a touch screen display, etc.), a speaker, a microphone, one or more cameras (e.g., still image cameras and/or video cameras), a flashlight (e.g., light emitting diode flash), and a keyboard.

In some embodiments, the peripheral component interface may include, but is not limited to, a non-volatile memory port, an audio jack, and a power interface.

In some embodiments, the sensors may include, but are not limited to, gyroscopic sensors, accelerometers, proximity sensors, ambient light sensors, and positioning units. The positioning unit may also be part of the network interface 1420 or interact with the network interface 1420 to communicate with components of a positioning network, such as Global Positioning System (GPS) satellites.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of these implementations. Embodiments of the present application may be implemented as a computer program or program code that is executed on a programmable system including at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Program code may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices in a known manner. For purposes of this application, a processing system includes any system having a processor such as, for example, a Digital Signal Processor (DSP), microcontroller, application specific integrated circuit (application specific integrated circuits, ASIC), or microprocessor.

The program code may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. Program code may also be implemented in assembly or machine language, if desired. Indeed, the mechanisms described in the present application are not limited in scope to any particular programming language. In either case, the language may be a compiled or interpreted language.

In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on one or more transitory or non-transitory machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed over a network or through other computer readable media. Thus, a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including but not limited to floppy diskettes, optical disks, read-only memories (CD-ROMs), magneto-optical disks, read-only memories (ROMs), random Access Memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or tangible machine-readable memory for transmitting information (e.g., carrier waves, infrared signal digital signals, etc.) in an electrical, optical, acoustical or other form of propagated signal using the internet. Thus, a machine-readable medium includes any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

In the drawings, some structural or methodological features may be shown in a particular arrangement and/or order. However, it should be understood that such a particular arrangement and/or ordering may not be required. Rather, in some embodiments, these features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of structural or methodological features in a particular figure is not meant to imply that such features are required in all embodiments, and in some embodiments, may not be included or may be combined with other features.

It should be noted that, in the embodiments of the present application, each unit/module is a logic unit/module, and in physical aspect, one logic unit/module may be one physical unit/module, or may be a part of one physical unit/module, or may be implemented by a combination of multiple physical units/modules, where the physical implementation manner of the logic unit/module itself is not the most important, and the combination of functions implemented by the logic unit/module is the key to solve the technical problem posed by the present application. Furthermore, to highlight the innovative part of the present application, the above-described device embodiments of the present application do not introduce units/modules that are less closely related to solving the technical problems presented by the present application, which does not indicate that the above-described device embodiments do not have other units/modules.

It should be noted that in the examples and descriptions of this patent, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

While the present application has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims

1. A motor driving method, characterized in that the method comprises:

and sending the first driving message to the first motor driving chip through the target IIC, wherein the first motor is connected with the first motor driving chip in the motor driving chips, and the first driving message is related to the action of the first motor.

2. The method of claim 1, wherein the first driving message is first vibration parameter information or a first instruction, wherein the first vibration parameter information is used to instruct the first motor driving chip to generate a first driving waveform signal for driving the first motor to vibrate, and the first instruction is used to trigger the first motor driving chip to output the first driving waveform signal to the first motor.

3. The method according to claim 2, wherein the method further comprises:

when the first driving message is first vibration parameter information, determining that a second vibration parameter to be sent corresponds to a second motor, and switching the slave address of the target IIC to the slave address of a second motor driving chip in the plurality of motor driving chips;

Transmitting second vibration parameter information to the second motor driving chip through the target IIC, wherein the second motor of the plurality of motors is connected with the second motor driving chip, and the second vibration parameter information is used for indicating the second motor driving chip to generate a second driving waveform signal for driving the second motor to vibrate;

determining that a second instruction to be sent corresponds to the second motor, and sending the second instruction to the second motor driving chip through the target IIC, wherein the second instruction is used for triggering the second motor driving chip to output the second driving waveform signal to the second motor;

determining that the first instruction to be sent corresponds to the first motor, and switching the slave address of the target IIC to the slave address of the first motor driving chip;

and sending the first instruction to the first motor driving chip through the target IIC.

4. The method of claim 3, wherein each of the plurality of motor drive chips has an IIC chip select pin, and wherein input parameters of the IIC chip select pins of different motor drive chips are different, and wherein different input parameters correspond to different slave addresses.

5. The method of claim 4, wherein the input parameter of the IIC chip select pin of the first motor drive chip is high and the input parameter of the IIC chip select pin of the second motor drive chip is low.

6. The method according to any one of claim 3 to 5, wherein,

the first vibration parameter information is used for indicating the first motor driving chip to configure an internal register to generate the first driving waveform signal;

the second vibration parameter information is used for indicating the second motor driving chip to configure an internal register to generate the second driving waveform signal.

7. A method according to claim 3, wherein the first vibration parameter information and the second vibration parameter information include at least the following information: waveform identification number, gain value, frequency and intensity.

8. A motor drive system, the system comprising: the system comprises a main control module, a plurality of motor driving chips connected with the main control module through a target integrated circuit IIC, and a plurality of motors connected with the motor driving chips one by one;

the master control module is used for determining that a first driving message to be sent corresponds to a first motor, and switching the slave address of the target IIC into the slave address of a first motor driving chip in the plurality of motor driving chips;

The main control module is used for sending the first driving message to the first motor driving chip through the target IIC, wherein the first motor is connected with the first motor driving chip, and the first driving message is related to the action of the first motor.

9. The system of claim 8, wherein the first driving message is first vibration parameter information or a first instruction, wherein the first vibration parameter information is used to instruct the first motor driving chip to generate a first driving waveform signal for driving the first motor to vibrate, and the first instruction is used to trigger the first motor driving chip to output the first driving waveform signal to the first motor.

10. The system of claim 9, wherein the system further comprises a controller configured to control the controller,

the main control module is further configured to determine that the second vibration parameter information to be sent corresponds to a second motor when the first driving message is first vibration parameter information, and switch the slave address of the target IIC to a slave address of a second motor driving chip in the plurality of motor driving chips;

the main control module is further configured to send the second vibration parameter information to the second motor driving chip through the target IIC, where the second motor is connected to the second motor driving chip, and the second vibration parameter information is used to instruct the second motor driving chip to generate a second driving waveform signal for driving the second motor to vibrate;

The main control module is further configured to determine that a second instruction to be sent corresponds to the second motor, send the second instruction to the second motor driving chip through a target IIC, and trigger the second motor driving chip to output the second driving waveform signal to the second motor;

the main control module is further used for determining that a first instruction to be sent corresponds to the first motor, and switching the slave address of the target IIC to the slave address of the first motor driving chip;

the main control module is further configured to send the first instruction to the first motor driving chip through the target IIC.

11. The system of claim 10, wherein each of the plurality of motor drive chips has an IIC chip select pin, and wherein input parameters of the IIC chip select pins of different motor drive chips are different, and wherein different input parameters correspond to different slave addresses.

12. The system of claim 11, wherein the input parameter of the IIC chip select pin of the first motor drive chip is high and the input parameter of the IIC chip select pin of the second motor drive chip is low.

13. The system according to any one of claims 10 to 12, wherein,

the first motor driving chip is used for configuring an internal register according to the first vibration parameter information to generate the first driving waveform signal and outputting the first driving waveform signal to the first motor based on the received first instruction;

the first motor is used for generating vibration according to the first driving waveform signal;

the second motor driving chip is used for configuring an internal register according to the second vibration parameter information to generate the second driving waveform signal and outputting the second driving waveform signal to the second motor based on the received second instruction;

the second motor is used for generating vibration according to the second driving waveform signal.

14. The system of claim 10, wherein the first vibration parameter information and the second vibration parameter information include at least the following information: waveform identification number, gain value, frequency and intensity.

15. An electronic device, comprising: a motor drive system according to any one of claims 8 to 14.