JP2007134683A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wireless chip having resistivity to a strong communication signal since, in the case of applying the strong communication signal to generate a power supply voltage from a communication signal, there is a risk that a large amount of voltage is generated in the wireless chip, and that a circuit may be electrically destroyed. <P>SOLUTION: A wireless chip having resistance to a strong communication signal is provided with an element in which a power source wire and a grounding wire are electrically short-circuited when a power supply voltage reaches a voltage at which an electric circuit is destroyed, that is, reaches a specified voltage value or more. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a semiconductor device for wireless communication. In particular, the present invention relates to a semiconductor device that supplies a power supply voltage generated from a communication signal to a circuit formed using a semiconductor thin film transistor.

  In recent years, a small semiconductor device (hereinafter referred to as a wireless chip) in which an ultra-small IC chip and an antenna for wireless communication are combined has attracted attention. The wireless chip can write and read data by exchanging communication signals using a wireless communication device (hereinafter referred to as a reader / writer).

As an application field of the wireless chip, for example, merchandise management in the distribution industry can be cited. In the current merchandise management, merchandise management using a bar code or the like is the mainstream, but since the bar code is optically read, the data cannot be read if there is a shield. On the other hand, when a wireless chip is used for merchandise management, data is read wirelessly, so if a wireless communication signal passes, it can be read even if there is a shield. Therefore, using a wireless chip for merchandise management is expected to improve merchandise management efficiency and cost. In addition, a wide range of applications such as a boarding ticket, an air passenger ticket, and automatic fee settlement are expected (see Patent Document 1).
JP 2000-149194 A

  A method for generating a power supply voltage from a communication signal in a wireless chip will be described with reference to FIGS. FIG. 3 shows a power supply circuit in the wireless chip, and FIG. 4 shows a time change of voltage in each part of the power supply circuit.

  In FIG. 3, the power supply circuit includes an antenna portion 301, a rectifying portion 302, and a storage capacitor portion 303. The antenna unit 301 includes an antenna 304 and a resonance capacitor 305. By receiving the communication signal, a potential difference (hereinafter referred to as an output potential of the antenna unit 301) is generated between the first output terminal 306 and the second output terminal 307 of the antenna unit 301. The rectifying unit 302 includes a diode 308. For simplicity, the rectification unit 302 will be described as a half-wave rectification unit. The first output terminal 306 and the second output terminal 307 of the antenna unit 301 are connected to the first input terminal 309 and the second input terminal 310 of the rectifying unit 302, and the first output terminal of the rectifying unit 302 is connected. A rectified potential difference (hereinafter referred to as an output potential of the rectifying unit 302) is generated between 311 and the second output terminal 312. The storage capacitor unit 303 has a storage capacitor 313. The first output terminal 311 and the second output terminal 312 of the rectifier 302 are connected to the first input terminal 314 and the second input terminal 315 of the storage capacitor 303, and the first of the storage capacitor 303 A potential difference (hereinafter referred to as an output potential of the storage capacitor portion 303) is generated between the output terminal 316 and the second output terminal 317. The output potential of the storage capacitor portion 303 becomes the power supply voltage of the wireless chip.

  In FIG. 4, the time change of the output potential in the antenna portion 301 in FIG. 3 is represented by a waveform 401 in FIG. At this time, the time change of the output potential of the rectifier 302 in FIG. 3 becomes a waveform 402 in FIG. Further, the time change of the output potential of the storage capacitor portion 303 in FIG. 3 becomes a waveform 403 in FIG. The diode 308 in the rectifier 302 is in a conductive state only when the potential at the first input terminal 309 is higher than the potential at the first output terminal 311 in the rectifier 302. Therefore, the diode 308 has a function of rectifying only the portion where the output potential of the antenna portion 301 is positive. The output potential of the rectifier 302 is smoothed by the storage capacitor 313 and becomes the output potential of the storage capacitor 303, but is gradually attenuated because it is consumed as power in the circuit of the wireless chip. In order to repeat the above, the output potential of the storage capacitor portion 303 changes with time as shown by the waveform 403.

  As described above, since the power supply voltage is generated from the communication signal in the wireless chip, when a communication signal having a large amplitude is given, a large voltage is generated so as to electrically destroy the circuit inside the wireless chip. There is a risk that. In addition, taking this in the other hand, it is also assumed that a third party intentionally gives a strong communication signal to the wireless chip and electrically destroys the circuit, thereby making it impossible to read information from the wireless chip. The Such destruction of a wireless chip by a communication signal having a strong amplitude will be referred to as a strong radio wave attack hereinafter. In order to prevent the information from being read from the wireless chip, the wireless chip needs to be resistant to such a strong radio wave attack.

  The present invention has been made in view of the above problems, and provides a wireless chip having high resistance to strong radio wave attacks. In particular, a wireless chip including a circuit that uses a power supply voltage generated inside a wireless chip as a specified value even when a strong communication signal is received is provided.

  In the wireless chip according to the present invention, in the power supply circuit, a circuit including an element that electrically shorts the power supply wiring and the ground wiring when the power supply circuit reaches a voltage that destroys the power supply circuit, that is, a power supply voltage that exceeds a specified voltage range. Have Note that since the power supply voltage has a predetermined potential difference, the element has a function of electrically short-circuiting the power supply wiring and the ground wiring when a potential difference exceeding the specified voltage range is reached. With such a configuration, even when a strong communication signal is given, the power supply voltage generated by the power supply circuit does not exceed the specified voltage range. Therefore, a highly reliable wireless chip having high resistance to strong radio wave attacks is provided.

  In the structure of the present invention disclosed in this specification, in a semiconductor device in which a power supply voltage is generated from a radio signal, the power supply circuit that generates the power supply voltage includes a leak element, and the leak element exceeds a specified voltage range. The electrical resistance of the leakage element when a voltage is generated in the power supply circuit is lower than the electrical resistance of the leakage element when a voltage within the specified voltage range is generated in the power supply circuit, thereby reducing the power supply voltage to the specified voltage. It is a semiconductor device characterized by being held within a range.

  According to another configuration of the present invention, in a semiconductor device in which a power supply voltage is generated from a radio signal, a power supply circuit that generates the power supply voltage includes a storage capacitor and a leak element, and the leak element is a voltage exceeding a specified voltage range. The electric resistance of the leakage element when the voltage is generated in the power supply circuit becomes lower than the electric resistance of the leakage element when the voltage within the range of the specified voltage is generated in the power supply circuit. Is supplied to the leakage element as a current, and the power supply voltage is maintained within a specified voltage range.

  In another configuration of the present invention, in a semiconductor device in which a power supply voltage is generated from a radio signal, the power supply circuit that generates the power supply voltage includes an antenna unit, a rectifier unit, and a storage capacitor unit, and the antenna unit includes an antenna And the resonant capacitor, the rectifier unit has a diode, the storage capacitor unit has a storage capacitor and a leak element, and the leak element has a voltage exceeding the specified voltage range in the power supply circuit. When the electrical resistance of the leakage element becomes lower than the electrical resistance of the leakage element when a voltage within the specified voltage range is generated in the power supply circuit, the electric charge accumulated in the storage capacitor flows as a current to the leakage element. The semiconductor device is characterized in that the power supply voltage is maintained within a specified voltage range.

  In the present invention, the rectifying unit can include a plurality of diodes.

  In the present invention, the power supply circuit is formed using a thin film transistor having a semiconductor thin film formed over a substrate having an insulating surface.

  In the present invention, any of a glass substrate, a quartz substrate, a plastic substrate, and an SOI substrate can be used as the substrate having an insulating surface.

  In the present invention, the potential difference between the first output terminal and the second output terminal of the storage capacitor portion is the power supply voltage.

  In the present invention, an N-type MOS transistor or a P-type MOS transistor can be applied as the leak element.

  In the present invention, an N-type memory transistor or a P-type memory transistor can be applied as the leak element.

  In the present invention, a MIS capacitor including a gate insulating film having a first region and a second region in which the gate insulating film is thinner than the first region can be applied to the leak element. Alternatively, the leak element has a MIS capacitor formed by stacking a semiconductor thin film, a gate insulating film, and a gate electrode. The gate insulating film is a film of the gate insulating film from the first region and the first region. You may have a 2nd area | region with thin thickness. In this case, the thickness of the gate insulating film in the second region is 50% to 80% of the thickness of the gate insulating film in the first region.

  In the present invention, a MIS capacitor formed by stacking a semiconductor thin film, a gate insulating film, and a gate electrode can be applied to the leak element. In this case, the gate insulating film includes a first region and a second region where the thickness of the gate insulating film is smaller than that of the first region, and the second region overlaps with an end portion of the gate electrode.

  In the present invention, a MIS capacitor formed by stacking a semiconductor thin film, a gate insulating film, and a gate electrode can be applied to the leak element. In this case, the gate insulating film includes a first region and a second region in which the gate insulating film is thinner than the first region, and the first region overlaps the semiconductor thin film, and the second region The region overlaps the end of the semiconductor thin film.

  According to the present invention, a highly reliable wireless chip can be provided as a wireless chip in which a power supply voltage is generated from a communication signal. In particular, the present invention is effective when the wireless chip is formed of a thin film transistor.

  Hereinafter, embodiments and examples of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of the embodiments and examples. Note that the same portions or portions having similar functions are denoted by the same reference symbols throughout the drawings for describing the embodiments and examples, and the repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment mode, a wireless chip according to the present invention will be described with reference to FIGS. FIG. 1 shows a power supply circuit in a wireless chip according to the present invention, and FIG.

  In FIG. 1, the power supply circuit includes an antenna portion 101, a rectifying portion 102, and a storage capacitor portion 103. The antenna unit 101 includes an antenna 104 and a resonance capacitor 105. By receiving the communication signal, a potential difference (hereinafter referred to as an output potential of the antenna unit 101) is generated between the first output terminal 106 and the second output terminal 107 of the antenna unit 101. The communication signal may be obtained from wired or wireless, and can be used in either form, but it has an antenna part and uses a form for obtaining a wireless communication signal (referred to as a wireless signal). I will explain.

  The rectifying unit 102 includes a diode 108. For simplicity, the rectification unit 102 is described as a half-wave rectification unit, but other than this, a full-wave rectification unit may be used. The first output terminal 106 and the second output terminal 107 of the antenna unit 101 are connected to the first input terminal 109 and the second input terminal 110 of the rectifying unit 102. The diode 108 has an input terminal connected to the first input terminal 109 of the rectifier 102 and an output terminal connected to the first output terminal 111. The diode 108 conducts only when the potential of the first input terminal 109 is higher than the potential of the second input terminal 110. Therefore, a rectified potential difference (hereinafter referred to as an output potential of the rectifying unit 102) is generated between the first output terminal 111 and the second output terminal 112 of the rectifying unit 102. Note that the output terminal and the input terminal can be collectively referred to as a connection terminal.

  The storage capacitor unit 103 includes a storage capacitor 113 and a leak element 118. The first output terminal 111 and the second output terminal 112 of the rectifying unit 102 are connected to the first input terminal 114 and the second input terminal 115 of the storage capacitor unit 103, and the first A potential difference (hereinafter referred to as an output potential of the storage capacitor portion 103) is generated between the output terminal 116 and the second output terminal 117. The output potential of the storage capacitor portion 103 becomes the power supply voltage of the wireless chip.

  The leak element 118 is an element having an electrical characteristic that the electrical resistance becomes very low when a voltage exceeding the specified voltage range is generated. The specified voltage is a voltage at which the circuit of the wireless chip, typically, the power supply circuit is not electrically destroyed. Specifically, the voltage is preferably 1V to 8V, but is not limited thereto. As the leak element 118, for example, a diode having a specified voltage as a threshold voltage, a transistor, or a MIS capacity in which a gate leak current becomes enormous when the range of the specified voltage is exceeded can be considered.

  In FIG. 2, the time change of the output potential in the antenna portion 101 of FIG. 1 is shown in a waveform 201 of FIG. At this time, the time change of the output potential of the rectifier 102 in FIG. 1 is a waveform 202 in FIG. Further, the time change of the output potential of the storage capacitor portion 103 in FIG. 1 is a waveform 203 in FIG. The diode 108 in the rectifying unit 102 becomes conductive only when the potential at the first input terminal 109 is higher than the potential at the first output terminal 111 in the rectifying unit 102. Therefore, the diode 108 has a function of rectifying only the portion where the output potential of the antenna portion 101 is a positive potential.

  Here, when the output potential of the rectifying unit 102, that is, the potential difference between the first input terminal 114 and the second input terminal 115 of the storage capacitor unit 103 is equal to or lower than the specified voltage, the storage capacitor 113 has the An output potential is applied and the supplied charge is accumulated. On the other hand, when the output potential of the rectifying unit 102 exceeds the specified voltage range, the leakage element 118 has a lower electrical resistance than when the output potential of the rectifying unit 102 is equal to or lower than the specified voltage. Therefore, the charge accumulated in the storage capacitor 113 flows to the leak element 118 as a current. That is, the output potential of the storage capacitor portion 103, that is, the waveform 203 in FIG. 2B does not increase beyond a specified value.

  The output potential of the rectifying unit 102 is smoothed by the storage capacitor 113 and becomes the output potential of the storage capacitor unit 103, but is gradually attenuated because it is consumed as power in the circuit of the wireless chip. In order to repeat the above, the output potential of the storage capacitor portion 103 changes with time as indicated by a waveform 203 in FIG.

  With the configuration as described above, even when a communication signal having a large amplitude is given to a wireless chip that generates a power supply voltage from a communication signal, the generated power supply voltage is within a specified voltage range. Can be held. Therefore, a highly reliable wireless chip is provided without the circuit being electrically destroyed even against a strong radio wave attack.

  The wireless chip in this embodiment can be formed over a glass substrate, a quartz substrate, a plastic substrate, or an SOI substrate. High-performance, low-power-consumption, high-reliability wireless chips can be achieved by using thin-film transistors that use semiconductor thin films formed on substrates with insulating surfaces such as glass substrates, quartz substrates, and plastic substrates. Without increasing, it is possible to provide lighter and cheaper.

(Embodiment 2)
In this embodiment, a wireless chip of the present invention, which is different from that described in Embodiment 1, will be described with reference to FIGS. FIG. 5 is a power supply circuit in the wireless chip in this embodiment, and FIG. 6 is a time change of voltage in each part of the power supply circuit.

  In FIG. 5, the power supply circuit includes an antenna portion 501, a rectifying portion 502, and a storage capacitor portion 503. The antenna portion 501 and the storage capacitor portion 503 are the same as those in Embodiment 1, except that the rectifier portion 502 includes the first diode 519 to the fourth diode 522 and a plurality of diodes. The antenna unit 501 includes an antenna 504 and a resonance capacitor 505, and receives a communication signal, whereby a potential difference (hereinafter referred to as the antenna unit 501) is generated between the first output terminal 506 and the second output terminal 507 of the antenna unit 501. Of the output potential). The communication signal may be obtained from wired or wireless, and can be used in either form, but it has an antenna part and uses a form for obtaining a wireless communication signal (referred to as a wireless signal). I will explain.

  In this embodiment, the rectification unit 502 is described as a full-wave rectification unit. The first output terminal 506 and the second output terminal 507 of the antenna unit 501 are connected to the first input terminal 509 and the second input terminal 510 of the rectifier unit 502, and the first output terminal of the rectifier unit 502 is connected. A rectified potential difference (hereinafter, referred to as an output potential of the rectifying unit 502) is generated between 511 and the second output terminal 512. The first diode 519 has an input terminal connected to the second output terminal 512 of the rectifying unit 502 and an output terminal connected to the first input terminal 509. The second diode 520 has an input terminal connected to the first input terminal 509 of the rectifying unit 502 and an output terminal connected to the first output terminal 511. The third diode 521 has an input terminal connected to the second output terminal 512 of the rectifying unit 502 and an output terminal connected to the second input terminal 510. The fourth diode 522 has an input terminal connected to the second input terminal 510 of the rectifying unit 502 and an output terminal connected to the first output terminal 511.

  The storage capacitor portion 503 includes a storage capacitor 513 and a leak element 518. The first output terminal 511 and the second output terminal 512 of the rectifier unit 502 are connected to the first input terminal 514 and the second input terminal 515 of the storage capacitor unit 503, and the first capacitor terminal 503 has a first output terminal 512. A potential difference (hereinafter referred to as an output potential of the storage capacitor portion 503) is generated between the output terminal 516 and the second output terminal 517. The output potential of the storage capacitor portion 503 becomes the power supply voltage of the wireless chip.

  The leak element 518 is an element having an electric characteristic that an electric resistance is lowered when a voltage exceeding a specified voltage range is generated. The specified voltage is a voltage at which the circuit of the wireless chip, typically, the power supply circuit is not electrically destroyed. Specifically, the voltage is preferably 1V to 8V, but is not limited thereto. As the leak element 518, for example, a diode having a specified voltage as a threshold voltage, a transistor, or a MIS capacitor in which a gate leak current becomes enormous when the specified voltage is exceeded can be considered.

  In FIG. 6, the time change of the output potential in the antenna portion 501 in FIG. 5 is represented by a waveform 601 in FIG. At this time, the time change of the output potential of the rectifier 502 in FIG. 5 is a waveform 602 in FIG. Further, the time change of the output potential of the storage capacitor portion 503 in FIG. 5 is a waveform 603 in FIG.

  The first diode 519 in the rectifying unit 502 is in a conductive state only when the potential at the second output terminal 512 is higher than the potential at the first input terminal 509 of the rectifying unit 502. In addition, the second diode 520 in the rectifier 502 is in a conductive state only when the potential at the first input terminal 509 is higher than the potential at the first output terminal 511 in the rectifier 502. Accordingly, there is a function of rectifying only the portion where the output potential of the antenna portion 501 is a positive potential. Further, the third diode 521 in the rectifying unit 502 is in a conductive state only when the potential at the second output terminal 512 is higher than the potential at the second input terminal 510 in the rectifying unit 502. In addition, the fourth diode 522 in the rectifier 502 is in a conductive state only when the potential at the second input terminal 510 is higher than the potential at the first output terminal 511 in the rectifier 502. Therefore, there is a function of rectifying only the portion where the output potential of the antenna portion 501 is a negative potential.

  Change over time of the output potential of the rectifier 102 of the half-wave rectifier in Embodiment 1 (waveform 202 in FIG. 2B) and change over time of the output potential of the rectifier 502 in this embodiment (FIG. 6B )) And the waveform 602), it can be seen that the time during which the output potential of the rectifier is output is doubled. That is, in the full-wave rectifier shown in this embodiment, the number of diodes is increased compared to the half-wave rectifier in Embodiment 1, but the output potential of antenna 501 obtained from the communication signal is efficiently held. It can be given to the capacitor portion 503.

  Here, when the output potential of the rectifying unit 502, that is, the potential difference between the first input terminal 514 and the second input terminal 515 of the storage capacitor unit 503 is equal to or lower than the specified voltage, the storage capacitor 513 has the An output potential is applied and the supplied charge is accumulated. On the other hand, when the output potential of the rectifying unit 502 exceeds the specified voltage range, the leakage element 518 has a lower electrical resistance than when the output potential of the rectifying unit 502 is equal to or lower than the specified voltage. Therefore, the charge accumulated in the storage capacitor 513 flows as a current to the leak element 518. In other words, the output potential of the storage capacitor portion 503, that is, the waveform 603 in FIG. 6B does not increase beyond the specified value.

  The output potential of the rectifier unit 502 is smoothed by the storage capacitor 513 and becomes the output potential of the storage capacitor unit 503, but is gradually attenuated because it is consumed as power in the circuit of the wireless chip. In order to repeat the above, the output potential of the storage capacitor portion 503 changes with time as shown by a waveform 603.

  With the above-described configuration, even when a strong communication signal is given to a wireless chip that generates a power supply voltage from a communication signal, the generated power supply voltage is maintained within a specified voltage range. be able to. Therefore, a highly reliable wireless chip is provided without the circuit being electrically destroyed even against a strong radio wave attack.

  The wireless chip in this embodiment can be formed over a glass substrate, a quartz substrate, a plastic substrate, or an SOI substrate. High-performance, low-power-consumption, high-reliability wireless chips can be achieved by using thin-film transistors that use semiconductor thin films formed on substrates with insulating surfaces such as glass substrates, quartz substrates, and plastic substrates. Without increasing, it is possible to provide lighter and cheaper.

  Embodiments of the present invention will be described below with reference to the drawings.

  In this example, an example in which a MOS transistor is used as an example of a leakage element in the structure of the wireless chip in the present invention described in Embodiment Modes 1 and 2 is described with reference to FIGS.

  FIG. 7A shows an example in which a leak element is formed using an N-type MOS transistor 701. The first terminal 702 and the second terminal 703 are electrically connected to the first output terminal 116 and the second output terminal 117 of the storage capacitor portion 103 in FIG. 1 described in Embodiment 1, respectively. The In addition, the first terminal 702 and the second terminal 703 are electrically connected to the first output terminal 516 and the second output terminal 517 of the storage capacitor portion 503 in FIG. 5 described in Embodiment 2, respectively. Connected.

  The threshold voltage of the N-type MOS transistor 701 is a specified voltage determined as a voltage at which the circuit of the wireless chip is not electrically destroyed. In Embodiment 1, when the potential of the first terminal 702 with respect to the second terminal 703 is equal to or lower than a specified voltage, the output potential of the rectifier 102 is applied to the storage capacitor 113 and the supplied charge is accumulated. On the other hand, when the output potential of the rectifying unit 102 exceeds the specified voltage range, the N-type MOS transistor 701 has a lower electrical resistance than when the output potential of the rectifying unit 102 is equal to or lower than the specified voltage, and the first terminal 702 When the second terminal 703 is electrically short-circuited, the charge accumulated in the storage capacitor 113 flows to the N-type MOS transistor 701 as a current. Similarly, in Embodiment 2, when the potential of the first terminal 702 with respect to the second terminal 703 is equal to or lower than a specified voltage, the output potential of the rectifier 502 is applied to the storage capacitor 513 and the supplied charge is accumulated. The On the other hand, when the output potential of the rectifying unit 502 exceeds the specified voltage range, the N-type MOS transistor 701 has a lower electrical resistance than when the output potential of the rectifying unit 502 is equal to or lower than the specified voltage, and the first terminal 702 When the second terminal 703 is electrically short-circuited, the charge accumulated in the storage capacitor 513 flows to the N-type MOS transistor 701 as a current. Therefore, the output potential of the storage capacitor portion 103 described in Embodiment 1 and the output potential of the storage capacitor portion 503 described in Embodiment 2 do not exceed the specified voltage range.

  FIG. 7B shows an example in which a leak element is configured using a P-type MOS transistor 704. The first terminal 705 and the second terminal 706 are electrically connected to the first output terminal 116 and the second output terminal 117 of the storage capacitor portion 103 in FIG. 1 described in Embodiment 1, respectively. The Alternatively, the first terminal 705 and the second terminal 706 are electrically connected to the first output terminal 516 and the second output terminal 517 of the storage capacitor portion 503 in FIG. 5 described in Embodiment 2, respectively. Connected.

  The absolute value of the threshold voltage of the P-type MOS transistor 704 falls within a specified voltage range determined as a voltage at which the circuit of the wireless chip is not electrically destroyed. In Embodiment 1, when the potential of the first terminal 705 with respect to the second terminal 706 is equal to or lower than a specified voltage, the output potential of the rectifier 102 is applied to the storage capacitor 113 and the supplied charge is accumulated. On the other hand, when the output potential of the rectifying unit 102 exceeds the specified voltage range, the P-type MOS transistor 704 has a lower electrical resistance than when the output potential of the rectifying unit 102 is equal to or lower than the specified voltage, and the first terminal 705 When the second terminal 706 is electrically short-circuited, the charge accumulated in the storage capacitor 113 flows to the P-type MOS transistor 704 as a current. Similarly, in Embodiment 2, when the potential of the first terminal 705 with respect to the second terminal 706 is equal to or lower than a specified voltage, the output potential of the rectifier 502 is applied to the storage capacitor 513 and the supplied charge is accumulated. The On the other hand, when the output potential of the rectifying unit 502 exceeds the specified voltage range, the P-type MOS transistor 704 has a lower electrical resistance than when the output potential of the rectifying unit 502 is equal to or lower than the specified voltage, and the first terminal 705 When the second terminal 706 is electrically short-circuited, the charge accumulated in the storage capacitor 513 flows to the P-type MOS transistor 704 as a current. Therefore, the output potential of the storage capacitor portion 103 described in Embodiment 1 and the output potential of the storage capacitor portion 503 described in Embodiment 2 do not exceed the specified voltage range.

  With the configuration as described above, even when a communication signal having a large amplitude is given to a wireless chip that generates a power supply voltage from a communication signal, the generated power supply voltage is within a specified voltage range. Can be held. Therefore, a highly reliable wireless chip is provided without the circuit being electrically destroyed even against a strong radio wave attack.

In this example, an example in which the wireless chip of the present invention described in Embodiments 1 and 2 is used and a memory transistor is used as an example of a leak element will be described with reference to FIGS. The memory transistor is an element having a memory function, and examples thereof include a transistor having a floating gate and a transistor having an electron trap level in a gate insulating film.

  FIG. 8A shows an example in which a leak element is formed using an N-type memory transistor 801. The first terminal 802 and the second terminal 803 are electrically connected to the first output terminal 116 and the second output terminal 117 of the storage capacitor portion 103 in FIG. 1 described in Embodiment 1, respectively. The Alternatively, the first terminal 802 and the second terminal 803 are electrically connected to the first output terminal 516 and the second output terminal 517 of the storage capacitor portion 503 in FIG. 5 described in Embodiment 2, respectively. Connected.

  The N-type memory transistor 801 can be a nonvolatile memory in which a floating gate is added to the gate insulating film of the N-type MOS transistor. In this case, the threshold voltage of the N-type memory transistor 801 can be determined by changing the amount of charge held in the floating gate. Further, the N-type memory transistor 801 can be a nonvolatile memory in which a nitride film that forms a charge trap level is added to the gate insulating film of the N-type MOS transistor. In this case, the threshold voltage of the N-type memory transistor 801 can be determined by changing the amount of charge held in the nitride film.

  The threshold voltage of the N-type memory transistor 801 is a specified voltage determined as a voltage at which the circuit of the wireless chip in the present invention is not electrically destroyed. In Embodiment 1, when the potential of the first terminal 802 with respect to the second terminal 803 is equal to or lower than a specified voltage, the output potential of the rectifier 102 is applied to the storage capacitor 113 and the supplied charge is accumulated. On the other hand, when the output potential of the rectifying unit 102 exceeds the range of the specified voltage, the N-type memory transistor 801 has a lower electrical resistance than when the output potential of the rectifying unit 102 is equal to or lower than the specified voltage, and the first terminal 802 When the second terminal 803 is electrically short-circuited, the charge accumulated in the storage capacitor 113 flows to the N-type memory transistor 801 as a current. Similarly, in Embodiment 2, when the potential of the first terminal 802 with respect to the second terminal 803 is equal to or lower than a specified voltage, the output potential of the rectifier 502 is applied to the storage capacitor 513 and the supplied charge is accumulated. The On the other hand, when the output potential of the rectifying unit 502 exceeds the range of the specified voltage, the N-type memory transistor 801 has a lower electrical resistance than when the output potential of the rectifying unit 502 is equal to or lower than the specified voltage, and the first terminal 802 When the second terminal 803 is electrically short-circuited, the charge accumulated in the storage capacitor 113 flows to the N-type memory transistor 801 as a current. Therefore, the output potential of the storage capacitor portion 103 described in Embodiment 1 and the output potential of the storage capacitor portion 503 described in Embodiment 2 do not exceed the specified voltage range.

FIG. 8B shows an example in which a leak element is configured using a P-type memory transistor 804. The first terminal 805 and the second terminal 806 are electrically connected to the first output terminal 116 and the second output terminal 117 of the storage capacitor portion 103 in FIG. 1 described in Embodiment 1, respectively. The Alternatively, the first terminal 805 and the second terminal 806 are electrically connected to the first output terminal 516 and the second output terminal 517 of the storage capacitor portion 503 in FIG. 5 described in Embodiment 2, respectively. Connected.

  The P-type memory transistor 804 can be a nonvolatile memory in which a floating gate is added to the gate insulating film of the P-type MOS transistor. In this case, the threshold voltage of the P-type memory transistor 804 can be determined by changing the amount of charge held in the floating gate. The P-type memory transistor 804 can be a non-volatile memory in which a nitride film that forms a charge trap level is added to the gate insulating film of the P-type MOS transistor. In this case, the threshold voltage of the P-type memory transistor 804 can be determined by changing the amount of charge held in the nitride film.

  The absolute value of the threshold voltage of the P-type memory transistor 804 is a specified voltage determined as a voltage at which the circuit of the wireless chip in the present invention is not electrically destroyed. In Embodiment 1, when the potential of the first terminal 805 with respect to the second terminal 806 is equal to or lower than the specified voltage, the output potential of the rectifier 102 is applied to the storage capacitor 113 and the supplied charge is accumulated. On the other hand, when the output potential of the rectifier 102 exceeds the specified voltage range, the P-type memory transistor 804 has a lower electrical resistance than when the output potential of the rectifier 102 is equal to or lower than the specified voltage, and the first terminal 805 When the second terminal 806 is electrically short-circuited, the charge accumulated in the storage capacitor 113 flows to the P-type memory transistor 804 as a current. Similarly, in Embodiment 2, when the potential of the first terminal 805 with respect to the second terminal 806 is equal to or lower than the specified voltage, the output potential of the rectifier 502 is applied to the storage capacitor 513 and the supplied charge is accumulated. The On the other hand, when the output potential of the rectifying unit 502 exceeds the specified voltage range, the P-type memory transistor 804 has a lower electrical resistance than when the output potential of the rectifying unit 502 is equal to or lower than the specified voltage, and the first terminal 805 When the second terminal 806 is electrically short-circuited, the charge accumulated in the storage capacitor 113 flows to the P-type memory transistor 804 as a current. Therefore, the output potential of the storage capacitor portion 103 described in Embodiment 1 and the output potential of the storage capacitor portion 503 described in Embodiment 2 do not exceed the specified voltage range.

  With the above-described configuration, even when a strong communication signal is given to a wireless chip that generates a power supply voltage from a communication signal, the generated power supply voltage is maintained within a specified voltage range. be able to. Therefore, a highly reliable wireless chip is provided without the circuit being electrically destroyed even against a strong radio wave attack.

  In this example, an example of using the MIS capacitor as an example of the leak element in the structure of the wireless chip in the present invention shown in Embodiment Modes 1 and 2 will be described with reference to FIGS. explain.

  FIG. 9 shows an example in which a leak element is configured using a MIS capacitor 901. The first terminal 902 and the second terminal 903 are electrically connected to the first output terminal 116 and the second output terminal 117 of the storage capacitor portion 103 in FIG. 1 described in Embodiment 1, respectively. The Alternatively, the first terminal 902 and the second terminal 903 are electrically connected to the first output terminal 516 and the second output terminal 517 of the storage capacitor portion 503 in FIG. 5 described in Embodiment 2, respectively. Connected.

  The MIS capacitor 901 has a characteristic that a gate leakage current becomes enormous when a voltage exceeding a specified voltage range determined as a voltage at which the circuit of the wireless chip in the present invention is not electrically destroyed is generated. Therefore, when the potential of the first terminal 902 with respect to the second terminal 903 exceeds the specified voltage range, the MIS capacitor 901 has a lower electrical resistance than when the output potential of the rectifying unit 502 is equal to or lower than the specified voltage. The terminal 902 and the second terminal 903 are electrically short-circuited. Therefore, the output potential of the storage capacitor portion 103 described in Embodiment 1 and the output potential of the storage capacitor portion 503 described in Embodiment 2 do not exceed the specified voltage range.

  FIG. 10 shows a layout and a cross-sectional view of the MIS capacitor 901 having the above characteristics. 10A, a gate insulating film 1016 is stacked over a semiconductor thin film 1001, and a gate electrode 1002 is formed thereover. Further, an interlayer insulating film is stacked, and a source electrode and a drain electrode 1003 are formed thereon. The source and drain electrodes 1003 are electrically connected to the semiconductor thin film 1001 through contacts 1004. Note that the gate electrode 1002 and the source and drain electrodes 1003 correspond to the first terminal 902 and the second terminal 903 in FIG. 9, respectively.

  The MIS capacitor 901 includes a gate insulating film 1016 having a first region and a second region where the thickness of the gate insulating film is thinner than the first region, and the leak path 1005 includes the second region of the gate insulating film. It is an area. That is, this is a region where the electric withstand voltage of the gate insulating film is low. In order to form the leak path 1005, for example, the gate insulating film 1016 may be formed and then formed by an etching process using a photomask. Here, the film thickness of the gate insulating film is determined so that an enormous gate leakage current flows through the leakage path 1005 when a voltage exceeding the specified voltage range is generated in the MIS capacitor. For example, a gate insulating film having a thickness of 3 nm to 10 nm can be formed on the surface of silicon by a thermal oxidation method. In order to allow gate leakage current to flow, the thickness of the gate insulating film in the second region is preferably in the range of 50% to 80% of the thickness of the gate insulating film in the first region. For example, when the thickness of the gate insulating film in the first region is 30 nm, the thickness of the gate insulating film in the second region is 15 nm to 24 nm.

  Therefore, the output potential of the storage capacitor portion 103 described in Embodiment 1 and the output potential of the storage capacitor portion 503 described in Embodiment 2 do not exceed the specified voltage range.

  10B, a gate insulating film 1017 is stacked over the semiconductor thin film 1006, and a gate electrode 1007 is formed thereover. Further, an interlayer insulating film is stacked, and a source electrode and a drain electrode 1008 are formed thereon. The source and drain electrodes 1008 are electrically connected to the semiconductor thin film 1006 through contacts 1009. Note that the gate electrode 1007 and the source and drain electrodes 1008 correspond to the first terminal 902 and the second terminal 903 in FIG. 9, respectively.

  The MIS capacitor 901 includes a gate insulating film 1017 having a first region and a second region in which the gate insulating film is thinner than the first region. The leak path 1010 includes the second region of the gate insulating film 1017. It is an area. The leak path 1010 is a region where the gate insulating film 1017 under the gate electrode 1007 is removed and a defect 1019 is generated when there is anisotropy in the gate forming step, and the gate insulating film 1017 is thin. It is. That is, this is a region where the electric withstand voltage of the gate insulating film is low. When a voltage exceeding the specified voltage range is generated in the MIS capacitor, a huge gate leak current flows through the leak path 1010. In FIG. 10B, a plurality of second regions of the gate insulating film 1017 are formed so as to overlap with an end portion of the gate electrode 1007. By applying the MIS capacitor having such a leak path, the output potential of the storage capacitor portion 103 described in Embodiment Mode 1 and the output potential of the storage capacitor portion 503 described in Embodiment Mode 2 are within the specified voltage range. Do not exceed.

  In FIG. 10C, a gate insulating film 1018 is stacked over the semiconductor thin film 1011 and a gate electrode 1012 is formed thereover. Further, an interlayer insulating film is stacked, and a source electrode and a drain electrode 1013 are formed thereon. The source and drain electrodes 1013 are electrically connected to the semiconductor thin film 1011 through contacts 1014. Note that the gate electrode 1012 and the source and drain electrodes 1013 correspond to the first terminal 902 and the second terminal 903 in FIG. 9, respectively.

  The MIS capacitor 901 includes a gate insulating film 1018 having a first region that overlaps the semiconductor thin film 1011 and a second region in which the thickness of the gate insulating film is thinner than the first region. This is the second area. The leak path 1015 is a region where a lattice defect 1020 is generated due to mechanical stress during the gate insulating film forming step, and the gate insulating film 1018 is thin. Such a thin region is a region where the electric withstand voltage of the gate insulating film is low. When a voltage exceeding the specified voltage range is generated in the MIS capacitor, a huge gate leak current flows through the leak path 1015. In FIG. 10C, a plurality of second regions of the gate insulating film 1018 are formed so as to overlap with an end portion of the semiconductor thin film 1011. By applying the MIS capacitor having such a leak path, the output potential of the storage capacitor portion 103 described in Embodiment Mode 1 and the output potential of the storage capacitor portion 503 described in Embodiment Mode 2 are within the specified voltage range. Do not exceed.

  With the configuration as described above, even when a communication signal having a large amplitude is given to a wireless chip that generates a power supply voltage from a communication signal, the generated power supply voltage is within a specified voltage range. Can be held. Therefore, a highly reliable wireless chip is provided without the circuit being electrically destroyed even against a strong radio wave attack.

  In this embodiment, the MIS capacitor is used for description, but it can be manufactured using a capacitor formed of a thin film transistor (referred to as a TFT capacitor). In the case of using a TFT capacitor, the thickness of the gate insulating film can be set to 20 nm to 100 nm. In FIG. 10A, the thickness of the second region of the gate insulating film may be 50% to 80% of the thickness of the first region. For example, when the thickness of the gate insulating film in the first region is 20 nm, the thickness of the gate insulating film in the second region is 10 nm to 16 nm.

In this embodiment, as an example of a semiconductor device of the present invention, a wireless chip having a cryptographic processing function will be described with reference to FIGS. 13 is a block diagram of the wireless chip, and FIG. 14 is a layout diagram of the wireless chip.

  First, the block configuration of the wireless chip will be described with reference to FIG. In FIG. 13, a wireless chip 2601 includes a CPU 2602, a ROM 2603, a RAM 2604, an arithmetic circuit 2606 having a controller 2605, an antenna unit 2607 having an antenna, a resonance circuit 2608 having a resonance capacitor, a power supply circuit 2609, and a reset. A circuit 2610, a clock generation circuit 2611, a demodulation circuit 2612, a modulation circuit 2613, and an analog unit 2615 having a power management circuit 2614 are included. The circuit configuration described above can be applied to the power supply circuit 2609.

  The controller 2605 includes a CPU interface (CPUIF) 2616, a control register 2617, a code extraction circuit 2618, and an encoding circuit 2619. Note that in FIG. 13, for simplification of description, the communication signal is illustrated as being divided into a reception signal 2620 and a transmission signal 2621, but in reality, both are superimposed, and the wireless chip 2601 and the reader / writer are overlapped. Are sent and received at the same time. Received signal 2620 is received by antenna section 2607 and resonant circuit 2608, and then demodulated by demodulation circuit 2612. The transmission signal 2621 is modulated by the modulation circuit 2613 and then transmitted from the antenna unit 2607.

  In FIG. 13, when the wireless chip 2601 is placed in a magnetic field formed by a communication signal, an induced electromotive force is generated by the antenna portion 2607 and the resonance circuit 2608. The induced electromotive force is held by an electric capacity in the power supply circuit 2609, and the potential is stabilized by the electric capacity, and is supplied as a power supply voltage to each circuit of the wireless chip 2601. The reset circuit 2610 generates an initial reset signal for the entire wireless chip 2601. For example, a signal that rises after a rise in the power supply voltage is generated as a reset signal. The clock generation circuit 2611 changes the frequency and duty ratio of the clock signal in accordance with the control signal generated by the power management circuit 2614. The demodulation circuit 2612 detects the fluctuation of the amplitude of the ASK reception signal 2620 as “0” / “1” reception data 2622. The demodulation circuit 2612 is a low-pass filter, for example. Further, the modulation circuit 2613 transmits the transmission data by changing the amplitude of the ASK transmission signal 2621. For example, when the transmission data 2623 is “0”, the resonance point of the resonance circuit 2608 is changed, and the amplitude of the communication signal is changed. The power management circuit 2614 monitors the power supply voltage supplied from the power supply circuit 2609 to the arithmetic circuit 2606 or the current consumption in the arithmetic circuit 2606, and a control signal for changing the frequency and duty ratio of the clock signal in the clock generation circuit 2611. Is generated.

  The operation of the wireless chip in this embodiment will be described. First, the wireless chip 2601 receives a reception signal 2620 including ciphertext data from a reader / writer. The received signal 2620 is demodulated by the demodulation circuit 2612, decomposed into a control command, ciphertext data, and the like by the code extraction circuit 2618 and stored in the control register 2617. Here, the control command is data specifying a response of the wireless chip 2601. For example, transmission of a unique ID number, operation stop, and decryption are designated. Here, it is assumed that a decryption control command is received.

  Subsequently, in the arithmetic circuit 2606, the CPU 2602 decrypts (decrypts) the ciphertext using the secret key 2624 stored in advance in the ROM 2603 according to the decryption program stored in the ROM 2603. The decrypted ciphertext (decrypted text) is stored in the control register 2617. At this time, the RAM 2604 is used as a data storage area. Note that the CPU 2602 accesses the ROM 2603, the RAM 2604, and the control register 2617 via the CPU interface (CPUIF) 2616. The CPU interface (CPUIF) 2616 has a function of generating an access signal for any of the ROM 2603, the RAM 2604, and the control register 2617 from an address requested by the CPU 2602.

  Finally, in the encoding circuit 2619, transmission data 2623 is generated from the decoded text, modulated by the modulation circuit 2613, and the transmission signal 2621 is transmitted from the antenna unit 2607 to the reader / writer.

  In this embodiment, as a calculation method, a method of processing by software, that is, a method of configuring a calculation circuit with a CPU and a large-scale memory and executing a program by the CPU has been described. It is also possible to select an appropriate calculation method and configure based on the method. For example, as a calculation method, other methods such as a method of processing the operation in hardware and a method of using both hardware and software are conceivable. In the method of processing in hardware, an arithmetic circuit may be configured with a dedicated circuit. In the method using both hardware and software, a dedicated circuit, a CPU, and a memory constitute an arithmetic circuit, a part of the arithmetic processing is performed by the dedicated circuit, and the remaining arithmetic processing program is executed by the CPU. .

  Next, the layout configuration of the wireless chip will be described with reference to FIG. In FIG. 14, parts corresponding to those in FIG. 13 are denoted by the same reference numerals and description thereof is omitted.

  In FIG. 14, an FPC pad 2707 is an electrode pad group used when an FPC (Flexible Print Circuit) is attached to the wireless chip 2601, and an antenna bump 2708 is an electrode pad for attaching an antenna (not shown). Note that when the antenna is attached, excessive pressure may be applied to the antenna bump 2708. Therefore, it is desirable not to dispose a component such as a transistor under the antenna bump 2708.

  The FPC pad 2707 is effective when used mainly for failure analysis. In the wireless chip, since the power supply voltage is obtained from the communication signal, for example, when a failure occurs in the antenna or the power supply circuit, the arithmetic circuit does not operate at all. For this reason, failure analysis becomes extremely difficult. However, the power supply voltage is supplied from the FPC to the wireless chip 2601 through the FPC pad 2707, and the arithmetic circuit is operated by inputting an arbitrary electric signal instead of the electric signal supplied from the antenna. Is possible. Therefore, failure analysis can be performed efficiently.

  Furthermore, it is more effective to arrange the FPC pad 2707 so that measurement using a prober is possible. That is, in the FPC pad 2707, the electrode pad is arranged in accordance with the pitch of the prober needle, whereby measurement by the prober becomes possible. By using a prober, it is possible to reduce the number of steps for attaching the FPC during failure analysis. Further, since measurement can be performed even when a plurality of wireless chips are formed on a substrate, the number of steps for dividing each wireless chip can be reduced. In addition, it is possible to perform a non-defective inspection of the wireless chip immediately before the step of attaching the antenna during mass production. Accordingly, defective products can be selected at an early stage of the process, so that production costs can be reduced.

  Note that the leakage element described in Embodiment Mode 1, Embodiment Mode 2, and Embodiments 1 to 3 can be incorporated in the power supply circuit 2609 in this embodiment. With such a configuration, in a wireless chip that internally generates a power supply voltage from a communication signal, the generated power supply voltage is maintained within a specified voltage range even when a strong communication signal is given. Can do. Therefore, a highly reliable wireless chip is provided without the circuit being electrically destroyed even against a strong radio wave attack.

  In this embodiment, a system example using the semiconductor device of the present invention will be described with reference to FIGS. In this embodiment, a personal computer user authentication system with excellent security using a wireless chip as a semiconductor device according to the present invention will be described.

  FIG. 11 is a schematic diagram of a user authentication system in the present embodiment, which shows a personal computer 2001 and a wireless chip 2002. An input device 2003 and a reader / writer 2004 are connected to the personal computer 2001.

  The personal computer 2001 and the wireless chip 2002 have a common key 2005 for encryption. Specifically, the data of the common key 2005 is stored in the memories of the personal computer 2001 and the wireless chip 2002, respectively. The common key 2005 is 64-bit to 128-bit data, for example, and is used for encryption of plaintext (data before encryption) and decryption of the ciphertext. As the common key, a different common key is created for each registered user, and the personal computer 2001 has all the common keys. In other words, the personal computer 2001 has as many common keys as the number of users registered in a regular manner. On the other hand, the wireless chip 2002 is owned by a properly registered user and has only a common key unique to the user. The common key must be stored so that it is not known to others.

  In this embodiment, a common key cryptosystem (ISO / IEC 9798-2 Information technology-Security techniques-Entity authentication-Part 2: An example of using a mechanical encryption metric) is used. Key encryption method (refer to ISO / IEC 9798-3 Information technology-Security techniques-Entity authentication-Part 3: Suitable for methods used in digital signature techniques, etc.) Can be used.

  The personal computer 2001 has means for encrypting plaintext using the common key 2005. Specifically, it is assumed that software for executing an encryption algorithm is installed. The wireless chip 2002 also has means for decrypting the ciphertext using the common key 2005. Specifically, a decoding algorithm is executed in the arithmetic circuit shown in the above embodiment.

  Hereinafter, a method of using the user authentication system in this embodiment will be described with reference to the flowchart of FIG.

  First, a user who wishes to use inputs the user name and password in the personal computer 2001 using the input device 2003 (user name input 2101). The password is registered in advance by an authorized user. The personal computer 2001 encrypts a certain plaintext from the input user name using the corresponding common key (encrypted data creation 2102). Here, the plaintext may be data having a specific meaning or meaningless data. Next, the encrypted data is transmitted from the reader / writer 2004 (encrypted data transmission 2103). The wireless chip 2002 receives the encrypted data, decrypts the encrypted data using the common key 2005 (decryption process 2104), and transmits the decrypted data to the reader / writer (decrypted data transmission 2105). The personal computer 2001 compares the decrypted data with the first plaintext (authentication 2106), and if it matches, the personal computer 2001 recognizes that the user who wishes to use is a registered user and makes it available (normal use 2107). ).

  In the user authentication system in the present embodiment as described above, the computer cannot be used unless the password is known and the wireless chip is not owned. Therefore, security is much higher than password-only authentication. Further, if the user carries the wireless chip, the user can use the personal computer without any change from the conventional authentication using only the password, and the new burden is small.

  In this embodiment, personal computer user authentication has been described. However, the present invention can be easily applied to other systems that can be used only by authorized users. For example, it can be easily applied to ATM (Automated Teller Machine cash dispenser), CD (Cash Dispenser cash dispenser), and the like.

  With the configuration as described above, a user authentication system with extremely high security using the semiconductor device of the present invention can be constructed at low cost.

  Note that this embodiment can be implemented by being freely combined with Embodiment Mode 1, Embodiment Mode 2, and Embodiments 1 to 4.

FIG. 3 is a diagram showing a power supply circuit of a semiconductor device according to the present invention. FIG. 6 shows signal waveforms of a power supply circuit of a semiconductor device according to the present invention. The figure which shows the example of the conventional power supply circuit. The figure which shows the example of the signal waveform of the conventional power supply circuit. FIG. 3 is a diagram showing a power supply circuit of a semiconductor device according to the present invention. FIG. 6 shows signal waveforms of a power supply circuit of a semiconductor device according to the present invention. The figure which shows the circuit which comprised the leak element of the semiconductor device in this invention with the MOS transistor. FIG. 4 is a diagram showing a circuit in which a leak element of a semiconductor device according to the present invention is configured by a memory transistor. FIG. 4 is a diagram showing a circuit in which a leak element of a semiconductor device according to the present invention is configured with a MIS capacitor. FIG. 6 is a diagram showing a layout of leak elements of a semiconductor device according to the present invention. The figure which shows the outline | summary of the user authentication system using the semiconductor device in this invention. The figure which shows the flowchart of the user authentication system using the semiconductor device in this invention. FIG. 6 illustrates a configuration example of a semiconductor device in the present invention. FIG. 6 is a diagram showing a layout example of a semiconductor device in the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Antenna part 102 Rectification part 103 Holding capacity part 104 Antenna 105 Resonance capacity 106 Output terminal 107 Output terminal 108 Diode 109 Input terminal 110 Input terminal 111 Output terminal 112 Output terminal 113 Holding capacity 114 Input terminal 115 Input terminal 116 Output terminal 117 Output terminal 118 Leak element 201 Waveform 202 Waveform 203 Waveform 301 Antenna unit 302 Rectifier unit 303 Retention capacitor unit 304 Antenna 305 Resonance capacitor 306 Output terminal 307 Output terminal 308 Diode 309 Input terminal 310 Input terminal 311 Output terminal 312 Output terminal 313 Retention capacitor 314 Input terminal 315 Input terminal 316 Output terminal 317 Output terminal 401 Waveform 402 Waveform 403 Waveform 501 Antenna part 502 Rectifying part 503 Retention capacity part 504 Antenna 505 Resonance capacity 50 6 Output terminal 507 Output terminal 509 Input terminal 510 Input terminal 511 Output terminal 512 Output terminal 513 Retention capacitor 514 Input terminal 515 Input terminal 516 Output terminal 517 Output terminal 518 Leak element 519 Diode 520 Diode 521 Diode 522 Diode 601 Waveform 602 Waveform 603 Waveform 701 N-type MOS transistor 702 Terminal 703 Terminal 704 P-type MOS transistor 705 Terminal 706 Terminal 801 N-type memory transistor 802 Terminal 803 Terminal 804 P-type memory transistor 805 Terminal 806 Terminal 901 MIS capacitor 902 Terminal 903 Terminal 1001 Semiconductor thin film 1002 Gate electrode 1003 Source electrode and drain electrode 1004 Contact 1005 Leakage path 1006 Semiconductor thin film 1007 Gate electrode 1008 Source electrode and drain electrode 1009 Contact 1010 Leakage path 1011 Semiconductor thin film 1012 Gate electrode 1013 Source and drain electrode 1014 Contact 1015 Leakage path 1016 Gate insulation film 1017 Gate insulation film 1018 Gate insulation film 1019 Defect 1020 Lattice defect 2001 Personal computer 2002 Wireless chip 2003 Input device 2004 Reader / writer 2005 Common key 2101 User name input 2102 Encrypted data creation 2103 Encrypted data transmission 2104 Decryption processing 2105 Decryption data transmission 2106 Authentication 2107 Normal use 2601 Wireless chip 2602 CPU
2603 ROM
2604 RAM
2605 Controller 2606 Arithmetic circuit 2607 Antenna unit 2608 Resonance circuit 2609 Power supply circuit 2610 Reset circuit 2611 Clock generation circuit 2612 Demodulation circuit 2613 Modulation circuit 2614 Power management circuit 2615 Analog unit 2616 CPU interface (CPUIF)
2617 Control register 2618 Code extraction circuit 2619 Encoding circuit 2620 Reception signal 2621 Transmission signal 2622 Reception data 2623 Transmission data 2624 Private key 2707 FPC pad 2708 Antenna bump

Claims (14)

In a semiconductor device in which a power supply voltage is generated from a radio signal,
The power supply circuit for generating the power supply voltage has a leak element,
The leak element is
The electrical resistance of the leak element when a voltage exceeding the specified voltage range is generated in the power supply circuit, and the electrical resistance of the leak element when a voltage within the specified voltage range is generated in the power supply circuit. By lowering
A semiconductor device characterized in that the power supply voltage is maintained within a range of the specified voltage. In a semiconductor device in which a power supply voltage is generated from a radio signal,
The power supply circuit for generating the power supply voltage has a storage capacitor and a leak element,
The leak element is
The electrical resistance of the leak element when a voltage exceeding the specified voltage range is generated in the power supply circuit, and the electrical resistance of the leak element when a voltage within the specified voltage range is generated in the power supply circuit. By lowering
A semiconductor device, wherein the charge accumulated in the storage capacitor is caused to flow as a current to the leak element, and the power supply voltage is held within the specified voltage range. In a semiconductor device in which a power supply voltage is generated from a radio signal,
The power supply circuit that generates the power supply voltage includes an antenna unit, a rectifying unit, and a storage capacitor unit,
The antenna unit has an antenna and a resonant capacitance,
The rectifying unit includes a diode,
The storage capacitor unit includes a storage capacitor and a leak element,
The leak element is
The electrical resistance of the leak element when a voltage exceeding the specified voltage range is generated in the power supply circuit, and the electrical resistance of the leak element when the voltage within the specified voltage range is generated in the power supply circuit. By lowering
A semiconductor device, wherein the charge accumulated in the storage capacitor is made to flow as a current through the leak element, and the power supply voltage is held within the specified voltage range. In claim 3,
The rectifying unit includes a plurality of the diodes. In any one of Claims 1 thru | or 4,
The power supply circuit includes a thin film transistor having a semiconductor thin film formed over a substrate having an insulating surface. In claim 5,
The substrate having an insulating surface is any one of a glass substrate, a quartz substrate, a plastic substrate, and an SOI substrate. In any one of Claims 1 thru | or 6,
A semiconductor device, wherein a potential difference between a first output terminal and a second output terminal of the storage capacitor portion becomes the power supply voltage. In any one of Claims 1 thru | or 7,
The semiconductor device according to claim 1, wherein the leak element is an N-type MOS transistor or a P-type MOS transistor. In any one of Claims 1 thru | or 7,
The semiconductor device, wherein the leak element is an N-type memory transistor or a P-type memory transistor. In any one of Claims 1 thru | or 7,
The semiconductor device according to claim 1, wherein the leak element has a MIS capacitor including a first region and a gate insulating film having a second region in which a gate insulating film is thinner than the first region. In any one of Claims 1 thru | or 7,
The leak element has a MIS capacitor formed by stacking a semiconductor thin film, a gate insulating film, and a gate electrode,
The semiconductor device, wherein the gate insulating film includes a first region and a second region where the thickness of the gate insulating film is smaller than that of the first region. In claim 10 or claim 11,
The semiconductor device according to claim 1, wherein the thickness of the gate insulating film in the second region is in a range of 50% to 80% of the thickness of the gate insulating film in the first region. In any one of Claims 1 thru | or 7,
The leak element has a MIS capacitor formed by stacking a semiconductor thin film, a gate insulating film, and a gate electrode,
The gate insulating film includes a first region and a second region in which the gate insulating film is thinner than the first region,
The semiconductor device, wherein the second region overlaps with an end portion of the gate electrode. In any one of Claims 1 thru | or 7,
The leak element has a MIS capacitor formed by stacking a semiconductor thin film, a gate insulating film, and a gate electrode,
The gate insulating film includes a first region and a second region in which the gate insulating film is thinner than the first region,
The first region overlaps the semiconductor thin film,
The semiconductor device according to claim 1, wherein the second region overlaps an end portion of the semiconductor thin film.

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