JP4906076B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device having a large-scale arithmetic circuit. In particular, the present invention relates to a semiconductor device in which an arithmetic circuit operates stably even when a power supply voltage fluctuates. In particular, the present invention relates to a semiconductor device in which a power supply voltage is supplied from a wireless communication signal and a large-scale circuit having an advanced calculation function is formed using a semiconductor thin film transistor.

In recent years, a small semiconductor device (hereinafter referred to as a wireless chip) combining an ultra-small IC chip and an antenna for wireless communication has attracted attention. The wireless chip can write and read data by transmitting and receiving a communication signal (operation magnetic field) using a wireless communication device (hereinafter referred to as a reader / writer).

As an application field of the wireless chip, for example, merchandise management in the distribution industry can be cited. At present, merchandise management using bar codes and the like is the mainstream, but since bar codes are optically read, data cannot be read if there is a shield. On the other hand, since the wireless chip reads data wirelessly, it can be read even if there is a shielding object. Accordingly, it is expected to improve the efficiency of product management and cost reduction. In addition, a wide range of applications such as a boarding ticket, an air passenger ticket, and automatic fee settlement are expected (see Patent Document 1).
JP 2000-149194 A

As the application field of wireless chips is expanding, the demand for higher-performance wireless chips is also increasing. For example, it is expected to prevent data leakage to a third party by encrypting transmission / reception data. For this, a method of processing the decryption / encryption process by hardware, a method of processing by software, and a method of using both hardware and software are conceivable. In the method of processing in hardware, an arithmetic circuit is configured by a dedicated circuit that performs decryption / encryption. In the method of processing in software, an arithmetic circuit is constituted by a CPU (Central Processing Unit) and a large-scale memory, and a decryption / encryption program is executed by the CPU. In the method using both hardware and software, the dedicated circuit, CPU, and memory constitute an arithmetic circuit, and the dedicated circuit performs a part of the decryption / encryption arithmetic processing, and the remaining arithmetic processing program is executed. Run on the CPU. However, in any case, a large-scale circuit is mounted on the wireless chip.

For example, ISO / IEC 15693 is defined as a standard for communication in a wireless chip. According to ISO / IEC 15693, 13.56 MHz ± 7 kHz is used as the frequency of the carrier wave in the communication signal, and the ASK (Amplitude Shift Keying Amplitude Displacement Keying) method is used for data transmission from the reader / writer to the wireless chip. FIG. 2 shows a communication signal at the time of data transmission to the wireless chip in the ASK method. In FIG. 2, a communication signal 201 is an electromagnetic wave that vibrates at the frequency of a carrier wave. Data transmitted by the communication signal 201 is represented by an envelope 202 of the amplitude of the communication signal 201. A case where the amplitude of the communication signal 201 is maximum is “1”, and a case where the amplitude is minimum is “0”. The wireless chip receives “0” and “1” from such a communication signal 201.

A power supply voltage and a clock signal necessary for the operation of the wireless chip are generated from the communication signal 201. Therefore, in order to operate an arithmetic circuit in a wireless chip, a large-scale antenna that can supply a larger current than a communication signal, a large-scale power supply circuit, a clock generation circuit that can supply a stable clock signal, and the like are required. There is a risk of increasing the chip area and increasing the chip price. Further, since the ASK method is used for data transmission, supply of the power supply voltage and the clock signal tends to become unstable when “0” is received.

If the supply of the power supply voltage or the clock signal becomes unstable, a malfunction occurs in the synchronous circuit. This will be described with reference to FIGS. FIG. 3 shows a shift register in which a first flip-flop (hereinafter referred to as FF) 301 and a second FF 302 are connected in series as an example of the synchronization circuit. The first FF 301 and the second FF 302 are the first data wiring at the rising edge of the first clock signal and the second clock signal supplied by the first clock wiring 303 and the second clock wiring 304, respectively. 305 and the voltage value of the second data line 306 are taken in, and the taken voltage value is output as the voltage value of the second data line 306 and the third data line 307.

FIG. 4 is a timing chart example of the shift register in FIG. FIG. 4A is a timing chart when the shift register in FIG. 3 performs an ideal operation. Here, timing charts of the first clock signal and the second clock signal supplied to the first clock wiring 303 and the second clock wiring 304 in FIG. 3 are respectively shown in FIG. 4A. A signal 401 and a second clock signal 402 are assumed. Note that there is no time difference between the first clock signal 401 and the second clock signal 402. A timing chart of voltage values of the first data wiring 305 in FIG. 3 is a first data signal 403 in FIG. In this case, timing charts of voltage values of the second data wiring 306 and the third data wiring 307 in FIG. 3 are the second data signal 404 and the third data signal 405 in FIG. 4A, respectively.

However, in FIG. 3, when there is a time difference between the first clock signal and the second clock signal supplied to the first clock wiring 303 and the second clock wiring 304, FIG. Unlike the timing chart in A), it malfunctions. FIG. 4B is a timing chart in the case of malfunction. A timing chart of the first clock signal and the second clock signal supplied to the first clock wiring 303 and the second clock wiring 304 in FIG. 3 is shown in the timing chart of the first clock signal 411 and the second clock signal in FIG. Two clock signals 412 are shown. Note that there is a time difference 416 between the first clock signal 411 and the second clock signal 412. That is, the second clock signal 412 is delayed with respect to the first clock signal 411. In addition, a timing chart of voltage values of the first data wiring 305 in FIG. 3 is a first data signal 413 in FIG. In this case, timing charts of voltage values of the second data wiring 306 and the third data wiring 307 in FIG. 3 are the second data signal 414 and the third data signal 415 in FIG. 4B, respectively.

Here, the timing chart of the voltage value of the second data wiring 306 in FIG. 3 is similar to the timing chart of FIG. 4A and the timing chart of FIG. However, the timing chart of the voltage value of the third data wiring 307 is different. This is because, due to the delay of the second clock signal 412 in FIG. 4B, the voltage value that should have been taken in at the next rising edge of the second clock signal 412 is taken in earlier by one cycle. Such behavior of FF is called data omission or racing. That is, in the synchronous circuit, if there is a time difference in the propagation of the clock signal, the circuit malfunctions.

For the propagation of the clock signal, it is possible in part to adjust the time difference at the time of design. However, when the power supply voltage fluctuates like a wireless chip, control is very difficult. In particular, the design becomes difficult as the circuit to be mounted becomes large. Note that fluctuations in power supply voltage and time differences in clock signal propagation are generally problematic not only in wireless chips but also in semiconductor devices having large-scale arithmetic circuits. In particular, it becomes a serious problem in a semiconductor device in which a large-scale circuit having an advanced arithmetic function is formed using a thin film transistor having a semiconductor.

The present invention has been made in view of the above problems, and provides a semiconductor device having a suitable configuration in a semiconductor device on which a large-scale circuit is mounted. A semiconductor device capable of stable operation even when there is a concern about fluctuations in power supply voltage. In particular, it is suitable for a semiconductor device on which a large-scale circuit formed using a semiconductor thin film transistor is mounted. Further, it is suitable for a wireless chip that generates a power supply voltage or a clock signal from a communication signal and uses the ASK method for data transmission / reception.

In the semiconductor device according to the present invention, a positive clock signal and a negative clock signal are generated, and thereby the FF is operated. Here, the positive clock signal and the negative clock signal have the same period, each of which includes a period of “1” and a period of “0” in one period, and has no period of “1” at the same time. Shall. Hereinafter, such a relationship between the positive clock signal and the negative clock signal is referred to as non-overlap, and one or both of the positive clock signal and the negative clock signal is referred to as non-overlapping clock. In addition, the large-scale arithmetic circuit can be stably operated by having a function of changing the cycle of the non-overlapping clock and the duty ratio according to the operating environment. The period “1” and the period “0” correspond to the HIGH state and LOW state of the clock signal, respectively.

With the above structure, a semiconductor device that can be stably operated even when a power supply voltage is unstable and a time difference occurs in propagation of a clock signal is provided. In addition, a large-scale arithmetic circuit can be mounted on the wireless chip, and a high-performance wireless chip is provided.

In particular, when a semiconductor device according to the present invention is manufactured using a thin film transistor having a semiconductor thin film formed over a substrate having an insulating surface such as a glass substrate, a quartz substrate, or a plastic substrate as an active layer, a large-area substrate is used in the manufacturing process. Can do. Therefore, the manufacturing cost of the semiconductor device in the present invention can be greatly reduced. Further, in particular, in the case of a plastic substrate, since it has mechanical flexibility in addition to the reduction in manufacturing cost, it is possible to give diversity to the handling after completion of the semiconductor device in the present invention.

One embodiment of the present invention includes an arithmetic circuit, a power management circuit, and a clock generation circuit, and the arithmetic circuit has a function of changing a period in which data is held by a first gate signal. Latch (hereinafter, exemplified using a level sensitive latch) and a second latch (hereinafter, exemplified using a level sensitive latch) having a function of changing a period in which data is held by the second gate signal. ), The power management circuit has a function of generating a control signal from the power supply voltage value supplied to the arithmetic circuit, and the clock generation circuit includes the first clock signal and the second clock. And the first gate signal and the second gate signal are based on the first clock signal generated in the clock generation circuit and the second clock signal. Generated Is a semiconductor device according to claim. The period in which both the first level-sensitive latch and the second level-sensitive latch hold data means that the clock signals in the LOW state are input to the first level-sensitive latch and the second level-sensitive latch, respectively. When it was done. Both the high level clock signals are input to the first level sensitive latch or the second level sensitive latch, respectively, so that data is held in the first level sensitive latch or the second level sensitive latch. May be.

One embodiment of the present invention includes an arithmetic circuit, a power management circuit, and a clock generation circuit, and the arithmetic circuit includes a first level-sensitive latch that uses the first clock signal as a gate signal, A second level sensitive latch that uses a clock signal as a gate signal, the power management circuit has a function of generating a control signal from a power supply voltage value supplied to the arithmetic circuit, and the clock generation circuit The semiconductor device is characterized in that a period in which both the first clock signal and the second clock signal are 0 is changed by a signal.

Another embodiment of the present invention includes an arithmetic circuit, a power management circuit, and a clock generation circuit. The arithmetic circuit includes a first level-sensitive latch that uses the first clock signal as a gate signal, A second level sensitive latch that uses a clock signal as a gate signal, the power management circuit has a function of generating a control signal from a current value supplied to the arithmetic circuit, and the clock generation circuit Thus, a period in which both the first clock signal and the second clock signal are 0 is changed.

Another embodiment of the present invention includes an arithmetic circuit, a power management circuit, and a clock generation circuit, and at least one of the arithmetic circuit, the power management circuit, and the clock generation circuit is formed over a substrate having an insulating surface. The arithmetic circuit has a first level sensitive latch using a first clock signal as a gate signal and a second level sensitive latch using a second clock signal as a gate signal. The power management circuit has a function of generating a control signal from a power supply voltage value supplied to the arithmetic circuit, and the clock generation circuit uses the control signal to generate a first clock signal and a second clock signal. The semiconductor device is characterized in that a period in which both clock signals are 0 is changed.

Another embodiment of the present invention includes an arithmetic circuit, a power management circuit, and a clock generation circuit, and at least one of the arithmetic circuit, the power management circuit, and the clock generation circuit is formed over a substrate having an insulating surface. The arithmetic circuit has a first level sensitive latch using a first clock signal as a gate signal and a second level sensitive latch using a second clock signal as a gate signal. The power management circuit has a function of generating a control signal from the current value supplied to the arithmetic circuit, and the clock generation circuit uses the control signal to generate a first clock signal and a second clock. The semiconductor device is characterized in that a period in which both signals are 0 is changed.

Another embodiment of the present invention includes an arithmetic circuit, a power management circuit, and a clock generation circuit. The arithmetic circuit, the power management circuit, and the clock generation circuit activate a semiconductor thin film formed over a substrate having an insulating surface. The arithmetic circuit has a first level sensitive latch that uses the first clock signal as a gate signal and a second level sensitive latch that uses the second clock signal as a gate signal. The power management circuit has a function of generating a control signal from a power supply voltage value supplied to the arithmetic circuit, and the clock generation circuit generates a first clock signal and a second clock signal according to the control signal. The semiconductor device is characterized in that the period in which both are 0 is changed.

Another embodiment of the present invention includes an arithmetic circuit, a power management circuit, and a clock generation circuit. The arithmetic circuit, the power management circuit, and the clock generation circuit activate a semiconductor thin film formed over a substrate having an insulating surface. The arithmetic circuit has a first level sensitive latch that uses the first clock signal as a gate signal and a second level sensitive latch that uses the second clock signal as a gate signal. The power management circuit has a function of generating a control signal from the current value supplied to the arithmetic circuit, and the clock generation circuit uses the control signal to generate a first clock signal and a second clock signal, The semiconductor device is characterized in that the period in which both are 0 is changed.

In the present invention, the first level sensitive latch can change the period in which data is held by the first gate signal, and the second level sensitive latch holds data by the second gate signal. You can change the period. The first gate signal and the second gate signal are generated based on the first clock signal and the second clock signal generated in the clock generation circuit, respectively. The period when the clock signal is 0 indicates the LOW state, and the period when the clock signal is 1 indicates the HIGH state.

As described above, by providing the power management circuit that generates the control signal from the current value supplied to the arithmetic circuit, the duty ratio of the clock signal supplied to the arithmetic circuit can be determined to an optimum value. For example, when the current value supplied to the arithmetic circuit is high, that is, when the current consumption is high, the power supply voltage becomes unstable, resulting in unstable circuit operation. Generate a signal.

In addition, by providing a clock generation circuit having a function of changing a period in which both the first clock signal and the second clock signal are 0 by the control signal, the duty ratio of the clock signal supplied to the arithmetic circuit Can be changed to an optimum value. For example, when a control signal for reducing the duty ratio of the clock signal is generated by the power management circuit, the duty of the clock signal is increased by increasing the period in which both the first clock signal and the second clock signal are 0. The ratio can be lowered. Therefore, the circuit operation can be stabilized.

In the present invention, any of a glass substrate, a quartz substrate, a plastic substrate, and an SOI substrate can be used as the substrate having an insulating surface.

In the present invention, the power management circuit may include a regulator and an operational amplifier circuit.

In the present invention, the power management circuit may include a regulator, an operational amplifier circuit, and an analog-digital conversion circuit.

In the present invention, the clock generation circuit may include means for changing the frequencies of the first clock signal and the second clock signal by a control signal.

In the present invention, the arithmetic circuit may include a CPU and a memory.

According to the present invention, a large-scale arithmetic circuit can be stably operated even when a power supply voltage fluctuates in a semiconductor device and a time difference occurs in propagation of a clock signal. Therefore, a highly reliable semiconductor device including a high-performance arithmetic circuit can be provided. In particular, by using a thin film transistor, a semiconductor device having a high-performance arithmetic circuit can be provided at low cost. In addition, a wireless chip having a high-performance arithmetic circuit can be provided at low cost in a wireless chip that supplies power supply voltage by electromagnetic induction from a communication signal and uses the ASK method for data transmission / reception.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.
(Embodiment 1)

As an embodiment of a semiconductor device according to the present invention, first, it will be shown using FIG. 5 and FIG. 6 that data can be prevented from being lost in a synchronous circuit by a non-overlapping clock. FIG. 5 shows a shift register as an example of a synchronization circuit constituting the semiconductor device of the present invention. FIG. 6 is a timing chart showing the operation of the shift register shown in FIG. In FIG. 5, first to fourth latches 501 to 504 are connected in series. The first to fourth latches 501 to 504 are latches that supply the first to fourth clock signals as gate signals to the first to fourth clock wirings 505 to 508, for example, level sensitive latches. In other words, when the first to fourth clock signals supplied to the first to fourth clock wirings 505 to 508 are “1”, the first to fourth latches 501 to 504 are respectively first to fourth. The voltage values of the data wirings 509 to 512 are fetched, and the fetched voltage values are output to the second to fifth data wirings 510 to 513.

Here, the shift register shown in FIG. 5 is equivalent to a circuit in which two FFs are connected in series when considered as follows. That is, the first latch 501 and the second latch 502 are used as the first FF, and the third latch 503 and the fourth latch 504 are used as the second FF. Here, a clock signal is supplied to the second clock wiring 506 and the fourth clock wiring 508, and an inverted signal of this clock signal is supplied to the first clock wiring 505 and the third clock wiring 507. In this way, an arbitrary synchronization circuit can be configured with a latch.

Next, a description will be given using the timing chart shown in FIG. FIG. 6A is a timing chart when the synchronization circuit in FIG. 5 performs an ideal operation. Here, timing charts of the first to fourth clock signals supplied to the first to fourth clock wirings 505 to 508 in FIG. 5 are respectively shown as the first to fourth clock signals 601 in FIG. ˜604. Here, it is assumed that there is no delay between the first clock signal 601 and the third clock signal 603. Further, it is assumed that there is no delay between the second clock signal 602 and the fourth clock signal 604. Further, a timing chart of voltage values of the first data wiring 509 in FIG. 5 is a first data signal 605 in FIG. In this case, the timing chart of the voltage values of the second to fifth data wirings 510 to 513 in FIG. 5 is the second to fifth data signals 606 to 609 in FIG.

In FIG. 5, there is a delay between the first clock signal and the third clock signal supplied to the first clock wiring 505 and the third clock wiring 507, and the second clock wiring 506 Consider a case where there is also a delay between the second clock signal and the fourth clock signal supplied to the fourth clock wiring 508. Here, timing charts of the first to fourth clock signals supplied to the first to fourth clock wirings 505 to 508 in FIG. 5 are respectively shown as the first to fourth clock signals 611 in FIG. ˜614. Here, the delay between the first clock signal 611 and the third clock signal 613 is a time difference 620, and the delay between the second clock signal 612 and the fourth clock signal 614 is a time difference 621. . Further, a timing chart of voltage values of the first data wiring 509 in FIG. 5 is a first data signal 615 in FIG. In this case, the timing chart of the voltage values of the second to fifth data wirings 510 to 513 in FIG. 5 is the second to fifth data signals 616 to 619 in FIG. The second data signal 616 and the third data signal 617 in FIG. 6B correspond to the second data signal 606 and the third data signal 607 in FIG. 6A, respectively. In addition, the fourth data signal 618 and the fifth data signal 619 in FIG. 6B are different from the second data signal 605 and the third data signal 606 in FIG. Although the value is output with a delay of the time difference 621, it is understood that no data omission occurs.

As described above, the synchronization circuit using the FF using the non-overlapping clock has a configuration in which data omission is unlikely to occur. The margin for the delay of the clock signal can be increased by changing the period of both the positive clock signal and the negative clock to “LOW”, that is, “0”. That is, if the operating frequency of the synchronizing circuit is lowered and the duty ratio of the clock signal is reduced, malfunction due to delay of the clock signal can be prevented. Note that the period during which both the positive clock signal and the negative clock are “HIGH”, that is, “1” can be lengthened, and the operating frequency of the synchronization circuit can be lowered. That is, the LOW or HIGH conditions of the clock signal can be set as appropriate.

FIG. 1 shows a structure of a wireless chip as an embodiment of a semiconductor device in the present invention. In FIG. 1, the wireless chip 101 includes an arithmetic circuit 102, a clock generation circuit 103, a power management circuit 104, a modulation / demodulation circuit 105, an antenna 106, a resonance circuit 107, and a power circuit 108. In FIG. 1, for simplification of explanation, the communication signal is shown as being divided into the reception signal 109 and the transmission signal 110, but in reality, both are integrated (overlapped) signals. Are simultaneously transmitted and received between the wireless chip 101 and the reader / writer. Hereinafter, the communication signal includes both a reception signal and a transmission signal. The reception signal 109 is received by the antenna 106 and the resonance circuit 107 and then demodulated by the modulation / demodulation circuit 105. The transmission signal 110 is modulated by the modulation / demodulation circuit 105 and then transmitted by the antenna 106.

In FIG. 1, when the wireless chip 101 is placed in a magnetic field formed by a communication signal, an induced electromotive force is generated by the antenna 106 and the resonance circuit 107. The induced electromotive force is held by an electric capacity in the power supply circuit 108, and the potential is stabilized by the electric capacity, and is supplied as a power supply voltage to each circuit of the wireless chip 101. The modulation / demodulation circuit 105 detects the fluctuation of the amplitude of the ASK reception signal 109 as “0” / “1” reception data. The modulation / demodulation circuit 105 is, for example, a low-pass filter. Further, the modulation / demodulation circuit 105 transmits the transmission data by changing the amplitude of the ASK transmission signal 110. For example, when the transmission data 112 is “0”, the resonance point of the resonance circuit 107 is changed, and the amplitude of the communication signal is changed.

The arithmetic circuit 102 may be configured based on the optimal arithmetic method selected according to the purpose. As a calculation method, a method of processing the operation in hardware, a method of processing in software, and a method of using both hardware and software can be considered. In the method of processing in hardware, an arithmetic circuit is configured by a dedicated circuit. In the method of processing in software, a CPU and a large-scale memory constitute an arithmetic circuit, and a program is executed by the CPU. In the method using both hardware and software, a dedicated circuit, a CPU, and a memory constitute an arithmetic circuit, a part of the arithmetic processing is performed by the dedicated circuit, and the remaining arithmetic processing program is executed by the CPU.

The function of changing the cycle of the non-overlapping clock and the duty ratio according to the operating environment, which is the main part of the semiconductor device in the present invention, is realized by the clock generation circuit 103 and the power management circuit 104.

The clock generation circuit 103 generates a non-overlap clock signal 111 to be supplied to the arithmetic circuit 102. The power management circuit 104 generates a control signal 114 to the clock generation circuit 103 from the power supply voltage supplied from the power supply circuit 108. In the clock generation circuit 103, the cycle and duty ratio of the non-overlapping clock signal 113 are controlled by the control signal 114 from the power management circuit 104.

The non-overlap clock signal 113 is generated from the reference clock signal. For example, when a reference clock having the same frequency as that of the received signal is used, the non-overlapping clock signal 113 can be generated by passing the inverter signal through a half-wave rectification using a diode. When a higher frequency reference clock is generated and the non-overlapping clock signal 113 is generated using the reference clock, a PLL (Phase Lock Loop) circuit, for example, is mounted.

Using this reference clock, an n (n ≧ 2) base counter is operated, and when the counter value is mpr to mpf (0 ≦ mpr ≦ mpf ≦ n−1), the positive clock signal is set to “1” and mnr to mnf. In the case of (0 ≦ mnr ≦ mnf ≦ n−1), a circuit that sets the negative clock signal to “1” is mounted, and n, mpr, mpf, mnr, and mnf are appropriately changed according to the value of the control signal 114 Thus, the cycle and the duty ratio of the clock signal can be changed. The above is the means for generating a non-overlapping clock signal from the control signal 114 generated by the power management circuit 104. Such a non-overlapping clock signal is input to a latch circuit such as a level sensitive latch.

The power management circuit 104 monitors the power supply voltage in the power supply circuit 108 and generates a control signal 114 for the clock generation circuit 103. For example, a regulator circuit is mounted on the power management circuit 104 and the reference voltage is generated from the power supply voltage supplied from the power supply circuit 108. The reference voltage is compared with the power supply voltage supplied from the power supply circuit 108, and the control signal 1142 is generated according to the result. The above is the means for generating the control signal 114 from the power supply voltage value supplied to the arithmetic circuit 102.

As the control signal 114 generated by the power management circuit 104, for example, “11” is set when the power supply voltage value is a desired value, and then “10” in the order of increasing power supply voltage value, that is, increasing delay of the clock signal. , “01” and “00”. At this time, for example, when the control signal 114 is “11”, the clock generation circuit 103 generates a clock signal with a frequency of 100 MHz and a duty ratio of 30%. When the control signal 114 is “10”, the frequency is 80 MHz and the duty ratio is 30. In the case of “01”, a clock signal having a frequency of 50 MHz and a duty ratio of 40% may be generated, and in the case of “00”, a clock signal having a frequency of 30 MHz and a duty ratio of 40% may be generated.

Note that what control signal 114 is generated by the power management circuit 104 depends on the configuration of the clock generation circuit 103 and the power management circuit 104. Also, what value the frequency of the clock signal and the duty ratio are specifically set depends on the circuit scale of the arithmetic circuit and the required specifications. Therefore, the practitioner can determine specific configurations of the clock generation circuit, the power management circuit, and the control signal.

In the semiconductor device of the present invention, when the current consumption is high, the circuit mounted on the semiconductor device generates heat, so that the delay of the clock signal increases. Therefore, the same problem as when the power supply voltage fluctuates occurs. That is, it is also effective to monitor the current consumption and change the non-overlapping clock period and the duty ratio.

The power management circuit 104 can monitor the current consumption in the arithmetic circuit 102 and generate the control signal 114 of the clock generation circuit 103. For example, a regulator circuit is mounted, and a reference voltage is generated from a power supply voltage supplied from the power supply circuit 108. This reference voltage is compared with a voltage generated in a reference resistor inserted between the power supply circuit 108 and the arithmetic circuit 102, that is, a voltage proportional to the consumption current in the arithmetic circuit 102, and a control signal 114 is generated according to the result. To do. The above is the means for generating the control signal 114 from the current value supplied to the arithmetic circuit 102.

As the control signal 114 generated by the power management circuit 104, for example, “00” is set when the current value is a desired value, and “01” and “10” are set in the order of decreasing current value, that is, increasing delay of the clock signal. "," 11 ". At this time, for example, when the control signal 114 is “00”, the clock generation circuit 103 generates a clock signal with a frequency of 100 MHz and a duty ratio of 30%. When the control signal 114 is “01”, the frequency is 80 MHz and the duty ratio is 30. %, A clock signal having a frequency of 50 MHz and a duty ratio of 40% is generated, and when “11”, a clock signal having a frequency of 30 MHz and a duty ratio of 40% is generated.

Note that what control signal 114 is generated by the power management circuit 104 depends on the configuration of the clock generation circuit 103 and the power management circuit 104. Also, what value the frequency of the clock signal and the duty ratio are specifically set depends on the circuit scale of the arithmetic circuit and the required specifications. Therefore, the practitioner can determine the specific configuration of the clock generation circuit and the power management circuit, the specific value of the control signal, and the like.

With the above structure, the arithmetic circuit can be stably operated even when the power supply voltage fluctuates in the semiconductor device and a time difference occurs in the propagation of the clock signal. Therefore, a highly reliable semiconductor device including a high-performance arithmetic circuit can be provided. In addition, in a wireless chip that supplies power supply voltage by induced electromotive force from a communication signal and transmits / receives communication data by the ASK method, the synchronization circuit is also provided when the communication signal is unstable or the power supply voltage becomes unstable. It can be operated stably. Therefore, a wireless chip with high performance and high reliability can be provided with a structure suitable for a wireless chip mounted with a large-scale arithmetic circuit.

In particular, when a semiconductor device according to the present invention is manufactured using a thin film transistor having a semiconductor thin film formed over a substrate having an insulating surface such as a glass substrate, a quartz substrate, or a plastic substrate as an active layer, a large-area substrate is used in the manufacturing process. Can do. Therefore, the manufacturing cost of the semiconductor device in the present invention can be greatly reduced. Further, in particular, in the case of a plastic substrate, since it has mechanical flexibility in addition to the reduction in manufacturing cost, it is possible to give diversity to the handling after completion of the semiconductor device in the present invention.

Embodiments of the present invention will be described below with reference to the drawings.

In this example, as an example of the power management circuit in the structure shown in the embodiment mode, a method for controlling a clock signal by monitoring fluctuations in power supply voltage will be described with reference to FIGS. FIG. 7 is a circuit diagram of the power management circuit in the present embodiment. FIG. 8 is a flowchart showing the operation of the power management circuit in this embodiment.

First, a circuit diagram of the power management circuit in this embodiment will be described with reference to FIG. In FIG. 7, the output terminal of the first regulator 701 is connected to the resistor 707, the output terminal of the second regulator 702 is connected to the resistor 709, and the output terminal of the nth regulator 703 is connected to the resistor 711. Has been. The input terminal of the first operational amplifier 719 is connected to the resistors 707, 708, 713, and 714, and the output terminal is connected to the resistor 713 and the first digital buffer 722. The input terminal of the second operational amplifier 720 is connected to the resistors 709, 710, 715, and 716, and the output terminal is connected to the resistor 715 and the second digital buffer 723. An input terminal of the nth operational amplifier 721 is connected to the resistors 711, 712, 717, and 718, and an output terminal is connected to the resistor 717 and the nth digital buffer 724.

In FIG. 7, the power supply voltage supplied from the power supply circuit 108 in FIG. 1 is supplied from the wiring 725 to the first to nth regulators 701 to 703, and to the first to nth reference potential wirings 704 to 706. First to nth reference potentials are output. The power supply voltage and the first to nth reference potentials are input to the first to nth operational amplifiers 719 to 721 via the resistors 707 to 718 as shown in FIG. The resistors 707 to 718 are necessary for operating the first to nth operational amplifiers 719 to 721 as an operation amplifier circuit. Outputs of the first to nth operational amplifiers 719 to 721 generate digital signals by the first to nth digital buffers 722 to 724, and are output to the wiring 726. This is the control signal 114 input from the power management circuit 104 to the clock generation circuit 103 in FIG.

Next, the operation of the power management circuit in this embodiment will be described with reference to FIG. Here, a case where n = 4 in the power management circuit in FIG. 7 will be described. In FIG. 8, a timing chart of the power supply voltage supplied from the power supply circuit 108 in FIG. Timing charts of the first to fourth reference potentials generated by the first to fourth regulators are denoted as 802 to 805. At this time, output timing charts of the first to fourth digital buffers are 806 to 809. When the power supply voltage is lower than the first to fourth reference potentials, the outputs of the first to fourth digital buffers are “0”.

With the configuration of the power management circuit described above, the state of the power supply voltage supplied by the power supply circuit 108 can be detected. That is, when the output of the first to fourth digital buffers, that is, the control signal 114 is “1”, “1”, “1”, “1”, “0”, “1”, “1”, “1” "0", "0", "1", "1", "0", "0", "0", "1", "0", "0", "0" In the case of “,” “0”, it can be detected that the power supply voltage is low in order. Therefore, the frequency of the non-overlapping clock can be changed in the clock generation circuit 103 using the control signal 114. Alternatively, the duty ratio may be changed in the clock generation circuit 103 using the control signal 114. Specifically, the frequency of the non-overlap clock may be lowered as the detected power supply voltage is lower. Alternatively, the duty ratio may be lowered as the detected power supply voltage is lower.

Depending on the state of the power supply voltage detected by the power management circuit 104, the specific value of the non-overlapping clock frequency or duty ratio set in the clock generation circuit 103 depends on the semiconductor device. The practitioner can make a decision based on the circuit scale, power consumption, computing performance, and the like of the installed computing circuit.

With the above structure, the arithmetic circuit can be stably operated even when the power supply voltage fluctuates in the semiconductor device and a time difference occurs in the propagation of the clock signal. Therefore, a highly reliable semiconductor device including a high-performance arithmetic circuit can be provided. This is particularly effective when the semiconductor device is formed of a thin film transistor. In addition, in a wireless chip that supplies power supply voltage by induced electromotive force from a communication signal and transmits / receives communication data by the ASK method, the synchronization circuit is also provided when the communication signal is unstable or the power supply voltage becomes unstable. It can be operated stably. Therefore, a wireless chip with high performance and high reliability can be provided with a structure suitable for a wireless chip mounted with a large-scale arithmetic circuit.

In this embodiment, as an example of the power management circuit in the configuration shown in the embodiment mode, an example different from the first embodiment in the method of controlling the clock signal by monitoring the fluctuation of the power supply voltage is shown in FIGS. 10 will be used for explanation. FIG. 9 is a circuit diagram of a power management circuit in the present embodiment. FIG. 10 is a flowchart showing the operation of the power management circuit in this embodiment.

First, a circuit diagram of the power management circuit in this embodiment will be described with reference to FIG. In FIG. 9, the output terminal of the first regulator 901 is connected to a resistor 903. The input terminal of the first operational amplifier 907 is connected to the resistors 903, 904, 905, and 906, and the output terminal is connected to the resistor 905 and the ADC (analog-digital converter) 908.

In FIG. 9, the power supply voltage supplied from the power supply circuit 108 in FIG. 1 is supplied to the regulator 901 from the wiring 909, and the reference potential is output to the reference potential wiring 902. The power supply voltage and the reference potential are input to the operational amplifier 907 from the wiring 909 and the reference potential wiring 902 through the resistors 903 to 906 as shown in FIG. The resistors 903 to 906 are necessary for operating the operational amplifier 907 as an operation amplifier circuit. The output voltage of the operational amplifier 907 generates a digital signal by the ADC 908 and is output to the wiring 910. This is the control signal 114 from the power management circuit 104 to the clock generation circuit 103 in FIG.

Next, the operation of the power management circuit in this embodiment will be described with reference to FIG. Here, a case will be described in which the power supply management circuit in FIG. 9 detects the power supply voltage at four levels. In FIG. 10, a timing chart of power supply voltage supplied from the power supply circuit 108 in FIG. A timing chart of the reference potential generated by the regulator 901 in FIG. At this time, the timing chart of the control signal 114 is 1003. The control signal 114 becomes “00”, “01”, “10”, and “11” in ascending order of the power supply voltage, that is, the difference between the reference potential and the power supply voltage is small.

With the configuration of the power management circuit described above, the state of the power supply voltage supplied by the power supply circuit 108 can be detected. That is, when the control signal 114 is “11”, “10”, “01”, and “00”, it can be detected that the power supply voltage is low. Therefore, the frequency of the non-overlapping clock may be changed in the clock generation circuit 103 using the control signal 114. Alternatively, the duty ratio may be changed in the clock generation circuit 103 using the control signal 114. Specifically, the frequency of the non-overlap clock may be lowered as the detected power supply voltage is lower. Alternatively, the duty ratio may be lowered as the detected power supply voltage is lower.

Depending on the state of the power supply voltage detected by the power management circuit 104, the specific value of the non-overlapping clock frequency or duty ratio set in the clock generation circuit 103 depends on the semiconductor device. The practitioner can make a decision based on the circuit scale, power consumption, computing performance, and the like of the installed computing circuit.

With the above structure, the arithmetic circuit can be stably operated even when the power supply voltage fluctuates in the semiconductor device and a time difference occurs in the propagation of the clock signal. Therefore, a highly reliable semiconductor device including a high-performance arithmetic circuit can be provided. This is particularly effective when the semiconductor device is formed of a thin film transistor. In addition, in a wireless chip that supplies power supply voltage by induced electromotive force from a communication signal and transmits / receives communication data by the ASK method, the synchronization circuit is also provided when the communication signal is unstable or the power supply voltage becomes unstable. It can be operated stably. Therefore, a wireless chip with high performance and high reliability can be provided with a structure suitable for a wireless chip mounted with a large-scale arithmetic circuit.

In this example, as an example of the power management circuit in the structure described in Embodiment Mode, a method for monitoring current consumption in an arithmetic circuit and controlling a clock signal will be described with reference to FIGS. FIG. 22 is a circuit diagram of the power management circuit. FIG. 23 is a flowchart showing the operation of the power management circuit.

First, a circuit diagram of the power management circuit in this embodiment will be described with reference to FIG. In FIG. 22, the input terminal of the first operational amplifier 2202 is connected to resistors 2203, 2204, 2205, and 2206, and the output terminal is connected to resistors 2205, 2213, and 2215. The output terminal of the first regulator 2208 is connected to the resistor 2212, and the output terminal of the second regulator 2209 is connected to the resistor 2214. The input terminal of the second operational amplifier 2220 is connected to the resistors 2212, 2213, 2216, and 2217, and the output terminal is connected to the resistor 2216 and the first digital buffer 2222. The input terminal of the (n + 1) th operational amplifier 2221 is connected to the resistors 2214, 2215, 2218, and 2219, and the output terminal is connected to the resistor 2218 and the second digital buffer 2223.

22, the power supply voltage supplied from the power supply circuit 108 in FIG. 1 is supplied from the wiring 2224 to the arithmetic circuit 102 in FIG. 1 via the monitor resistor 2201. A voltage proportional to the current consumption in the arithmetic circuit 102 is generated between both ends of the monitor resistor 2201. When this voltage is used as the input voltage of the amplifier circuit having the first operational amplifier 2202 and the first to fourth resistors 2203 to 2206, the monitor voltage is output to the monitor voltage wiring 2207.

The power supply voltage is supplied to the first to nth regulators 2208 to 2209, and the first to nth reference potentials are output to the first to nth reference potential wirings 2210 to 2211. The monitor voltage and the first to nth reference potentials are input to the second to (n + 1) th operational amplifiers 2220 to 2221 through resistors 2212 to 2219 as shown in FIG. The resistors 2212 to 2219 are necessary for operating the second to (n + 1) th operational amplifiers 2220 to 2221 as an operation amplifier circuit. Outputs of the second to (n + 1) th operational amplifiers 2220 to 2221 generate digital signals by the first to nth digital buffers 2222 to 2223, and are output to the wiring 2225. This is the control signal 114 from the power management circuit 104 to the clock generation circuit 103 in FIG.

Next, the operation of the power management circuit in this embodiment will be described with reference to FIG. Here, a case where n = 4 in the power management circuit in FIG. 22 will be described. In FIG. 23, 2301 is a timing chart of the current flowing through the monitor resistor 2201 in FIG. The monitor voltage timing chart is 2302. Timing charts of the first to fourth reference potentials generated by the first to fourth regulators are denoted by 2303 to 2306. At this time, output timing charts of the first to fourth digital buffers are 2307 to 2310. When the monitor voltage wiring 2207 is lower than the first to fourth reference potentials, the outputs of the first to fourth digital buffers are “0”.

With the configuration of the power management circuit described above, the current consumption state in the arithmetic circuit 102 can be detected. That is, when the output of the first to fourth digital buffers, that is, the control signal 114 is “0”, “0”, “0”, “0”, “0”, “0”, “0”, “1” "", "0", "1", "1", "0", "1", "1", "1", "1", "1", "1" In the case of “,” “1”, it can be detected that the current consumption is low in order. Therefore, the frequency of the non-overlapping clock may be changed in the clock generation circuit 103 using the control signal 114. Alternatively, the duty ratio may be changed. Specifically, the frequency of the non-overlap clock may be lowered as the detected current consumption is higher.

Depending on the current consumption state detected by the power management circuit 104, the specific value of the non-overlapping clock frequency or duty ratio set in the clock generation circuit 103 depends on the semiconductor device. The practitioner can make a decision based on the circuit scale, power consumption, computing performance, and the like of the installed computing circuit.

With the above structure, the arithmetic circuit can be stably operated even when the power supply voltage fluctuates in the semiconductor device and a time difference occurs in the propagation of the clock signal. Therefore, a highly reliable semiconductor device including a high-performance arithmetic circuit can be provided. This is particularly effective when the semiconductor device is formed of a thin film transistor. In addition, in a wireless chip that supplies power supply voltage by induced electromotive force from a communication signal and transmits / receives communication data by the ASK method, the synchronization circuit is also provided when the communication signal is unstable or the power supply voltage becomes unstable. It can be operated stably. Therefore, a wireless chip with high performance and high reliability can be provided with a structure suitable for a wireless chip mounted with a large-scale arithmetic circuit.

In this embodiment, as an example of the power management circuit in the configuration shown in the embodiment mode, an example different from the third embodiment in the method of controlling the clock signal by monitoring the fluctuation of current consumption is shown in FIGS. 25 will be described. FIG. 24 is a circuit diagram of the power management circuit in the present embodiment. FIG. 25 is a flowchart showing the operation of the power management circuit in this embodiment.

First, a circuit diagram of the power management circuit in this embodiment will be described with reference to FIG. In FIG. 24, the input terminal of the first operational amplifier 2402 is connected to resistors 2403, 2404, 2405, and 2406, and the output terminal is connected to a resistor 2405 and a regulator 2408. The output terminal of the regulator 2408 is connected to the resistor 2410. The input terminal of the second operational amplifier 2414 is connected to resistors 2410, 2411, 2412, and 2413, and the output terminal is connected to an ADC (analog-digital converter) 2415.

24, the power supply voltage supplied from the power supply circuit 108 in FIG. 1 is supplied from the wiring 2416 to the arithmetic circuit 102 in FIG. A voltage proportional to the current consumption in the arithmetic circuit 102 is generated between both ends of the monitor resistor 2401. When this voltage is used as an input voltage of an amplifier circuit composed of the first operational amplifier 2402 and the first to fourth resistors 2403 to 2406, the monitor voltage is output to the monitor voltage wiring 2407.

The power supply voltage is supplied to the regulator 2408 through the wiring 2416, and the reference potential is output to the reference potential wiring 2409. The power supply voltage and the reference potential are input to the second operational amplifier 2414 through the resistors 2410 to 2413 as shown in FIG. Note that the resistors 2410 to 2413 are necessary for operating the second operational amplifier 2414 as an operational amplifier circuit. The output of the second operational amplifier 2414 generates a digital signal by the ADC 2415 and is output to the wiring 2417. This is the control signal 114 from the power management circuit 104 to the clock generation circuit 103 in FIG.

Next, the operation of the power management circuit in this embodiment will be described with reference to FIG. Here, a case will be described in which the power supply management circuit in FIG. 24 detects the power supply voltage at four levels. In FIG. 25, 2501 is a timing chart of the current flowing through the monitor resistor 2401 in FIG. The monitor voltage timing chart is 2502. A timing chart of the reference potential generated by the regulator 2408 in FIG. At this time, the timing chart of the control signal 114 is 2504. The control signal 114 becomes “00”, “01”, “10”, and “11” in order of decreasing monitor voltage, that is, current consumption.

With the configuration of the power management circuit described above, the power consumption state in the arithmetic circuit 102 can be detected. That is, when the control signal 114 is “11”, “10”, “01”, “00”, it can be detected that the consumption current is higher in the order. Therefore, the frequency of the non-overlapping clock may be changed in the clock generation circuit 103 using the control signal 114. Alternatively, the duty ratio may be changed. Specifically, the higher the detected current consumption, the lower the frequency of the non-overlap clock or the duty ratio.

Depending on the current consumption state detected by the power management circuit 104, the specific value of the non-overlapping clock frequency or duty ratio set in the clock generation circuit 103 depends on the semiconductor device. The practitioner can make a decision based on the circuit scale, power consumption, computing performance, and the like of the installed computing circuit.

With the above structure, the arithmetic circuit can be stably operated even when the power supply voltage fluctuates in the semiconductor device and a time difference occurs in the propagation of the clock signal. Therefore, a highly reliable semiconductor device including a high-performance arithmetic circuit can be provided. This is particularly effective when the semiconductor device is formed of a thin film transistor. In addition, in a wireless chip that supplies power supply voltage by induced electromotive force from a communication signal and transmits / receives communication data by the ASK method, the synchronization circuit is also provided when the communication signal is unstable or the power supply voltage becomes unstable. It can be operated stably. Therefore, a wireless chip with high performance and high reliability can be provided with a structure suitable for a wireless chip mounted with a large-scale arithmetic circuit.

In this embodiment, the case where a semiconductor device of the present invention is formed using a thin film transistor (TFT) will be described with reference to FIGS.

FIG. 11A is a cross-sectional view of the TFT portion 1101 and the memory portion 1102 formed over the insulating substrate 1110. The TFT portion 1101 is preferably used for a transistor in an arithmetic circuit, for example. The memory unit 1102 is preferably used for a memory element of a nonvolatile memory, for example. As the insulating substrate 1110, a glass substrate, a quartz substrate, a substrate made of silicon, a metal substrate, a plastic substrate, or the like can be used.

In the case where a glass substrate is used, a thinned and polished surface opposite to the side on which the TFT or the like is formed can be used. Such a thin glass substrate can achieve a reduction in weight and thickness of the apparatus.

A base film 1111 is provided over the insulating substrate 1110. Thin film transistors 1120 and 1121 are provided in the TFT portion 1101 through a base film 1111, and thin film transistors 1122 are provided in the memory portion 1102 through a base film 1111. Each thin film transistor includes a semiconductor film 1112 patterned into an island shape (processed into a predetermined shape), a gate electrode 1114 provided via a gate insulating film, and an insulator (so-called sidewall) provided on a side surface of the gate electrode. 1113. The semiconductor film 1112 is formed to have a thickness of 0.2 μm or less, typically 40 nm to 170 nm, preferably 50 nm to 150 nm. Further, an insulating film 1116 covering the sidewall 1113 and the semiconductor film 1112, and an electrode 1115 connected to the impurity region formed in the semiconductor film 1112 are provided. Note that since the electrode 1115 is connected to the impurity region, a contact hole can be formed in the gate insulating film and the insulating film 1116, a conductive film can be formed in the contact hole, and the conductive film can be patterned.

In the thin film transistor included in the wireless chip of the present invention, an insulating film such as a gate insulating film can be manufactured using high-density plasma treatment. The high density plasma treatment means that the plasma density is 1 × 10 ¹¹ cm ⁻³ or more, preferably 1 × 10 ¹¹ cm ⁻³ to 9 × 10 ¹⁵ cm ⁻³ , and microwaves (for example, frequency 2.45 GHz) This is plasma processing using high frequency. When plasma is generated under such conditions, the low electron temperature is changed from 0.2 eV to 2 eV. As described above, high-density plasma characterized by low electron temperature has low kinetic energy of active species, and thus can form a film with less plasma damage and fewer defects. In the case where a formation object and a gate insulating film are to be formed, a substrate on which a patterned semiconductor film is formed is placed in a film formation chamber capable of such plasma treatment. Then, a film forming process is performed with a distance between an electrode for plasma generation, a so-called antenna, and an object to be formed being 20 mm to 80 mm, preferably 20 mm to 60 mm. Such a high-density plasma treatment can realize a low-temperature process (substrate temperature of 400 ° C. or lower). Therefore, a plastic having low heat resistance can be formed on the substrate.

Such an insulating film can be formed in a nitrogen atmosphere or an oxygen atmosphere. The nitrogen atmosphere is typically a mixed atmosphere of nitrogen and a rare gas, or a mixed atmosphere of nitrogen, hydrogen, and a rare gas. As the rare gas, at least one of helium, neon, argon, krypton, and xenon can be used. The oxygen atmosphere is typically a mixed atmosphere of oxygen and a rare gas, a mixed atmosphere of oxygen, hydrogen, and a rare gas, or a mixed atmosphere of dinitrogen monoxide and a rare gas. As the rare gas, at least one of helium, neon, argon, krypton, and xenon can be used.

The insulating film formed in this way has little damage to other films and becomes dense. In addition, an insulating film formed by high-density plasma treatment can improve an interface state in contact with the insulating film. For example, when the gate insulating film is formed using high-density plasma treatment, the interface state with the semiconductor film can be improved. As a result, the electrical characteristics of the thin film transistor can be improved.

Although the case where high-density plasma treatment is used for manufacturing the insulating film has been described, the semiconductor film may be subjected to high-density plasma treatment. The semiconductor film surface can be modified by high-density plasma treatment. As a result, the interface state can be improved and thus the electrical characteristics of the thin film transistor can be improved.

In order to improve flatness, insulating films 1117 and 1118 are preferably provided. At this time, the insulating film 1117 is preferably formed from an organic material, and the insulating film 1118 is preferably formed from an inorganic material. In the case where the insulating films 1117 and 1118 are provided, the electrode 1115 can be formed so as to be connected to the impurity regions through the contact holes in the insulating films 1117 and 1118.

Further, an insulating film 1125 is provided, and a lower electrode 1127 is formed so as to be connected to the electrode 1115. An insulating film 1128 is formed which covers an end portion of the lower electrode 1127 and has an opening so that the lower electrode 1127 is exposed. A memory material layer 1129 is formed in the opening, and an upper electrode 1130 is formed. In this manner, the memory element 1123 having the lower electrode 1127, the memory material layer 1129, and the upper electrode 1130 is formed. The memory material layer 1129 can be formed of an organic material or an inorganic material. The lower electrode 1127 or the upper electrode 1130 can be formed of a conductive material. For example, it can be formed of a film made of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), or silicon (Si), or an alloy film using these elements. Alternatively, a light-transmitting material such as indium tin oxide (ITO), indium tin oxide containing silicon oxide, or indium oxide containing 2 to 20% zinc oxide can be used.

In addition, an insulating film 1131 is preferably formed in order to improve planarity and prevent an impurity element from entering.

For the insulating film described in this embodiment, an inorganic material or an organic material can be used. As the inorganic material, silicon oxide or silicon nitride can be used. As the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane, or polysilazane can be used. Note that siloxane has a skeleton structure of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Polysilazane is formed using a polymer material having a bond of silicon (Si) and nitrogen (N) as a starting material.

FIG. 11B is a cross-sectional view of a memory in which a memory material layer is formed in a contact hole 1151 of an electrode 1115 unlike FIG. 11A. Similarly to FIG. 11A, the memory element 1123 can be formed by using the electrode 1115 as the lower electrode and forming the memory material layer 1129 and the upper electrode 1130 over the electrode 1115. After that, an insulating film 1131 is formed. The other structures are the same as those in FIG.

When the memory element is formed in the contact hole 1151 in this manner, the memory element can be reduced in size. In addition, since a memory electrode is unnecessary, a manufacturing process can be reduced, and a wireless chip mounted with a memory can be provided at low cost.

As described above, a semiconductor device is composed of a thin film transistor using a semiconductor thin film formed on a substrate having an insulating surface such as a glass substrate, a quartz substrate, or a plastic substrate as an active layer, thereby achieving high performance and low power consumption. This semiconductor device can be provided at a lower weight and at a lower cost.

This embodiment can be implemented by being freely combined with the embodiment mode and the above embodiment.

In this embodiment, a method for manufacturing a semiconductor device, which is different from that in the above embodiment, will be described.

As in the above embodiment, an insulating substrate is prepared and a release layer is formed. The release layer can be formed over the entire surface of the insulating substrate or selectively. For the release layer, an element selected from W, Ti, Ta, Mo, Nb, Nd, Ni, Co, Zr, Zn, Ru, Rh, Pd, Os, Ir, and Si or an alloy containing the element as a main component It can be formed from materials or compound materials. For the separation layer, a single-layer structure of the above elements or a stacked structure of the above elements can be used. Such a release layer can be formed by a CVD method, a sputtering method, an electron beam, or the like. In this embodiment, W is formed by a CVD method. At this time, the treatment may be performed with plasma using O ₂ , N _2, or N ₂ O. Then, the peeling process which is a subsequent process can be easily performed.

After that, as in the above embodiment, a base film and a semiconductor film are formed over the separation layer. When heat treatment is performed on the semiconductor film, the separation layer can also be heated. In the heat treatment, when an amorphous semiconductor film is formed by a CVD method, the semiconductor film contains a large amount of hydrogen; therefore, heat treatment for removing the hydrogen or crystallization of the amorphous semiconductor film is performed. There is a heat treatment for. By the heat treatment for removing hydrogen, peeling of the semiconductor film can be prevented.

After that, as in the above embodiment, a thin film transistor is formed using a semiconductor film.
A circuit included in the semiconductor device is formed by electrically connecting the plurality of thin film transistors. Such circuits include wireless communication circuits such as a power supply circuit, system reset circuit, demodulation circuit, and modulation circuit, and logic circuits such as a CPU, ROM, RAM, and controller.

Thereafter, the insulating substrate is physically and chemically separated, and a thin film transistor or the like is transferred to a flexible substrate such as a plastic substrate. At this time, the insulating substrate can be peeled by changing the state of the peeling layer. For example, an opening is provided so that a part of the release layer is exposed, and the exposed release layer is irradiated with laser. By irradiating the peeling layer with a laser, a trigger for peeling can be given. Thereafter, the insulating substrate and the thin film transistor or the like can be physically peeled off, or the thin film transistor or the like may be naturally peeled off from the insulating substrate without applying a special force due to the stress of the film.

A semiconductor device in which a thin film transistor or the like is transferred to a flexible substrate can be formed. Such a semiconductor device has the added value of being lightweight, thin, and rich in flexibility.

This embodiment can be implemented by being freely combined with the embodiment mode and the above embodiment.

In this embodiment, a layout of a thin film transistor which forms part of a circuit in a semiconductor device of the present invention will be described with reference to FIGS.

A semiconductor layer corresponding to the semiconductor film 1112 described in Embodiment 3 is provided on the entire surface or part of a substrate having an insulating surface (a region having a larger area than that determined as a semiconductor region of a transistor) with a base film or the like interposed therebetween. Formed. Then, a mask pattern is formed on the semiconductor layer by photolithography. By etching the semiconductor layer using the mask pattern, an island-shaped semiconductor pattern 1201 having a specific shape including a source region, a drain region, and a channel formation region of the thin film transistor illustrated in FIG. 12 can be formed.

The shape of the patterned semiconductor layer is determined in consideration of the required circuit characteristics and appropriate layout based on the characteristics of the thin film transistor.

In the thin film transistor included in the circuit of the wireless chip of the present invention, the photomask for forming the semiconductor layer has a pattern. This photomask pattern has corners, and one side (of a right triangle) is rounded by removing the corners to a size of 10 μm or less. The shape of this mask pattern can be transferred as a pattern shape of a semiconductor layer as shown in FIG. In addition, when transferring to the semiconductor layer, the corner of the semiconductor pattern 1201 may be transferred so as to be more rounded than the corner of the photomask pattern. In other words, the corners of the semiconductor film pattern may be provided with roundness that is smoother than the photomask pattern. In FIG. 12, a gate electrode 1114, a gate wiring 1301, an electrode 1115, and the like which are formed later are indicated by dotted lines.

Next, a gate insulating film is formed over the semiconductor layer that is patterned so that the corners are rounded. Then, as shown in Embodiment 3, the gate electrode 1114 and the gate wiring 1301 are formed so as to partially overlap the semiconductor layer. The gate electrode or the gate wiring can be formed by a photolithography technique by forming a metal layer or a semiconductor layer.

The photomask for forming the gate electrode or the gate wiring has a pattern. This photomask pattern has corners, and one side of the right triangle formed at the corners is 10 μm or less, or 1/2 or less of the line width of the wiring, and 1/5 or more of the line width. The corner is deleted. The shape of this mask pattern can be transferred as a pattern shape of a gate electrode or a gate wiring as shown in FIG. Further, when transferring to the gate electrode or the gate wiring, the corner of the gate electrode or the gate wiring may be further rounded. In other words, the corners of the gate electrode or the gate wiring may be provided with roundness with a smoother pattern shape than the photomask pattern.

In the corner portion of the gate electrode or the gate wiring formed using such a photomask, the outer periphery of the gate electrode or the gate wiring forms a curve at the corner portion viewed from the upper surface. Also, the inner periphery of the corner portion is formed so that the inner periphery is rounded along the outer periphery of the corner portion. Note that in FIG. 13, electrodes 1115 to be formed later are indicated by dotted lines.

Such a gate electrode or gate wiring is bent into a rectangle due to layout restrictions. Therefore, a rounded corner portion of the gate electrode or gate wiring is provided with a convex portion (outer side) and a concave portion (inner side). This rounded convex portion can suppress generation of fine powder due to abnormal discharge during dry etching by plasma. Also, in the rounded recess, even if there is fine powder that can be produced during washing, it can be washed away that it tends to collect at the corner. As a result, the yield can be greatly improved.

Next, an insulating layer or the like corresponding to the insulating films 1116, 1117, and 1118 is formed over the gate electrode or the gate wiring as described in the third embodiment. Of course, in the present invention, the insulating film may be a single layer.

Over the insulating layer, an opening is formed in a predetermined position in the insulating film, and a wiring corresponding to the electrode 1115 is formed in the opening. This opening is provided in order to establish electrical connection between the semiconductor layer or gate wiring layer located in the lower layer and the wiring layer. The wiring is formed with a mask pattern by a photolithography technique and formed into a predetermined pattern by etching.

A certain element can be connected by wiring. This wiring does not connect a specific element with a straight line, but bends into a rectangle (hereinafter referred to as a bent portion) due to layout restrictions. In addition, the wiring width of the wiring may change in the opening and other regions. For example, in the opening, when the opening is equal to or larger than the wiring width, the wiring width is changed so as to widen at that portion. Further, since the wiring also serves as one electrode of the capacitor portion in the circuit layout, the wiring width may be increased.

In this case, in the bent portion of the photomask pattern, one side of the right-angled triangle to be formed is 10 μm or less, or half or less of the line width of the wiring, and a corner portion having a size of 1/5 or more of the line width. Is deleted. Then, as shown in FIG. 14, the wiring pattern is similarly rounded. The corner portion of the wiring is ½ or less of the line width, and the bent portion can be rounded to 1/5 or more. That is, the outer periphery of the wiring layer at the corner portion viewed from the upper surface forms a curve. Also, the inner periphery of the corner portion is formed so that the inner periphery is rounded along the outer periphery of the corner portion. In such rounded wiring, the convex part in the bent part suppresses the generation of fine powder due to abnormal discharge during dry etching by plasma, and in the concave part, even if it is fine powder made when cleaning, As a result of washing away the fact that it tends to gather at the corner, it has the effect that the yield improvement can be expected greatly. By rounding the corners of the wiring, it can be expected to be electrically conducted.

In the circuit having the layout shown in FIG. 14, the bend and the corner of the portion where the wiring width changes are smoothed and rounded to suppress the generation of fine powder due to abnormal discharge during dry etching by plasma, Even if it is a fine powder that has been produced at the time of washing, it has the effect that a significant improvement in yield can be expected as a result of washing away that it tends to collect at the corner. That is, the problem of dust and fine powder in the manufacturing process can be solved. In addition, it can be expected that the wiring is electrically conductive by adopting a configuration in which the corners of the wiring are rounded. In particular, it is very advantageous to be able to wash away dust in wiring such as a drive circuit section provided with a large number of parallel wirings.

In the present embodiment, the three-layer layout of the semiconductor layer, the gate wiring, and the wiring has been described as having a rounded corner or bend, but the present invention is not limited to this. That is, in any one layer, it is only necessary to round the corners or the bent portions to solve problems such as dust and fine powder in the manufacturing process.

By configuring the semiconductor device using the layout as described above, a semiconductor device with high performance and low power consumption can be provided at a lower weight and at a lower cost.

Note that this embodiment can be implemented by being freely combined with the embodiment mode and the above embodiment.

In this embodiment, an example of forming a static RAM (SRAM) as one of the elements constituting the semiconductor device of the present invention will be described with reference to FIGS.

The semiconductor layers 1510 and 1511 illustrated in FIG. 15A are preferably formed using silicon or a crystalline semiconductor containing silicon as a component. For example, polycrystalline silicon or single crystal silicon obtained by crystallizing a silicon film by laser annealing or the like is applied. In addition, a metal oxide semiconductor, amorphous silicon, or an organic semiconductor that exhibits semiconductor characteristics can be used.

In any case, the semiconductor layer to be formed first is formed over the entire surface or part of the substrate having an insulating surface (a region having a larger area than that determined as a semiconductor region of the transistor). Then, a mask pattern is formed on the semiconductor layer by photolithography. By etching the semiconductor layer using the mask pattern, island-shaped semiconductor layers 1510 and 1511 having specific shapes including the source and drain regions of the TFT and the channel formation region are formed. The semiconductor layers 1510 and 1511 are determined in consideration of appropriate layout.

A photomask for forming the semiconductor layers 1510 and 1511 shown in FIG. 15A includes a mask pattern 1520 shown in FIG. The mask pattern 1520 differs depending on whether the resist used in the photolithography process is a positive type or a negative type. In the case of using a positive resist, the mask pattern 1520 shown in FIG. 15B is manufactured as a light shielding portion. The mask pattern 1520 has a shape obtained by deleting the top A of the polygon. Further, the bent portion B has a shape that is bent over a plurality of steps so that the corner portion does not become a right angle. The pattern of this photomask is, for example, a corner portion of the pattern (a right triangle) with a side portion deleted to a size of 10 μm or less.

The shape of the mask pattern 1520 illustrated in FIG. 15B is reflected in the semiconductor layers 1510 and 1511 illustrated in FIG. In that case, a shape similar to the mask pattern 1520 may be transferred, or the corner of the mask pattern 1520 may be transferred to be more rounded. That is, a rounded portion having a smoother pattern shape than the mask pattern 1520 may be provided.

Over the semiconductor layers 1510 and 1511, an insulating layer containing at least part of silicon oxide or silicon nitride is formed. One purpose of forming this insulating layer is a gate insulating layer. Then, as shown in FIG. 16A, gate wirings 1612, 1613, and 1614 are formed so as to partially overlap the semiconductor layer. The gate wiring 1612 is formed corresponding to the semiconductor layer 1510. The gate wiring 1613 is formed corresponding to the semiconductor layers 1510 and 1511. The gate wiring 1614 is formed corresponding to the semiconductor layers 1510 and 1511. For the gate wiring, a metal layer or a highly conductive semiconductor layer is formed, and its shape is formed on the insulating layer by a photolithography technique.

A photomask for forming this gate wiring is provided with a mask pattern 1621 shown in FIG. This mask pattern 1621 is a corner, and one side (of a right triangle) is 10 μm or less, or less than 1/2 of the line width of the wiring, and the corner is deleted to a size of 1/5 or more of the line width. is doing. The shape of the mask pattern 1621 shown in FIG. 16B is reflected in the gate wirings 1612, 1613, and 1614 shown in FIG. In that case, a shape similar to the mask pattern 1621 may be transferred, or the corner of the mask pattern 1621 may be transferred so as to be further rounded. That is, a rounded portion having a smoother pattern shape than the mask pattern 1621 may be provided. That is, the corners of the gate wirings 1612, 1613, and 1614 are rounded at the corners that are 1/2 or less of the line width and 1/5 or more. The convex part suppresses the generation of fine powder due to abnormal discharge during dry etching by plasma, and the concave part improves the yield as a result of washing away even if fine powder is easily collected at the corner during cleaning. It has the effect that it can be expected greatly.

The interlayer insulating layer is a layer formed next to the gate wirings 1612, 1613, and 1614. The interlayer insulating layer is formed using an inorganic insulating material such as silicon oxide or an organic insulating material using polyimide, acrylic resin, or the like. An insulating layer such as silicon nitride or silicon nitride oxide may be interposed between the interlayer insulating layer and the gate wirings 1612, 1613 and 1614. An insulating layer such as silicon nitride or silicon nitride oxide may be provided over the interlayer insulating layer. This insulating layer can prevent the semiconductor layer and the gate insulating layer from being contaminated by impurities that are not good for the TFT, such as exogenous metal ions and moisture.

Openings are formed in predetermined positions in the interlayer insulating layer. For example, it is provided corresponding to the gate wiring or semiconductor layer in the lower layer. A wiring layer formed of one or more layers of metal or metal compound is formed with a mask pattern by a photolithography technique and formed into a predetermined pattern by etching. Then, as illustrated in FIG. 17A, wirings 1715 to 1720 are formed so as to partially overlap the semiconductor layer. A wiring connects between specific elements. The wiring does not connect a specific element with a straight line, but includes a bent portion due to layout restrictions. In addition, the wiring width changes in the contact portion and other regions. In the contact portion, when the contact hole is equal to or larger than the wiring width, the wiring width is changed to widen at that portion.

A photomask for forming the wirings 1715 to 1720 includes a mask pattern 1722 shown in FIG. Even in this case, the wiring is a corner portion of which one side (of a right triangle) is 10 μm or less, or is a half or less of the line width of the wiring and has a corner portion with a size of 1/5 or more of the line width. Remove the corners and make the corners have a rounded pattern. The corners are ½ or less of the line width, and the corners are rounded to 1/5 or more. In such wiring, the convex part suppresses the generation of fine powder due to abnormal discharge when dry etching with plasma, and the concave part is easy to collect even in the case of cleaning even if it is fine powder. As a result of washing away, the yield can be greatly improved. It can be expected that the corner portion of the wiring is electrically conducted by taking a round. In addition, a large number of parallel wires are very convenient for washing away dust.

In FIG. 17A, n-channel thin film transistors 1721 to 1724 and p-channel thin film transistors 1725 and 1726 are formed. The n-channel thin film transistor 1723 and the p-channel thin film transistor 1725 and the n-channel thin film transistor 1724 and the p-channel thin film transistor 1726 form an inverter. The circuit including these six thin film transistors forms an SRAM. An insulating layer such as silicon nitride or silicon oxide may be formed over these thin film transistors.

With the above structure, a high-performance and low-power consumption semiconductor element can be provided at a lower weight and at a lower cost.

Note that this embodiment can be implemented by being freely combined with the embodiment mode and the above embodiment.

In this embodiment, a transistor included in a semiconductor device of the present invention will be described with reference to FIGS.

The transistor included in the semiconductor device of the present invention can be formed using a thin film transistor (TFT) in addition to a MOS transistor formed on a single crystal substrate. FIG. 18 is a diagram showing a cross-sectional structure of a thin film transistor constituting these circuits. FIG. 18 shows an n-channel thin film transistor 1821, an n-channel thin film transistor 1822, a capacitor 1824, a resistor 1825, and a p-channel thin film transistor 1823. Each thin film transistor includes a semiconductor layer 1805, an insulating layer 1808, and a gate electrode 1809. The gate electrode 1809 is formed with a stacked structure of a first conductive layer 1803 and a second conductive layer 1802. 19A to 19E are top views corresponding to the n-channel thin film transistor 1821, the n-channel thin film transistor 1822, the capacitor 1824, the resistor 1825, and the p-channel thin film transistor 1823 shown in FIG. You can refer to them together.

In FIG. 18, an n-channel thin film transistor 1821 is also referred to as a low concentration drain (LDD) on both sides of a gate electrode in a channel length direction (carrier flow direction), and forms a source and drain region that forms a contact with a wiring 1804. An impurity region 1807 doped at a lower concentration than the impurity concentration of the impurity region 1806 to be formed is formed in the semiconductor layer 1805. In the case where the n-channel thin film transistor 1821 is formed, phosphorus or the like is added to the impurity regions 1806 and 1807 as an impurity imparting n-type conductivity. LDD is formed as a means for suppressing hot electron degradation and short channel effect.

As shown in FIG. 19A, in the gate electrode 1809 of the n-channel thin film transistor 1821, the first conductive layer 1803 is formed to extend on both sides of the second conductive layer 1802. In this case, the first conductive layer 1803 is formed thinner than the second conductive layer. The thickness of the first conductive layer 1803 is formed so that ion species accelerated by an electric field of 10 to 100 kV can pass through. The impurity region 1807 is formed so as to overlap with the first conductive layer 1803 of the gate electrode 1809. That is, an LDD region overlapping with the gate electrode 1809 is formed. In this structure, an impurity region 1807 is formed in a self-aligned manner in the gate electrode 1809 by adding one conductivity type impurity through the first conductive layer 1803 using the second conductive layer 1802 as a mask. That is, the LDD overlapping with the gate electrode is formed in a self-aligning manner.

A thin film transistor having LDD on both sides is applied to a rectifying TFT of the power supply circuit 108 in the embodiment and a thin film transistor forming a transmission gate (also referred to as an analog switch) used in a logic circuit. In these TFTs, since both positive and negative voltages are applied to the source electrode and the drain electrode, it is preferable to provide LDDs on both sides of the gate electrode.

Further, the first conductive layer 1803 may be patterned so that both ends thereof are aligned when the second conductive layer 1802 is used to form a gate wiring. As a result, a fine gate wiring can be formed. Further, it is not necessary to form the LDD overlapping the gate electrode in a self-aligning manner.

In FIG. 18, an n-channel thin film transistor 1822 has a semiconductor layer 1805 formed with an impurity region 1807 doped at a lower concentration than the impurity concentration of the impurity region 1806 on one side of a gate electrode. As shown in FIG. 19B, in the gate electrode 1809 of the n-channel thin film transistor 1822, the first conductive layer 1803 is formed to extend to one side of the second conductive layer 1802. In this case as well, LDD can be formed in a self-aligned manner by adding an impurity of one conductivity type through the first conductive layer 1803 using the second conductive layer 1802 as a mask.

A thin film transistor having an LDD on one side may be applied to a thin film transistor in which only a positive voltage or only a negative voltage is applied between the source and drain electrodes. Specifically, it may be applied to a thin film transistor forming a logic gate such as an inverter circuit, a NAND circuit, a NOR circuit, or a latch circuit, or a thin film transistor forming an analog circuit such as a sense amplifier, a constant voltage generation circuit, or a VCO.

In FIG. 18, the capacitor 1824 is formed with a first conductive layer 1803 and a semiconductor layer 1805 sandwiching an insulating layer 1808. A semiconductor layer 1805 that forms the capacitor 1824 includes an impurity region 1810 and an impurity region 1811. The impurity region 1811 is formed in the semiconductor layer 1805 so as to overlap with the first conductive layer 1803. Further, the impurity region 1810 forms a contact with the wiring 1804. Since the impurity region 1811 can be doped with one conductivity type impurity through the first conductive layer 1803, the impurity concentrations in the impurity region 1810 and the impurity region 1811 can be the same or different. It is. In any case, since the semiconductor layer 1805 functions as an electrode in the capacitor 1824, it is preferable to reduce the resistance by adding an impurity of one conductivity type. Further, as shown in FIG. 19C, the first conductive layer 1803 can sufficiently function as an electrode by using the second conductive layer 1802 as an auxiliary electrode. As described above, by using a composite electrode structure in which the first conductive layer 1803 and the second conductive layer 1802 are combined, the capacitor 1824 can be formed in a self-aligning manner.

The capacitor is used as a storage capacitor included in the power supply circuit 108 in the embodiment or a resonance capacitor included in the resonance circuit 107. In particular, since both positive and negative voltages are applied between the two terminals of the capacitive element, the resonant capacitor needs to function as a capacitor regardless of whether the voltage between the two terminals is positive or negative.

In FIG. 19D, the resistance element 1825 is formed of the first conductive layer 1803. Since the first conductive layer 1803 is formed to a thickness of about 30 to 150 nm, a resistance element can be configured by appropriately setting the width and length thereof.

The resistance element is used as a resistance load included in the modulation / demodulation circuit 105 in the embodiment. Also, it may be used as a load when current is controlled by a VCO or the like. The resistance element may be formed using a semiconductor layer containing an impurity element at a high concentration or a thin metal layer. In contrast to a semiconductor layer whose resistance value depends on film thickness, film quality, impurity concentration, activation rate, etc., the metal layer has a resistance value determined by a small number of parameters such as film thickness and film quality, so that variation in resistance elements is reduced. Can be preferable.

In FIG. 19E, a p-channel thin film transistor 1823 includes an impurity region 1812 in a semiconductor layer 1805. The impurity region 1812 forms source and drain regions that form a contact with the wiring 1804. The structure of the gate electrode 1809 is a structure in which the first conductive layer 1803 and the second conductive layer 1802 overlap each other. The p-channel thin film transistor 1823 has a single drain structure without an LDD. In the case of forming the p-channel thin film transistor 1823, boron or the like is added to the impurity region 1812 as an impurity imparting p-type conductivity. On the other hand, when phosphorus is added to the impurity region 1812, an n-channel thin film transistor having a single drain structure can be obtained.

One or both of the semiconductor layer 1805 and the insulating layer 1808 functioning as a gate insulating layer are excited by microwaves, have an electron temperature of 2 eV or less, an ion energy of 5 eV or less, and an electron density of about 10 ¹¹ to 10 ¹³ / cm ^3. Oxidation or nitridation may be performed by high density plasma treatment. At this time, the substrate temperature is set to 300 to 450 ° C., and the semiconductor layer 1805 functions as a gate insulating layer by processing in an oxidizing atmosphere (O ₂ , N ₂ O, or the like) or a nitriding atmosphere (N ₂ , NH _3, or the like). The defect level at the interface of the insulating layer 1808 can be reduced. By performing this treatment on the insulating layer 1808 functioning as a gate insulating layer, the insulating layer can be densified. That is, generation of charged defects can be suppressed, and variation in threshold voltage of the transistor can be suppressed. In the case where the transistor is driven with a voltage of 3 V or lower, the insulating layer oxidized or nitrided by this plasma treatment can be used as the insulating layer 1808 that functions as a gate insulating layer. When the driving voltage of the transistor is 3 V or more, the gate is formed by combining an insulating layer formed on the surface of the semiconductor layer 1805 by this plasma treatment and an insulating layer deposited by a CVD method (plasma CVD method or thermal CVD method). An insulating layer 1808 functioning as an insulating layer can be formed. Similarly, this insulating layer can also be used as a dielectric layer of the capacitor 1824. In this case, since the insulating layer formed by this plasma treatment is formed with a thickness of 1 to 10 nm and is a dense film, a capacitor having a large charge capacity can be formed.

As described with reference to FIGS. 18 and 19, elements having various structures can be formed by combining conductive layers having different film thicknesses. The region where only the first conductive layer is formed and the region where the first conductive layer and the second conductive layer are laminated are a photo provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a translucent film. It can be formed using a mask or a reticle. That is, in the photolithography process, when the photoresist is exposed, the amount of light transmitted through the photomask is adjusted to vary the thickness of the resist mask to be developed. In this case, a resist having a complicated shape may be formed by providing a slit having a resolution limit or less in a photomask or a reticle. Alternatively, the mask pattern formed of the photoresist material may be deformed by baking at about 200 ° C. after development.

Further, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film, a region where only the first conductive layer is formed, the first conductive layer and the second conductive layer A region where the conductive layer is stacked can be formed continuously. As shown in FIG. 19A, a region where only the first conductive layer is formed can be selectively formed over the semiconductor layer. Such a region is effective on the semiconductor layer, but is not necessary in other regions (a wiring region continuous with the gate electrode). By using this photomask or reticle, it is not necessary to form a region of only the first conductive layer in the wiring portion, so that the wiring density can be substantially increased.

18 and 19, the first conductive layer is a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or a refractory metal. An alloy or a compound mainly composed of is formed with a thickness of 30 to 50 nm. The second conductive layer is made of a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or an alloy or compound containing a refractory metal as a main component. To a thickness of 300 to 600 nm. For example, different conductive materials are used for the first conductive layer and the second conductive layer, and a difference in etching rate is caused in an etching process performed later. As an example, TaN can be used for the first conductive layer, and a tungsten film can be used for the second conductive layer.

In this embodiment, transistors, capacitors, and resistors having different electrode structures are formed by the same patterning process using a photomask or reticle provided with an auxiliary pattern having a light intensity reducing function consisting of a diffraction grating pattern or a semi-transmissive film. It shows that it can be made separately. Thus, elements having different forms can be formed and integrated without increasing the number of steps in accordance with circuit characteristics.

By forming a semiconductor device with the above transistors, a wireless chip with high performance and low power consumption can be provided at a lower weight and at a lower cost.

This embodiment can be implemented by being freely combined with the embodiment mode and the above embodiment.

In this embodiment, a system example using the semiconductor device of the present invention will be described with reference to FIGS. In this embodiment, a personal computer user authentication system with excellent security using a wireless chip as a semiconductor device according to the present invention will be described.

FIG. 20 is a schematic diagram of a user authentication system in this embodiment, which shows a personal computer 2001 and a wireless chip 2002. An input device 2003 and a reader / writer 2004 are connected to the personal computer 2001.

The personal computer 2001 and the wireless chip 2002 have a common key 2005 for encryption. Specifically, the data of the common key 2005 is stored in the memories of the personal computer 2001 and the wireless chip 2002, respectively. The common key 2005 is 64-bit to 128-bit data, for example, and is used for encryption of plaintext (data before encryption) and decryption of the ciphertext. As the common key, a different common key is created for each registered user, and the personal computer 2001 has all the common keys. In other words, the personal computer 2001 has as many common keys as the number of users registered in a regular manner. On the other hand, the wireless chip 2002 is owned by a properly registered user and has only a common key unique to the user. The common key must be stored so that it is not known to others.

In this embodiment, a common key cryptosystem (ISO / IEC 9798-2 Information technology-Security techniques-Entity authentication-Part 2: An example of using a mechanical encryption metric) is used. Key encryption method (refer to ISO / IEC 9798-3 Information technology-Security techniques-Entity authentication-Part 3: also in the method used by the machinery using digital signature method, etc.) Easy to apply.

The personal computer 2001 has means for encrypting plaintext using the common key 2005. Specifically, it is assumed that software for executing an encryption algorithm is installed. The wireless chip 2002 also has means for decrypting the ciphertext using the common key 2005. Specifically, a decoding algorithm is executed in the arithmetic circuit shown in the above embodiment.

Hereinafter, a method of using the user authentication system in this embodiment will be described with reference to the flowchart of FIG.

First, a user who wishes to use inputs the user name and password in the personal computer 2001 using the input device 2003 (user name input 2101). The password is registered in advance by an authorized user. The personal computer 2001 encrypts a certain plain text from the input user name using the corresponding common key (encrypted data creation 2102). Here, the plaintext may be data having a specific meaning or meaningless data. Next, the encrypted data is transmitted from the reader / writer 2004 (encrypted data transmission 2103). The wireless chip 2002 receives the encrypted data, decrypts the encrypted data using the common key 2005 (decryption process 2104), and transmits the decrypted data to the reader / writer (decrypted data transmission 2105). The personal computer 2001 compares the decrypted data with the first plaintext (authentication 2106), and if it matches, the personal computer 2001 recognizes that the user who wants to use is a registered user and makes it available (normal use 2107). ).

In the user authentication system in the present embodiment as described above, the computer cannot be used unless the password is known and the wireless chip is not owned. Therefore, security is much higher than password-only authentication. In addition, if the user carries the wireless chip, the user can use the personal computer without any change from the conventional authentication using only the password, and there is little new burden.

In this embodiment, personal computer user authentication has been described. However, the present invention can be easily applied to other systems that can be used only by authorized users. For example, it can be easily applied to ATM (Automated Teller Machine), CD (Cash Dispenser) and the like.

With the configuration as described above, a user authentication system with extremely high security using the semiconductor device of the present invention can be constructed at low cost.

Note that this embodiment can be implemented by being freely combined with the embodiment mode and the above embodiment.

In this embodiment, as an example of a semiconductor device in the present invention, a wireless chip having a cryptographic processing function will be described with reference to FIGS. 26 is a block diagram of the wireless chip, FIG. 27 is a layout diagram of the wireless chip, and FIG. 28 is a cross-sectional view of the wireless chip.

First, the block configuration of the wireless chip is described with reference to FIG. In FIG. 26, the wireless chip 2601 includes an arithmetic circuit 2606 including a CPU 2602, a ROM 2603, a RAM 2604, a controller 2605, an antenna 2607, a resonance circuit 2608, a power supply circuit 2609, a reset circuit 2610, and a clock generation. The analog unit 2615 includes a circuit 2611, a demodulation circuit 2612, a modulation circuit 2613, and a power management circuit 2614. The controller 2605 includes a CPU interface (CPUIF) 2616, a control register 2617, a code extraction circuit 2618, and an encoding circuit 2619. In FIG. 26, for simplification of explanation, the communication signal is shown as being divided into a reception signal 2620 and a transmission signal 2621. However, in actuality, both are integrated (overlapped) signals. The wireless chip 2601 and the reader / writer are simultaneously transmitted and received. Received signal 2620 is received by antenna 2607 and resonant circuit 2608, and then demodulated by demodulation circuit 2612. Further, the transmission signal 2621 is modulated by the modulation circuit 2613 and then transmitted from the antenna 2607.

In FIG. 26, when the wireless chip 2601 is placed in a magnetic field formed by a communication signal, an induced electromotive force is generated by the antenna 2607 and the resonance circuit 2608. The induced electromotive force is held by an electric capacity in the power supply circuit 2609, and the potential is stabilized by the electric capacity, and is supplied as a power supply voltage to each circuit of the wireless chip 2601. The reset circuit 2610 generates an initial reset signal for the entire wireless chip 2601. For example, a signal that rises after a rise in the power supply voltage is generated as a reset signal. The clock generation circuit 2611 changes the frequency and duty ratio of the clock signal in accordance with the control signal generated by the power management circuit 2614. The demodulation circuit 2612 detects the fluctuation of the amplitude of the ASK reception signal 2620 as “0” / “1” reception data 2622. The demodulation circuit 2612 is a low-pass filter, for example. Further, the modulation circuit 2613 transmits the transmission data by changing the amplitude of the ASK transmission signal 2621. For example, when the transmission data 2623 is “0”, the resonance point of the resonance circuit 2608 is changed, and the amplitude of the communication signal is changed. The power management circuit 2614 monitors the power supply voltage supplied from the power supply circuit 2609 to the arithmetic circuit 2606 or the current consumption in the arithmetic circuit 2606, and a control signal for changing the frequency and duty ratio of the clock signal in the clock generation circuit 2611. Is generated.

The operation of the wireless chip in this embodiment will be described. First, the wireless chip 2601 receives ciphertext data included in the reception signal 2620 transmitted from the reader / writer. The received signal 2620 is demodulated by the demodulation circuit 2612, decomposed into a control command, ciphertext data, and the like by the code extraction circuit 2618 and stored in the control register 2617. Here, the control command is data specifying a response of the wireless chip 2601. For example, transmission of a unique ID number, operation stop, and decryption are designated. Here, it is assumed that a decryption control command is received.

Subsequently, in the arithmetic circuit 2606, the CPU 2602 decrypts (decrypts) the ciphertext using the secret key 2624 stored in advance in the ROM 2603 according to the decryption program stored in the ROM 2603. The decrypted ciphertext (decrypted text) is stored in the control register 2617. At this time, the RAM 2604 is used as a data storage area. Note that the CPU 2602 accesses the ROM 2603, the RAM 2604, and the control register 2617 via the CPUIF 2616. The CPU IF 2616 has a function of generating an access signal for any of the ROM 2603, the RAM 2604, and the control register 2617 from an address requested by the CPU 2602.

Finally, in the encoding circuit 2619, transmission data 2623 is generated from the decoded text, modulated by the modulation circuit 2613, and the transmission signal 2621 is transmitted from the antenna 2607 to the reader / writer.

In this embodiment, as a calculation method, a method of processing by software, that is, a method of configuring a calculation circuit with a CPU and a large-scale memory and executing a program by the CPU has been described. It is also possible to select an appropriate calculation method and configure based on the method. For example, as a calculation method, other methods such as a method of processing the operation in hardware and a method of using both hardware and software are conceivable. In the method of processing in hardware, an arithmetic circuit may be configured with a dedicated circuit. In the method using both hardware and software, a dedicated circuit, a CPU, and a memory constitute an arithmetic circuit, a part of the arithmetic processing is performed by the dedicated circuit, and the remaining arithmetic processing program is executed by the CPU. .

Next, the layout configuration of the wireless chip is described with reference to FIG. In FIG. 27, parts corresponding to those in FIG. 26 are denoted by the same reference numerals and description thereof is omitted.

In FIG. 27, an FPC pad 2707 is an electrode pad group used when an FPC (Flexible Print Circuit) is attached to the wireless chip 2601, and an antenna bump 2708 is an electrode pad for attaching an antenna (not shown). Note that when the antenna is attached, excessive pressure may be applied to the antenna bump 2708. Therefore, it is desirable not to dispose a component such as a transistor under the antenna bump 2708.

The FPC pad 2707 is effective when used mainly for failure analysis. In the wireless chip, since the power supply voltage is obtained from the communication signal, for example, when a failure occurs in the antenna or the power supply circuit, the arithmetic circuit does not operate at all. For this reason, failure analysis becomes extremely difficult. However, the power supply voltage is supplied from the FPC to the wireless chip 2601 through the FPC pad 2707, and the arithmetic circuit is operated by inputting an arbitrary electric signal instead of the electric signal supplied from the antenna. Is possible. Therefore, failure analysis can be performed efficiently.

Furthermore, it is more effective to arrange the FPC pad 2707 so that measurement using a prober is possible. That is, in the FPC pad 2707, the electrode pad is arranged in accordance with the pitch of the prober needle, whereby measurement by the prober becomes possible. By using a prober, it is possible to reduce the number of steps for attaching the FPC during failure analysis. Further, since measurement can be performed even when a plurality of wireless chips are formed on a substrate, the number of steps for dividing each wireless chip can be reduced. In addition, it is possible to perform a non-defective inspection of the wireless chip immediately before the step of attaching the antenna during mass production. Accordingly, defective products can be selected at an early stage of the process, so that production costs can be reduced.

A cross-sectional view of such a wireless chip is shown in FIG. First, as shown in FIG. 18, the wiring 1804 is formed. An insulating layer 1853 is formed so as to cover the wiring 1804. The insulating layer 1853 can be formed using an inorganic material or an organic material. As the inorganic material, silicon oxide or silicon nitride can be used. As the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane, or polysilazane can be used. Note that siloxane has a skeleton structure of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Polysilazane is formed using a polymer material having a bond of silicon (Si) and nitrogen (N) as a starting material.

In the connection region 1850, an opening is formed in the insulating layer 1853 so that the wiring 1851 formed at the same time as the wiring 1804 is exposed. In the opening, a corner portion at the upper end is rounded and a side surface is preferably tapered. This is because it is possible to prevent disconnection of the pattern formed thereafter.

A connection wiring 1852 is formed in the opening. The connection wiring 1852 can be formed of a film made of an element of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), or silicon (Si), an alloy film using these elements, or the like. Alternatively, a light-transmitting material such as indium tin oxide (ITO), indium tin oxide containing silicon oxide, or indium oxide containing 2 to 20% zinc oxide can be used. At this time, the connection wiring 1852 is not overlapped with regions such as the n-channel thin film transistor 1821, the n-channel thin film transistor 1822, the capacitor 1824, the resistor 1825, and the p-channel thin film transistor 1823. This is to prevent generation of unnecessary parasitic capacitance.

An insulating layer 1854 is formed so as to cover the insulating layer 1853 and the connection wiring 1852. The insulating layer 1854 can be manufactured in a manner similar to that of the insulating layer 1853.

An opening is formed in the insulating layer 1854 so that the connection wiring 1852 provided over the insulating layer 1853 is exposed. An anisotropic conductor 1856 having conductive fine particles 1855 is provided in the opening, and an FPC (flexible printed circuit) 1858 having a conductive layer 1857 is connected.

In this manner, the wireless chip of the present invention can be manufactured.

The antenna may be any size and shape that meets the purpose within the range stipulated by the Radio Law. Signals to be transmitted and received include 125 kHz, 13.56 MHz, 915 MHz, 2.45 GHz, and the like, and ISO standards are set for each. As a specific antenna, a dipole antenna, a patch antenna, a loop antenna, a Yagi antenna, or the like may be used. In this embodiment, an antenna shape connected to a wireless chip is described.

FIG. 29A illustrates a wireless chip 1601 to which an external antenna 1602 is connected. In FIG. 29A, a wireless chip 1601 is provided in the center, and an antenna 1602 is connected to a connection terminal of the wireless chip 1601. In order to secure the length of the antenna, the antenna 1602 is bent into a rectangular shape.

FIG. 29B illustrates a mode in which the external antenna 1603 is provided on a connection terminal on one end side of the wireless chip 1601. In order to secure the length of the antenna, the antenna 1603 is bent into a rectangular shape.

FIG. 29C illustrates a mode in which external antennas 1604 bent in a rectangular shape are provided at both ends of the wireless chip 1601.

FIG. 29D illustrates a mode in which a linear external antenna 1605 is provided at both ends of the wireless chip 1601.

As described above, the shape of the antenna may be selected in accordance with the structure or polarization of the wireless chip or the application. Therefore, a folded dipole antenna may be used as long as it is a dipole antenna. As long as it is a loop antenna, it may be a circular loop antenna or a square loop antenna. If it is a patch antenna, a circular patch antenna or a square antenna may be used.

In the case of a patch antenna, an antenna using a dielectric material such as ceramic may be used. The antenna can be miniaturized by increasing the dielectric constant of the dielectric material used as the patch antenna substrate. In the case of the patch antenna, since the mechanical strength is high, it can be used repeatedly.

The dielectric material of the patch antenna can be formed of ceramic, organic resin, a mixture of ceramic and organic resin, or the like. Representative examples of ceramics include alumina, glass, forsterite and the like. Furthermore, a plurality of ceramics may be mixed and used. In order to obtain a high dielectric constant, the dielectric layer is preferably formed of a ferroelectric material. Typical examples of the ferroelectric material include barium titanate (BaTiO ₃ ), lead titanate (PbTiO ₃ ), strontium titanate (SrTiO ₃ ), lead zirconate (PbZrO ₃ ), lithium diobate (LiNbO ₃ ). And lead zirconate titanate (PZT). Further, a plurality of ferroelectric materials may be mixed and used.

Note that the structure described in any of the above embodiments and examples can be applied to the wireless chip 1601.

In this embodiment, the semiconductor device of the present invention is formed on a plastic substrate. Note that the semiconductor device of this embodiment includes an RF circuit for wireless communication and a CPU in an arithmetic circuit.

Table 1 shows communication specifications of the semiconductor device of the present invention.

A 13.56 MHz band radio signal is used for communication, and the communication standard and protocol are partially compliant with ISO / IEC 15693. In the semiconductor device of the present invention, the power supply voltage is supplied from the radio signal via the antenna. Although the semiconductor device of the present invention has an external antenna, it may be a built-in antenna integrally formed with a circuit. The data transfer rate is 26.48 kbit / s, data encoding from the reader / writer to the semiconductor device is pulse position modulation, and data encoding from the semiconductor device to the reader / writer is the Manchester system.

Table 2 shows an outline of the semiconductor device of the present invention.

Since the semiconductor device of the present invention can be formed using a thin film transistor over a flexible substrate as described above, a very lightweight semiconductor device of 103 mg can be provided.

Next, FIG. 30 shows a block configuration of the semiconductor device of the present invention. The semiconductor device 550 of the present invention includes a wireless circuit 551 and a logic circuit 570. The wireless circuit 551 includes a resonance capacitor 552, a power supply circuit 553, a system reset circuit 554, a clock generator 555, a demodulation circuit 556, a modulation circuit 557, and the like. The resonance capacitor 552 can form a resonance circuit together with the external antenna 574. The power supply circuit 553 includes a rectifier circuit and a storage capacitor, and can generate a power supply voltage. The system reset circuit 554 can generate a system reset signal, and the clock generator 555 can generate a system clock signal. The demodulation circuit 556 has an LPF (Low Pass Filter) and can extract data from a radio signal. The modulation circuit 557 can superimpose data on a radio signal by the Manchester method. These circuits can be formed from thin film transistors.

The logic circuit 570 includes a controller 560, a CPU 571, a ROM 572, a RAM 573, and the like. The controller 560 includes a clock control circuit 561, a control register 562, a reception data register 563, a transmission data register 564, a wireless interface 567, and a CPU interface 568. Have These circuits and the like can be formed from thin film transistors. The demodulation circuit 556 and the modulation circuit 557 can exchange signals with the control register 562, the reception data register 563, and the transmission data register 564 through the wireless interface 567. The clock generator 555 is controlled by the clock control circuit 561, and the clock control circuit 561 operates based on the control register 562. The control register 562, the reception data register 563, and the transmission data register 564 can exchange signals with the CPU 571, the ROM 572, and the RAM 573 via the CPU interface 568.

The CPU included in the semiconductor device is an 8-bit CISC, and can be configured with the flip-flops of the two-phase non-overlap clock operation described in the above embodiment. By using a flip-flop with a two-phase non-overlapping clock operation, it is possible to prevent malfunction caused by variations in clock skew and TFT characteristics and improve reliability. As the ROM 572, a 2 KB mask ROM can be applied, and a program, a secret key, and the like can be stored. A 64B SRAM can be applied to the RAM 573, and the SRAM can be used as a work area of the CPU. Thus, the circuit configuration of the memory cell is devised to improve the reliability of writing / reading. The controller 560 has a function as a state machine of the semiconductor device.

FIG. 31 shows a state transition diagram in this semiconductor device. By changing the state flag in the control register 562, the operation state 580, the reception state 581, and the transmission state 582 are changed in order. In the reception state 581, serial data extracted from the wireless signal is stored in the reception data register 563. In the calculation state 580, the CPU 571 performs processing using the program stored in the ROM 572 and data in the reception data register 563, and stores transmission data in the transmission data register 564. In the transmission state 582, the transmission data stored in the transmission data register 564 is converted into serial data and sequentially transmitted. The logic circuit 570 is divided into a reception block, a calculation block, and a transmission block for each circuit operating in the calculation state 580, the reception state 581, and the transmission state 582, and a clock control circuit supplies a clock signal to each block. Control is performed at 561. Such precise control of the clock signal can reduce current consumption in the semiconductor device and improve reliability.

Such a design of the semiconductor device can be determined as follows. The wireless circuit 551 can be designed using SPICE for each sub-circuit, then performing a custom layout, performing operation verification using Nanosim (R) for the entire RF circuit, and determining the design.
After the RTL design using Verilog HDL (R), the CPU 571 can determine the design by performing custom layout for the registers, logic synthesis using standard cells, and automatic layout for others. The ROM 572 and the RAM 573 can be designed by performing a custom layout after designing a memory cell by SPICE. The CPU 571, the ROM 572, and the RAM 573 may perform detailed timing verification using Nanosim (R) after layout. The controller 560 can be designed by performing logic synthesis using standard cells and automatic layout after RTL design using Verilog HDL (R).

In this semiconductor device, SAFE (Secure And Fast Encryption Route) can be adopted as an algorithm for encryption processing. SAFER is mainly composed of 8-bit arithmetic and is an algorithm suitable for an 8-bit CPU. A wireless chip having this semiconductor device can be equipped with a function of receiving ciphertext data, decrypting it using a secret key, and transmitting plaintext data to a reader / writer. Of course, other cryptographic processing algorithms such as DES and AES may be employed in the semiconductor device.

A photograph of a wireless chip having this semiconductor device formed on glass and a wireless chip having this semiconductor device formed on a flexible substrate is shown in FIG. 32, and an enlarged photograph and a block diagram of the wireless chip are shown in FIG. . The present invention can provide such a very thin wireless chip.

FIG. 34 shows the result of measuring the communication signal waveform of the wireless chip of the present invention with a spectrum analyzer. In FIG. 34A, the vertical axis represents signal intensity, the horizontal axis represents time, in FIG. 34B, the vertical axis represents signal intensity, the horizontal axis represents frequency, and in FIG. 34C, the vertical axis represents signal intensity, horizontal The waveform of the signal when the axis is time is shown. As a measurement example, after receiving ciphertext data, it is a result of decrypting using a secret key and transmitting plaintext data. The measurement is a result of measurement using a 13.56 MHz band signal with a wireless chip formed on a flexible substrate. The current consumption of this wireless chip was 2.3 mA when the internally generated voltage was 1.8V. Thus, a wireless chip with low power consumption can be obtained.

Schematic diagram of semiconductor device in the present invention The figure which shows the communication signal at the time of the data transmission / reception in ASK system Diagram showing the synchronization circuit Timing chart example of synchronous circuit The figure which shows the synchronous circuit of the semiconductor device in this invention Timing chart example of a synchronization circuit of a semiconductor device according to the present invention FIG. 1 is a diagram showing a power management circuit for a semiconductor device according to the present invention (1). Timing chart example (1) of the power management circuit of the semiconductor device in the present invention FIG. 2 shows a power management circuit for a semiconductor device according to the present invention (2). Timing chart example (2) of the power management circuit of the semiconductor device in the present invention Sectional drawing (1) of the semiconductor device in this invention Layout of semiconductor device in the present invention (1) (semiconductor layer) Layout of semiconductor device in the present invention (1) (gate wiring) Layout of semiconductor device according to the present invention (1) (wiring) Layout of semiconductor device in the present invention (2) (semiconductor layer) Layout of semiconductor device in the present invention (2) (gate wiring) Layout of semiconductor device in the present invention (2) (wiring) Sectional drawing (2) of the semiconductor device in this invention Electrical element constituting semiconductor device in the present invention Schematic diagram of a user authentication system using a semiconductor device in the present invention Flowchart of user authentication system using semiconductor device in the present invention FIG. 3 shows a power management circuit for a semiconductor device according to the present invention (3). Timing chart example of power supply management circuit of semiconductor device in the present invention (3) FIG. 4 shows a power management circuit for a semiconductor device according to the present invention (4). Timing chart example (4) of the power management circuit of the semiconductor device in the present invention Block diagram of a semiconductor device in the present invention Block diagram of a semiconductor device in the present invention The figure which shows the cross section of the semiconductor device in this invention The figure which shows the antenna shape of the semiconductor device in this invention Block diagram of a semiconductor device in the present invention State transition diagram of operation of semiconductor device in the present invention Photograph of a semiconductor device in the present invention Block diagram of a semiconductor device of the present invention Operational measurement diagram of semiconductor device of the present invention

Claims (13)

An arithmetic circuit, a power management circuit, a clock generation circuit, and a power circuit ;
The arithmetic circuit has a first latch having a function of changing a period of holding data by a first gate signal, and a function of changing a period of holding data by a second gate signal. 2 latches,
The power management circuit compares a reference voltage based on a power supply voltage supplied from the power supply circuit with a power supply voltage supplied from the arithmetic circuit, and generates a control signal from the voltage value supplied to the arithmetic circuit. Has the function to
The clock generation circuit has a function of generating a first clock signal and a second clock signal;
The first gate signal and the second gate signal are generated based on the first clock signal and the second clock signal generated in the clock generation circuit, respectively. . An arithmetic circuit, a power management circuit, a clock generation circuit, and a power circuit ;
The arithmetic circuit has a first latch having a function of changing a period of holding data by a first gate signal, and a function of changing a period of holding data by a second gate signal. 2 latches,
The power management circuit compares a reference voltage based on a power supply voltage supplied from the power supply circuit with a power supply voltage supplied from the arithmetic circuit, and generates a control signal from the voltage value supplied to the arithmetic circuit. Has the function to
The clock generation circuit has a function of generating a first clock signal and a second clock signal, and the control signal causes the first clock signal and the second clock signal to be period as a LOW is changed,
The semiconductor device, wherein the first gate signal and the second gate signal are generated based on a first clock signal and a second clock signal generated in the clock generation circuit. An arithmetic circuit, a power management circuit, a clock generation circuit, and a power circuit ;
The arithmetic circuit has a first latch having a function of changing a period of holding data by a first gate signal, and a function of changing a period of holding data by a second gate signal. 2 latches,
The power management circuit compares a reference voltage based on a power supply voltage supplied from the power supply circuit with a voltage generated in a resistance between the arithmetic circuit and the power supply circuit, and supplies a current supplied to the arithmetic circuit. It has a function to generate a control signal from a value ,
The clock generation circuit has a function of generating a first clock signal and a second clock signal;
The first gate signal and the second gate signal are generated based on the first clock signal and the second clock signal generated in the clock generation circuit, respectively. . An arithmetic circuit, a power management circuit, a clock generation circuit, and a power circuit ;
The arithmetic circuit has a first latch having a function of changing a period of holding data by a first gate signal, and a function of changing a period of holding data by a second gate signal. 2 latches,
The power management circuit compares a reference voltage based on a power supply voltage supplied from the power supply circuit with a voltage generated in a resistance between the arithmetic circuit and the power supply circuit, and supplies a current supplied to the arithmetic circuit. It has a function to generate a control signal from a value ,
The clock generation circuit has a function of generating a first clock signal and a second clock signal, and the control signal causes the first clock signal and the second clock signal to be period as a LOW is changed,
The semiconductor device, wherein the first gate signal and the second gate signal are generated based on a first clock signal and a second clock signal generated in the clock generation circuit. In any one of Claims 1 thru | or 4,
The arithmetic circuit, the power management circuit, said clock generating circuit, and at least one of said power supply circuit is a semiconductor, characterized in that the organic thin film transistors as an active layer of a semiconductor thin film provided on a substrate having an insulating surface apparatus. In claim 5 ,
The substrate having an insulating surface is any one of a glass substrate, a quartz substrate, a plastic substrate, and an SOI substrate. In any one of Claims 1 thru | or 6 ,
The power supply management circuit includes a regulator and an operational amplifier circuit. In any one of Claims 1 thru | or 6,
The power management circuit includes a regulator and an operational amplifier circuit,
An output terminal of the regulator is electrically connected to the first resistor;
A semiconductor device, wherein an input terminal of the operational amplifier circuit is electrically connected to the first resistor and the second resistor, and an output terminal is electrically connected to a digital buffer. In any one of Claims 1 thru | or 6,
The power management circuit includes a regulator and an operational amplifier circuit,
An output terminal of the regulator is electrically connected to the first resistor;
An input terminal of the operational amplifier circuit is electrically connected to the first resistor and the second resistor, and an output terminal is electrically connected to a digital buffer,
The input terminal of the regulator has a power supply potential corresponding to a power supply voltage supplied from the power supply circuit,
An output terminal of the regulator has a reference potential corresponding to the reference voltage. In any one of Claims 1 thru | or 6,
The power management circuit includes a regulator and an operational amplifier circuit,
An output terminal of the regulator is electrically connected to the first resistor;
An input terminal of the operational amplifier circuit is electrically connected to the first resistor and the second resistor, and an output terminal is electrically connected to a digital buffer,
The input terminal of the regulator has a power supply potential corresponding to a power supply voltage supplied from the power supply circuit,
The output terminal of the regulator has a reference potential corresponding to the reference voltage,
The power supply voltage is input to the operational amplifier circuit via the second resistor, and the reference voltage is input to the operational amplifier circuit via the first resistor,
An output signal from the operational amplifier circuit becomes the control signal through the digital buffer. In any one of Claims 1 thru | or 6 ,
The power supply management circuit includes a regulator, an operational amplifier circuit, and an analog-digital conversion circuit. In any one of Claims 1 thru | or 11,
The semiconductor device according to claim 1, wherein the clock generation circuit includes means for changing a frequency of the first clock signal and the second clock signal according to the control signal. In any one of Claims 1 to 12,
The arithmetic circuit includes a CPU and a memory.