JP2007129699A - チップ上の再構成可能なネットワーク - Google Patents

チップ上の再構成可能なネットワーク Download PDF

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Publication number
JP2007129699A
JP2007129699A JP2006271642A JP2006271642A JP2007129699A JP 2007129699 A JP2007129699 A JP 2007129699A JP 2006271642 A JP2006271642 A JP 2006271642A JP 2006271642 A JP2006271642 A JP 2006271642A JP 2007129699 A JP2007129699 A JP 2007129699A
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network
reconfigurable
unit
chip
interface
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Japanese (ja)
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JP2007129699A5 (enExample
Inventor
Jeremy Ramos
ジェレミー・ラモス
Scott D Stackelhouse
スコット・ディー・スタックルハウス
Ian A Troxel
イアン・エイ・トロクセル
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Honeywell International Inc
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Honeywell International Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Microcomputers (AREA)
JP2006271642A 2005-10-03 2006-10-03 チップ上の再構成可能なネットワーク Withdrawn JP2007129699A (ja)

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US11/242,509 US7382154B2 (en) 2005-10-03 2005-10-03 Reconfigurable network on a chip

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JP2007129699A5 JP2007129699A5 (enExample) 2009-11-12

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EP (1) EP1770541A1 (enExample)
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011512598A (ja) * 2008-02-19 2011-04-21 マイクロン テクノロジー， インク． チップ上にネットワークを有するメモリ・デバイスの方法、装置、及びシステム
KR101182988B1 (ko) 2009-04-28 2012-09-18 인터내셔널 비지네스 머신즈 코포레이션 다층 반도체 스택을 위한 범용 층간 상호 연결
US9047991B2 (en) 2008-09-11 2015-06-02 Micron Technology, Inc. Methods, apparatus, and systems to repair memory
US9123552B2 (en) 2010-03-30 2015-09-01 Micron Technology, Inc. Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same
US9524254B2 (en) 2008-07-02 2016-12-20 Micron Technology, Inc. Multi-serial interface stacked-die memory architecture
JP2017502418A (ja) * 2013-12-30 2017-01-19 ネットスピード システムズ 可変な数のコア群、入出力（ｉ／ｏ）装置、ディレクトリ構造、及びコヒーレンシポイントを有する、キャッシュコヒーレントｎｏｃ（ネットワークオンチップ）
CN113632069A (zh) * 2019-03-27 2021-11-09 赛灵思公司 自适应集成可编程设备平台

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8782654B2 (en) 2004-03-13 2014-07-15 Adaptive Computing Enterprises, Inc. Co-allocating a reservation spanning different compute resources types
US9176785B2 (en) 2004-03-13 2015-11-03 Adaptive Computing Enterprises, Inc. System and method for providing multi-resource management support in a compute environment
US20070266388A1 (en) 2004-06-18 2007-11-15 Cluster Resources, Inc. System and method for providing advanced reservations in a compute environment
US8176490B1 (en) 2004-08-20 2012-05-08 Adaptive Computing Enterprises, Inc. System and method of interfacing a workload manager and scheduler with an identity manager
US8271980B2 (en) 2004-11-08 2012-09-18 Adaptive Computing Enterprises, Inc. System and method of providing system jobs within a compute environment
US8863143B2 (en) 2006-03-16 2014-10-14 Adaptive Computing Enterprises, Inc. System and method for managing a hybrid compute environment
EP2360587B1 (en) 2005-03-16 2017-10-04 III Holdings 12, LLC Automatic workload transfer to an on-demand center
US9231886B2 (en) 2005-03-16 2016-01-05 Adaptive Computing Enterprises, Inc. Simple integration of an on-demand compute environment
EP1872249B1 (en) 2005-04-07 2016-12-07 Adaptive Computing Enterprises, Inc. On-demand access to compute resources
US7765382B2 (en) * 2007-04-04 2010-07-27 Harris Corporation Propagating reconfiguration command over asynchronous self-synchronous global and inter-cluster local buses coupling wrappers of clusters of processing module matrix
US8041773B2 (en) 2007-09-24 2011-10-18 The Research Foundation Of State University Of New York Automatic clustering for self-organizing grids
FR2927438B1 (fr) * 2008-02-08 2010-03-05 Commissariat Energie Atomique Methode de prechargement dans une hierarchie de memoires des configurations d'un systeme heterogene reconfigurable de traitement de l'information
FR2928758B1 (fr) * 2008-03-13 2012-10-12 Mbda France Systeme de routage de donnees.
US8078784B2 (en) * 2008-04-23 2011-12-13 Airhop Communications Method and apparatus for data movement in a system on a chip
US20090307408A1 (en) * 2008-06-09 2009-12-10 Rowan Nigel Naylor Peer-to-Peer Embedded System Communication Method and Apparatus
US8082474B2 (en) 2008-07-01 2011-12-20 International Business Machines Corporation Bit shadowing in a memory system
US7895374B2 (en) 2008-07-01 2011-02-22 International Business Machines Corporation Dynamic segment sparing and repair in a memory system
US8234540B2 (en) 2008-07-01 2012-07-31 International Business Machines Corporation Error correcting code protected quasi-static bit communication on a high-speed bus
US8139430B2 (en) 2008-07-01 2012-03-20 International Business Machines Corporation Power-on initialization and test for a cascade interconnect memory system
US8082475B2 (en) 2008-07-01 2011-12-20 International Business Machines Corporation Enhanced microprocessor interconnect with bit shadowing
US8245105B2 (en) 2008-07-01 2012-08-14 International Business Machines Corporation Cascade interconnect memory system with enhanced reliability
US8201069B2 (en) 2008-07-01 2012-06-12 International Business Machines Corporation Cyclical redundancy code for use in a high-speed serial link
US7979759B2 (en) 2009-01-08 2011-07-12 International Business Machines Corporation Test and bring-up of an enhanced cascade interconnect memory system
US20100180154A1 (en) * 2009-01-13 2010-07-15 International Business Machines Corporation Built In Self-Test of Memory Stressor
US8599863B2 (en) 2009-10-30 2013-12-03 Calxeda, Inc. System and method for using a multi-protocol fabric module across a distributed server interconnect fabric
US9465771B2 (en) 2009-09-24 2016-10-11 Iii Holdings 2, Llc Server on a chip and node cards comprising one or more of same
US9054990B2 (en) 2009-10-30 2015-06-09 Iii Holdings 2, Llc System and method for data center security enhancements leveraging server SOCs or server fabrics
US20130107444A1 (en) 2011-10-28 2013-05-02 Calxeda, Inc. System and method for flexible storage and networking provisioning in large scalable processor installations
US9077654B2 (en) 2009-10-30 2015-07-07 Iii Holdings 2, Llc System and method for data center security enhancements leveraging managed server SOCs
US9876735B2 (en) 2009-10-30 2018-01-23 Iii Holdings 2, Llc Performance and power optimized computer system architectures and methods leveraging power optimized tree fabric interconnect
US20110103391A1 (en) 2009-10-30 2011-05-05 Smooth-Stone, Inc. C/O Barry Evans System and method for high-performance, low-power data center interconnect fabric
US9311269B2 (en) 2009-10-30 2016-04-12 Iii Holdings 2, Llc Network proxy for high-performance, low-power data center interconnect fabric
US9648102B1 (en) 2012-12-27 2017-05-09 Iii Holdings 2, Llc Memcached server functionality in a cluster of data processing nodes
US11720290B2 (en) 2009-10-30 2023-08-08 Iii Holdings 2, Llc Memcached server functionality in a cluster of data processing nodes
US10877695B2 (en) 2009-10-30 2020-12-29 Iii Holdings 2, Llc Memcached server functionality in a cluster of data processing nodes
US9680770B2 (en) 2009-10-30 2017-06-13 Iii Holdings 2, Llc System and method for using a multi-protocol fabric module across a distributed server interconnect fabric
CN102025614B (zh) * 2010-11-25 2013-01-30 浙江大学 一种线上可重构的4元树状片上网络系统及其重构方法
US9092594B2 (en) 2011-10-31 2015-07-28 Iii Holdings 2, Llc Node card management in a modular and large scalable server system
US10270709B2 (en) 2015-06-26 2019-04-23 Microsoft Technology Licensing, Llc Allocating acceleration component functionality for supporting services
CN105393504B (zh) * 2014-07-02 2018-09-28 华为技术有限公司 计算机系统
US10296392B2 (en) 2015-04-17 2019-05-21 Microsoft Technology Licensing, Llc Implementing a multi-component service using plural hardware acceleration components
US9792154B2 (en) 2015-04-17 2017-10-17 Microsoft Technology Licensing, Llc Data processing system having a hardware acceleration plane and a software plane
US10511478B2 (en) 2015-04-17 2019-12-17 Microsoft Technology Licensing, Llc Changing between different roles at acceleration components
US10198294B2 (en) 2015-04-17 2019-02-05 Microsoft Licensing Technology, LLC Handling tenant requests in a system that uses hardware acceleration components
US10216555B2 (en) 2015-06-26 2019-02-26 Microsoft Technology Licensing, Llc Partially reconfiguring acceleration components
US9819542B2 (en) 2015-06-26 2017-11-14 Microsoft Technology Licensing, Llc Configuring acceleration components over a network
CN107835529B (zh) * 2017-09-30 2020-04-21 北京空间飞行器总体设计部 天基骨干网动态接入系统、节点、管理中心及方法
US11113076B2 (en) * 2017-10-06 2021-09-07 North Sea Investment Co. Ltd. Coordinating power transitions between a smart interconnect and heterogeneous components
US10396053B2 (en) 2017-11-17 2019-08-27 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10566301B2 (en) * 2017-11-17 2020-02-18 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10884949B2 (en) 2019-04-05 2021-01-05 International Business Machines Corporation On-chip logic accelerator
US10963411B1 (en) * 2019-07-03 2021-03-30 Xilinx, Inc. Integrating rows of input/output blocks with memory controllers in a columnar programmable fabric archeture
US10754666B1 (en) 2019-07-29 2020-08-25 Rad Data Communications Ltd. Hardware micro-services platform
GB2586277B (en) * 2019-08-16 2022-11-23 Siemens Ind Software Inc Broadcasting event messages in a system on chip
US12063148B2 (en) * 2020-06-18 2024-08-13 F5, Inc. Orchestrating configuration of a programmable accelerator
CN115793551B (zh) * 2023-02-08 2023-06-02 中国电子科技集团公司第十研究所 航天电子载荷超大规模多功能综合化处理平台

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6006321A (en) * 1997-06-13 1999-12-21 Malleable Technologies, Inc. Programmable logic datapath that may be used in a field programmable device
US6535043B2 (en) * 2000-05-26 2003-03-18 Lattice Semiconductor Corp Clock signal selection system, method of generating a clock signal and programmable clock manager including same
US7076595B1 (en) * 2001-05-18 2006-07-11 Xilinx, Inc. Programmable logic device including programmable interface core and central processing unit
US6573748B1 (en) * 2001-11-06 2003-06-03 Xilinx, Inc. Programmable logic device with output register for specifying memory space during reconfiguration
US6627985B2 (en) * 2001-12-05 2003-09-30 Arbor Company Llp Reconfigurable processor module comprising hybrid stacked integrated circuit die elements
WO2004015764A2 (en) 2002-08-08 2004-02-19 Leedy Glenn J Vertical system integration
KR20050085545A (ko) 2002-12-12 2005-08-29 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 코프로세서, 코프로세싱 시스템, 집적 회로, 수신기, 기능유닛 및 인터페이싱 방법
EP1443417A1 (en) 2003-01-31 2004-08-04 STMicroelectronics S.r.l. A reconfigurable signal processor with embedded flash memory device
DE602004006955T2 (de) * 2003-11-25 2008-02-28 Interuniversitair Micro-Elektronica Centrum Heterogenes Mehrrechnersystem in Form eines Network on Chip, sowie Verfahren und Betriebssystem zur Kontrolle desselben

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9229887B2 (en) 2008-02-19 2016-01-05 Micron Technology, Inc. Memory device with network on chip methods, apparatus, and systems
JP2011512598A (ja) * 2008-02-19 2011-04-21 マイクロン テクノロジー， インク． チップ上にネットワークを有するメモリ・デバイスの方法、装置、及びシステム
US9524254B2 (en) 2008-07-02 2016-12-20 Micron Technology, Inc. Multi-serial interface stacked-die memory architecture
US10332614B2 (en) 2008-09-11 2019-06-25 Micron Technology, Inc. Methods, apparatus, and systems to repair memory
US9047991B2 (en) 2008-09-11 2015-06-02 Micron Technology, Inc. Methods, apparatus, and systems to repair memory
US9852813B2 (en) 2008-09-11 2017-12-26 Micron Technology, Inc. Methods, apparatus, and systems to repair memory
KR101182988B1 (ko) 2009-04-28 2012-09-18 인터내셔널 비지네스 머신즈 코포레이션 다층 반도체 스택을 위한 범용 층간 상호 연결
US9123552B2 (en) 2010-03-30 2015-09-01 Micron Technology, Inc. Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same
US9484326B2 (en) 2010-03-30 2016-11-01 Micron Technology, Inc. Apparatuses having stacked devices and methods of connecting dice stacks
JP2017502418A (ja) * 2013-12-30 2017-01-19 ネットスピード システムズ 可変な数のコア群、入出力（ｉ／ｏ）装置、ディレクトリ構造、及びコヒーレンシポイントを有する、キャッシュコヒーレントｎｏｃ（ネットワークオンチップ）
CN113632069A (zh) * 2019-03-27 2021-11-09 赛灵思公司 自适应集成可编程设备平台
JP2022527760A (ja) * 2019-03-27 2022-06-06 ザイリンクス インコーポレイテッド 適応型集積プログラマブルデバイスプラットフォーム
JP7581230B2 (ja) 2019-03-27 2024-11-12 ザイリンクス インコーポレイテッド 適応型集積プログラマブルデバイスプラットフォーム
CN113632069B (zh) * 2019-03-27 2024-11-19 赛灵思公司 自适应集成可编程设备平台
US12261603B2 (en) 2019-03-27 2025-03-25 Xilinx, Inc. Adaptive integrated programmable device platform

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EP1770541A1 (en) 2007-04-04
US7382154B2 (en) 2008-06-03
US20070075734A1 (en) 2007-04-05

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