JP2007129086A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance a breakdown voltage of a semiconductor device formed with a trench isolation film. <P>SOLUTION: In an element region, p-type semiconductor pillar layers 13 and n-type semiconductor pillar layers 14 are alternately formed to form a pillar layer 15. In an end region surrounding the element region, a trench isolation film 31 is formed, and inside and outside of the trench isolation film 31 also, p-type semiconductor pillar layers 13A and n-type semiconductor pillar layers 14A are formed. The first side 31A and the second side 31B of the trench isolation film 31 intersect at about 45° in the longitudinal direction of the pillar layers 13, 14. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a termination structure surrounding an element region.

  In semiconductor elements such as power MOSFETs, there is a trade-off relationship between element breakdown voltage and on-resistance. It is an important issue to improve this trade-off and to provide a semiconductor element with high breakdown voltage and low on-resistance. is there. As an example of a MOSFET that solves this problem, there is known a structure in which a p-type pillar layer and an n-type pillar layer each having a strip-shaped cross section called a super junction structure are alternately embedded in a drift layer in a lateral direction (for example, Patent Documents). 1). The super junction structure makes the charge amount (impurity amount) contained in the p-type pillar layer and the n-type pillar layer the same, thereby creating a pseudo non-doped layer, maintaining a high breakdown voltage, and highly doped n-type. By passing a current through the pillar layer, a low on-resistance exceeding the material limit is realized.

On the other hand, such a semiconductor device includes an element region in which a source region and a gate electrode of a MOSFET are formed, and a termination region surrounding the device region. In order to increase the breakdown voltage of the element, various termination region structures have been proposed. For example, a termination region structure is known in which a termination trench surrounding an element region is formed in the termination region, and a trench insulating film is buried in the termination trench (see, for example, Patent Document 2).
JP 2001-15744 A JP 2002-170955 A

  An object of the present invention is to provide a semiconductor device in which the breakdown voltage of a semiconductor device in which a trench insulating film is formed in a termination region is improved.

  A semiconductor device according to one aspect of the present invention includes a first semiconductor layer of a first conductivity type, a first semiconductor pillar layer of a first conductivity type, and a second semiconductor pillar layer of a second conductivity type. A pillar layer formed alternately in a stripe shape in a first direction along the surface of the semiconductor layer, a semiconductor element formed on the pillar layer, and a boundary between an element region in which the semiconductor element is formed and a termination region And a trench insulating film embedded in the termination trench to insulate and isolate the element region and the termination region, and the termination trench has at least a first side and a second side intersecting each other. And the first direction is formed to intersect the first side and the second side at an acute angle.

  According to the present invention, it is possible to provide a semiconductor device in which the breakdown voltage of the semiconductor device in which the trench insulating film is formed in the termination region is improved.

  Next, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a plan view of the semiconductor device according to the present embodiment, and FIG. 2 is a cross-sectional view taken along line A-A ′ in FIG. 1. In FIG. 1, the gate electrode and the like to be described later are not shown for simplification.

  As shown in FIG. 1, pillars as a super junction structure in which p-type semiconductor pillar layers 13 and n-type semiconductor pillar layers 14 are alternately formed in the element region of the semiconductor device of the present embodiment. A MOSFET having a layer 15 is formed. In the termination region surrounding the element region, a trench insulating film 31 is formed in a substantially square shape as shown in FIG. Further, on the inner side and the outer side of the trench insulating film 31, a p-type semiconductor pillar layer 13 and a p-type semiconductor pillar layer 13A and an n-type semiconductor pillar layer 14B similar to the n-type semiconductor pillar layer 14 are substantially provided over the entire circumference. A uniform width is formed. Thus, it is preferable to form the pillar layers 13A and 14A adjacent to the trench insulating film 31 in order to improve the device breakdown voltage. The adjacent pillar layers 13A and 14A are preferably formed with a uniform width over the entire circumference of the trench insulating film 31 surrounding the element region in order to improve the element breakdown voltage.

  The p-type semiconductor pillar layers 13 and 14 formed in the element region are approximately about the first side 31A and the second side 31B (substantially orthogonal to the first side) of the trench insulating film 31 formed in a substantially square shape. It extends with the 45 degree direction as the longitudinal direction. In other words, the pillar layers 13 and 14 are formed so that the two sides 31A and 13B intersecting the trench insulating film 31 have a longitudinal direction in a direction intersecting at the same angle.

  As shown in the A-A ′ cross-sectional view of FIG. 2, the pillar layer 15 is formed on the n + -type drain layer 11 by a process described later. A drain electrode 10 is formed on the back surface of the drain layer 11. A p-type base layer 16 is formed on the pillar layer 15, and an n + -type source layer 17 of the MOSFET is formed on the p-type base layer 16. A gate electrode 19 is formed on a p-type base layer 16 (channel) sandwiched between the n + -type source layer 17 and the n-type pillar layer 14 via a gate insulating film 18. The n + type source layer 17 and the p type base layer 16 are electrically connected to the source electrode 20. The source electrode 20 includes a field plate electrode 21 extended to the termination region in order to extend the depletion layer in the lateral direction and improve the breakdown voltage when the MOSFET is not conducting. A field plate insulating film 32 is formed between the field plate electrode 21 and the pillar layer 15. When a predetermined gate voltage is applied to the gate electrode 18, an inversion layer is formed in the p-type base layer 17 directly below the gate electrode 19, that is, the channel, and the drain and source of the MOSFET are conducted. Since the formation process of these MOSFETs is well known, detailed description thereof is omitted.

  A trench T1 is formed at the boundary between the element region where the MOSFET is formed and the termination region, and a trench insulating film 31 is formed in the trench T1 via the insulating film 30. As described above, the longitudinal directions of the pillar layers 13 and 14 in the element region intersect at an acute angle of about 45 degrees with respect to the first side 31A and the second side 31B of the trench insulating film 31 formed in a substantially square shape. . In other words, each of the pillar layers 13 and 14 is formed so as to have a longitudinal direction in a direction that forms substantially the same acute angle with respect to the two intersecting sides 31A and 31B of the trench insulating film 31. In this respect, in the conventional semiconductor device, the arrangement direction of the pillar layers in the element region and the direction of one side of the rectangular trench insulating film are different from each other. With such an arrangement relationship, the pillar layers 13A and 14A along the trench insulating film 31 can be formed simultaneously with the pillar layers 13 and 14 formed in the element region in one process and over the entire circumference. Therefore, it is possible to form a substantially uniform width. In the case of the configuration of the prior art, a similar pillar layer is formed for the element isolation trench parallel to the pillar layer in the element region, while ion implantation is performed for the element isolation trench perpendicular to the pillar layer in the element region. Not enough and therefore no pillar layer is formed. For this reason, a uniform pn pillar layer could not be formed around the trench insulating film.

  Next, the manufacturing process of the semiconductor device of the present embodiment will be described with reference to FIGS. First, as shown in FIG. 3, an n-type epitaxial layer 12 is grown on an n + -type substrate that becomes the n + -type drain layer 11. Next, as shown in FIG. 4, a trench T1 for embedding the trench insulating film 31 and a trench T2 for forming the pillar layer 15 in the element region are formed in the n-type epitaxial layer 12 by using a photolithography method. To do. Subsequently, as shown in FIG. 5, arsenic (As) and boron (B) are ion-implanted into the side surfaces of the trenches T1 and T2. The angle of ion implantation with respect to the trench T2 is, for example, about 5 ° to 7 °. For the trench T1, the same ion implantation is performed at the same time, although the implantation angle is different from the implantation angle for the trench T2.

  Thereafter, heat treatment is performed at 1150 ° C. for about 24 hours to simultaneously diffuse As and B from both sides of the n-type epitaxial layer 12 having a mesa structure sandwiched between the trenches T1 and T2. At this time, since the diffusion coefficient of B is about one digit larger than the diffusion coefficient of As, as shown in FIG. 6, in the central part of the n-type epitaxial layer 2 having a mesa structure divided by the trenches T1 and T2, A strip-shaped p-type semiconductor pillar layer 13 is formed by B having a large diffusion coefficient, and a strip-shaped n-type semiconductor pillar layer 14 is formed in a self-aligned manner on the surface side of the mesa structure.

  On the other hand, the side surface of the trench T1 is ion-implanted at an ion implantation angle different from that for the trench T2, but the two orthogonal sides of the trench T1 are implanted under the same conditions. Therefore, the pillar layers 13A and 14A formed on the side surfaces of the trench T1 also have a uniform thickness over the entire circumference.

  Subsequently, as shown in FIG. 7, p-type silicon having the same impurity concentration as that of the p-type semiconductor pillar layer 13 formed in the mesa structure is epitaxially grown in the trench T2 to fill the trench T2. Thereby, the pillar layer 15 in the element region, that is, the super junction structure is completed. Further, as shown in FIG. 8, after the insulating film 30 is formed on the side surface of the trench T1 by sputtering or the like, a solution containing silica particles is applied to fill the trench T1. Thereafter, the components of the MOSFET are formed by using a known photolithography method, ion implantation, CVD method or the like, thereby completing the MOSFET as shown in FIG.

  According to the process described above, the pillar layers 13 and 14 constituting the super junction structure in the element region are formed, and at the same time, the pillar layers 13A and 14A around the trench insulating film 31 are formed. Moreover, since the direction of the trench T1 is set as described above, the pillar layers 13A and 14A can be formed substantially uniformly over the entire circumference of the trench T1.

  The embodiment of the invention has been described above, but the present invention is not limited to this, and various substitutions, diversions, additions, deletions, and the like are possible without departing from the spirit of the invention. For example, in the above embodiment, the longitudinal direction of the pillar layers 13 and 14 intersects the two sides of the trench insulating film 31 at the same angle (for example, 45 °), but the angle intersecting the two sides is If it is an acute angle, the two angles need not be exactly the same. Further, for example, in the above-described embodiment, the trench insulating film 31 has a square shape, but as shown in FIG. 9, it can also have a rectangular shape with one side being long. Further, as shown in FIG. 10, the sides constituting the trench insulating film 31 may partially intersect at an acute angle (θ <90 °). In this case, the pillar layer 15 extends in the direction of the bisector (θ / 2) of the angle θ so that the longitudinal direction of the pillar layer 15 in the element region intersects the two sides at substantially the same angle. By arranging them, the pillar layers 13 and 14 in the element region and the pillar layers 13A and 14A on both sides of the trench insulating film 31 can be formed simultaneously and with a uniform thickness. In the above embodiment, the planar type MOSFET is formed in the element region. However, the present invention can also be applied to the case where a trench gate type MOSFET, IGBT, or the like is formed. .

1 is a plan view of a semiconductor device according to an embodiment of the present invention. It is A-A 'sectional drawing of FIG. 2 shows a manufacturing process of the semiconductor device of FIG. 2 shows a manufacturing process of the semiconductor device of FIG. 2 shows a manufacturing process of the semiconductor device of FIG. 2 shows a manufacturing process of the semiconductor device of FIG. 2 shows a manufacturing process of the semiconductor device of FIG. 2 shows a manufacturing process of the semiconductor device of FIG. The modification of embodiment of this invention is shown. The modification of embodiment of this invention is shown.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Drain electrode, 11 ... N + type drain layer, 12 ... N type epitaxial layer, 13 ... P type semiconductor pillar layer, 14 ... N type semiconductor pillar layer, 15 ... Pillar 16 ... p-type base layer 17 ... n + type source layer 18 ... gate insulating film 19 ... gate electrode 20 ... field plate electrode 30 ... insulating film 31 ... trench insulating film, 32 ... insulating film.

Claims (5)

A first semiconductor layer of a first conductivity type;
A pillar layer formed by alternately forming a first semiconductor pillar layer of a first conductivity type and a second semiconductor pillar layer of a second conductivity type in a stripe shape in a first direction along the surface of the first semiconductor layer; ,
A semiconductor element formed on the pillar layer;
A termination trench formed at a boundary between an element region in which the semiconductor element is formed and a termination region;
A trench insulating film embedded in the termination trench and insulatingly separating the element region and the termination region;
The termination trench includes at least a first side and a second side that intersect each other, and the first direction is formed so as to form an acute angle between the first side and the second side. apparatus.   The semiconductor device according to claim 1, wherein an angle formed by the first direction with the first side and an angle formed by the first direction with the second side are substantially the same.   2. The semiconductor device according to claim 1, wherein the first side and the second side are orthogonal to each other, and the first direction forms an angle of 45 ° with the first side and the second side. In the pillar layer, an epitaxial layer is formed on the first semiconductor layer, trenches are formed in the epitaxial layer at a predetermined interval, and then a first conductivity type impurity and a second conductivity type impurity are formed on a wall surface of the trench. Is formed by thermal diffusion after being implanted at a predetermined implantation angle by an ion implantation method,
The semiconductor device according to claim 1, wherein the termination trench is formed by embedding an insulating film after being subjected to ion implantation and thermal diffusion by the ion implantation method.   The semiconductor device according to claim 1, wherein a pillar layer similar to the element region is formed on a wall surface of the termination trench.

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