JP2007123309A - Digital signal processing substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem wherein it is difficult to reduce the size, thickness and cost by a digital noise countermeasure, and to provide a digital signal processing substrate in which reduction in size, thickness and cost is achieved through digital noise reduction. <P>SOLUTION: The digital signal processing substrate comprises an LSI 16, a power supply input line 18 for supplying power thereto, and a decoupling capacitor connected between the power supply input line 18 and the earth. A surface mounting solid electrolytic capacitor 19 having ESR of 25 mΩ (100 kHz) or less and ESL of 800 pH (500 MHz) or less, is employed as the decoupling capacitor. Generation of digital noise is reduced sharply by connecting the earth of the solid electrolytic capacitor 19 and the earth of the LSI 16 on the same plane thus achieving reduction in size, thickness and cost simultaneously. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a digital signal processing board used for various electronic devices.

  In recent years, the digitization of home appliances has progressed rapidly, and this tendency is particularly prominent in the audio / video field. One of the technologies that support such digital home appliances is digital signal processing technology that converts analog signals into digital signals and compresses them, and uses this technology to process a large number of signals at high speed. is there.

  FIG. 9 is a circuit diagram showing the basic configuration of this type of conventional digital signal processing board. In FIG. 9, 25 is an LSI, 26 is a power source, 27 is a power input line connecting the power source 26 and the LSI 25, 28 is a solid electrolytic capacitor as a decoupling capacitor connected between the power input line 27 and the ground, 29 is a DC / DC converter connected to the power input line 27, and 30 and 31 are inputs of the DC / DC converter 29. A smoothing capacitor 32 connected between the power input line 27 on the output side and the output side and the ground, and a capacitor for noise removal described later.

  With the conventional digital signal processing board configured as described above, the clock that is the operating frequency of the LSI 25 is also speeded up along with the speeding up of the equipment in which the LSI 25 is used. Since the power consumption increases as the speed of the LSI 25 increases, the power supply 26 is often driven at a low voltage by reducing the voltage of the power supply 26 so as to suppress the power consumption and minimize the heat generation.

  Therefore, the LSI 25 driven at a low voltage is easily affected by the fluctuation of the load. For this reason, when a sharp power consumption occurs in the LSI 25 due to the fluctuation of the load, a current is supplied from the solid electrolytic capacitor 28 to the LSI 25. It was comprised so that the electric power feeding voltage to could be kept stable.

If the ESR value of the solid electrolytic capacitor 28 is R, the ESL value is L, and the current supplied from the solid electrolytic capacitor 28 to the LSI 25 is i,
V = R * i + L * di / dt
A voltage drop occurs by V indicated by. That is, when ESR and ESL are increased, the power supply voltage to the LSI 25 cannot be sufficiently guaranteed.

As prior art document information related to the invention of this application, for example, Patent Document 1 is known.
JP 2003-133177 A

  However, the conventional digital signal processing board generates digital noise as shown in the frequency characteristic diagram of FIG. 10 in order to compress and process a large amount of signals at high speed. In order to reduce this digital noise, a large amount of noise removing capacitor 32 (generally a multilayer ceramic capacitor is used between the LSI 25 and the ground as shown in the circuit diagram of FIG. ) And the capacitor 32 for reducing digital noise must use 30 or more capacitors 32 for one LSI 25. Therefore, the LSI 25 has a large amount of capacitors 32 mounted thereon. Must be mounted near the printed circuit board, resulting in a digital signal processing board Stratified to cost up from the fact that must be increased in size there is a problem that is inevitable.

  In addition, since the digital noise can be evaluated only after the digital signal processing board is completed, the capacitor 32 for reducing the digital noise can only be selected by cut-and-try. In addition, there was a problem that it placed a heavy burden on the development schedule and costs.

  Furthermore, with the ESR and ESL characteristics of the solid electrolytic capacitor 28 used as the decoupling capacitor, it is necessary to guarantee the power supply voltage necessary for driving the LSI 25 against the steep power consumption of the LSI 25 driven at a low voltage. Naturally, there was a limit, and there was a problem that the solid electrolytic capacitor 28 needed to be further reduced in ESR and ESL.

  The present invention solves such a conventional problem, reduces the size and thickness by reducing the occurrence of digital noise, and reduces the power consumption of an LSI driven at a low voltage. Another object of the present invention is to provide a digital signal processing board that can guarantee a sufficient power supply voltage.

  In order to solve the above problems, the present invention provides an LSI to which an element for clock operation is connected, a power input line for supplying power to the LSI, a decoupling capacitor connected between the power input line and ground. In the digital signal processing board having at least, a surface mount type solid electrolytic capacitor having an ESR of 25 mΩ (100 kHz) or less and an ESL of 800 pH (500 MHz) or less is used as the decoupling capacitor. It is configured to be connected to the ground on the same plane as the ground of the LSI.

  As described above, the digital signal processing board according to the present invention uses a low ESR, low ESL solid electrolytic capacitor as a decoupling capacitor, and the ground of the solid electrolytic capacitor is connected to the ground on the same plane as the ground of the LSI. The configuration can greatly reduce the generation of digital noise, eliminating the need to connect a large number of capacitors for reducing digital noise as in the past, and achieving both a small size and a low price at the same time. The effect of becoming like this is acquired.

(Embodiment 1)
Hereinafter, the first and second aspects of the present invention will be described with reference to the first embodiment.

1 is a circuit diagram showing a configuration of a digital signal processing board according to Embodiment 1 of the present invention, and FIG.
FIGS. 1A and 1B are cross-sectional views of the main part of the multilayer substrate on which the circuit is formed. In FIGS. 1 and 2, 16 is an LSI, 17 is a power source, and 18 (Vcc in FIG. 2) is the power source 17. And a power input line 19 connecting the LSI 16 and a solid electrolytic capacitor 19 as a decoupling capacitor connected between the power input line 18 and the ground. The ground of the solid electrolytic capacitor 19 is a surface to which the ground of the LSI 16 is connected. By connecting to the same surface as (G1 in FIG. 2 (a)), it is connected to the same ground at the shortest distance to suppress generation of unnecessary impedance.

  20 is a DC / DC converter connected to the power input line 18 on the input side of the solid electrolytic capacitor 19 as the decoupling capacitor, and 21 and 22 are power input lines on the input side and output side of the DC / DC converter 20. The input capacitor 21 and the output smoothing capacitor are respectively connected between 18 and the ground, and the ground of the input capacitor 21 is the same as the surface (G1 in FIG. 2B) to which the ground of the DC / DC converter 20 is connected. By connecting to the same, it is connected to the same ground at the shortest distance to suppress generation of unnecessary impedance. Reference numeral 23 denotes a noise removing capacitor.

  Further, the solid electrolytic capacitor 19 and the output smoothing capacitor 22 as the decoupling capacitor are surface mount type solid electrolytic capacitors using a conductive polymer as a solid electrolyte, and the characteristics thereof are ESR of 25 mΩ (100 kHz). In the following, ESL is 800 pH (500 MHz) or less and a rating of 6.3 V 47 μF is used.

  In this way, the low ESR and low ESL solid electrolytic capacitors 19 and 22 are used, the ground of the solid electrolytic capacitor 19 is flush with the ground of the LSI 16, and the ground of the input capacitor 21 is grounded of the DC / DC converter 20. The configuration connected to the same plane can sufficiently ensure the supply voltage required to drive the LSI 16 and is generated by the clock required to synchronize the LSI 16 that transmits the power input line 18. Since high-frequency radiation noise and switching noise generated from the switching elements constituting the DC / DC converter 20 can be efficiently drawn into the ground layer of the substrate via the solid electrolytic capacitors 19 and 22 and the input capacitor 21, High-frequency radiation noise transmitted through the input line 18 In which it is possible to greatly reduce the fine switching noise from the power input line 18.

  FIG. 3 is a frequency characteristic diagram showing the digital noise of the digital signal processing board according to the present embodiment. As is clear from the frequency characteristic diagram shown in FIG. Not only can this be greatly reduced, but the number of noise removing capacitors 23 connected between the LSI 16 and the ground can be reduced to about 1/2 to 1/3.

  As described above, the digital signal processing board according to the present embodiment not only can greatly reduce digital noise by using a low ESR and low ESL solid electrolytic capacitor as a decoupling capacitor and an output smoothing capacitor. Therefore, it is possible to greatly contribute to the reduction in size and thickness by reducing the number of capacitors for removing digital noise.

  FIG. 4 shows an example in which the ground of the solid electrolytic capacitor 19 as a decoupling capacitor is not connected to the same plane as the ground of the LSI 16, and the ground of the LSI 16 is placed on the ground layer indicated by G1. The ground of 19 is connected to the ground layer indicated by G2, but when connected to such a different ground layer, the circuit length becomes longer and the impedance becomes higher, and the effect of reducing the digital noise is reduced. Therefore, it is not preferable.

  In the present embodiment, a description has been given of a configuration in which a solid electrolytic capacitor having a low ESR and a low ESL is used only for the solid electrolytic capacitor 19 and the output smoothing capacitor 22 as a decoupling capacitor. A solid electrolytic capacitor with low ESR and low ESL may be used.

(Embodiment 2)
Hereinafter, the second and second embodiments of the present invention will be described.

  5A to 5D are a plan sectional view, a front sectional view, a bottom sectional view, and a side sectional view showing a configuration of a solid electrolytic capacitor used in a digital signal processing board according to a second embodiment of the present invention. 6 is a partially cutaway perspective view showing the configuration of a capacitor element used in the solid electrolytic capacitor, and FIG. 7 is a main portion showing the configuration of an anode comb terminal and a cathode comb terminal used in the solid electrolytic capacitor. FIG. 8A to FIG. 8C show a cross section AA, a cross section BB, and a cross section CC in FIG. 7, respectively.

  5 to 8, reference numeral 1 denotes a capacitor element. The capacitor element 1 is an insulating resist after the surface of an anode body 2 made of an aluminum foil, which is a valve metal, is roughened to form an anodized film layer. By providing the portion 3, the anode portion 4 and the cathode forming portion 5 are separated, and the cathode portion is formed by sequentially laminating a solid electrolyte layer 6 and a cathode layer 7 made of carbon and silver paste on the surface of the cathode forming portion 5. It is formed and configured.

  Reference numeral 8 denotes an anode comb frame. The anode portion 4 is placed in a state where a plurality of the capacitor elements 1 (5 in the present embodiment) are stacked on the anode comb frame 8, and the guide portions 8a at both ends are placed. The anode part 4 is wrapped and bent, and laser welding is performed at the joining part 8b to join together.

  Reference numeral 9 denotes a cathode comb frame. A plurality of the capacitor elements 1 are stacked on the cathode comb frame 9 and a cathode portion is placed via a conductive adhesive (not shown). A plurality of capacitor elements 1 are laminated and integrated by the anode comb frame 8 and the cathode comb frame 9 in this manner, and fixed and fixed by the guide portion 9b. Called a unit.

  Reference numeral 10 denotes an anode comb terminal. The anode comb terminal 10 is tapered at both ends in a direction intersecting with a direction connecting to a cathode comb terminal 11 described later so as to extend obliquely upward from a lower surface serving as a mounting surface. A planar joining surface 10a joined to the anode comb frame 8 through a gap is provided so as to form a stepped step (FIG. 8 (a)), and the mounting surface toward the cathode comb terminal 11 is provided. A shielding portion 10b in which a flat portion 10g is formed via a taper portion 10f provided so as to extend obliquely upward from the lower surface is provided so as to form a stepped step (FIG. 8C). These are integrally formed by punching a single substrate and bending it. The anode comb frame 8 of the capacitor element unit is placed on the joint surface 10a, and a laser is produced at the joint 10c. It is obtained by bonding by performing contact. Reference numeral 10d denotes a projecting portion that extends from one end of the lower surface of the anode comb terminal 10 so as to project from an exterior resin 12 to be described later. This projecting portion 10d is bent upward along the side surface of the exterior resin 12. It is what.

  Reference numeral 11 denotes a cathode comb terminal. The cathode comb terminal 11 is formed so that a lower surface as a mounting surface is formed in substantially the same shape as the cathode portion of the capacitor element 1 so as to be as close as possible to the anode comb terminal 10. The cathode comb is connected to a part of both ends in a direction intersecting with the direction connecting the anode comb terminal 10 via a taper portion 11f provided so as to extend obliquely upward from a lower surface serving as a mounting surface. A planar joining surface 11a joined to the frame 9 is provided so as to form a stepped step (FIG. 8 (b)), and obliquely upward from the lower surface serving as a mounting surface in the direction of the anode comb terminal 10. A shielding part 11b formed with a flat surface part 11h is provided so as to form a stepped step through a taper part 11g provided so as to extend to the side, and these are punched and bent by one base material. And it is formed integrally by, placing a cathode comb frame 9 of the capacitor element unit on the bonding surface 11a, which are joined by performing the laser welding at the joint 11c. Reference numerals 11d and 11e are protrusions extending from one end of the lower surface of the cathode comb terminal 11 so as to protrude from an exterior resin 12 which will be described later. The protrusions 11d and 11e extend along the side surface of the exterior resin 12. It is bent upward.

  Reference numeral 12 denotes an insulating exterior resin that integrally covers the capacitor element unit in a state in which the lower surfaces serving as the mounting surfaces of the anode comb terminal 10 and the cathode comb terminal 11 are exposed. In this embodiment, an epoxy resin is used. It was.

  13 is a conductive silver paste interposed in a gap formed between the cathode comb frame 9 and the cathode comb terminal 11 of the capacitor element unit bonded to the bonding surface 11a provided on the cathode comb terminal 11, The purpose is to increase the connection reliability and reduce the connection resistance.

  A plurality of anode comb terminals 10 and cathode comb terminals 11 thus configured are continuously provided at a predetermined interval on a hoop-like base material made of a copper alloy. The capacitor element unit is mounted on the comb terminal 11 and joined, and after being integrally covered with the outer layer resin 12, it is divided from the base material into individual pieces.

  The tapered portion 10e and the joining surface 10a provided on the anode comb terminal 10, the shielding portion 10b including the tapered portion 10f and the flat portion 10g, and the tapered portion 11f provided on the cathode comb terminal 11 and the joining surface 11a and the tapered portion 11g. The shielding portion 11b composed of the flat portion 11h is covered with the exterior resin 12 so as not to be exposed to the appearance, and thus the flat portion is provided stepwise through the tapered portion. Since it becomes difficult to form R at the boundary with the lower surface that becomes the mounting surface of each comb terminal, it is possible to prevent the exterior resin 12 from wrapping around the lower surface that becomes the mounting surface of each comb terminal. It will be like that.

  The solid electrolytic capacitor according to the present embodiment configured as described above is configured such that the anode part 4 and the cathode part of the capacitor element 1 are taken out by the substantially flat plate-like anode comb terminal 10 and cathode comb terminal 11. The lead-out distance from the capacitor element 1 to each terminal is shortened as much as possible, and the lower surface of the cathode comb terminal 11 is brought as close as possible to the lower surface of the anode comb terminal 10 so as to be between the anode comb terminal 10 and the cathode comb terminal 11. By adopting a configuration in which the path is the shortest distance, the ESR characteristic is excellent and the low ESL can be realized. In particular, with respect to the ESL characteristic, the solid electrolytic capacitor according to the present embodiment has a pH of 500 pH. As a result, it is possible to obtain a good result that is 1/3 compared with 1500 pH of the conventional example.

  Further, joining surfaces 10a and 11a are respectively provided on the anode comb terminal 10 and the cathode comb terminal 11, and the anode comb frame 8 and the cathode comb frame 9 are joined to each other by laser welding at the joining surfaces 10a and 11a. 10a and 11a are each covered with the exterior resin 12, so that the weld marks resulting from the joining are covered with the exterior resin 12, so that the appearance is not only beautiful, but the weld marks cause floating during mounting, resulting in poor mounting. There is no fear of causing any problems, and it can greatly contribute to the improvement of reliability.

  The anode comb terminal 10 and the cathode comb terminal 11 are respectively provided with shielding portions 10b and 11b extending obliquely upward from the lower surface end surfaces of the anode comb terminal 10 and the cathode comb terminal 11 toward the counterpart comb terminal, With the configuration in which the shielding portions 10b and 11b are respectively covered with the exterior resin 12, it becomes possible to greatly reduce the moisture contained in the oxygen entering from the exterior resin 12 reaching the capacitor element 1 and adversely affecting it. It will be possible to contribute to the improvement of reliability.

  In the present embodiment, the anode body 2 constituting the capacitor element 1 has been described by taking an example of a configuration made of an aluminum foil. However, the present invention is not limited to this, and a tantalum or niobium foil, Alternatively, a sintered body or a combination of these materials may be used.

  The characteristics and the like of the solid electrolytic capacitor according to the present embodiment configured as described above will be described below.

  Using the solid electrolytic capacitor manufactured in this embodiment, the equivalent series resistance value (ESR) is changed, and the capacitance, the tangent of the loss angle, the equivalent series inductance (ESL), the leakage current (10 V applied, two-minute value) (Table 1) shows the results of measuring the initial characteristics of). A solid electrolytic capacitor with a rating of 6.3 V 47 μF was used.

  As is clear from Table 1, it can be seen that the capacitor 23 for removing digital noise can be efficiently reduced by setting the ESR to 25 mΩ or less.

  Further, by using the solid electrolytic capacitor manufactured in this embodiment, the distance between the anode comb terminal and the cathode comb terminal (the part indicated by the symbol L in FIG. 3) is changed, and the capacitance, the tangent of the loss angle, and the equivalent Table 2 shows the results of measuring initial characteristics of series resistance value (ESR), equivalent series inductance (ESL), and leakage current (10 V applied, binary value).

  As is clear from Table 2, the ESL value decreases by shortening the distance between the anode comb terminal and the cathode comb terminal, and the ESL becomes 800 pH or less by reducing the distance between both terminals to 2 mm or less. Thus, the capacitor 23 for removing digital noise can be efficiently reduced as in the above (Table 1).

  As described above, since the generation of digital noise can be greatly reduced by using the solid electrolytic capacitor of the present invention for the decoupling capacitor and the output smoothing capacitor, the conventional digital noise removing capacitor can be reduced and the size can be reduced. Thinning and price reduction can be realized at the same time.

  The digital signal processing board according to the present invention not only can greatly reduce digital noise, but also greatly reduces the number of capacitors for removing digital noise and can greatly contribute to reduction in size and thickness and cost. It is useful for all household electrical appliances that have digital signal processing, especially for television.

1 is a circuit diagram showing the configuration of a digital signal processing board according to Embodiment 1 of the present invention. (A), (b) principal part sectional drawing of the multilayer substrate in which the circuit was formed Frequency characteristics diagram showing digital noise characteristics of the digital signal processing board Cross-sectional view of the main part showing an example when the same ground is not connected to the same surface (A) Plan sectional drawing which showed the composition of the solid electrolytic capacitor used for the digital signal processing board by Embodiment 2 of the present invention, (b) The front sectional view, (c) The bottom sectional view, (d) Cross-sectional side view Partially cutaway perspective view showing the configuration of a capacitor element used in the solid electrolytic capacitor Main part perspective view showing the configuration of an anode comb terminal and a cathode comb terminal used in the solid electrolytic capacitor (A) AA sectional view in FIG. 7, (b) BB sectional view, (c) CC sectional view Circuit diagram showing the configuration of a conventional digital signal processing board Frequency characteristics diagram showing digital noise characteristics of a conventional digital signal processing board

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Capacitor element 2 Anode body 3 Resist part 4 Anode part 5 Cathode formation part 6 Solid electrolyte layer 7 Cathode layer 8 Anode comb frame 8a, 9a, 9b Guide part 8b, 10c, 11c Junction part 9 Cathode comb frame 10 Anode comb terminal 10a , 11a Joint surface 10b, 11b Shielding part 10d, 11d, 11e Protruding part 10e, 10f, 11f, 11g Taper part 10g, 11h Flat part 11 Cathode comb terminal 12 Exterior resin 13 Conductive silver paste 16 LSI
17 Power Supply 18 Power Input Line 19 Solid Electrolytic Capacitor 20 DC / DC Converter 21 Input Capacitor 22 Output Smoothing Capacitor 23 Noise Eliminating Capacitor

Claims (4)

In a digital signal processing board having at least an LSI to which an element for clock operation is connected, a power input line for supplying power to the LSI, and a decoupling capacitor connected between the power input line and the ground, As a decoupling capacitor, a surface mount type solid electrolytic capacitor having an ESR of 25 mΩ (100 kHz) or less and an ESL of 800 pH (500 MHz) or less is used, and the ground of the solid electrolytic capacitor is the same as the surface to which the LSI ground is connected. Digital signal processing board connected to. The DC / DC converter to which the clock operation element is connected is connected to the power supply input line on the input side of the decoupling capacitor, and input is made between the power supply input lines on the input side and output side of the DC / DC converter and the ground. A capacitor and an output smoothing capacitor are respectively connected. As the output smoothing capacitor, a surface mount type solid electrolytic capacitor having an ESR of 25 mΩ (100 kHz) or less and an ESL of 800 pH (500 MHz) or less is used. The digital signal processing board according to claim 1, wherein the digital signal processing board is connected to the same surface as the surface to which the ground of the DC converter is connected. A surface mounting type solid electrolytic capacitor used as a decoupling capacitor and an output smoothing capacitor includes a capacitor element using a conductive polymer as a solid electrolyte, an anode comb terminal joined to an anode part and a cathode part of the capacitor element, and A cathode comb terminal and an insulating comb resin covering the capacitor element with the anode comb terminal and the lower surface on which the cathode comb terminal is mounted exposed, respectively. The anode comb terminal and the cathode comb exposed on the lower surface The digital signal processing board according to claim 1 or 2, wherein a distance between terminals is 2 mm or less. A plurality of capacitor elements are stacked, and an anode comb frame and a cathode comb frame are joined to the anode part and the cathode part, respectively, to form a capacitor element unit. The anode comb frame and the cathode comb frame of the capacitor element unit are respectively connected to the anode comb terminal. And a solid electrolytic capacitor having a structure bonded to the cathode comb terminal, and upward at least a part of both ends of the anode comb terminal and the cathode comb terminal in a direction intersecting with the direction connecting the anode comb terminal and the cathode comb terminal. A stepped step is formed to form a flat joint surface that is joined to the anode comb frame and the cathode comb frame, and the lower surface of the cathode comb terminal is formed in substantially the same shape as the cathode portion of the capacitor element. Shielding portions that extend diagonally upward from the lower end of the comb terminal and the cathode comb terminal toward the corresponding comb terminal are shaded with the anode comb terminal. Provided integrally with the lead terminal, a digital signal processing board according to claim 3 which is adapted the joining surfaces as well as the shielding part is coated exterior resin.

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