JP2007116617A - Pll circuit and radio communication device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a noise which is generated in the operation of a charge pump circuit while the complication of a circuit structure is suppressed. <P>SOLUTION: A base band part 2 outputs a control signal CS1 to a PLL circuit 4 while transmission data MS1 is transmitted. The PLL circuit 4 stops the operation of the charge pump circuit contained in the PLL circuit 4 based on the control signal CS1 sent from the base band part 2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a PLL circuit and a wireless communication apparatus, and is particularly suitable for application to a method for reducing noise generated in a PLL circuit.

In the frequency multiplication circuit, in order to obtain a stable high-frequency clock signal, the clock of the crystal oscillator is multiplied by a PLL circuit.
Further, for example, in Patent Document 1, in order to realize a stable filter output voltage without ripple, a phase difference signal detected by a frequency phase comparison method is received, and this signal is converted into a smooth current or a smooth voltage, A method is disclosed in which a phase-synchronizing circuit is provided with a charge pump circuit that can hold the value until the next phase difference signal is input.
JP-A-5-75451

However, in general PLL circuits, phase synchronization is always performed, and in particular, there is a problem that the control voltage of the voltage controlled oscillator fluctuates due to the operation of the charge pump circuit and causes noise (jitter).
Further, in the method disclosed in Patent Document 1, in order to smooth the phase difference signal detected by the frequency phase comparison method and hold the value, not only the circuit becomes complicated, but also for each phase comparison. There is a problem that the noise generated in the system cannot be completely removed.

  Therefore, an object of the present invention is to provide a PLL circuit and a wireless communication apparatus that can reduce noise generated due to the operation of the charge pump circuit while suppressing the complexity of the circuit configuration.

  In order to solve the above-described problem, according to a PLL circuit according to one aspect of the present invention, a voltage-controlled oscillator that controls an oscillation frequency of a clock signal based on a control voltage and a clock signal from the voltage-controlled oscillator are separated. A frequency divider that circulates, a phase comparison circuit that outputs a signal corresponding to a phase shift between a clock signal output from the frequency divider and a reference clock, and the signal output from the phase comparison circuit And a charge pump circuit that generates a control voltage and stops the operation while maintaining the control voltage based on a control signal input from the outside.

As a result, when the system incorporating the PLL circuit is operating, the operation of the charge pump circuit can be stopped without impairing the phase synchronization function with respect to the reference clock. For this reason, it is possible to reduce noise generated due to the operation of the charge pump circuit while suppressing the complexity of the circuit configuration.
According to the PLL circuit of one aspect of the present invention, the voltage controlled oscillator that controls the oscillation frequency of the clock signal based on the control voltage, and the clock signal from the voltage controlled oscillator are divided and input from the outside. A frequency divider that stops the operation based on the control signal, a signal corresponding to a phase shift between the clock signal output from the frequency divider and the reference clock, and an operation based on the control signal And a charge pump circuit that generates the control voltage based on the signal output from the phase comparison circuit and stops the operation while holding the control voltage based on the control signal. It is characterized by that.

Thereby, when the system incorporating the PLL circuit is operating, the operations of the frequency divider, the phase comparison circuit, and the charge pump circuit can be stopped without impairing the phase synchronization function with respect to the reference clock. For this reason, it is possible to reduce noise generated due to the operation of the charge pump circuit while suppressing the complexity of the circuit configuration.
According to the PLL circuit of one aspect of the present invention, the charge pump circuit includes a P-channel transistor or an N-channel corresponding to a phase shift direction between the clock signal output from the frequency divider and the reference clock. A first circuit that turns on one of the transistors and a second circuit that turns off both the P-channel transistor and the N-channel transistor based on the control signal are provided.

Thus, by simply adding the second circuit, the operation of the charge pump circuit can be stopped while maintaining the control voltage generated based on the signal output from the phase comparison circuit, and the circuit configuration is complicated. While suppressing, it is possible to reduce noise generated due to the operation of the charge pump circuit.
According to the wireless communication device of one aspect of the present invention, a baseband unit that generates transmission data, a PLL circuit that generates a multiplied clock obtained by multiplying the reference clock while synchronizing a phase with the reference clock, and a transmission A wireless transmission unit that transmits the transmission data while modulating the multiplication clock with data, and the PLL circuit stops at least the operation of the charge pump circuit based on a control signal sent from the baseband unit It is characterized by.

Thereby, when the transmitter is operating, the operation of the charge pump circuit can be stopped while outputting the multiplied clock synchronized with the reference clock. For this reason, it is possible to reduce noise generated due to the operation of the charge pump circuit while suppressing the complexity of the circuit configuration of the transmitter.
In the wireless communication device according to one aspect of the present invention, the baseband unit stops at least the operation of the charge pump circuit during a period in which the transmission data is transmitted.

Thus, the operation of the charge pump circuit can be stopped without interrupting the transmission operation of the transmission data during the period in which the transmission data is being transmitted. For this reason, it is possible to reduce noise generated due to the operation of the charge pump circuit while suppressing the complexity of the circuit configuration of the transmitter.
Further, according to the wireless communication device of one aspect of the present invention, the PLL circuit that generates the multiplied clock obtained by multiplying the reference clock while synchronizing the phase with the reference clock, and the received data mixed with the multiplied clock A wireless receiving unit that receives received data; and a baseband unit that performs baseband processing of received data received by the wireless receiving unit, wherein the PLL circuit is based on a control signal sent from the baseband unit And at least the operation of the charge pump circuit is stopped.

Thereby, when the receiver is operating, the operation of the charge pump circuit can be stopped while outputting the multiplied clock synchronized with the reference clock. For this reason, it is possible to reduce the noise generated due to the operation of the charge pump circuit while suppressing the complexity of the circuit configuration of the receiver.
In the wireless communication device according to one aspect of the present invention, the baseband unit stops at least the operation of the charge pump circuit during a period in which the received data is received.

  Thus, the operation of the charge pump circuit can be stopped without interfering with the reception operation of the reception data during the period in which the reception data is received. For this reason, it is possible to reduce the noise generated due to the operation of the charge pump circuit while suppressing the complexity of the circuit configuration of the receiver.

Hereinafter, a PLL circuit and a wireless communication apparatus according to embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration of a wireless communication apparatus according to the first embodiment of the present invention.
In FIG. 1, a transmission unit 1 that performs wireless transmission of data includes a baseband unit 2 that generates transmission data MS1, a PLL circuit 4 that generates a multiplied clock CL1 that is multiplied by a reference clock while synchronizing the phase with the reference clock, and An RF unit 3 is provided for transmitting the transmission data MS1 while modulating the multiplied clock CL1 with the transmission data MS1. Here, the baseband unit 2 can output the control signal CS1 to the PLL circuit 4 during the transmission period of the transmission data MS1. The PLL circuit 4 can stop the operation of the charge pump circuit included in the PLL circuit 4 on the basis of the control signal CS1 sent from the baseband unit 2.

That is, the PLL circuit 4 generates a multiplied clock CL1 obtained by multiplying the reference clock while synchronizing the phase with the reference clock, and outputs it to the RF unit 3. When the baseband unit 2 transmits the transmission data MS1, the transmission data MS1 is output to the RF unit 3 and the control signal CS1 is output to the PLL circuit 4. When the PLL circuit 4 receives the control signal CS1 from the baseband unit 2, the PLL circuit 4 stops the operation of the charge pump circuit while maintaining the control voltage generated by the charge pump circuit. Further, when the RF unit 3 receives the transmission data MS1 from the baseband unit 2, the RF unit 3 transmits the modulated clock CL1 output from the PLL circuit 4 while the operation of the charge pump circuit is stopped while modulating the transmission data MS1 with the transmission data MS1. Thus, the operation of the charge pump circuit can be stopped without interfering with the transmission operation of the transmission data MS1 during the period in which the transmission data MS1 is being transmitted. For this reason, it becomes possible to reduce noise generated due to the operation of the charge pump circuit while suppressing the complexity of the circuit configuration of the transmission unit 1.

FIG. 2 is a block diagram showing a schematic configuration of the PLL circuit 4 of FIG.
In FIG. 2, a frequency divider 15 that divides the multiplied clock generated by the voltage controlled oscillator 14, and a phase comparison circuit that detects a phase difference between the reference clock and the divided clock divided by the frequency divider 15. 11. A charge pump circuit 12 that outputs a control current corresponding to the phase difference between the reference clock and the frequency-divided clock divided by the frequency divider 15 and stops the operation based on the control signal CS1, and a charge pump circuit A loop filter 13 that integrates the control current output from 12 and outputs a control voltage, and a voltage controlled oscillator 14 that generates a multiplied clock based on the control voltage output from the loop filter 13 are provided.

  Then, the phase comparison circuit 11 detects the phase difference between the reference clock input from the outside and the frequency-divided clock divided by the frequency divider 15, and corresponds to the phase delay of the frequency-divided clock with respect to the reference clock. The UP signal is output to the charge pump circuit 12 and a DOWN signal corresponding to the advance of the phase of the divided clock with respect to the reference clock is output to the charge pump circuit 12. When the UP signal is input, the charge pump circuit 12 charges the loop filter 13. When the DOWN signal is input, the charge pump circuit 12 decharges the charge accumulated in the loop filter 13. The voltage control oscillator 14 outputs a control voltage defined by the charge accumulated in the voltage control oscillator 14.

Then, the voltage controlled oscillator 14 changes the oscillation frequency according to the control voltage output from the loop filter 13, and the oscillation frequency so that the phases of the reference clock and the divided clock divided by the frequency divider 15 coincide with each other. , A multiplied clock obtained by multiplying the reference clock is generated.
Then, when the control signal CS1 is output from the baseband unit 2 in FIG. 1 during the period in which the transmission data MS1 is being transmitted, the charge pump circuit 12 stops the charge charging / decharging, thereby performing desired control. Stops operation while holding the voltage.

Thus, during transmission of the transmission data MS1, the control voltage unit of the voltage controlled oscillator 14 that is most susceptible to noise can be separated from the surrounding circuits, and a very stable multiplication clock for transmission can be generated. High quality communication can be realized. Also,
In order to realize a stable control voltage free from ripples, complicated switching circuits, smoothing circuits, hold circuits, and the like are not necessary, so that development man-hours and costs can be reduced. Furthermore, the charge pump circuit 12 can be operated intermittently, and low power consumption can be realized.

FIG. 3 is a diagram showing a circuit configuration of the charge pump circuit 12 of FIG.
In FIG. 3, P-channel field effect transistors PM2, PM1 and N-channel field effect transistors NM1, NM2 are sequentially connected in series. Here, the P channel field effect transistor PM1 and the N channel field effect transistor NM1 constitute a CMOS circuit, and the P channel field effect transistor PM2 and the N channel field effect transistor NM2 constitute a bias circuit. Bias voltages BS1 and BS2 are input to the gates of the P-channel field effect transistor PM2 and the N-channel field effect transistor NM2, respectively, and an UP signal is input to the gate of the P-channel field effect transistor PM1. The DOWN signal is input to the gate of the effect transistor NM1. A P-channel field effect transistor PM3 is connected between the gate of the P-channel field effect transistor PM1 and the power supply potential, and an N-channel field effect is connected between the gate of the N-channel field effect transistor NM1 and the ground potential. Transistor NM3 is connected. A control signal CS1 is input to the gate of the P-channel field effect transistor PM3 via the inverter IV, and a control signal CS1 is input to the gate of the N-channel field effect transistor NM3.

  When operating the charge pump circuit 12, the P-channel field effect transistor PM3 and the N-channel field effect transistor NM3 are turned off by setting the control signal CS1 to the low level. When the UP signal is output from the phase comparison circuit 11, the P-channel field effect transistor PM 1 is turned on, the N-channel field effect transistor NM 1 is turned off, and a charge is charged from the loop filter 13. On the other hand, when the DOWN signal is output from the phase comparison circuit 11, the N-channel field effect transistor NM1 is turned on, the P-channel field effect transistor PM1 is turned off, and the charge is discharged to the loop filter 13.

  On the other hand, when stopping the operation of the charge pump circuit 12, the P-channel field effect transistor PM3 and the N-channel field effect transistor NM3 are turned on by setting the control signal CS1 to a high level. When the P-channel field effect transistor PM3 and the N-channel field effect transistor NM3 are turned on, the gate of the N-channel field effect transistor NM1 becomes low level and the gate of the P-channel field effect transistor PM1 becomes high level. Both the transistor NM1 and the P-channel field effect transistor PM1 gate are turned off. Therefore, the electric charge accumulated in the loop filter 13 is held as it is, and a control voltage defined by the electric charge is output to the voltage controlled oscillator 14.

  Thus, by adding the P-channel field effect transistor PM3, the N-channel field effect transistor NM3, and the inverter IV, the charge pump circuit 12 maintains the control voltage generated based on the signal output from the phase comparison circuit 11. The operation can be stopped, and the noise generated due to the operation of the charge pump circuit 12 can be reduced while suppressing the complexity of the circuit configuration.

FIG. 4 is a block diagram showing another example of the schematic configuration of the PLL circuit 4 of FIG.
In FIG. 4, not only the operation of the charge pump circuit 12 is stopped based on the control signal CS1, but also the operations of the phase comparison circuit 11 and the frequency divider 15 can be stopped. Therefore, noise generated due to the operations of the phase comparison circuit 11, the charge pump circuit 12, and the frequency divider 15 is reduced while operating the voltage controlled oscillator 14 based on the control voltage held in the loop filter 13. And power consumption can be reduced.

FIG. 5 is a block diagram showing a schematic configuration of a wireless communication apparatus according to the second embodiment of the present invention.
In FIG. 5, a receiving unit 21 that wirelessly receives data includes a PLL circuit 24 that generates a multiplied clock CL2 obtained by multiplying the reference clock while synchronizing the phase with the reference clock, and receives the received data while mixing it with the multiplied clock CL2. An RF unit 23 that receives data and a baseband unit 22 that performs baseband processing of received data received by the RF unit 23 are provided. Here, the baseband unit 22 can output the control signal CS <b> 2 to the PLL circuit 24 during a period in which the reception data is received. The PLL circuit 24 can stop the operation of the charge pump circuit included in the PLL circuit 24 based on the control signal CS <b> 2 sent from the baseband unit 22.

  That is, the PLL circuit 24 generates a multiplied clock CL2 obtained by multiplying the reference clock while synchronizing the phase with the reference clock, and outputs it to the RF unit 23. When the reception data is received by the RF unit 23, the baseband unit 22 outputs a control signal CS2 to the PLL circuit 24. Then, when receiving the control signal CS2 from the baseband unit 22, the PLL circuit 24 stops the operation of the charge pump circuit while maintaining the control voltage generated by the charge pump circuit. When the received data is input, the RF unit 23 receives the received data while mixing the multiplied clock CL2 output from the PLL circuit 24 with the received data while the operation of the charge pump circuit is stopped. Send to part 22.

Thus, the operation of the charge pump circuit can be stopped without interfering with the reception operation of the reception data during the period in which the reception data is received. For this reason, it is possible to reduce noise generated due to the operation of the charge pump circuit while suppressing the complexity of the circuit configuration of the receiving unit 21.
Of course, the configuration of FIG. 4 may be used for the PLL circuit 24 and the phase comparison circuit, the charge pump circuit, and the frequency divider may be stopped by the control signal CS2.

1 is a block diagram showing a schematic configuration of a wireless communication apparatus according to a first embodiment of the present invention. The block diagram which shows schematic structure of the PLL circuit 4 of FIG. FIG. 3 is a diagram showing a circuit configuration of a charge pump circuit 12 of FIG. 2. FIG. 3 is a block diagram showing another example of a schematic configuration of the PLL circuit 4 of FIG. 1. The block diagram which shows schematic structure of the radio | wireless communication apparatus which concerns on 2nd Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Transmission part, 2 and 22 Baseband part, 3, 23 RF part, 4, 24 PLL circuit, 11 Phase comparison circuit, 12 Charge pump circuit, 13 Loop filter, 14 Voltage control oscillator, 15 Frequency divider, PM1, PM2 , PM3 P channel field effect transistor, NM1, NM2, NM3 N channel field effect transistor, IV inverter, 21 receiver

Claims (7)

A voltage controlled oscillator that controls the oscillation frequency of the clock signal based on the control voltage;
A frequency divider for dividing a clock signal from the voltage controlled oscillator;
A phase comparison circuit that outputs a signal corresponding to a phase shift between the clock signal output from the frequency divider and a reference clock;
A charge pump circuit that generates the control voltage based on a signal output from the phase comparison circuit and stops operation while holding the control voltage based on a control signal input from the outside. PLL circuit. A voltage controlled oscillator that controls the oscillation frequency of the clock signal based on the control voltage;
A frequency divider that divides the clock signal from the voltage controlled oscillator and stops operation based on a control signal input from the outside;
A phase comparison circuit that outputs a signal corresponding to a phase shift between the clock signal output from the frequency divider and a reference clock, and stops operation based on the control signal;
A PLL circuit comprising: a charge pump circuit that generates the control voltage based on a signal output from the phase comparison circuit and stops operation while maintaining the control voltage based on the control signal. The charge pump circuit
A first circuit that turns on either the P-channel transistor or the N-channel transistor in accordance with the phase shift direction of the clock signal output from the frequency divider and the reference clock;
And a second circuit that turns off both the P-channel transistor and the N-channel transistor based on the control signal. A baseband unit for generating transmission data;
A PLL circuit that generates a multiplied clock obtained by multiplying the reference clock while synchronizing the phase with the reference clock;
A wireless transmission unit that transmits the transmission data while modulating the multiplied clock with transmission data,
The said PLL circuit stops the operation | movement of a charge pump circuit at least based on the control signal sent from the said baseband part, The radio | wireless communication apparatus characterized by the above-mentioned.   The wireless communication apparatus according to claim 4, wherein the baseband unit stops the operation of the charge pump circuit at least during a period in which the transmission data is transmitted. A PLL circuit that generates a multiplied clock obtained by multiplying the reference clock while synchronizing the phase with the reference clock;
A wireless receiver for receiving the received data while mixing the received data with the multiplied clock;
A baseband unit that performs baseband processing of received data received by the wireless reception unit,
The said PLL circuit stops the operation | movement of a charge pump circuit at least based on the control signal sent from the said baseband part, The radio | wireless communication apparatus characterized by the above-mentioned. The wireless communication apparatus according to claim 6, wherein the baseband unit stops the operation of the charge pump circuit at least during a period in which the reception data is received.

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