JP2007116501A - Arithmetic encoding and decoding device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an arithmetic encoding and decoding device which is inexpensively manufactured without enlarging a buffer amount. <P>SOLUTION: The device comprises: a symbol predicting part (12) for predicting that symbol data being decoded takes a value for increasing processing man-hours in subsequent processing procedures to be determined by the value of the symbol data; a context generating part (4) for reading a context, based on the decoding symbol data or the prediction symbol data; an arithmetic part (7) for inputting the context and decoding encoding data; a comparing part (13) for comparing the decoding symbol data with the prediction symbol data; and a control part (10) for performing control to conduct decoding with the use of the context which is read based on the prediction symbol data when the comparison result is coincidence and to conduct decoding after performing context reading processing again based on the decoding symbol data when the result is not coincidence. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an arithmetic code decoding apparatus used for moving picture compression encoding.

H. H.264, buffer ITU-T uses H.264 as a standard method for video compression encoding. H.264 is standardized.
As shown in FIG. 6, the moving image compression encoding system includes an image conversion encoding unit 21, an entropy encoding unit 22, and a multiplex transmission unit 23.
The image transform coding unit 21 DCT transforms and quantizes the motion compensation predicted prediction error from the input video signal, and outputs the result to the entropy coding unit 22. The entropy encoding unit 22 performs variable-length encoding of the DCT coefficient in the input data, and encodes other accompanying data using an exponential Golomb code and an arithmetic code. Various types of variable-length encoded data are multiplexed according to the format, and the amount of information generated is uniformly adjusted via a buffer, and output from the multiplex transmission unit 23.
As described above, H.P. In H.264, an arithmetic code is used as one of entropy coding. These encoding / decoding require a data smoothing buffer.

Arithmetic code An arithmetic code divides a symbol sequence by recursively dividing a probability interval (range) between 0 and 1 according to the appearance probability of each symbol to be encoded (subdivided once). The binary decimal representing the position is used as a code corresponding to the representative point in the partial section.
H. The arithmetic code used in H.264 is called CABAC (context adaptive binary arithmetic code), and the syntax element that is the data to be encoded is binarized into symbol strings of “0” and “1”. In addition, the symbol is identified as belonging to the dominant probability symbol (MPS) or the inferior probability symbol (LPS) according to the appearance probability, and is encoded. The appearance probabilities of “0” and “1” are given in a table associated with the syntax element as an initial value, and are adapted to be updated according to the input symbol value. The context is a word indicating the situation around the symbol. Specifically, as will be described later, the value of the dominant probability symbol (“0” or “1”) of the encoding target symbol and the probability thereof. Represents a range (see Non-Patent Document 1).

Encoding unit The configuration of the encoding / decoding device will be described using an H.264 arithmetic code as an example. As shown in FIG. 7 (A), the arithmetic code encoding apparatus converts a syntax element (SE) represented by a normal multi-value to be encoded into a binary symbol data (SD) string of variable length. A binarization unit 6 for conversion, a context calculation unit 4 for calculating a context (Ctx) of a symbol, an arithmetic encoding unit 5 for calculating and outputting an arithmetic code data (CD) sequence from the context and the input symbol, And a symbol is input, syntax element information for the next symbol is output, and the encoding control unit 9 controls these.

As shown in FIG. 7B, the decoding unit arithmetic code decoding apparatus includes a context calculation unit 4 for calculating a symbol context (Ctx), and the context and encoded data (CD) sequence to be decoded. An arithmetic decoding unit 7 that decodes and outputs a symbol (SD) from the symbol, an SE restoration unit 8 that restores a syntax element (SE) from the decoded symbol sequence, and a symbol for the next symbol by inputting the symbol It is composed of a decoding control unit 10 that outputs tax element information and controls them.

As shown in FIG. 7C, the context calculation unit 4 includes a context reading unit 1, a probability update unit 2, and three tables representing the probability of symbols (probability table, LPS range table, probability update table). And is commonly used for encoding and decoding.
The probability table 3-1 is a table in which the probability state number (sIdx) and the dominant probability symbol (MPS) are described with the context number (cIdx) as a headline, and the value of sIdx can be updated. The LPS range table 3-2 is a table in which the probability range (Rng) is described with the probability state number (sIdx) as a heading. The probability update table 3-3 uses the probability state number (sIdx) as a heading, and in accordance with the encoded symbol values (MPS, LPS), the next sIdx value (t_MPS, corresponding to the update probability of the probability table) t_LPS).
The context reading unit 1 inputs the syntax element information of the symbol, and outputs a context (Ctx) including a dominant probability symbol (MPS) and a probability range (Rng).
The updating unit 3 inputs the context number (cIdx), the probability state number (sIdx), and the symbol (SD), and updates the probability state number (sIdx) in the probability table.

Encoding Flow Next, the arithmetic code encoding process will be described with reference to the flowchart of FIG.
First, for order control, initialization is performed such as a counter for identifying syntax elements, the progress of encoding processing, that is, a code register (CR) for storing code data (CD) strings (step S21).
The binarization unit 6 converts the syntax element (SE) into a binary symbol (SD) sequence and binarizes it (step S22).
The encoding control unit 9 analyzes the syntax element (SE) information (SE type, bit order in the SE, etc.) about the symbol to be encoded next from the information about the current symbol to obtain SE information. (Step S23).
The context reading unit 1 obtains a context (Ctx) from the input SE information and outputs it to the arithmetic coding unit 5 (step S24). That is, the context number (cIdx) is obtained from the SE information, and the probability state number (sIdx) and the dominant probability symbol (MPS) are read with reference to the probability table by the cIdx, and further, the above-mentioned reference is made with reference to the LPS range table. A probability range (Rng) having sIdx as a headline is read, and a context (Ctx) composed of MPS and Rng is output.
One bit of the symbol (SD) binarized in step S22 is read and output to the arithmetic coding unit 5 (step S25).
The arithmetic encoding unit 5 encodes the input symbol (SD) based on the context (Ctx) (step S26).
The probability update unit 2 reads the next sIdx from the probability update table according to the input symbol (SD), and updates the probability table (step S27). That is, referring to the probability update table, the next value of sIdx (t_MPS or t_LPS) is obtained from the probability state number (sIdx) and information indicating whether the encoded SD is MPS or LPS. Then, the probability state number sIdx having the context number (cIdx) in the probability table as a headline is replaced with the value of the next sIdx. As described above, the probability is dynamically updated according to the appearance probability of each symbol.
The above procedure is repeated until all bits of the syntax element (SE) are completed, and the encoding of the SE is completed (step S28).
Further, the coding is repeated until coding of all syntax elements is completed (step S29).

Decoding Flow Arithmetic code decoding processing will be described with reference to the flowchart of FIG.
First, initial setting for order control is performed (step S31).
The code data (CD) string to be decoded is read into the code register (CR) (step S32).
Similar to the encoding, the decoding control unit 10 analyzes the SE information about the symbol to be decoded next from the decoded symbol information, and outputs it as SE information (step S33).
The context reading unit 1 obtains the context (Ctx) from the input SE information, and outputs it to the arithmetic decoding unit 7 (step S34).
The arithmetic decoding unit 6 decodes 1 bit of the symbol (SD) from the code register (CR) to be decoded based on the context (step S35).
Similar to encoding, the probability update unit 2 updates the probability in the probability table according to the decoded symbol (SD) (step S36), and stores the decoded SD (step S37).
The above procedure is repeated until the decoding of all bits of the syntax element (SE) is completed (step S38). When the decoding is completed, the SE restoration unit 8 restores the syntax element from the stored symbol (SD) sequence. (Step S39).
Further, the decoding is repeated until the restoration of all the syntax elements (SE) is completed (step S40).

A CABAC-type arithmetic coding / decoding device can be realized by a configuration and processing higher than that of speedup, but since complicated processing is required for each symbol, speedup and a small circuit scale are expected. Therefore, a method for speeding up will be described.
In the encoding process, as shown in FIG. 9A, the three steps of encoding control, context reading, and updating are all input regardless of the result of arithmetic encoding because the symbol (SD) sequence is known. Information is in place. Therefore, as shown in FIG. 9B, the three steps of encoding control, context reading, and updating can be speeded up by operating in parallel with the arithmetic encoding step. Since the update step may be processed before the next context read, it may be processed before or after the arithmetic coding step.
On the other hand, in the decoding process, as shown in FIG. 10A, update and decoding control require the value of the symbol (SD) of the arithmetic decoding result, and context reading requires the update result. For this reason, in the decoding process, the arithmetic decoding step cannot be operated in parallel with the decoding control and the context reading step. For example, the processing shown in FIG. 10B is performed, and the speed cannot be increased simply by the parallel processing. .

Conventional Example Therefore, as shown in FIG. 11, a method for speeding up the decoding process by parallel processing has been proposed. That is, instead of the decoded symbol necessary for decoding control, a prediction symbol (pSD = MPS) is used, assuming that the symbol to be decoded is the dominant probability symbol (MPS) in the previous context read step. The decoding control step proceeds in parallel with the arithmetic decoding step, and only if the prediction symbol (pSD) is compared with the symbol (dSD) actually decoded by the arithmetic decoder later and is wrong. The actual decoding symbol (dSD) is used to redo the three steps of update, encoding control, and context reading. (For example, refer to Patent Document 1.) In this method, since the MPS having a high appearance probability is selected as the prediction symbol, the probability of the prediction is high, the total processing time can be shortened, and the speed can be increased.
Japanese Patent Laid-Open No. 9-148941 (page 8-7, Fig. 1-3) Supervised by Sakae Okubo “H.264 / AVC Textbook”, Impress 2004 ITU-T Rec. H. H.264 (2003) “Advanced video coding for generic audiovisual services”

  However, the method using the dominant probability symbol (MPS) as a symbol prediction value has a high predictive predictive value and can be accelerated in terms of the total time. The maximum value cannot be reduced. For this reason, in terms of circuit, there is a problem that the amount of the buffer for smoothing the data flow cannot be reduced, the circuit scale is increased, and the manufacturing cost cannot be reduced.

  Accordingly, the present invention has been made to solve the above-described problems, and an object of the present invention is to provide an arithmetic code decoding apparatus that is inexpensive to manufacture without increasing the buffer amount.

The first invention in the present invention is an arithmetic coding / decoding device that reads out a context from a context table in which information necessary for decoding the next symbol data is described based on the immediately preceding symbol data and decodes the coded data The symbol prediction unit (SD prediction unit 12) that predicts that the immediately preceding symbol data being decoded has a value that increases the number of processing steps among the subsequent processing procedures determined by the value of the symbol data, Based on the immediately preceding decoded symbol data or the prediction symbol data predicted by the symbol prediction unit, a context generation unit (context calculation unit 4) that reads out and outputs the context, and inputs the context, the encoded data Between the arithmetic unit (arithmetic decoder 7) for decoding the decoded symbol data immediately before And a comparison unit (comparison unit 13) that compares the prediction symbol data predicted by the symbol prediction unit and a result of comparison by the comparison unit match, The context read based on the prediction symbol data is output to the arithmetic unit, and when it is determined that they do not match, the context is read again based on the result of the immediately preceding decoded symbol data, There is provided an arithmetic code decoding device comprising: a control unit (decoding control unit 10) that controls to output the read context to the arithmetic unit.
According to a second aspect of the present invention, there is provided an arithmetic coding / decoding device that reads out a context from a context table in which information necessary for decoding next symbol data is described based on immediately preceding symbol data, and decodes encoded data. The context is input and the encoded data is decoded (step S6). At the same time, the decoding result of the symbol data being decoded is a value that increases the number of processing steps in the subsequent processing procedures determined by the value of the symbol data. Based on the predicted symbol data predicted to be taken and read in advance, a context reading process (steps S1 and S2) is performed. When decoding of the encoded data is completed and a decoding result of the symbol data is obtained, a decoding result is obtained. Is compared with the predicted symbol data (step S3), and the compared results are compared. Are determined to match, the context read based on the predicted symbol data is output to the arithmetic unit (step S3), and if it is determined that they do not match, Based on the symbol data of the immediately preceding decoding result, the context reading process is performed again (steps S4 and S5), the read context is output to the arithmetic unit, and the encoded data is decoded by the output context ( An arithmetic code decoding method characterized by performing step S6) is provided.

According to the first aspect of the present invention, the symbol prediction unit that predicts that the immediately preceding symbol data being decoded takes a value that increases the number of processing steps among the subsequent processing procedures determined by the value of the symbol data. Then, based on the immediately preceding decoded symbol data or the predicted symbol data predicted by the symbol prediction unit, a context is read and output, and the context is input to decode the encoded data It is determined that the calculation unit, the comparison result of the immediately preceding decoded symbol data, the comparison unit that compares the prediction symbol data predicted by the symbol prediction unit, and the comparison result of the comparison unit are the same If it is, the context read based on the predicted symbol data is output to the arithmetic unit and does not match A control unit that performs a context read process again based on the result of the immediately preceding decoded symbol data and outputs the read context to the calculation unit.
According to the second invention, the context is input and the encoded data is decoded. At the same time, the decoding result of the symbol data being decoded is a processing step in the subsequent processing procedures determined by the value of the symbol data. Based on the predicted symbol data that has been prefetched by predicting that the number of man-hours will be increased, the context is read out, and when the decoding of the encoded data is completed and the decoding result of the symbol data is obtained, the decoding result The symbol data and the predicted symbol data are compared, and if it is determined that the compared results match, the context read based on the predicted symbol data is output to the arithmetic unit If it is determined that they do not match, the context read process is performed again based on the symbol data of the immediately preceding decoding result. Was carried out, the context read and output to the arithmetic unit, decodes the encoded data by said output contexts.
For this reason, in the present invention, it is possible to always select a symbol having a large number of processing steps and perform prefetch prediction, and to perform the context read processing in parallel with the decoding processing. Only a large number of symbols can reduce the processing time. In addition, when the prediction is lost, the context is read again by the actual decoded symbol, so that the decoding can be performed correctly and the parallel operation time is not used. Therefore, the processing time is not much different from the case where the parallel operation is not performed.
As a result, the processing time for symbols with a low processing man-hour does not change, and the processing time for symbols with a high processing man-hour can be shortened. By smoothing the data processing man-hours, the amount of buffer memory required can be reduced, the circuit scale can be reduced, and an appropriate speed increase can be achieved.

  The arithmetic code decoding apparatus according to each embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a diagram showing a configuration of an arithmetic code decoding apparatus according to an embodiment of the present invention. FIG. 2 is a flowchart of the decoding process in the arithmetic code decoding apparatus of the present invention. 3A and 3B are explanatory diagrams of “symbols with a large number of processing steps” in the arithmetic coding / decoding apparatus of the present invention, in which FIG. 3A is an example of a binarization method, and FIG. FIG. 4 is a diagram showing symbol predictive values of syntax elements when binarization is performed by table lookup in the arithmetic code decoding apparatus of the present invention. FIG. 5 is a timing chart of the decoding processing procedure in the arithmetic code decoding apparatus of the present invention.

Configuration As shown in FIG. 1, the arithmetic code decoding apparatus according to the present invention includes a context calculation unit 4, an arithmetic decoder 7, an SE restoration unit 8, and a decoding control unit 10. Hereinafter, in the configuration of the present invention, the decoding control unit 10 different from the decoder in FIG. 7B described in the background art will be mainly described.
The decoding control unit 10 includes an SE analysis unit 11, a symbol prediction unit 12, and a symbol comparison unit 13.
Based on the information from the SE analysis unit, the symbol prediction unit 12 selects a symbol that requires a larger number of processing steps by a method described later, and outputs this as a prediction symbol (pSD). Further, the symbol comparison unit 13 compares the prediction symbol (pSD) output from the symbol prediction unit with the actual decoded symbol (dSD) decoded by the arithmetic decoder 7 to determine whether or not they match. Outputs judgment and judgment result.
The SE analysis unit 11 analyzes the prediction symbol pre-read from the symbol prediction unit 1, the determination result of the symbol comparison unit, and the syntax element SE, and controls the decoding operation as in the conventional decoding control unit 10. The SE information of the symbol that is used for decoding is output to the context calculation unit 4.

Decoding Flow Next, the decoding processing operation in the arithmetic code decoding apparatus of the present invention will be described with reference to FIG. Since the basic flow of the decoding process is the same as the flow described with reference to FIG. 8B in the background art, different steps from “S” to “C” in FIG. 8B will be described. In the following description, the symbols and step suffixes n and n + 1 are the cycle numbers of the decoding flow and represent the timing context.
In the decoding control unit 10, the “high processing man-hour” prediction symbol (pSDn) output from the symbol prediction unit 12 is input, and the SE analysis unit 11 analyzes information on a symbol to be decoded next and outputs it as SE information. To do. (Step S1). At this time, normally, the decoding process of the prediction symbol one cycle before (corresponding to step S6 described later) is in progress in parallel operation.
The context reading unit 1 reads the context (Ctx) from the input SE information and outputs it to the arithmetic decoder 7 as in the encoding (step S2).
The symbol comparison unit 13 compares the symbol (dSDn) decoded by the arithmetic decoder 7 and the prediction symbol (pSDn). If both symbols match, the process jumps to step S6, and if different, step S4. (Step S3).
In the decoding control unit 10, the SE analysis unit 11 inputs the decoded symbol (dSDn) (corresponding to the inversion of the prediction symbol input in step S1), and reanalyzes the information of the symbol to be decoded next. And output as SE information (step S4).
The context reading unit 1 obtains a context (Ctx) from the input SE information and outputs it to the arithmetic decoding unit 7 (step S5). The above steps 3 to 5 correspond to inputting the decoded symbol (dSDn) and reading out the context again when the prediction of the prediction symbol is out of sync and does not match the decoded symbol.
The arithmetic decoding unit 6 decodes the symbol (dSDn + 1) from the code string of the code register (CR) based on the correct context (Ctx) read in step S2 or step S5 (step S6).
The probability update unit 2 updates the probability of the probability table 3-1, based on the decoded symbol (dSDn + 1) decoded in step S6, and stores the decoded symbol (step S7).

Symbol Prediction Next, a method for predicting a symbol (pSD) having a large number of processing steps will be described.
H. In the case of encoding with H.264 CABAC, the encoding order of syntax elements (SE) is determined, but it is basically a variable length, and the binary symbol length of the SE itself differs depending on the data. In addition, when encoding an SE, which of the plurality of processing procedures is executed is determined by the value of the preceding symbol. For this reason, in the decoding of the variable length code, the subsequent processing changes depending on the symbol value, and the processing man-hours until the end of the SE decoding changes.
Therefore, in the present invention, the number of man-hours for processing the subsequent symbol is determined by analyzing the symbol being decoded. H. Syntax elements used in H.264 arithmetic codes are roughly classified into five types according to the binarization method. Hereinafter, according to the binarization method, examples of predicted values and the reasons thereof will be shown (see Non-Patent Document 2).
1 Unary binarization The symbol prediction value is 1.
2 Truncated unary binarization The symbol prediction value is 1.
3 Combined unary / Kth-order exponent Golomb binarization The symbol prediction value is 1.
Regarding the above 1, 2, and 3, as shown in FIG. 3A, the syntax element (SE) is binarized so that “1... 110” and 1 are consecutive and 0 ends. ing. For this reason, as shown in FIG. 3B, when 0 is output to the symbol, the processing of the syntax element ends and the process proceeds to the next state (syntax element). On the other hand, when 1 is output, the processing of the syntax element is still continued, and the number of processing steps increases.
The update process of the probability table at this time is apparently updated for each data, but actually the process is stored in memory, the context is read using the update probability, and the update write to the table is It is possible to speed up by carrying out at the end.
4 Fixed-length binarization 1) Pre_intra4x4_pred_mode_flag
The symbol prediction value is set to 0.
When this flag is 1, the prediction direction has been predicted and the process proceeds to the next step. However, when the flag is 0, the prediction is lost and the syntax element shifts to Rem_intra4x4_pred_mode and new processing occurs. There are many processing man-hours.
2) Last_significant_coeff_flag
The symbol prediction value is set to 0.
When this flag is 1, the process proceeds to the next step, Coeff_abs_level_minus1, but when this flag is 0, the process returns to the previous step Significant_coeff_flag, and the number of processing steps is large.
3) Coded_block_pattern_luma
The symbol prediction value is 1.
When this flag is 0, there is no coefficient in the 8 × 8 block, and the processing after Significant_coeff_flag does not need to be performed, so the number of processing steps is small. Conversely, when this flag is 1, the number of processing steps is large.
4) Coded_block_flag
The symbol prediction value is 1.
For the same reason as Coded_block_pattern_luma.
5) Significant_coeff_flag
The symbol prediction value is 1.
When this flag is 1, processing must be performed with Coeff_abs_level_minus1 and Coeff_sign_flag in the subsequent stage, which increases the number of processing steps.
5 Table Lookup Symbol prediction values are shown in the table of FIG.
Each description is omitted, but in each case, as shown in FIG. 3B, symbols that require further data processing are selected and used as predicted values. That is, with respect to the above 4 and 5, for each step, a process with a large number of processing steps is stored in advance from a plurality of processing procedures, and it may be selected at the time of prediction.
In addition, although the prediction method of "a symbol with many processing man-hours" was demonstrated above, when the next context is decided irrespective of the value of the symbol under decoding processing, since it does not relate to the size of processing man-hours, symbol comparison Do not do. For example, when a new syntax element is started, since the previous decoding output is not necessary for the calculation of the context, the parallel processing can be originally performed. The symbol prediction unit may predict a known predetermined value.

Reduction of processing man-hour difference Next, it will be explained that the processing time of a symbol having a large processing man-hour is shortened by parallel processing. FIG. 5 is a timing chart showing an example of the decoding process, and the parallel processing is shown in the upper and lower stages.
First, in response to the context (Ctx) from the previous cycle, a decoding step n-1 including arithmetic coding S6 and update S7 is started. At the same time, the prediction symbol (pSDn−1) is prefetched, and a reading step n including decoding control S1 and context reading S2 is started.
Next, when the symbol (dSDn-1) is decoded by the decoding step n-1, pSDn-1 and dSDn-1 are compared. In this example, since the comparison result matches, the Ctx output from the reading step n is received. Thus, the decoding step n is started. That is, since the decoding result is a symbol having a large number of processing steps, the prediction is successful, the parallel processing becomes effective, and the processing time is shortened.
At the same time, the prediction symbol (pSDn) is pre-read and the reading step n + 1 is started.
When the symbol (dSDn) is decoded by the decoding step n, pSDn and dSDn are compared. In this example, the comparison result is inconsistent, and therefore, based on the symbol (dSDn), the decoding control S4 and the context reading S5 are included. A reread step n + 1 is started. That is, in this case, since the decoding result is a symbol with a small number of processing steps, the prediction is lost, the parallel processing becomes invalid, and the process proceeds to a re-reading step that is originally necessary. For this reason, processing time cannot be shortened.
Then, upon receiving Ctx output from the re-reading step n + 1, the decoding step n + 1 is started, and dSDn + 1 is decoded.
At the same time, the reading step n + 2 for the next symbol is started.
By taking the above procedure, a symbol having a large number of processing steps is predicted, and the processing time is shortened by parallel processing. Further, a symbol with a small number of processing steps is not predicted and is read out again, but can be processed almost the same as the time without pre-reading shown in FIG. 10B. In this method, the concept of time reduction is the same as that of the conventional example, but since the method of selecting a prediction symbol is different, the processing time can be shortened only for symbols with a large number of processing steps.

As described above, according to the present invention, since there is the above-described configuration, the processing time of a symbol with a large number of processing steps is shortened, and the difference between the processing number of a symbol with a large number of processing steps and a symbol with a small number of processing steps is reduced. By smoothing the number of processing steps, the required buffer memory amount can be reduced and the circuit scale can be reduced. Furthermore, compared with the case of not prefetching, the circuit scale does not increase so much and the speed can be increased.

It is a figure which shows the structure of the arithmetic code decoding apparatus in embodiment of this invention. It is a flowchart of the decoding process in the arithmetic code decoding apparatus of this invention. In the arithmetic code decoding apparatus of this invention, it is explanatory drawing of the "symbol with many processing man-hours", (A) is a binarization method example, (B) is a processing flow example. It is a figure which shows the symbol prediction value of a syntax element in the case of binarizing by the table look-up in the arithmetic coding / decoding apparatus of this invention. It is a timing chart of the decoding process procedure in the arithmetic code decoding apparatus of this invention. It is a figure which shows the structure of a moving image compression encoding system. It is a block diagram of an arithmetic coding / decoding apparatus, (A) shows an encoder, (B) shows a decoder, and (C) shows a context calculation unit. In the flowchart of the encoding / decoding process in an arithmetic encoding / decoding apparatus, (A) shows an encoding process and (B) shows a decoding process. It is a timing chart of the encoding process sequence in an arithmetic encoding / decoding apparatus, (A) is information required for a process, (B) is explanatory drawing of the example of a process sequence. It is a timing chart of the decoding process sequence in an arithmetic coding / decoding apparatus, (A) is information required for a process, (B) is explanatory drawing of the example of a process sequence. It is a timing chart of the decoding process procedure in the conventional arithmetic code decoding apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Context reading part 2 Probability update part 3 Various tables 4 Context calculation part 7 Arithmetic decoder 8 Syntax element decompression | restoration part 10 Decoding control part 11 Syntax element analysis part 12 Symbol prediction part 13 Symbol comparison part SE Syntax element SD Symbol Data MPS Dominant probability symbol LPS Inferior probability symbol pSD Predicted symbol data dSD Decoded symbol data CD Code data CR Code register Ctx Context Rng Probability range Probability interval cIdx Context number sIdx Probability state number t_MPS, t_LPS Value of sIdx after probability update

Claims (2)

In the arithmetic coding / decoding device that reads the context from the context table in which information necessary for decoding the next symbol data is described based on the immediately preceding symbol data and decodes the coded data,
The symbol prediction unit that predicts that the immediately preceding symbol data being decoded has a value that increases the number of processing steps among the subsequent processing procedures determined by the value of the symbol data,
Based on the immediately preceding decoded symbol data or the prediction symbol data predicted by the symbol prediction unit, a context generation unit that reads and outputs a context;
An arithmetic unit that inputs the context and decodes encoded data;
A comparison unit that compares the result of the preceding decoded symbol data with the prediction symbol data predicted by the symbol prediction unit;
When it is determined that the comparison results in the comparison unit match, the context read based on the prediction symbol data is output to the calculation unit, and it is determined that they do not match A control unit that performs a context read process again based on the result of the immediately preceding decoded symbol data, and controls to output the read context to the arithmetic unit;
An arithmetic code decoding apparatus comprising: In the arithmetic coding / decoding device that reads the context from the context table in which information necessary for decoding the next symbol data is described based on the immediately preceding symbol data and decodes the coded data,
At the same time as inputting the context and decoding the encoded data,
The decoding result of the symbol data being decoded is a context reading process based on predictive symbol data that is prefetched by predicting that it takes a value that increases the number of processing steps among subsequent processing procedures determined by the value of the symbol data And
When decoding of the encoded data is completed and a decoding result of symbol data is obtained, the symbol data of the decoding result is compared with the predicted symbol data,
When it is determined that the compared results match, the context read based on the predicted symbol data is output to the arithmetic unit, and when it is determined that they do not match, Based on the symbol data of the immediately preceding decoding result, the context is read again, and the read context is output to the arithmetic unit,
An arithmetic code decoding method, wherein encoded data is decoded according to the output context.

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