JP2013009167A - Entropy encoding apparatus, entropy decoding apparatus, entropy encoding method and entropy decoding method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a processing load of encoding binary symbols having an unbiased occurrence probability of '0' and '1' while maintaining the same compression rate as CABAC.SOLUTION: In addition to an arithmetic encoding section 6, a bypass encoding section 7 is provided to output as encoded bits binary symbols output from an encoding method changeover switch 4. An encoded data output section 8 multiplexes encoded bits output from the arithmetic encoding section 6 and the encoded bits output from the bypass encoding section 7 to generate encoded data.

Description

  The present invention relates to an entropy coding apparatus and entropy coding method for binarizing a multi-level symbol sequence and entropy-encoding the binary symbol sequence, and a binary symbol sequence by decoding a binary symbol sequence from encoded data The present invention relates to an entropy decoding device and an entropy decoding method for converting a multi-value into a multi-value symbol sequence and outputting a multi-value symbol sequence.

Conventionally, as a technique for efficiently entropy encoding multi-level symbol sequences having different occurrence probabilities, for example, CABAC (Context-based Adaptive Binary Arithmetic Coding) described in Non-Patent Document 1 is known.
CABAC binarizes the encoding target symbols, estimates the occurrence probability of the dominant symbol of each binary symbol based on the context, and uses the occurrence probability of the dominant symbol to arithmetically code each binary symbol. Technology.

  Arithmetic coding for a binary symbol uses a probability information indicating the occurrence probability of the dominant symbol of the binary symbol, and information indicating whether or not the binary symbol is a dominant symbol. This is entropy encoding means that divides the number line I into sections and uses the finally obtained probability section coordinates on the number line as encoded data.

FIG. 12 is a conceptual diagram in the case of arithmetic coding a binary symbol sequence.
FIG. 12 shows an example in which processing is performed one by one in order from the first binary symbol in the binary symbol sequence.
Here, dominant symbol information indicating whether each binary symbol in the binary symbol sequence is a dominant symbol (indicating which of “0” and “1” is a symbol having a high probability of occurrence). Information) and the probability information indicating the probability of occurrence of the dominant symbol are known.
At the time of processing the k-th binary symbol b _k from the beginning probability interval I _k (thick line portion on the number line in FIG. 12) Distant, dominant symbols in binary symbol b _k occurrence probability p _k (0. The probability interval I _k is divided into p _k l _k and (1−p _k ) l _k using 5 <p _k ≦ 1).
Here, l _k represents the length of the probability interval I _k .
At this time, for example, a section having a length p _k l _k (dominant symbol section: I _Mk ) is always positioned on the lower side, and a section having a length (1-p _k ) l _k (inferior symbol section: I _Lk ) is The probability interval I _k is divided so as to be always on the upper side.

When the binary symbol b _k is a dominant symbol, I _{k + 1} = I _Mk, and when the binary symbol b _k is an inferior symbol, I _{k + 1} = I _Lk .
By repeating this process with I ₀ = I, one probability interval on the number line is uniquely obtained according to the input binary symbol sequence.
A representation of the coordinates in this probability interval in binary numbers is the output of arithmetic coding.
On the decoding side, if the dominant symbol information of each binary symbol and the occurrence probability information of the dominant symbol are known, the binary symbol sequence is uniquely decoded from the coordinate values on the number line output from the encoding side. Can do.

FIG. 13 is an explanatory diagram showing a binary representation of coordinates on a number line.
As can be seen from FIG. 13, as the length of the section is larger, the coordinates in the section can be expressed with a smaller number of bits. Therefore, the more dominant symbols, the higher the efficiency of compression, and the higher the probability of occurrence of the dominant symbols, the higher the efficiency of compression.
When binary symbols are sequentially input, a bit series indicating coordinate values as an output can be sequentially output from the head of the bit series.

H. is an international standard for video coding. In CABAC used in H.264, a sequential arithmetic encoding process that does not use multiplication and division is realized by the concept described below.
H. In the CABAC arithmetic coding module in H.264, a number line of integer precision from “0” to “1023” is held internally, and the probability interval is handled as an interval on this discrete number line. Is called.
In addition, the occurrence probability of the dominant symbol is expressed in a pseudo manner by an integer precision variable called a probability state, and the length of the dominant symbol interval and the length of the inferior symbol interval are also added to the integer using a predefined table. Calculated with subtraction only.

As the arithmetic coding proceeds, the probability interval length becomes shorter and cannot be expressed in 1024 stages. Therefore, every time the probability interval length becomes a certain value or less, a certain interval on the number line including the probability interval is cut out. A process (renormalization) of enlarging to 2 times is performed.
Specifically, the renormalization process is performed so that the probability interval length is maintained at 256 to 510. That is, when the probability interval length becomes less than 256, renormalization is performed until the probability interval length exceeds 256.

The number line that the arithmetic coding module internally after performing renormalization n times is the current number line I from “0” to “1” considered in the arithmetic coding algorithm. A section in which a probability section exists is cut out with a width of 1/2 ⁿ and expressed in an enlarged manner.
Hereinafter, the section represented by the internally held number line is referred to as a processing section, and the processing section when n renormalizations are performed is J _n, and J ₀ = I.
Here, as a partial section of the processing section J _n, a section from “512” to “1023” is J _un , a section from “0” to “511” is J _ln , and a section from “256” to “768” is J _cn. If the probability interval is completely included in J _un at the renormalization timing, J _{n + 1} = J _un (see FIG. 14A), and the probability interval is J _ln. Is completely included in J _{n + 1} = J _ln (see FIG. 14B), and J _{n + 1} = J _cn when the probability interval crosses J _un and J _ln. (See FIG. 14C).

Each time renormalization is performed, one bit is output according to the following rule.
When J _{n + 1} = J _cn , a “indeterminate” bit is output.
When J _{n + 1} = J _un , “1” is output if there is no unconfirmed bit output so far.
On the other hand, if there is an unconfirmed bit, the unconfirmed bit that is earliest in time series is confirmed to “1”, all the unconfirmed bits after that are confirmed to “0”, and “0” is further set. Output.
When J _{n + 1} = J _ln , “0” is output if there is no unconfirmed bit in the bits output so far.
On the other hand, if there is an unconfirmed bit, the earliest unconfirmed bit in the time series is confirmed to “0”, all the unconfirmed bits thereafter are confirmed to “1”, and “1” is further set. Output.

FIG. 15 is an explanatory diagram showing the position and length of the processing section J _n on the number line I when re-normalization is performed according to the above-mentioned rule.
In FIG. 15, J _un is shown as the upper half of J _n and J _ln is shown as the lower half. Moreover, the bold line on the number line represents the probability interval at each time point.
In the first renormalization, since the probability interval is included in J ₁₀ and there is no unconfirmed bit, “0” is output and J ₁ = J ₁₀ .
In the second renormalization, since the probability interval is included in J _u1 and there is no undetermined bit, “1” is output and J ₂ = J _u1 .
In the third renormalization, since the probability interval is included in J _c2 , an unconfirmed bit is output and J ₃ = J _c2 .
In the fourth renormalization, since the probability interval is included in _Ju3 and there is an undetermined bit, the undetermined bit output at the third renormalization is fixed to "1" and "0" Is output.

As shown in FIG. 15, when the bit sequence output from the arithmetic coding module at the time point when renormalization is performed n times, if there is no undetermined bit, the processing section J _n at that time point The coordinates in the whole number line I are shown.
After all the input bin sequences have been encoded, an appropriate termination process is performed so that there is no undefined bit, so that a bit sequence indicating coordinates on the number line I that can uniquely decode the input bin sequence is obtained. can get.
Based on the above concept, sequential arithmetic coding without using multiplication and division is realized.

In addition, the sequential arithmetic decoding process that does not use multiplication and division is realized by the following concept.
Similarly to the encoding side, the decoding side holds the probability interval information while repeating renormalization so that the probability interval length is maintained at 256 to 510.
If the probability information of each bin and the initial value of the probability interval coincide with those of the encoding side, the probability interval at the time of decoding a certain bin is internally held by the arithmetic encoding module when the bin is encoded. Matches the current probability interval.
The probability interval retained internally at the time of performing re-normalization n times is obtained by cutting the interval including the probability interval on the number line I with a width of 1/2 ^{n + 1} and discretizing it in 512 steps. Can be considered.

In the arithmetic decoding process, the section H _n is obtained while reading the input bit series, and the decoding process is performed by overlapping the section H _n and the probability section.
FIG. 16 is an explanatory diagram showing the arithmetic decoding process.
A thick line in the figure represents a probability interval on the number line I, and is divided into a dominant symbol interval and an inferior symbol interval.
At this time, bits are read until either the dominant symbol period or the inferior symbol period overlaps with the period H _n .
That is, when the probability interval is divided as shown in FIG. 16, since the interval H ₁ obtained by reading the first bit overlaps both the dominant symbol interval and the inferior symbol interval, the next bit is read. It is.
Similarly, the sections H ₂ and H ₃ overlap both the dominant symbol section and the inferior symbol section, and the section H ₄ overlaps only the dominant symbol section when reading up to the fourth bit.
Therefore, in this case, information that the bin decoded here is the dominant symbol is output as a decoding result. Such processing is performed while repeating renormalization.

Since the internal probability interval is expressed in 512 steps, when renormalization is performed n times, the interval H _{n + 9} read further 9 bits from that becomes one step in length. It always overlaps either the dominant symbol interval or the inferior symbol interval.
Therefore, the decoding process can be advanced even by an operation of reading fixedly 9 bits at the time of initialization of the decoding process and reading 1 bit after renormalization thereafter.
Based on the above concept, sequential arithmetic decoding without multiplication and division is realized.

As described above, bin encoding probability information is required for arithmetic encoding / decoding. H. In CABAC used in H.264, an encoding mode is determined for each bin, and the method for obtaining the bin probability information is different based on the encoding mode.
Examples of the encoding mode include a normal arithmetic encoding mode and a bypass encoding mode.
The normal arithmetic coding mode is a mode in which coding is performed using the dominant symbol information and the dominant symbol occurrence probability estimated based on the known context information.
The bypass coding mode is a mode in which a dominant symbol is not defined and encoding is performed using a fixed symbol occurrence probability of 0.5.
Here, in the encoding by the above bypass encoding mode, encoding is performed on the assumption that the occurrence probabilities of “0” and “1” are equal. Therefore, compression is impossible in terms of information theory, and 1 bin of actual operation is also possible. One bit is always output for encoding. Thus, the bypass coding mode can be rephrased as a coding mode in which binary symbols are arithmetically coded without any compression.
Although it is not necessary to perform the estimation process of the probability state in the normal arithmetic coding mode, it is necessary to perform operations such as segmentation similarly.

In the framework of arithmetic coding, the value of a bit output at the time of coding a certain bin changes depending on the probability state of the preceding and succeeding bins. Therefore, even when compression is not performed, the above arithmetic code is used. It is necessary to perform encoding / decoding based on the encoding method.
As can be seen, the conventional CABAC bypass coding mode has the effect of reducing the amount of computation by not performing the probability state estimation, but other processing such as segmentation is performed in the same manner as the normal arithmetic coding mode. Therefore, a certain calculation load is applied.

D. Marpe, H. Schwarz, and T. Wiegand, “Context-adaptive binary arithmetic coding in the H.264 / AVC video compression standard”, IEEE Trans. Circuits Syst. Video Technol., Vol. 620-636 (2003).

  Since the conventional entropy coding apparatus is configured as described above, CABAC introduces a bypass coding mode for binary symbols in which the occurrence probabilities of “0” and “1” are not biased. The processing load of the probability state estimation process is reduced. However, operations related to the division of the number line need to be processed in the same way as normal arithmetic encoding / decoding, so that a large amount of calculation is still required for the encoding processing and decoding processing of the bypass code. There was a problem.

The present invention has been made in order to solve the above-described problems, and performs encoding for binary symbols in which the occurrence probability of “0” and “1” is not biased while maintaining the same compression rate as CABAC. An object of the present invention is to obtain an entropy encoding device and an entropy encoding method that can reduce the processing load.
It is another object of the present invention to provide an entropy decoding apparatus and an entropy decoding method capable of decoding binary symbols in which the occurrence probabilities of “0” and “1” are not biased by a decoding process with a small processing load. To do.

  The entropy coding apparatus according to the present invention binarizes a multi-level symbol in a multi-level symbol sequence and outputs a sequence of one or more binary symbols, and the binary symbol relates to the multi-level symbol. Symbol binarizing means for outputting a bin number indicating whether it is a binary symbol, and a dominant symbol indicating a dominant symbol having a high probability of occurring in the binary symbol corresponding to the bin number output from the symbol binarizing means A probability information output means for outputting probability information indicating the occurrence probability of the dominant symbol, and a code for determining a coding mode in a binary symbol corresponding to the bin number output from the symbol binarization means If the encoding mode determined by the encoding mode determining means and the encoding mode determining means is the arithmetic encoding mode, the probability information output means An encoded binary symbol output means for referring to the dominant symbol information output from, and outputting as a coded binary symbol a flag indicating whether or not the binary symbol corresponding to the bin number is a dominant symbol; The encoded binary symbol output from the encoded binary symbol output means is arithmetically encoded using the probability of occurrence of the dominant symbol indicated by the probability information output from the probability information output means, and the encoded result is the encoding result. If the coding mode determined by the arithmetic coding means for outputting the bit and the coding mode determining means is the bypass coding mode, the binary symbol output from the symbol binarizing means is output as the coded bit. A bypass encoding means, and the multiplexing means outputs an encoding bit output from the arithmetic encoding means and an encoding output from the bypass encoding means. The it by multiplexing is obtained so as to generate encoded data.

  According to the present invention, a multilevel symbol in a multilevel symbol sequence is binarized to output a sequence of one or more binary symbols, and the binary symbol of which the binary symbol is related to the multilevel symbol Symbol binarizing means for outputting a bin number indicating whether or not, and dominant symbol information indicating a dominant symbol that has a high probability of occurring in the binary symbol corresponding to the bin number output from the symbol binarizing means is output. Probability information output means for outputting probability information indicating the occurrence probability of the dominant symbol, and encoding mode determination means for determining the encoding mode in the binary symbol corresponding to the bin number output from the symbol binarizing means If the coding mode determined by the coding mode determining means is the arithmetic coding mode, the dominant signal output from the probability information output means is displayed. The encoded binary symbol output means for outputting as a coded binary symbol a flag indicating whether or not the binary symbol corresponding to the bin number is a dominant symbol with reference to the volume information, and the probability information output means Arithmetic encoding the encoded binary symbol output from the encoded binary symbol output means using the occurrence probability of the dominant symbol indicated by the output probability information, and outputting the encoded bit as the encoding result An encoding unit; and a bypass encoding unit that outputs a binary symbol output from the symbol binarization unit as an encoding bit if the encoding mode determined by the encoding mode determination unit is a bypass encoding mode; And the multiplexing means multiplexes the encoded bit output from the arithmetic encoding means and the encoded bit output from the bypass encoding means. Since it is configured to generate data, it is possible to reduce the processing load of encoding for binary symbols in which the occurrence probabilities of “0” and “1” are not biased while maintaining the same compression rate as CABAC. effective.

It is a block diagram which shows the entropy encoding apparatus by Embodiment 1 of this invention. It is a flowchart which shows the processing content of the entropy encoding apparatus by Embodiment 1 of this invention. It is explanatory drawing which shows an example of the binarization table of a multi-value symbol. It is a flowchart which shows the arithmetic encoding process of the arithmetic encoding part 6. FIG. (A) represents Range, Low, etc., (b) is explanatory drawing which shows the probability area divided | segmented into the dominant symbol area and the inferior symbol area. It is explanatory drawing which shows the input-output relationship of a bin series and a bit series in case an encoding mode is either an arithmetic encoding mode or a bypass encoding mode. It is explanatory drawing which shows the input-output relationship of a bin series and a bit series in case arithmetic coding mode and bypass coding mode are mixed. It is explanatory drawing which shows the variable-length code example of the number D of prefetch bits, and the example of multiplexing. It is a block diagram which shows the entropy decoding apparatus by Embodiment 2 of this invention. It is a flowchart which shows the processing content of the entropy decoding apparatus by Embodiment 2 of this invention. 4 is a flowchart showing an arithmetic decoding process of the arithmetic decoding unit 25. It is a conceptual diagram in the case of carrying out arithmetic coding of the binary symbol series. It is explanatory drawing which shows the binary number expression of the coordinate on a number line. It is explanatory drawing which shows the relationship between the process area at the time of performing a probability area and renormalization. It is an explanatory view showing the position and length of the processing section J _n in numbers straight I. It is explanatory drawing which shows an arithmetic decoding process.

Embodiment 1 FIG.
1 is a block diagram showing an entropy encoding apparatus according to Embodiment 1 of the present invention.
In FIG. 1, a binarization unit 1 refers to a binarization table of multilevel symbols, binarizes the multilevel symbols in the multilevel symbol sequence, and generates a sequence of binary symbols having a length of 1 or more. A process of outputting to the encoding method changeover switch 4 is performed.
Also, the binarization unit 1 refers to the binarization table of the multilevel symbols, and obtains a bin number indicating which binary symbol each binary symbol is related to the multilevel symbol, as a probability information output unit 2 And the process output to the encoding mode determination part 3 is implemented.
The binarization unit 1 constitutes symbol binarization means.

  Probability information output unit 2 indicates, for each bin number, a dominant symbol (“0” or “1” having a higher probability of occurrence in a binary symbol corresponding to the bin number in advance). Predominate symbol information indicating the symbol) and probability information indicating the occurrence probability of the preferential symbol are stored, and preferential symbol information indicating the preferential symbol corresponding to the bin number output from the binarization unit 1 is encoded bin While outputting to the output part 5, the process which outputs the probability information which shows the occurrence probability of the dominant symbol to the arithmetic coding part 6 is implemented. The probability information output unit 2 constitutes probability information output means.

  The encoding mode determination unit 3 stores in advance the encoding mode (arithmetic encoding mode, bypass encoding mode) in the binary symbol corresponding to the bin number for each bin number, and outputs from the binarization unit 1 A process for outputting the encoding mode corresponding to the bin number to the encoding method changeover switch 4 is performed.

When the encoding mode changeover switch 4 determines that the encoding mode of the binary symbol corresponding to the bin number output from the binarization unit 1 is the arithmetic encoding mode by the encoding mode determination unit 3, the binary code When the symbol is output to the encoding bin output unit 5 and the encoding mode of the binary symbol corresponding to the bin number is determined as the bypass encoding mode by the encoding mode determination unit 3, the binary symbol is bypassed. A process of outputting to the encoding unit 7 is performed.
The encoding mode determination unit 3 and the encoding method changeover switch 4 constitute an encoding mode determination unit.

When the encoding bin output unit 5 receives the binary symbol from the encoding method changeover switch 4, the encoding bin output unit 5 refers to the dominant symbol information output from the probability information output unit 2 and determines whether or not the binary symbol is the dominant symbol. Is output to the arithmetic coding unit 6 as a coded binary symbol.
That is, the encoding bin output unit 5 indicates, for each binary symbol in the binary symbol sequence output from the encoding scheme changeover switch 4, the dominant symbol information output from the probability information output unit 2 for the binary symbol. It is determined whether or not it matches the dominant symbol, and a process of outputting the determination result to the arithmetic encoding unit 6 as an encoded binary symbol is performed.
The encoded bin output unit 5 constitutes encoded binary symbol output means.

  The arithmetic encoding unit 6 arithmetically encodes the encoded binary symbol output from the encoded bin output unit 5 using the occurrence probability information of the dominant symbol indicated by the probability information output from the probability information output unit 2, A process of outputting an encoding bit as an encoding result to the arithmetic code buffer 10 of the encoded data output unit 8 is performed. The arithmetic encoding unit 6 constitutes arithmetic encoding means.

When the bypass encoding unit 7 receives a binary symbol from the encoding system changeover switch 4, the bypass encoding unit 7 performs a process of outputting the binary symbol as an encoding bit to the bypass code buffer 9 of the encoded data output unit 8.
That is, when the binary symbol output from the encoding method switch 4 is “0”, the bypass encoding unit 7 outputs the encoded bit of “0” to the bypass code buffer 9 of the encoded data output unit 8. When the binary symbol output from the encoding method switch 4 is “1”, a process of outputting the encoded bit of “1” to the bypass code buffer 9 of the encoded data output unit 8 is performed.
The bypass encoding unit 7 constitutes bypass encoding means.

The encoded data output unit 8 includes the encoded bit and bypass code output from the arithmetic encoding unit 6 in the order corresponding to the read timing of the encoded bit when the entropy decoding apparatus of FIG. 9 performs arithmetic decoding of the encoded bit. The encoding bit output from the encoding unit 7 is multiplexed to generate encoded data.
That is, the encoded data output unit 8 assigns a serial number to each encoded bit in the two encoded bit sequences output from the arithmetic encoding unit 6 and the bypass encoding unit 7, Based on the number, each encoded bit in the two encoded bit sequences is multiplexed, and processing for generating encoded data as one encoded bit sequence is performed.
The encoded data output unit 8 constitutes a multiplexing means.

The bypass code buffer 9 is a storage medium that stores the encoded bit sequence output from the bypass encoding unit 7.
The arithmetic code buffer 10 is a storage medium that stores the encoded bit sequence output from the arithmetic encoding unit 6.
The encoded data multiplexing unit 11 assigns the number of the order read by the entropy decoding device of FIG. 9 to each encoded bit in the encoded bit sequence stored in the bypass code buffer 9 and the arithmetic code buffer 10. Based on the number, a process of multiplexing and outputting each encoded bit in the encoded bit sequence stored in the bypass code buffer 9 and the arithmetic code buffer 10 is performed.

In the example of FIG. 1, a binarization unit 1, a probability information output unit 2, a coding mode determination unit 3, a coding mode changeover switch 4, a coding bin output unit 5, an arithmetic code, which are components of the entropy coding device. Each of the encoding unit 6, the bypass encoding unit 7 and the encoded data output unit 8 is configured by dedicated hardware (for example, a semiconductor integrated circuit on which a CPU is mounted, or a one-chip microcomputer). Assuming, all or part of the entropy encoding device may be configured by a computer.
When all or part of the entropy encoding device is configured by a computer, the binarization unit 1, the probability information output unit 2, the encoding mode determination unit 3, the encoding method changeover switch 4, and the encoding bin output All or part of the program describing the processing contents of the unit 5, the arithmetic encoding unit 6, the bypass encoding unit 7 and the encoded data output unit 8 is stored in the memory of the computer, and the CPU of the computer stores the memory The program stored in the program may be executed.
FIG. 2 is a flowchart showing the processing contents of the entropy coding apparatus according to Embodiment 1 of the present invention.

Next, the operation will be described.
When the multi-level symbol sequence is input, the binarization unit 1 binarizes the multi-level symbol in the multi-level symbol sequence according to a rule determined in advance according to the type of the multi-level symbol. The sequence of value symbols is output to the encoding method changeover switch 4 (step ST1).
Here, FIG. 3 is an explanatory diagram showing an example of a binarization table for multilevel symbols.
Since the types of multilevel symbols input to the binarization unit 1 (for example, macroblock types in image encoding, DCT coefficients, etc.) are determined by syntax, the binarization unit 1 inputs multilevels. The type of symbol can be recognized.

In the example of FIG. 3, if the type of the input multilevel symbol is the multilevel symbol A, the multilevel symbol in the multilevel symbol sequence is binarized with reference to the binarization table of (a), If the type of the multilevel symbol is the multilevel symbol B, the multilevel symbol in the multilevel symbol sequence is binarized with reference to the binarization table of (b).
If the type of multi-level symbol is multi-level symbol C, the multi-level symbol in the multi-level symbol sequence is binarized with reference to the binarization table of (c).
For example, if the type of the multi-level symbol is the multi-level symbol A and the value of the multi-level symbol is “2”, the binarization unit 1 changes the binary symbol to “1”, “0”, “1”. "" Is output.

Further, the binarization unit 1 refers to the binarization table of the multilevel symbols, and obtains a bin number indicating what number of binary symbols one or more binary symbols are related to the multilevel symbols. It outputs to the output part 2 and the encoding mode determination part 3.
For example, when outputting a sequence of “1”, “0”, “1” as a binary symbol corresponding to a multilevel symbol of “2”, it corresponds to a sequence of “1”, “0”, “1”. “0”, “1”, “2” are output as the bin numbers to be processed.
Further, when a series of “1”, “1”, “1”, “0”, “0” is output as a binary symbol corresponding to a multi-value symbol of “7”, “1”, “1” , “0”, “1”, “2”, “3”, “4” are output as the bin numbers corresponding to the series of “1”, “0”, “0”.

  The encoding mode determination unit 3 stores in advance information on the encoding mode corresponding to the bin number for each bin number (for example, bin as information related to information such as the type of multi-level symbol). When the bin number is received from the binarization unit 1, by referring to the information of the encoding mode, the binary symbol corresponding to the bin number is stored. The encoding mode is determined and output to the encoding method changeover switch 4. (Step ST2).

In the binarization table of FIG. 3, information on the coding mode corresponding to the bin number of the binary symbol is recorded.
In the example of FIG. 3, the “0” encoding mode is the arithmetic encoding mode, and the “1” encoding mode is the bypass encoding mode.
For example, when a bin number series of “0”, “1”, “2”, “3”, “4” is output from the binarizing unit 1, the encoding mode corresponding to the bin number of “0” Is the arithmetic coding mode, the coding mode corresponding to the bin number of “1” is the arithmetic coding mode, the coding mode corresponding to the bin number of “2” is the arithmetic coding mode, and corresponds to the bin number of “3” The encoding mode to be performed is the arithmetic encoding mode, and the encoding mode corresponding to the bin number of “4” is the bypass encoding mode.
When a bin number series of “9”, “10”, “11”, “12” is output from the binarization unit 1, the coding mode corresponding to the bin number of “9” is bypass coding. Mode, the encoding mode corresponding to the bin number of “10” is the arithmetic encoding mode, the encoding mode corresponding to the bin number of “11” is the arithmetic encoding mode, and the encoding mode corresponding to the bin number of “12” Enters bypass encoding mode.

When the encoding scheme changeover switch 4 receives the binary symbol sequence from the binarizing unit 1, the encoding mode of the binary symbols in the binary symbol sequence is changed to the arithmetic encoding mode by the encoding mode determining unit 3. If determined (when the encoding mode corresponding to the bin number of the binary symbol is “0”), the binary symbol is output to the encoded bin output unit 5 (step ST3).
On the other hand, when the encoding mode of the binary symbol in the binary symbol sequence is determined as the bypass encoding mode by the encoding mode determination unit 3 (the encoding mode corresponding to the bin number of the binary symbol is When it is “1”, the binary symbol is output to the bypass encoding unit 7 (step ST3).
In the above example, the operation in the case where the encoding apparatus has only the arithmetic encoding mode and the bypass encoding mode has been described. However, the encoding apparatus selects an encoding mode X other than the arithmetic encoding mode and the bypass encoding mode. If so, the encoding mode determination unit 3 can determine the encoding mode information corresponding to the encoding mode X, and the encoding method changeover switch 4 can determine the encoding mode corresponding to the encoding mode X. When the information is received, the binary symbol can be output to the module that performs the encoding process corresponding to the encoding mode X.

When the encoding method of the binary symbol is determined to be the bypass encoding mode, and the bypass encoding unit 7 receives the binary symbol from the encoding method changeover switch 4, the bypass encoding unit 7 sets the binary symbol as an encoding bit (2 Value symbol = encoded bit), and the encoded bit is stored in the bypass code buffer 9 of the encoded data output unit 8 (step ST4).
That is, when the bypass encoding unit 7 receives the binary symbol from the encoding system changeover switch 4 and the binary symbol is “0”, the bypass encoding unit 7 sets the encoded bit of “0” to the encoded data output unit 8. When the binary symbol is “1”, the encoded bit of “1” is stored in the bypass code buffer 9 of the encoded data output unit 8.

For each bin number, the probability information output unit 2 preliminarily selects a dominant symbol (“0” or “1” having a higher probability of occurrence in a binary symbol corresponding to the bin number). Dominating symbol information indicating the symbol) and probability information indicating the occurrence probability of the dominating symbol.
For example, in the case of the binarization table shown in FIG. 3A, the probability that a multi-valued symbol of “0” will occur in a multi-valued symbol having values of “0” to “9” is about 70%. In this case, the probability that the symbol “0” is generated in the binary symbol corresponding to the bin number “0” is about 70%, and therefore, the dominant symbol in the binary symbol is the symbol “0”. Become. The probability of occurrence of this dominant symbol is about 70%.
When the probability information output unit 2 receives the bin number from the binarization unit 1, the probability information output unit 2 outputs the dominant symbol information indicating the dominant symbol corresponding to the bin number to the encoded bin output unit 5, and the occurrence probability of the dominant symbol Is output to the arithmetic coding unit 6 (step ST5).

The encoding bin output unit 5 determines that the encoding method of the binary symbols is the calculation encoding mode, and receives the binary symbol from the encoding method switch 4, the superiority output from the probability information output unit 2 With reference to the symbol information, a flag indicating whether or not the binary symbol is the dominant symbol is output to the arithmetic encoding unit 6 as an encoded binary symbol (step ST6).
That is, the encoding bin output unit 5 receives, for each binary symbol in the binary symbol sequence output from the encoding scheme changeover switch 4, the dominant symbol information from which the binary symbol is output from the probability information output unit 2. It is determined whether or not it matches the dominant symbol shown, and the determination result is output to the arithmetic encoding unit 6 as an encoded binary symbol (for example, match = 1, mismatch = 0).

  When the arithmetic encoding unit 6 receives the encoded binary symbol from the encoded bin output unit 5, the arithmetic encoding unit 6 uses the dominant symbol occurrence probability information indicated by the probability information output from the probability information output unit 2 to perform the encoding 2 The value symbol is arithmetically encoded (step ST7), and the encoded bit as the encoding result is stored in the arithmetic code buffer 10 of the encoded data output unit 8 (step ST8).

Hereinafter, the arithmetic encoding process of the arithmetic encoding unit 6 will be specifically described.
FIG. 4 is a flowchart showing the arithmetic encoding process of the arithmetic encoding unit 6.
The arithmetic encoding process shown in this flowchart is the same as that described in the background art section. It conforms to the arithmetic coding algorithm used by H.264 CABAC. Terms used in the background art column are also used.
First, an outline of the arithmetic encoding process will be described.

The arithmetic coding unit 6 holds information on the probability interval using two registers, Range and Low.
As shown in FIG. 5A, Range represents the length of the current probability interval, and Low represents the distance from the lower limit of the processing interval to the lower limit of the probability interval. The initial values of these registers are Range = 510 and Low = 0.
The division of the probability interval is a process using integers as described in the background art section.
Using the value of Range and the probability information indicating the occurrence probability of the dominant symbol output from the probability information output unit 2, from the value of LPSLLength determined by table reference, the probability interval is represented as shown in FIG. Divide into dominant symbol interval and inferior symbol interval.
In addition, it has an RCounter that is a counter indicating the number of bits currently “indeterminate”. The initial value of RCounter is 0.
Based on the above, the flow of the operation of encoding the encoded binary symbol that is bin of bin number k will be described. However, the number of encoded bits output at this time is n-1.

First, the arithmetic encoding unit 6 divides the processing depending on whether the input bin (b _k ), which is the encoded binary symbol output from the encoded bin output unit 5, is a dominant symbol or an inferior symbol (see FIG. Step ST21 of 4).
When the input bin (b _k ) is the dominant symbol, the arithmetic encoding unit 6 updates the probability interval to the dominant symbol interval (step ST22).
Range = Range-LPSLlength
This corresponds to the process of I _k = I _{Mk−1 that} updates the dominant symbol interval as the next probability interval.

When the input bin (b _k ) is an inferior symbol, the arithmetic encoding unit 6 updates the probability interval to the inferior symbol interval (step ST23).
Low = Range-LPLength
Range = LPSLlength
This corresponds to the processing of I _k = I _{Lk−1 that} updates the inferior symbol interval as the next probability interval.

Next, the arithmetic encoding unit 6 performs a loop process on the condition of the value of Range.
The loop continuation condition is Range <256, and while the loop continuation condition is satisfied, the following processes of steps ST25 to ST29 are repeatedly performed (step ST24). If Range ≧ 256, the process is terminated.
The processes in steps ST25 to ST29 correspond to the above-described renormalization process.

Steps ST25 and ST26 are branch portions that determine whether the current probability interval is included in J _un , J _cn , or J _ln and switch processing.
When a Low ≧ 512 as the current probability interval is included in J _un, performs the processing of step ST27 (step ST25).
Low <If it is 256, the current probability interval as contained in J _ln, it performs the processing of step ST28 (step ST25, ST26).
512> If a Low ≧ 256, the current probability interval as contained in J _cn, performs the processing of step ST29 (step ST25, ST26).
Hereinafter, processing contents of steps ST27, ST28, and ST29 will be described.

(1) Processing contents of step ST27 The arithmetic encoding unit 6 sets Low = (Low−512) × 2 and Range = Range × 2. This corresponds to the renormalization process shown in FIG.
Further, when RCounter ≧ 1, the arithmetic encoding unit 6 determines the bit of the arithmetic code bit number n-RCounter to “1”, and sets the bits of the arithmetic code bit number n-RCounter + 1 to the arithmetic code bit number n−1. Set to “0”.
Then, a bit of “0” is stored in the arithmetic code buffer 10 as the bit of the arithmetic code bit number n, and RCounter = 0 is set.
When RCounter = 0, a bit of “1” is stored in the arithmetic code buffer 10 as the bit of the arithmetic code bit number n.

(2) Processing contents of step ST28 The arithmetic encoding unit 6 sets Low = Low × 2 and Range = Range × 2. This corresponds to the renormalization process shown in FIG.
Further, when RCounter ≧ 1, the arithmetic encoding unit 6 determines the bit of the arithmetic code bit number n-RCounter to be “0”, and sets the bits of the arithmetic code bit number n-RCounter + 1 to the arithmetic code bit number n−1. Set to “1”.
Then, a bit of “1” is stored in the arithmetic code buffer 10 as the bit of the arithmetic code bit number n, and RCounter = 0 is set.
When RCounter = 0, a bit of “0” is stored in the arithmetic code buffer 10 as the bit of the arithmetic code bit number n.

(3) Processing contents of step ST29 The arithmetic encoding unit 6 sets Low = (Low−256) × 2 and Range = Range × 2. This corresponds to the renormalization process shown in FIG.
Further, the arithmetic encoding unit 6 sets RCounter = RCounter + 1, and stores “undetermined” bit in the arithmetic code buffer 10 as the bit of the arithmetic code bit number n.

The encoded data multiplexing unit 11 of the encoded data output unit 8 performs the entropy decoding apparatus shown in FIG. 9 for each encoded bit in the encoded bit sequence stored in the bypass code buffer 9 and the arithmetic code buffer 10. (Step ST9 in FIG. 2), and based on the number, the coded bits in the coded bit sequence stored in the bypass code buffer 9 and the arithmetic code buffer 10 are multiplexed and coded. Encoded data is generated and the encoded data is output (step ST10).
Hereinafter, an example of the processing content of the encoded data multiplexing unit 11 will be specifically described.

The encoded data multiplexing unit 11 multiplexes encoded bits by a multiplexing method that does not increase the amount of encoded data at all.
In this multiplexing method, each code in a sequence of coding bits (bypass code bit) stored in the bypass code buffer 9 and a sequence of coding bits (arithmetic code bit) stored in the arithmetic code buffer 10 is used. The order read by the entropy decoding device in FIG. 9 is assigned to the coded bits, and the bypass code bit and the arithmetic code bit are multiplexed as coded data based on the order.

Here, the order read by the entropy decoding device in FIG. 9 is based on the decoding operation, when performing bin coding in the arithmetic coding mode and bypass code mode, when decoding bins in the arithmetic coding mode. When it is necessary to read a bit, the head of the unread portion of the input bit sequence at that time is an arithmetic code bit necessary for decoding the bin, and the bit is decoded when decoding the bin in the bypass encoding mode. Similarly, when reading is necessary, this means an order in which the beginning of the unread portion of the input bit sequence at that time is a bypass code bit necessary for decoding the bin.
That is, the entropy decoding device of FIG. 9 indicates an order in which decoding can be performed correctly only by reading the bit from the head of the unread portion of the input bit sequence.

If the bit sequence is multiplexed in this order, it is of course possible to discriminate the arithmetic code bit and bypass code bit in the input bit sequence without requiring additional information.
The order of bits read by the entropy decoding device in FIG. 9 differs depending on the operation of arithmetic decoding. Therefore, it is necessary to change the multiplexing operation depending on the arithmetic decoding operation in the entropy decoding apparatus of FIG.
Hereinafter, as an example, the operation of the arithmetic encoding unit 6 is assumed as the operation of the entropy encoding device, and the encoded data input unit 21 and the arithmetic decoding unit 25 (described later) are described as the operation of the entropy decoding device in FIG. Assuming the operation of the second embodiment), the specific operation of multiplexing will be described.

First, the coding mode is determined to be the arithmetic coding mode, a sequence of coded bits is output by the arithmetic coding unit 6 of the entropy coding device, and a sequence of coded bits by the arithmetic decoding unit 25 of the entropy decoding device. The operation of bit output and input when I is arithmetically decoded will be described.
As described above, the arithmetic coding unit 6 calculates zero or more “0”, “1”, or “indeterminate” coded bits (arithmetic) in the calculation coding of one coded binary symbol (bin). Code bit).
Here, in FIG. 6A, a sequence of encoded binary symbols (bin sequence) output from the encoded bin output unit 5 is input to the arithmetic encoding unit 6, and the arithmetic encoding unit 6 encodes 2. An example is shown in which a sequence of value symbols is calculated and encoded to output a sequence of encoded bits (arithmetic code bits).
The arrow in the figure indicates that in the arithmetic coding of the original coded binary symbol from which the arrow has come out, the previous coded bit pointed to by the arrow is output.
In the example of FIG. 6A, the encoded bit of bit number n is output in the arithmetic encoding of the encoded binary symbol (bin) of bin number k. In addition, in the arithmetic encoding of the encoded binary symbol (bin) with the bin numbers k + 1 and k + 2, the encoded bit is not output, and in the arithmetic encoding of the encoded binary symbol (bin) with the bin number k + 3, the bit number is output. Two encoded bits n + 1 and n + 2 are output.

FIG. 6B shows a sequence of encoded bits (arithmetic code bits) output from the arithmetic encoding unit 6 after the encoded data input unit 21 inputs the sequence of the encoded bits. An example is shown in which a sequence is input to an arithmetic decoding unit 25 via a decoding method switch 24, and the arithmetic decoding unit 25 arithmetically decodes a sequence of encoded bits and outputs a sequence of decoded binary symbols (bin). .
The arrow in the figure indicates that in the decoding of the bin pointed to by the arrow, the original encoded bit indicated by the arrow is input.
In the example of FIG. 6B, the encoded bit of bit number n + 9 is input in the arithmetic decoding of the decoded binary symbol (bin) of bin number k. In addition, in the arithmetic decoding of the decoded binary symbol (bin) of the bin numbers k + 1 and k + 2, the encoded bit is not input, and in the arithmetic decoding of the decoded binary symbol (bin) of the bin number k + 3, the bit numbers n + 10 and n + 11 Two encoded bits are input.

As shown in FIGS. 6A and 6B, the number of encoded bits output by the arithmetic encoding of the encoded binary symbol (bin) of bin number K is the decoded binary symbol (bin) of bin number K. ) Equal to the number of encoded bits input by arithmetic decoding.
Further, when the bit number of the coded bit sequence output by the arithmetic coding of the coded binary symbol (bin) of bin number K is N to N + d, the arithmetic decoding of the decoded binary symbol (bin) of bin number K is performed. The bit numbers of the encoded bit sequence input in (1) are N + 9 to N + d + 9.
In other words, the encoded bit input to the arithmetic decoding unit 25 at the time of arithmetic decoding of the decoded binary symbol (bin) having the bin number K is the encoded binary symbol (bin) having the bin number K by the arithmetic encoding unit 6. From the encoded bit output at the time of the arithmetic encoding, the encoded bit is 9 bits ahead. The operation in which the entropy decoding apparatus prefetches 9 bits will be described in the second embodiment.

Next, the coding mode is determined to be a bypass coding mode, a sequence of encoded bits is output from the bypass encoding unit 7 of the entropy encoding device, and a sequence of encoded bits is output from the bypass decoding unit 27 of the entropy decoding device. The operation of bit output and input when is decoded will be described.
As described above, the bypass encoding unit 7 outputs one “0” or “1” encoding bit (bypass code bit) in encoding one binary symbol (bin).
Here, in FIG. 6C, a binary symbol sequence (bin sequence) is input to the bypass encoding unit 7, and the bypass encoding unit 7 encodes the binary symbol sequence to generate an encoded bit (bypass code). An example of outputting a (bit) series is shown.
In the example of FIG. 6C, when the bins having bin numbers k, k + 1, k + 2, k + 3, and k + 4 are encoded, encoded bits having bit numbers m, m + 1, m + 2, m + 3, and m + 4 are output, respectively.

FIG. 6D shows a case where the encoded bit (bypass code bit) sequence output from the bypass encoding unit 7 is input to the encoded data input unit 21 and then the encoded bit input from the encoded data input unit 21. An example is shown in which a sequence is input to a bypass decoding unit 27 via a decoding scheme changeover switch 24, and the bypass decoding unit 27 decodes a sequence of encoded bits and outputs a sequence of decoded binary symbols (bin).
In the example of FIG. 6D, when the decoded binary symbol (bin) of the bin numbers k, k + 1, k + 2, k + 3, and k + 4 is decoded, the encoded bits (bypass) of the bit numbers m, m + 1, m + 2, m + 3, and m + 4, respectively. Code bit) is input.

  As shown in FIGS. 6C and 6D, the number of encoded bits and the bit number output by encoding the binary symbol (bin) with bin number K are the decoded binary symbol (bin) with bin number K. It is equal to the number of encoded bits and the bit number input in the decoding of).

Next, the operation of multiplexing the arithmetic code bit and the bypass code bit when the bypass code mode and the arithmetic coding mode are mixed will be described.
FIG. 7 is an explanatory diagram showing the input / output relationship between the bin sequence and the bit sequence when the arithmetic coding mode and the bypass coding mode coexist.
In the upper bin series in FIG. 7A, the thin line square represents the bin in the arithmetic code mode, and the thick line square represents the bin in the bypass code mode.
In the lower bit series in FIG. 7A, the thin line square represents an arithmetic code bit, and the thick line square represents a bypass code bit.
The arithmetic code bit and the bypass code bit are individually numbered.
The arrow in the figure indicates that, as in FIG. 6A and the like, in the encoding of the bin that is the source of the arrow, the bit is multiplexed and output at the position indicated by the arrow.

The bin with the bin number k + 1 is a bin in the bypass encoding mode. At the time of encoding this bin, the latest bit number is n among the arithmetic code bit sequences output so far.
At this time, the mth bypass code bit output when the k + 1th bin is encoded is multiplexed next to the n + 9th arithmetic code bit delayed by n to 9 bits.
Similarly, for the (m + 1) th bypass code bit output by the bin encoding of the k + 3th bypass encoding mode, at the time of performing this encoding, the latest arithmetic code bit sequence output so far Since the bit number of n is n, it is multiplexed between the (n + 9) th arithmetic code bit and the (n + 10) th arithmetic code bit.
In this case, since the mth bypass code bit exists at the same position, it is multiplexed next to the mth bypass code bit.

FIG. 7B shows a decoding operation in which the multiplexed bit sequence is input. As described above, the bit input to the arithmetic decoding unit 25 when decoding the bin with the bin number K is the arithmetic code from the bit output by the arithmetic encoding unit 6 when the bin with the bin number K is encoded. Counting by the bit number, it becomes 9 bits ahead.
Therefore, at the time of decoding the bin in the arithmetic coding mode of the bin number k, the n + 9th arithmetic code bit which is the head of the unread bit sequence at this time is read.
The (k + 1) th bin is in the bypass encoding mode, but at the time of decoding this bin, the start of the unread bit sequence becomes the mth bypass code bit according to the result of the above multiplexing, and this bit is read.
Similarly, the k + 3th bin is also in the bypass encoding mode, but when this bin is decoded, the head of the unread bit sequence becomes the m + 1th bypass code bit, and this bit is read.
The bins from k + 4 to k + 15 are all bins in the arithmetic coding mode. However, when decoding these, they are correctly decoded by reading the head of the unread bit sequence at the time of decoding.

  Note that the processing of steps ST1 to ST10 in FIG. 2 is repeatedly executed until the processing of all the multilevel symbol sequences is completed (step ST11).

  As is apparent from the above, according to the first embodiment, the multi-level symbol in the multi-level symbol sequence is binarized to output a sequence of one or more binary symbols, and the binary symbols are many. There is a high probability of occurrence in the binarization unit 1 that outputs a bin number indicating what number binary symbol is associated with the value symbol and the binary symbol that corresponds to the bin number output from the binarization unit 1 In the binary symbol corresponding to the bin number output from the probability information output unit 2 that outputs the dominant symbol information indicating the dominant symbol and outputs the probability information indicating the occurrence probability of the dominant symbol, and the binarizing unit 1 The encoding mode determination unit 3 that determines the encoding mode and the encoding mode of the binary symbol corresponding to the bin number output from the binarization unit 1 are arithmetic codes by the encoding mode determination unit 3. When the coding mode is determined, the binary symbol is output to the coding bin output unit 5, and the coding mode of the binary symbol corresponding to the bin number is changed to the bypass coding mode by the coding mode determination unit 3. If determined, the encoding method switch 4 that outputs the binary symbol to the bypass encoding unit 7 and the superiority output from the probability information output unit 2 when the binary symbol is received from the encoding method switch 4 An encoding bin output unit 5 that outputs a flag indicating whether or not a binary symbol corresponding to the bin number is a dominant symbol with reference to the symbol information as an encoded binary symbol; The encoded binary symbol output from the encoded bin output unit 5 is arithmetically encoded using the probability of occurrence of the dominant symbol indicated by the output probability information, and the encoded result is obtained. An arithmetic coding unit 6 that outputs a coding bit, and a bypass code that outputs a binary symbol output from the binarizing unit 1 as a coding bit when a binary symbol is received from the coding system switch 4 The encoded data output unit 8 multiplexes the encoded bit output from the arithmetic encoding unit 6 and the encoded bit output from the bypass encoding unit 7 to generate encoded data. With this configuration, there is an effect that it is possible to reduce the processing load of encoding for binary symbols in which the occurrence probabilities of “0” and “1” are not biased while maintaining the same compression rate as CABAC. In addition, the entropy decoding device also has an effect of reducing the processing load of decoding for binary symbols in which the occurrence probabilities of “0” and “1” are not biased.

In the first embodiment, when the entropy decoding apparatus of FIG. 1 performs arithmetic decoding, the encoded data multiplexing unit 11 of the encoded data output unit 8 assumes that 9-bit bits are prefetched in a fixed manner. However, the arithmetic code bit and the bypass code bit are multiplexed. However, when the entropy decoding apparatus performs arithmetic decoding, it may be implemented so that 16-bit bits are prefetched fixedly.
Therefore, when the entropy decoding apparatus performs arithmetic decoding, information indicating how many bits should be prefetched in a fixed manner (decoding operation information defining the read timing of the encoded bits) is used as the encoded data multiplexing unit 11. However, you may make it notify to an entropy decoding apparatus.

In this case, when the entropy decoding apparatus performs arithmetic decoding, the encoded data multiplexing unit 11 multiplexes the arithmetic code bit and the bypass code bit on the assumption that the number of bits indicated by the decoding operation information is prefetched. become.
On the other hand, when performing the arithmetic decoding, the entropy decoding device prefetches the number of bits indicated by the decoding operation information notified from the entropy encoding device.
The encoded data multiplexing unit 11 may transmit the decoding operation information to the entropy decoding device separately from the encoded data, or multiplex the decoding operation information with the encoded data and transmit it to the entropy decoding device. Also good.

When decoding operation information is multiplexed with encoded data and transmitted to the entropy decoding device, the encoded data multiplexing unit 11 performs variable length encoding on the decoding operation information (for example, table reference variable length encoding). Variable-length coding method). FIG. 8A is an example of a binarization table showing a variable length code example of the number D of prefetch bits that is decoding operation information.
For example, when a multi-level symbol sequence is applied to moving image data, it can be multiplexed into a sequence parameter set (SPS) as shown in FIG. 8B.
Here, an example is shown in which the decoding operation information is the number D of prefetch bits. However, any information that prescribes the read timing of the encoded bits when the entropy decoding apparatus performs arithmetic decoding, and is limited to the number D of prefetch bits. is not.

Embodiment 2. FIG.
FIG. 9 is a block diagram showing an entropy decoding apparatus according to Embodiment 2 of the present invention.
In FIG. 9, when the encoded data input unit 21 inputs the encoded data generated by the entropy encoding device of FIG. 1, the encoded data sequence is read out from the beginning of the read position of the encoded data, and the encoded bit sequence Is output to the decoding method changeover switch 24.
In addition, the encoded data input unit 21 refers to the binarization table of the multilevel symbol, and obtains a binary symbol (binary symbol when the encoded bit is decoded) obtained from the encoded bit in the encoded bit sequence. ) Is output to the probability information output unit 22, the encoding mode determination unit 23, and the multi-level conversion unit 28.
The encoded data input unit 21 constitutes an encoded bit sequence reading unit.

  Probability information output unit 22 indicates, for each bin number, a dominant symbol (“0” or “1” having a higher probability of occurrence in a binary symbol corresponding to the bin number). Predominate symbol information indicating the symbol) and probability information indicating the occurrence probability of the dominant symbol, and storing the probability information indicating the occurrence probability of the dominant symbol corresponding to the bin number output from the encoded data input unit 21. While outputting to the arithmetic decoding part 25, the process which outputs the dominant symbol information which shows the dominant symbol to the bin output part 26 is implemented. The probability information output unit 22 constitutes probability information output means.

  The encoding mode determining unit 23 stores in advance the encoding mode (arithmetic encoding mode, bypass encoding mode) in the binary symbol corresponding to the bin number for each bin number. A process of outputting the encoding mode in the binary symbol corresponding to the output bin number to the decoding method changeover switch 24 is performed.

When the coding mode of the binary symbol corresponding to the bin number output from the coded data input unit 21 is determined to be the arithmetic coding mode by the coding mode determining unit 23, the decoding method changeover switch 24 is coded data. When the encoding bit output from the input unit 21 is output to the arithmetic decoding unit 25 and the encoding mode of the binary symbol corresponding to the bin number is determined as the bypass encoding mode by the encoding mode determination unit 23 Then, a process of outputting the encoded bit to the bypass decoding unit 27 is performed.
The encoding mode determining unit 23 and the decoding method changeover switch 24 constitute encoding mode determining means.

  When the arithmetic decoding unit 25 receives the encoded bit from the decoding method changeover switch 24, the arithmetic decoding unit 25 arithmetically decodes the encoded bit using the occurrence probability information of the dominant symbol indicated by the probability information output from the probability information output unit 22, A process of outputting the decoded binary symbol that is the decoding result to the bin output unit 26 is performed. The arithmetic decoding unit 25 constitutes arithmetic decoding means.

When the bin output unit 26 receives the decoded binary symbol sequence from the arithmetic decoding unit 25, the bin output unit 26 refers to the dominant symbol information output from the probability information output unit 22 to determine whether or not the decoded binary symbol is a dominant symbol. A process of outputting the indicated flag to the multilevel conversion unit 28 as a binary symbol is performed.
That is, for each binary symbol in the decoded binary symbol sequence output from the arithmetic decoding unit 25, the bin output unit 26 outputs the dominant symbol indicated by the dominant symbol information output from the probability information output unit 22 of the binary symbol. And a process of outputting the determination result to the multilevel conversion unit 28 as a binary symbol.
The bin output unit 26 constitutes a bin output unit.

When the bypass decoding unit 27 receives the encoded bit from the decoding scheme changeover switch 24, the bypass decoding unit 27 performs a process of outputting the encoded bit to the multilevel converting unit 28 as a binary symbol.
That is, the bypass decoding unit 27 outputs a binary symbol of “0” to the multilevel conversion unit 28 when the encoding bit output from the decoding method changeover switch 24 is “0”, and from the decoding method changeover switch 24. When the output encoded bit is “1”, a process of outputting a binary symbol of “1” to the multi-level unit 28 is performed.
The bypass decoding unit 27 constitutes a bypass decoding unit.

The multi-level unit 28 multiplexes the binary symbol output from the bin output unit 26 and the binary symbol output from the bypass decoding unit 27 to generate a binary symbol sequence, and the binary in the binary symbol sequence A process of multi-symbolizing symbols and outputting a series of multi-level symbols is performed.
That is, the multi-value quantization unit 28 refers to the bin number output from the encoded data input unit 21 and determines the binary symbol output from the bin output unit 26 and the binary symbol output from the bypass decoding unit 27. A process of generating a binary symbol sequence by integrating, referring to a binarization table of multilevel symbols, multileveling binary symbols in the binary symbol sequence, and outputting a sequence of multilevel symbols To implement.
Note that the multi-value conversion unit 28 constitutes a symbol multi-value conversion means.

In the example of FIG. 9, the encoded data input unit 21, the probability information output unit 22, the encoding mode determination unit 23, the decoding method changeover switch 24, the arithmetic decoding unit 25, the bin output unit 26, which are components of the entropy decoding device, It is assumed that each of the bypass decoding unit 27 and the multi-value conversion unit 28 is configured by dedicated hardware (for example, a semiconductor integrated circuit on which a CPU is mounted, or a one-chip microcomputer). All or a part of the entropy decoding device may be configured by a computer.
When all or a part of the entropy decoding apparatus is configured by a computer, the encoded data input unit 21, the probability information output unit 22, the encoding mode determination unit 23, the decoding method changeover switch 24, the arithmetic decoding unit 25, and the bin output All or a part of the program describing the processing contents of the unit 26, bypass decoding unit 27 and multi-value conversion unit 28 is stored in the memory of the computer, and the CPU of the computer executes the program stored in the memory You just have to do it.
FIG. 10 is a flowchart showing the processing contents of the entropy decoding apparatus according to Embodiment 2 of the present invention.

Next, the operation will be described.
When the encoded data input unit 21 receives the encoded data generated by the entropy encoding device of FIG. 1, the encoded data input unit 21 reads out an encoded bit sequence having a length of 0 or more from the beginning of the read position of the encoded data. The encoded bit sequence is output to the decoding scheme changeover switch 24 (step ST31).
Also, the encoded data input unit 21 refers to the binarization table of the multi-level symbol, and obtains a binary symbol (binary when the encoded bit is decoded) obtained from the encoded bit in the encoded bit sequence. The bin number indicating the number of the binary symbol related to the multilevel symbol is output to the probability information output unit 22, the encoding mode determination unit 23, and the multilevel conversion unit 28.

Here, as described in the first embodiment, the encoded data is encoded in 2 bits in a certain encoding mode because the encoded bits are multiplexed in a multiplexing scheme that takes into consideration the order of reading by the entropy decoding device. When decoding a value symbol, a sequence of encoded bits having a length of 0 or more at the beginning of the read position in the encoded data is always a sequence of encoded bits encoded by the encoding mode.
Therefore, the encoded data input unit 21 may always read the data at the beginning of the read position of the encoded data.

  The encoding mode determination unit 23 stores in advance the encoding mode (arithmetic encoding mode, bypass encoding mode) in the binary symbol corresponding to the bin number for each bin number, and the encoded data input unit 21 When the bin number is received, the encoding mode for the binary symbol corresponding to the bin number is determined and output to the decoding method changeover switch 24. (Step ST32).

The encoding mode information corresponding to the bin number stored in the encoding mode determination unit 23 matches the encoding mode information corresponding to the bin number stored in the encoding mode determination unit 3 in FIG. ing.
When the binarization table of FIG. 3 is stored, for example, a sequence of bin numbers “0”, “1”, “2”, “3”, “4” is output from the encoded data input unit 21. The encoding mode corresponding to the bin number “0” is the arithmetic encoding mode, the encoding mode corresponding to the bin number “1” is the arithmetic encoding mode, and the encoding mode corresponding to the bin number “2”. The mode is the arithmetic coding mode, the coding mode corresponding to the bin number “3” is the arithmetic coding mode, and the coding mode corresponding to the bin number “4” is the bypass coding mode.
When a sequence of bin numbers “9”, “10”, “11”, and “12” is output from the encoded data input unit 21, the encoding mode corresponding to the bin number of “9” is a bypass code. Coding mode, the coding mode corresponding to the bin number of “10” is the arithmetic coding mode, the coding mode corresponding to the bin number of “11” is the arithmetic coding mode, and the coding mode corresponds to the bin number of “12”. The mode becomes a bypass coding mode.

When receiving the encoded bit sequence from the encoded data input unit 21, the decoding scheme changeover switch 24 determines the encoding mode of the binary symbol corresponding to the bin number output from the encoded data input unit 21. When the arithmetic coding mode is determined by the unit 23, the encoded bit sequence is output to the arithmetic decoding unit 25 (step ST33).
On the other hand, when the encoding mode of the binary symbol corresponding to the bin number is determined to be the bypass encoding mode by the encoding mode determining unit 23, the encoded bit sequence is output to the bypass decoding unit 27 (step ST33). ).
In the above example, the operation in the case where the encoding device and the decoding device that created the input encoded data have only the arithmetic encoding mode and the bypass encoding mode has been described. When the encoding mode X other than the bypass encoding mode is included, the encoding mode determination unit 23 can determine the encoding mode information corresponding to the encoding mode X, and the decoding scheme changeover switch 24 When the encoding mode information corresponding to the encoding mode X is received, the binary symbol can be output to the module that performs the encoding process corresponding to the encoding mode X.

When the encoding scheme is determined to be the bypass encoding mode and the bypass decoding unit 27 receives the encoded bit sequence from the decoding scheme changeover switch 24, each of the encoded bits in the encoded bit sequence is converted into a binary symbol. (Encoding bit = binary symbol) and the binary symbol is output to the multi-level unit 28 (step ST34).
That is, when the bypass decoding unit 27 receives the encoding bit from the decoding method changeover switch 24 and the encoding bit is “0”, the bypass decoding unit 27 outputs a binary symbol of “0” to the multilevel conversion unit 28, If the encoded bit is “1”, a binary symbol of “1” is output to the multilevel conversion unit 28.

For each bin number, the probability information output unit 22 preliminarily selects a dominant symbol (“0” or “1” having a higher probability of occurrence in a binary symbol corresponding to the bin number). Dominating symbol information indicating the symbol) and probability information indicating the occurrence probability of the dominating symbol. The probability information for the bin number stored in the probability information output unit 22 matches the probability information for the bin stored in the probability information output unit 2 of FIG.
For example, in the case of the binarization table shown in FIG. 3A, the probability that a multi-valued symbol of “0” will occur in a multi-valued symbol having values of “0” to “9” is about 70%. In this case, the probability that the symbol “0” is generated in the binary symbol corresponding to the bin number “0” is about 70%, and therefore, the dominant symbol in the binary symbol is the symbol “0”. Become. The probability of occurrence of this dominant symbol is about 70%.
When the probability information output unit 22 receives the bin number from the encoded data input unit 21, the probability information output unit 22 outputs the dominant symbol information indicating the dominant symbol corresponding to the bin number to the bin output unit 26, and the occurrence probability of the dominant symbol. The indicated probability information is output to the arithmetic decoding unit 25 (step ST35).

When the encoding method is determined to be the arithmetic encoding mode and the arithmetic decoding unit 25 receives the encoding bit from the decoding method switch 24, the arithmetic decoding unit 25 generates a dominant symbol indicated by the probability information output from the probability information output unit 22. Using the probability information, the encoded bit is arithmetically decoded, and the decoded binary symbol that is the decoding result is output to the bin output unit 26 (step ST36).
In the entropy encoding device, as described above, when the entropy decoding device performs arithmetic decoding, for example, it is assumed that 9-bit bits are prefetched in a fixed manner (in the entropy decoding device, the bit is set at a preset read timing). Since the bypass code bit and the arithmetic code bit are multiplexed, the operation of the arithmetic decoding process in the arithmetic decoding unit 25 is the same as that of the bypass code bit in the encoded data multiplexing unit 11. It must be consistent with the multiplexing of the arithmetic code bit.

ただし、ｑ_nは、復号方式切替スイッチ２４から算術復号部２５に対して、ｎ番目に入力された符号化ｂｉｔである。 Hereinafter, the arithmetic decoding process in the arithmetic decoding unit 25 will be specifically described.
FIG. 11 is a flowchart showing the arithmetic decoding process of the arithmetic decoding unit 25.
The arithmetic decoding unit 25 has Range and Value registers therein.
As shown in FIG. 5B, Range represents the length of the current probability interval, and Value represents the length from the lower limit of the probability interval to the lower limit of the interval H _n indicated by the input data. The initial values of these registers are as follows.

However, q _n is an n-th encoded bit input from the decoding method changeover switch 24 to the arithmetic decoding unit 25.

That is, the arithmetic decoding unit 25 needs to input the first 9-bit data of the encoded data before starting decoding.
According to the multiplexing method described in the first embodiment, the top 9 bits are arithmetic coding bits. In the initial state, Value represents the distance from the lower limit of the probability interval to the lower limit of H ₉ .
Like the arithmetic coding unit 6 described in the first embodiment, the probability interval division is called LPSLlength that is determined by table reference using the value of Range and the occurrence probability of the dominant symbol output from the probability information output unit 22. From the value, as shown in FIG. 5B, the probability interval is divided into a dominant symbol interval and an inferior symbol interval.

Based on the above, the flow of the decoding operation of bin (H _k ) with bin number k will be described. It is assumed that n + 8 bits are input to the arithmetic decoding unit 25 at the time of this decoding process.
First, the arithmetic decoding unit 25 updates the probability interval to the dominant symbol interval (step ST41 in FIG. 11).
Range = Range-LPSLlength
This corresponds to the processing of I _k = I _{Mk−1 that} updates the dominant symbol interval as the next probability interval.

Next, the arithmetic decoding unit 25 determines whether or not the section coordinates overlap with the dominant symbol section by comparing the values of Value and Range (step ST42).
If Value <Range, the arithmetic decoding unit 25 determines that the output bin (b _k ) that is the decoded binary symbol sequence is the dominant symbol, and outputs it to the bin output unit 26 (step ST43). This corresponds to the determination of whether or not the lower limit coordinate of H _{n + 8} is included in the dominant symbol section.

If Value> = Range, the arithmetic decoding unit 25 determines that the output bin (b _k ) that is the decoded binary symbol sequence is an inferior symbol, and outputs it to the bin output unit 26 (step ST44).
In addition, the arithmetic decoding unit 25 updates the probability interval to the inferior symbol interval (step ST45).
Value = Value-Range
Range = LPSLlength
This corresponds to the processing of I _k = I _{Lk−1 that} updates the inferior symbol interval as the next probability interval.

Next, the arithmetic decoding unit 25 performs a loop process on the condition of the value of Range.
The loop continuation condition is Range <256, and while the loop continuation condition is satisfied, the following process of step ST47 is repeatedly performed (step ST46).
In the loop, calculation of Range = Range × 2, Value = Value × 2 + q _{n + 8 + i} is performed. Here, i is the number of loops, and q _{n + 8 + i} is the (n + 8 + i) th arithmetic code bit output from the decoding method changeover switch 24.
When Range ≧ 256, the arithmetic decoding process ends (step ST46).

Since the arithmetic decoding unit 25 performs the above-described operation, the arithmetic decoding unit 25 compares the operation of the Range at the time when the bin encoding of the bin number k is completed in the arithmetic encoding unit 6 as compared with the operation of the arithmetic encoding unit 6 of FIG. The value is equal to the value of Range at the time when the arithmetic decoding unit 25 finishes decoding the bin with the bin number k.
In addition, when the arithmetic encoding unit 6 outputs n arithmetic codes bit at the time when the encoding of the bin with the bin number k is completed, the arithmetic decoding unit 25 finishes decoding the bin with the bin number k. At this point, n + 9 arithmetic code bits are read.

  Here, the arithmetic decoding unit 25 fixedly pre-reads 9-bit bits (in the entropy decoding device, pre-reads 9 bits at a preset read timing) and performs arithmetic decoding. When decoding operation information is notified from the device, arithmetic decoding is performed by prefetching the number of bits indicated by the decoding operation information.

When the bin output unit 26 receives the decoded binary symbol from the arithmetic decoding unit 25, the bin output unit 26 refers to the dominant symbol information output from the probability information output unit 22 to determine whether or not the decoded binary symbol is a dominant symbol. The indicated flag is output as a binary symbol to the multilevel conversion unit 28 (step ST37 in FIG. 10).
That is, for each binary symbol in the decoded binary symbol sequence output from the arithmetic decoding unit 25, the bin output unit 26 uses the dominant symbol information indicated by the dominant symbol information output from the probability information output unit 22 to the binary symbol. It is determined whether or not it matches the symbol, and the determination result is output to the multilevel conversion unit 28 as a binary symbol.

The multi-level unit 28 multiplexes the binary symbol output from the bin output unit 26 and the binary symbol output from the bypass decoding unit 27 to generate a binary symbol sequence, and 2 in the binary symbol sequence A multi-valued symbol is converted into a multi-value symbol sequence.
That is, the multi-level unit 28 refers to the bin number output from the encoded data input unit 21 and the binary symbol output from the bin output unit 26 and the binary symbol output from the bypass decoding unit 27. Are integrated to generate a binary symbol sequence (step ST38).
Further, the multi-level unit 28 refers to the multi-level symbol binarization table, multi-levels the binary symbols in the binary symbol sequence, and outputs a multi-level symbol sequence (step ST39). .
For example, when the type of the multi-level symbol is the multi-level symbol A, the binary symbol series is “1111”, and the bin numbers corresponding to the binary symbol series are “0”, “1”, “2”. If “3”, the value of the multi-value symbol is “9” (refer to the binarization table in FIG. 3A).
The processes of steps ST31 to ST39 are repeatedly performed until the processing of all encoded data is completed (step ST40).

  As is apparent from the above, according to the second embodiment, an encoded bit sequence multiplexed with encoded data is read, and there are many binary symbols obtained from the encoded bits in the encoded bit sequence. The encoded data input unit 21 that outputs a bin number indicating what number binary symbol is associated with the value symbol, and the probability of occurrence in the binary symbol corresponding to the bin number output from the encoded data input unit 21 2 outputs the dominant symbol information indicating a dominant symbol having a high value, outputs probability information indicating the occurrence probability of the dominant symbol, and 2 corresponding to the bin number output from the encoded data input unit 21. Corresponding to the bin number output from the encoding mode determination unit 23 for determining the encoding mode in the value symbol and the encoded data input unit 21 When the encoding mode of the value symbol is determined to be the arithmetic encoding mode by the encoding mode determination unit 23, the encoding bit output from the encoded data input unit 21 is output to the arithmetic decoding unit 25, and the bin number is output. When the coding mode of the binary symbol corresponding to is determined to be the bypass coding mode by the coding mode determination unit 23, a decoding method switch 24 that outputs the coding bit to the bypass decoding unit 27, and a decoding method When the encoded bit is received from the changeover switch 24, the encoded bit output from the encoded data input unit 21 is arithmetically decoded using the occurrence probability of the dominant symbol indicated by the probability information output from the probability information output unit 22. The arithmetic decoding unit 25 that outputs the decoded binary symbol that is the decoding result and the dominant symbol information output from the probability information output unit 22 are referred to. Then, a bin output unit 26 that outputs, as a binary symbol, a flag that indicates whether each decoded binary symbol in the decoded binary symbol sequence output from the arithmetic decoding unit 25 is a dominant symbol, and a decoding scheme switching When a coded bit is received from the switch 24, a bypass decoding unit 27 that outputs the coded bit output from the coded data input unit 21 as a binary symbol is provided. The output binary symbol and the binary symbol output from the bypass decoding unit 27 are multiplexed to generate a binary symbol sequence, and the binary symbol in the binary symbol sequence is converted into a multi-level value. Since the sequence is output, it is possible to decode a binary symbol in which the occurrence probabilities of “0” and “1” are not biased by a decoding process with a small processing load. . That is, there is an effect that a multi-level symbol can be obtained by decoding a binary symbol sequence from encoded data by a decoding process with a processing load less than that of the conventional CABAC.

  In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .

  DESCRIPTION OF SYMBOLS 1 Binarization part (symbol binarization means) 2 Probability information output part (Probability information output means) 3 Encoding mode determination part (Encoding mode determination means) 4 Encoding system changeover switch (Encoding mode determination) Means), 5 encoded bin output section (encoded binary symbol output means), 6 arithmetic encoding section (arithmetic encoding means), 7 bypass encoding section (bypass encoding means), 8 encoded data output section ( Multiplexing means), 9 bypass code buffer, 10 arithmetic code buffer, 11 encoded data multiplexing section, 21 encoded data input section (encoded bit sequence reading means), 22 probability information output section (probability information output means), 23 Coding mode decision unit (coding mode decision unit), 24 Decoding method changeover switch (coding mode decision unit), 25 Arithmetic decoding unit (arithmetic decoding unit), 26 bin output (Bin output means), 27 bypass decoding section (bypass decoding means), 28 multi-value conversion section (symbol multi-value conversion means).

Claims (8)

  The multi-level symbol in the multi-level symbol sequence is binarized to output a sequence of one or more binary symbols, and indicates the binary symbol of the multi-level symbol which is the binary symbol. a symbol binarizing unit for outputting a bin number; and outputting preferential symbol information indicating a dominant symbol having a high probability of occurring in a binary symbol corresponding to the bin number output from the symbol binarizing unit; Probability information output means for outputting probability information indicating the occurrence probability of a symbol, coding mode determination means for determining a coding mode in a binary symbol corresponding to a bin number output from the symbol binarization means, and If the encoding mode determined by the encoding mode determining means is the arithmetic encoding mode, the superiority output from the probability information output means Encoded binary symbol output means for referring to the symbol information and outputting as a coded binary symbol a flag indicating whether or not the binary symbol corresponding to the bin number is a dominant symbol; and the probability information output means The encoded binary symbol output from the encoded binary symbol output means is arithmetically encoded using the probability of occurrence of the dominant symbol indicated by the probability information output from, and the encoded bit that is the encoding result is output. If the encoding mode determined by the arithmetic encoding means and the encoding mode determining means is the bypass encoding mode, the bypass that outputs the binary symbol output from the symbol binarizing means as the encoding bit The encoding means, the encoding bit output from the arithmetic encoding means and the encoding bit output from the bypass encoding means are multiplexed. Entropy coding apparatus and a multiplexing means for generating an encoded data.   The multiplexing means outputs the encoded bits output from the arithmetic encoding means and the bypass encoding means in an order corresponding to the read timing of the encoded bits when the entropy decoding apparatus arithmetically decodes the encoded bits. The entropy coding apparatus according to claim 1, wherein the coding bits are multiplexed.   The multiplexing means notifies the entropy decoding device of decoding operation information defining the read timing of the encoded bit when the entropy decoding device arithmetically decodes the encoded bit, and calculates the arithmetic code in an order corresponding to the read timing. The entropy encoding apparatus according to claim 1, wherein the encoding bit output from the encoding means and the encoding bit output from the bypass encoding means are multiplexed.   A bin indicating the number of binary symbols related to a multi-level symbol, which is obtained by reading out a coded bit sequence multiplexed with the coded data and obtained from the coded bit in the coded bit sequence. A coded bit sequence reading means for outputting a number, and dominant symbol information indicating a dominant symbol that has a high probability of occurring in a binary symbol corresponding to the bin number output from the coded bit sequence reading means, and Probability information output means for outputting probability information indicating the probability of occurrence of a dominant symbol; Coding mode determination means for determining a coding mode in a binary symbol corresponding to the bin number output from the coded bit sequence reading means; If the encoding mode determined by the encoding mode determination means is the arithmetic encoding mode, Using the occurrence probability of the dominant symbol indicated by the probability information output from the probability information output means, the coded bits in the coded bit sequence output from the coded bit sequence reading means are arithmetically decoded, and the decoding result is Whether the decoded binary symbol output from the arithmetic decoding means is a dominant symbol by referring to the arithmetic decoding means for outputting a certain decoded binary symbol and the dominant symbol information output from the probability information output means. If the encoding mode determined by the encoding mode determining unit is a bypass encoding mode, the encoding output from the encoded bit sequence reading unit is output. Bypass decoding means for outputting the encoded bits in the bit sequence as binary symbols, and 2 output from the bin output means Symbols that multiplex symbols and binary symbols output from the bypass decoding means to generate binary symbol sequences, multi-binarize binary symbols in the binary symbol sequences, and output multi-level symbol sequences An entropy decoding device comprising multi-value conversion means.   The arithmetic decoding means reads the encoded bit in the encoded bit sequence output from the encoded bit sequence reading means at a preset read timing, and the dominant symbol indicated by the probability information output from the probability information output means 5. The entropy decoding apparatus according to claim 4, wherein the encoded bit is arithmetically decoded using a probability of occurrence of.   The arithmetic decoding means reads the encoded bit in the encoded bit sequence output from the encoded bit sequence reading means at the read timing specified by the decoding operation information notified from the entropy encoding device, and from the probability information output means 5. The entropy decoding apparatus according to claim 4, wherein the encoded bit is arithmetically decoded using a probability of occurrence of a dominant symbol indicated by the output probability information.   The symbol binarization means binarizes the multi-level symbols in the multi-level symbol sequence and outputs a sequence of one or more binary symbols, and the binary symbol that is related to the multi-level symbol A symbol binarization processing step for outputting a bin number indicating whether the symbol is a value symbol, and a probability information output means has a probability of occurring in the binary symbol corresponding to the bin number output in the symbol binarization processing step. A probability information output processing step for outputting preferential symbol information indicating a high preferential symbol and outputting probability information indicating the occurrence probability of the preferential symbol, and an encoding mode determining means are output in the symbol binarization processing step. An encoding mode determination processing step for determining an encoding mode in a binary symbol corresponding to the bin number, and an encoded binary symbol If the encoding mode determined in the encoding mode determination processing step is the arithmetic encoding mode, the output means refers to the dominant symbol information output in the probability information output processing step and corresponds to the bin number. An encoded binary symbol output processing step for outputting a flag indicating whether or not the binary symbol to be performed is a dominant symbol as an encoded binary symbol, and an arithmetic encoding means output in the probability information output processing step. Arithmetic code that uses the occurrence probability of the dominant symbol indicated by the probability information to arithmetically encode the encoded binary symbol output in the encoded binary symbol output processing step and outputs an encoded bit that is the encoding result And the bypass encoding means determines that the encoding mode determined by the encoding mode determination processing step is a bypass code. If the encoding mode is selected, the bypass encoding processing step for outputting the binary symbol output in the symbol binarization processing step as an encoding bit, and the multiplexing means outputs the code output in the arithmetic encoding processing step. Encoding method comprising: a multiplexing bit and a multiplexing step that multiplexes the encoding bit output in the bypass encoding step to generate encoded data.   The coded bit sequence reading means reads the coded bit sequence multiplexed with the coded data, and the binary symbol obtained from the coded bit in the coded bit sequence is what number 2 An encoded bit sequence read processing step for outputting a bin number indicating whether it is a value symbol, and a probability information output means occur in a binary symbol corresponding to the bin number output in the encoded bit sequence read processing step. A probability information output processing step for outputting the dominant symbol information indicating the dominant symbol having a high probability and outputting the probability information indicating the occurrence probability of the dominant symbol; and the encoding mode determining means includes the encoded bit sequence reading processing step. A code for determining the encoding mode in the binary symbol corresponding to the bin number output in If the coding mode determined by the coding mode determination processing step and the arithmetic decoding means is the arithmetic coding mode, the probability information output in the probability information output processing step indicates the superiority Arithmetic decoding processing step of arithmetically decoding the encoded bit in the encoded bit sequence output in the encoded bit sequence reading processing step using the occurrence probability of the symbol, and outputting a decoded binary symbol which is the decoding result And a bin output means refers to the dominant symbol information output in the probability information output processing step and sets a flag indicating whether or not the decoded binary symbol output in the arithmetic decoding processing step is a dominant symbol. A bin output processing step for outputting as a binary symbol, and a bypass decoding means, the encoding mode determination processing step. If the coding mode determined by the group is the bypass coding mode, a bypass decoding processing step for outputting the coded bit in the coded bit sequence output in the coded bit sequence reading processing step as a binary symbol; The symbol multi-value conversion means multiplexes the binary symbol output in the bin output processing step and the binary symbol output in the bypass decoding processing step to generate a binary symbol sequence, and the binary symbol sequence An entropy decoding method comprising: a multilevel symbol processing step of multileveling a binary symbol and outputting a sequence of multilevel symbols.

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