JP2007115935A - High withstand voltage semiconductor device and its manufacturing method - Google Patents

High withstand voltage semiconductor device and its manufacturing method Download PDF

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JP2007115935A
JP2007115935A JP2005306719A JP2005306719A JP2007115935A JP 2007115935 A JP2007115935 A JP 2007115935A JP 2005306719 A JP2005306719 A JP 2005306719A JP 2005306719 A JP2005306719 A JP 2005306719A JP 2007115935 A JP2007115935 A JP 2007115935A
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diffusion region
semiconductor device
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Hiromasa Omori
寛将 大森
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Sanken Electric Co Ltd
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    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high withstand voltage semiconductor device and its manufacturing method capable of forming an FLR using a columnar region having the same structure as that of a transistor in a cell region and relaxing an electrical field concentration in an element periphery region. <P>SOLUTION: The high withstand voltage semiconductor device of this invention comprises a plurality of FLRs having a reserve structure at predetermined intervals at a termination adjacent to the periphery of a cell region with the element formed. The FLR comprises trenches provided circularly and continuously on the surface of a first conductive-type substrate, a second conductive-type first diffusion region provided along the periphery of the trench, an insulating material filled in the inside of the trench, a second conductive-type second diffusion region provided circularly and continuously along each side of the semiconductor device divided into an inner periphery side diffusion layer and the periphery side diffusion layer by the insulating material, and a conductive material inserted into the inner periphery side diffusion region and the periphery side diffusion region of the second diffusion region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置に関し、特に大電力の制御に用いることを目的とした高耐圧半導体装置及びその製造方法に係わるものである。   The present invention relates to a semiconductor device, and more particularly to a high voltage semiconductor device intended for use in high power control and a method for manufacturing the same.

パワーエレクトロニクス分野において、装置の小型化に伴い高耐圧半導体装置が多用されるようになってきている。そのため、高耐圧半導体装置に対しては、より高耐圧化・大電流化が望まれている。
この高耐圧化及び大電流化を実現させるため、高濃度の基板でも高耐圧化を可能とするスーパージャンクション構造を有する半導体装置が用いられている。
上記スーパージャンクション構造の例として、図１８に示す縦型ＭＯＳの構造を簡単に説明する。 In the field of power electronics, high-voltage semiconductor devices have come to be used frequently with the miniaturization of devices. Therefore, higher breakdown voltage and higher current are desired for high breakdown voltage semiconductor devices.
In order to realize this high withstand voltage and large current, a semiconductor device having a super junction structure that enables high withstand voltage even with a high concentration substrate is used.
As an example of the super junction structure, the structure of the vertical MOS shown in FIG. 18 will be briefly described.

この縦型ＭＯＳは、Ｎ＋型のドレイン層１００と、このドレイン層１００の上部に形成されたＮ−型のドリフト層１０１と、ドリフト層１０１内に形成され、かつドリフト層１０１に対し、反対導電型であるＰ−型のベース領域１０２と、ベース領域１０２内に形成された、ベース領域１０２に対し、反対導電型のＮ＋型のソース領域１０３とを備えている。
また、上記縦型ＭＯＳは、ベース領域１０２やソース領域１０２等が露出する半導体基板の上面から、ドリフト層１０１の厚み方向に延伸する（ドリフト層１０１に空けられた）トレンチ１０４を有している。 The vertical MOS includes an N + -type drain layer 100, an N − -type drift layer 101 formed on the drain layer 100, and is formed in the drift layer 101 and is opposite to the drift layer 101. A P − type base region 102 having a conductivity type and an N + type source region 103 having an opposite conductivity type to the base region 102 formed in the base region 102 are provided.
The vertical MOS has a trench 104 extending in the thickness direction of the drift layer 101 (spaced in the drift layer 101) from the upper surface of the semiconductor substrate from which the base region 102, the source region 102, and the like are exposed. .

そして、縦型ＭＯＳは、このトレンチ１０４の外周縁及び外周面に沿ってベース領域１０２と同じ導電型であるｐ−型の柱状部拡散層（ピラー領域）１０５を延伸させると共にトレンチ１０４内に絶縁体１０６が充填されている。
また、上記半導体基板の表面にゲート酸化膜が形成され、このゲート酸化膜表面の所定の位置にゲート電極１０７のパターンが形成され、露出されたゲート酸化膜１０６及びゲート電極１０７上に絶縁膜１０８が形成されている。
ソース領域１０３及びベース領域１０２を露出させるコンタクトホール１０９が形成され、このコンタクトホール１０９により、ソース電極１０３及びベース領域１０２とコンタクトが取られたソース電極１１０が設けられている（例えば、特許文献１参照）。 The vertical MOS extends a p − -type columnar diffusion layer (pillar region) 105 having the same conductivity type as the base region 102 along the outer peripheral edge and outer peripheral surface of the trench 104 and is insulated in the trench 104. The body 106 is filled.
A gate oxide film is formed on the surface of the semiconductor substrate, a pattern of the gate electrode 107 is formed at a predetermined position on the surface of the gate oxide film, and the insulating film 108 is formed on the exposed gate oxide film 106 and the gate electrode 107. Is formed.
A contact hole 109 exposing the source region 103 and the base region 102 is formed, and a source electrode 110 in contact with the source electrode 103 and the base region 102 is provided by the contact hole 109 (for example, Patent Document 1). reference).

図１８に示す素子構造によれば、ベース領域１０２直下に延伸する柱状部拡散層１０５が所謂リサーフ領域として機能するため、素子の高耐圧化か図られると共に、比較的低いオン電圧のＭＯＳＦＥＴを実現することができる。
すなわち、ベース領域１０２とドリフト領域１０１との界面に形成される第１のＰＮ接合に対し、逆方向電圧（ソース電圧＜ドレイン電圧）が印加されると、この第１のＰＮ接合から空乏層が広がる。
また、このとき、柱状部拡散層１０５とドリフト領域１０１との界面に形成される第２のＰＮ接合における空乏層も広がる。
上述したように、逆方向電圧が印加された際、第１及び第２のＰＮ接合において生成される空乏層がドリフト領域１０１内に良好に広がることにより電解集中を緩和し、素子の高耐圧化を実現することができる。 According to the element structure shown in FIG. 18, the columnar portion diffusion layer 105 extending immediately below the base region 102 functions as a so-called RESURF region, so that the device can have a higher breakdown voltage and a relatively low on-voltage MOSFET can be realized. can do.
That is, when a reverse voltage (source voltage <drain voltage) is applied to the first PN junction formed at the interface between the base region 102 and the drift region 101, a depletion layer is formed from the first PN junction. spread.
At this time, the depletion layer in the second PN junction formed at the interface between the columnar portion diffusion layer 105 and the drift region 101 also spreads.
As described above, when a reverse voltage is applied, the depletion layer generated in the first and second PN junctions spreads well in the drift region 101, thereby reducing the concentration of electrolysis and increasing the breakdown voltage of the device. Can be realized.

また、このように逆方向電圧が印加される際、ドリフト層１０１内に空乏層が良好に広がることから、ドリフト層１０１の不純物濃度を比較的高く設定することができる。
これにドリフト層１０１の抵抗を低下させることができるため、縦型ＭＯＳ等の素子のオン抵抗も比較的低くなる。
このように、柱状領域１０５を形成したＭＯＳＦＥＴによれば、トレードオフ関係にある、素子の高耐圧化と低オン抵抗化の両方を達成することができる。
また、トレンチ１０４に沿って柱状部拡散層１０５を設けることにより、ドリフト層１０１の厚み方向に深く延伸する柱状部拡散層１０５を容易に形成できるという利点もある。
すなわち、ドリフト層１０１にトレンチ１０４を形成し、このトレンチ１０４の内壁面を通じて不純物を導入して柱状領域１０５を形成することができ、複数のエピタキシャル成長を繰り返して柱状領域１０５を形成する方法に比較し、柱状領域１０５を深く形成できるとともに、容易に任意の深さに形成することができる。
特開２００３−８６８００号公報 Further, when the reverse voltage is applied in this way, the depletion layer spreads well in the drift layer 101, so that the impurity concentration of the drift layer 101 can be set relatively high.
In addition, since the resistance of the drift layer 101 can be lowered, the on-resistance of an element such as a vertical MOS becomes relatively low.
Thus, according to the MOSFET in which the columnar region 105 is formed, it is possible to achieve both a high breakdown voltage and a low on-resistance of the element which are in a trade-off relationship.
Further, by providing the columnar portion diffusion layer 105 along the trench 104, there is also an advantage that the columnar portion diffusion layer 105 extending deeply in the thickness direction of the drift layer 101 can be easily formed.
That is, a trench 104 is formed in the drift layer 101, and impurities can be introduced through the inner wall surface of the trench 104 to form the columnar region 105. Compared with a method in which a plurality of epitaxial growths are repeated to form the columnar region 105. The columnar region 105 can be formed deep and can be easily formed to an arbitrary depth.
JP 2003-86800 A

上述した半導体素子の高耐圧化を良好に達成するため、図１に示すように、トランジスタを形成するセル領域を囲む素子外周領域（半導体基板の外周側）の電界集中も緩和する必要がある。
このため、図１のＡ−Ａにおける線視断面図の図１９に示すように、素子外周領域にも複数の柱状領域（ソース領域を有さず、ソース電極に接続されていない）を形成して電界緩和を図ることが必要となる。
すなわち、上記セル領域を包囲する、環状に形成された柱状領域からなるＦＬＲ（Field Limiting Ring）領域を形成し、空乏層を素子外周方向に良好に広げることにより、セル領域おける最外周の素子に対する電界集中を緩和することが考えられる。 In order to satisfactorily achieve the high breakdown voltage of the semiconductor element described above, as shown in FIG. 1, it is necessary to alleviate the electric field concentration in the element outer peripheral region (the outer peripheral side of the semiconductor substrate) surrounding the cell region in which the transistor is formed.
For this reason, as shown in FIG. 19 in the sectional view taken along line AA in FIG. 1, a plurality of columnar regions (having no source region and not connected to the source electrode) are also formed in the element outer peripheral region. Therefore, it is necessary to reduce the electric field.
That is, by forming an FLR (Field Limiting Ring) region composed of a ring-shaped columnar region surrounding the cell region and spreading the depletion layer well in the outer peripheral direction of the device, It is conceivable to reduce the electric field concentration.

しかしながら、図１９の従来例においては、実際に作成して耐圧を測定してみると、上述したＦＬＲ構造においては、十分な電界緩和効果が得られないことが確認された。
この要因としては、柱状領域のトレンチ１０４内部に充填された絶縁体が、図１に示すようにセル領域を連続的な環状にて包囲しているため、電位の伝達を阻害していることが考えられる。
すなわち、図１９に示す従来の柱状領域の構造において、柱状部分の絶縁体が連続した壁となり、柱状領域を内側部分と外側部分とに分割し、この絶縁体の壁により内側部分の電位が外側部分へ十分に伝達されないことが考えられる。
これは、図２０に示すシミュレーション結果（空乏層の電位分布）からも、空乏層の素子外周側への広がりが制限されることが判る。このシミュレーションは、二次元デバイスシミュレータで行った。 However, in the conventional example of FIG. 19, when the breakdown voltage was actually created and measured, it was confirmed that the above-described FLR structure could not provide a sufficient electric field relaxation effect.
The cause is that the insulator filled in the trench 104 in the columnar region surrounds the cell region in a continuous ring shape as shown in FIG. Conceivable.
That is, in the structure of the conventional columnar region shown in FIG. 19, the insulator of the columnar part becomes a continuous wall, the columnar region is divided into an inner part and an outer part, and the potential of the inner part is outside by the wall of this insulator. It is conceivable that it is not sufficiently transmitted to the part.
From the simulation result (potential distribution of the depletion layer) shown in FIG. 20, it can be seen that the spread of the depletion layer to the element outer peripheral side is limited. This simulation was performed with a two-dimensional device simulator.

本発明は、このような事情に鑑みてなされたもので、セル領域のトランジスタと同様な構造の柱状領域を用いたＦＬＲを形成し、素子外周領域における電界集中を緩和する高耐圧半導体装置を提供することを目的とする。   The present invention has been made in view of such circumstances, and provides a high breakdown voltage semiconductor device that forms an FLR using a columnar region having a structure similar to that of a transistor in a cell region and relaxes electric field concentration in the element outer peripheral region. The purpose is to do.

本発明の高耐圧半導体装置は、素子が形成されたセル領域の外周に隣接した終端部において、リサーフ構造を有するＦＬＲが所定の間隔にて複数設けられた高耐圧半導体装置であり、前記ＦＬＲが、第１導電型の基板表面に、環状に連続して設けられたトレンチと、該トレンチ外周面に沿って設けられた第２の導電型の第１の拡散領域と、前記トレンチ内部に充填された絶縁体と、前記絶縁体により、内周側拡散層と外周側拡散層とに分割された、半導体装置の各辺に沿うように環状に連続して設けられた第２導電型の第２の拡散領域と、前記第２の拡散領域における内周側拡散領域と外周側拡散領域とに介挿された導電体とを有することを特徴とする。   The high withstand voltage semiconductor device of the present invention is a high withstand voltage semiconductor device in which a plurality of FLRs having a RESURF structure are provided at a predetermined interval at a terminal portion adjacent to the outer periphery of a cell region in which an element is formed. A trench provided continuously in a ring shape on the surface of the first conductivity type substrate, a first diffusion region of the second conductivity type provided along the outer peripheral surface of the trench, and the inside of the trench is filled. And a second conductivity type second electrode that is divided into an inner peripheral diffusion layer and an outer peripheral diffusion layer by the insulator and continuously provided in an annular shape along each side of the semiconductor device. And a conductor interposed between the inner and outer diffusion regions in the second diffusion region.

本発明の高耐圧半導体装置は、前記ＦＬＲがそれぞれ電気的に分離されて形成されていることを特徴とする。   The high breakdown voltage semiconductor device of the present invention is characterized in that the FLRs are formed so as to be electrically separated from each other.

本発明の高耐圧半導体装置は、前記導電体が金属で構成され、前記第２の拡散領域の内周側拡散領域及び外周側拡散領域各々にコンタクトにて接続されていることを特徴とする。   The high breakdown voltage semiconductor device of the present invention is characterized in that the conductor is made of a metal and is connected to each of an inner peripheral diffusion region and an outer peripheral diffusion region of the second diffusion region by a contact.

本発明の高耐圧半導体装置は、前記導電体が第２導電型の半導体部で構成され、前記第２の拡散領域の内周側拡散領域及び外周側拡散領域各々に接続されていることを特徴とする。   In the high breakdown voltage semiconductor device of the present invention, the conductor is formed of a semiconductor portion of a second conductivity type, and is connected to each of the inner peripheral diffusion region and the outer peripheral diffusion region of the second diffusion region. And

本発明の高耐圧半導体装置は、前記トレンチが間欠に形成され、トレンチが間欠された領域に第２の導電体の拡散層が形成され、この拡散層により前記第２の拡散領域の内周側拡散領域及び外周側拡散領域とが接続されていることを特徴とする。   In the high breakdown voltage semiconductor device according to the present invention, the trench is intermittently formed, and a diffusion layer of a second conductor is formed in the region where the trench is intermittently formed, and the inner side of the second diffusion region is formed by the diffusion layer. The diffusion region and the outer peripheral diffusion region are connected.

本発明の高耐圧半導体装置の製造方法は、素子が形成されたセル領域の外周に隣接した終端部において、リサーフ構造を有するＦＬＲが所定の間隔にて複数設けられた高耐圧半導体装置の製造方法であり、前記ＦＬＲの形成において、第１導電型の基板表面トレンチを環状に連続して設ける第１の工程と、該トレンチの外周面に沿って第２導電型の第１の拡散層を形成する第２の工程と、前記トレンチ内部に絶縁体を充填する第３の工程と、前記絶縁体により、内周側拡散層と外周側拡散層とに分割され、半導体装置の各辺に沿うように環状に連続して設けられる第２導電型の第２の拡散領域を形成する第４の工程と、前記第２の拡散領域の内周側拡散領域及び外周側拡散領域を接続する導電部を形成する第５の工程とを有することを特徴とする   The manufacturing method of a high breakdown voltage semiconductor device according to the present invention is a method of manufacturing a high breakdown voltage semiconductor device in which a plurality of FLRs having a RESURF structure are provided at predetermined intervals in a terminal portion adjacent to the outer periphery of a cell region in which an element is formed. In the formation of the FLR, a first step of continuously providing a first conductive type substrate surface trench in a ring shape and a second conductive type first diffusion layer are formed along the outer peripheral surface of the trench And a third step of filling the trench with an insulator, and the insulator is divided into an inner peripheral diffusion layer and an outer peripheral diffusion layer so as to be along each side of the semiconductor device. A fourth step of forming a second diffusion region of the second conductivity type provided continuously in a ring shape, and a conductive portion connecting the inner peripheral diffusion region and the outer peripheral diffusion region of the second diffusion region. And having a fifth step of forming That

本発明の高耐圧半導体装置の製造方法は、前記第５の工程が、金属を堆積させる工程と、該金属をＦＬＲ各々における第２の拡散領域の内周側拡散領域と外周側拡散領域とを接続する導電部としてパターニングする工程とを有することを特徴とする。   In the method of manufacturing a high voltage semiconductor device according to the present invention, the fifth step includes a step of depositing a metal, and an inner peripheral side diffusion region and an outer peripheral side diffusion region of the second diffusion region in each FLR. And a step of patterning as a conductive portion to be connected.

本発明の高耐圧半導体装置の製造方法は、前記第１の工程において、前記トレンチを、間欠的に形成し、前記第５の工程が前記トレンチの間欠部分に、第２の拡散領域の内周側拡散領域と外周側拡散領域とを接続する第２の導電体の拡散層を形成する工程とを有することを特徴とする。   In the method of manufacturing a high breakdown voltage semiconductor device according to the present invention, in the first step, the trench is intermittently formed, and the fifth step is performed on the inner periphery of the second diffusion region in the intermittent portion of the trench. Forming a diffusion layer of a second conductor that connects the side diffusion region and the outer peripheral side diffusion region.

本発明の高耐圧半導体装置の製造方法は、各ＦＬＲの前記導電部が、他のＦＬＲの導電部に対して絶縁されたパターンとして形成されることを特徴とする。   The high breakdown voltage semiconductor device manufacturing method of the present invention is characterized in that the conductive portion of each FLR is formed as a pattern insulated from the conductive portions of other FLRs.

本発明の高耐圧半導体装置の製造方法は、前記第２の工程が、第２の導電型の不純物をイオン注入または拡散源を用いた拡散処理により第１の拡散層を形成する工程を有することを特徴とする。   In the method of manufacturing a high breakdown voltage semiconductor device of the present invention, the second step includes a step of forming a first diffusion layer by ion implantation of a second conductivity type impurity or diffusion treatment using a diffusion source. It is characterized by.

以上説明したように、本発明によれば、素子外周部に形成した、内部の縦型トランジスタと同様な柱状領域（リサーフ構造）のＦＬＲにおいて、各柱状領域に埋め込まれた絶縁体により、素子中央側と素子外周側とに分離された拡散領域を、導電体により接続することで、内周側の柱状領域から外周側の柱状領域へと、複数の柱状領域にわたり、効率的に電位を伝達することができ、従来の構造に比較して、空乏層を外側の柱状領域まで良好に延ばすことにより、効率的な電界緩和が可能となり、上述した柱状領域の構造によりにより、素子の外周側の終端部（リサーフが環状に形成されているリサーフ領域）における耐圧を向上させることができる。
また、本発明によれば、素子におけるセル領域内のトランジスタとほぼ同様な構造の柱状領域（リサーフ構造）を形成することができるため、余分な工程を加える必要がほとんど無く、容易に耐圧を向上させる構造を構成することが可能となる。 As described above, according to the present invention, in the FLR of the columnar region (Resurf structure) similar to the internal vertical transistor formed in the outer peripheral portion of the device, the insulator is embedded in each columnar region, so that the element center By connecting the diffusion region separated into the outer peripheral side and the device outer peripheral side with a conductor, the potential is efficiently transmitted from the inner peripheral side columnar region to the outer peripheral side columnar region over a plurality of columnar regions. Compared with the conventional structure, the depletion layer can be effectively extended to the outer columnar region to effectively reduce the electric field. The structure of the columnar region described above enables the termination on the outer peripheral side of the device. The breakdown voltage in the portion (the RESURF region where the RESURF is formed in an annular shape) can be improved.
In addition, according to the present invention, since a columnar region (Resurf structure) having a structure similar to that of a transistor in a cell region of an element can be formed, almost no extra process is required and the breakdown voltage can be easily improved. It is possible to configure the structure to be made.

＜第１の実施形態＞
以下、本発明の第１の実施形態による半導体装置の製造方法の一例を図面を参照して説明する。
本実施形態における素子の平面構造を、図１における領域Ｂの拡大図である図２、及び図２のＣ−Ｃにおける線視断面図である図３を用いて説明する。
ＦＬＲ領域において、セル領域部におけるトランジスタと同様の構造の柱状領域を形成する構造としては従来例と同様である。
すなわち、Ｎ＋型の不純物半導体層であるドレイン層１００上部に、ｎ−型の不純物半導体層であるドリフト層１０１が形成された基板を用い、このドリフト層１０１の表面部に、ｐ型不純物の拡散層であるトランジスタのベース層１０２が形成されている。 <First Embodiment>
Hereinafter, an example of a semiconductor device manufacturing method according to the first embodiment of the present invention will be described with reference to the drawings.
The planar structure of the element in the present embodiment will be described with reference to FIG. 2 which is an enlarged view of the region B in FIG. 1 and FIG. 3 which is a cross-sectional view taken along line CC in FIG.
In the FLR region, the structure in which the columnar region having the same structure as that of the transistor in the cell region is formed is the same as in the conventional example.
That is, a substrate in which a drift layer 101 which is an n − -type impurity semiconductor layer is formed on the drain layer 100 which is an N + -type impurity semiconductor layer is used, and a p-type impurity is formed on the surface of the drift layer 101. A base layer 102 of a transistor which is a diffusion layer is formed.

このベース層１０２を内周側拡散層１０２Ａと外周側拡散層１０２Ｂとに分離する位置に、ベース層１０２を貫通してトレンチ１０４が形成されている。ここで、内周側とは高耐圧半導体装置の中心方向を向いている側を示し、外周側とは高耐圧半導体の中心と逆方向、すなわち高耐圧半導体装置の中心から外部方向（外周部方向）を向いている側を示している。
上記トレンチ１０４の外周面部にはＰ−型の不純物半導体拡散層である柱状部拡散層１０５（リサーフ層）が形成され、トレンチ１０４内部には絶縁体１０６が充填されて配設されている。トレンチ１０４は、素子のセル領域を囲む溝（堀）形状にて連続して形成されている。このトレンチ１０４内の絶縁体１０６及びトレンチ１０４外周面に形成されている柱状部拡散層１０５とによりリサーフ構造が形成されている。ベース層１０２の幅は、柱状部拡散層１０５の幅より広く形成されている（ここでの幅は、素子の表面に平行方向の各拡散層の幅）。 A trench 104 is formed through the base layer 102 at a position where the base layer 102 is separated into the inner peripheral diffusion layer 102A and the outer peripheral diffusion layer 102B. Here, the inner peripheral side indicates the side facing the center direction of the high voltage semiconductor device, and the outer peripheral side is opposite to the center of the high voltage semiconductor device, that is, from the center of the high voltage semiconductor device to the external direction (periphery direction). ) Shows the side facing.
A columnar portion diffusion layer 105 (Resurf layer) which is a P − type impurity semiconductor diffusion layer is formed on the outer peripheral surface portion of the trench 104, and an insulator 106 is filled inside the trench 104. The trench 104 is continuously formed in a groove (moat) shape surrounding the cell region of the element. A RESURF structure is formed by the insulator 106 in the trench 104 and the columnar portion diffusion layer 105 formed on the outer peripheral surface of the trench 104. The width of the base layer 102 is formed wider than the width of the columnar portion diffusion layer 105 (here, the width is the width of each diffusion layer in the direction parallel to the surface of the element).

セル領域のトランジスタには、ベース層１０２内にＮ＋＋型の不純物半導体層であるソース領域１０３及び表面Ｎ＋層１１２と、この表面Ｎ＋層１１２上部にゲート絶縁膜を介してゲート電極１０７が設けられている。ここで、不純物の濃度は、Ｎ＋＋型＞Ｎ＋型＞Ｎ型、及びＰ型＞Ｐ−型の関係となっている。
また、ドレイン層１００の裏面部にドレイン電極１１１が設けられ、ソース領域１０３に対してソース電極１１０が形成されている。
また、素子の外周領域において、素子の周縁部における表面には、ガードリング１１３が設けられ、ガードリング電極１１９を介してドレイン電極１１１と電気的に接続されている。 In the transistor in the cell region, a source region 103 and a surface N + layer 112 which are N ++ type impurity semiconductor layers are formed in a base layer 102, and a gate electrode 107 is formed on the surface N + layer 112 via a gate insulating film. Is provided. Here, the impurity concentration has a relationship of N ++ type> N + type> N type and P type> P − type.
A drain electrode 111 is provided on the back surface of the drain layer 100, and a source electrode 110 is formed with respect to the source region 103.
In the outer peripheral region of the element, a guard ring 113 is provided on the surface at the peripheral edge of the element, and is electrically connected to the drain electrode 111 via the guard ring electrode 119.

本実施形態においては、従来例と異なる点として、トレンチ１０４内に充填された絶縁体１０６により分離された内周側拡散層１０２Ａと外周側拡散層１０２Ｂとを接続する（短絡する）導電体１０を設けている。また、同様に、リサーフ層である柱状部拡散層１０５もほとんど絶縁体１０６により分離されており、十分に電位を伝達することができないが、内周側拡散層１０２Ａ，導電体１０及び外周側拡散層１０２Ｂを介して接続され、電位が伝達されることとなる。   In this embodiment, as a point different from the conventional example, the conductor 10 that connects (short-circuits) the inner peripheral diffusion layer 102A and the outer peripheral diffusion layer 102B separated by the insulator 106 filled in the trench 104. Is provided. Similarly, the columnar portion diffusion layer 105, which is a RESURF layer, is almost separated by the insulator 106 and cannot sufficiently transmit the potential, but the inner diffusion layer 102A, the conductor 10, and the outer diffusion It is connected through the layer 102B, and a potential is transmitted.

すなわち、露出しているドリフト層１０１，内周側拡散層１０２Ａ，外周側拡散層１０２Ｂ及び絶縁体１０６の上部に絶縁膜１０８を形成して、内周側拡散層１０２Ａ及び外周側拡散層１０２Ｂ各々に対し、少なくとも１部表面が露出するコンタクトホールを形成し、導電体１０のパターンを形成する。ここで、内周側拡散層１０２Ａ及び外周側拡散層１０２Ｂの全周にわたりコンタクトを形成し、導電体１０を各柱状領域上に環状全面に形成する構成とする場合、電位の伝達がさらに良好に行われる。これにより、各柱状領域において、内周側拡散層１０２Ａと外周側拡散層１０２Ｂとがコンタクトホール内の導電体及び導電体１０のパターンを介して電気的に接続されている。
上述の構成においては、導電体１０が、各柱状領域間にて必ず分離して構成されなければならない。すなわち、上記導電体１０のパターンは、ＦＬＲ領域における各柱状領域間において分離されたストライプ形状となっており、各トレンチ１０４上部に形成され、素子の外周部に沿って環状に形成されている。 That is, the insulating film 108 is formed on the exposed drift layer 101, inner peripheral diffusion layer 102A, outer peripheral diffusion layer 102B, and insulator 106, and the inner peripheral diffusion layer 102A and the outer peripheral diffusion layer 102B are respectively formed. On the other hand, a contact hole in which at least a part of the surface is exposed is formed, and a pattern of the conductor 10 is formed. Here, when the contact is formed over the entire circumference of the inner peripheral diffusion layer 102A and the outer peripheral diffusion layer 102B, and the conductor 10 is formed on the entire ring surface on each columnar region, the potential transmission is further improved. Done. Thereby, in each columnar region, the inner peripheral diffusion layer 102A and the outer peripheral diffusion layer 102B are electrically connected via the conductor in the contact hole and the pattern of the conductor 10.
In the above-described configuration, the conductor 10 must be configured to be separated between the columnar regions. That is, the pattern of the conductor 10 has a stripe shape separated between the respective columnar regions in the FLR region, is formed on the upper portion of each trench 104, and is formed in an annular shape along the outer periphery of the element.

上述した構造により、図３におけるセル領域のＭＯＳトランジスタにおいて、ドレイン電極１１１及びソース電極１１０間に電圧が印加され、ゲート電極１０７に閾値を超える電圧が印加されるとトランジスタがオン状態、すなわち、ゲート電極１０７直下のベース層１０２の表面部にチャネルが形成され、キャリア（電子）がソース領域１０３から、ドリフト層１０１を経てドレイン層１００に到達することにより、ドレイン電極１１１とソース電極１１０との間に電流が流れる。
ここで、ドレイン電極１１１に印加される電圧ＶD及びソース電極１１０に印加される電圧ＶSとはＶD＞ＶSの関係であり、またゲート電極１０７に印加される電圧ＶG及びソース電極１１０に印加される電圧ＶSとはＶG＞ＶSの関係である。 With the structure described above, in the MOS transistor in the cell region in FIG. 3, when a voltage is applied between the drain electrode 111 and the source electrode 110 and a voltage exceeding a threshold is applied to the gate electrode 107, the transistor is turned on, that is, the gate A channel is formed in the surface portion of the base layer 102 immediately below the electrode 107, and carriers (electrons) reach the drain layer 100 from the source region 103 through the drift layer 101, whereby the drain electrode 111 and the source electrode 110 are interposed. Current flows through
Here, the voltage VD applied to the drain electrode 111 and the voltage VS applied to the source electrode 110 have a relationship of VD> VS, and the voltage VG applied to the gate electrode 107 and the source electrode 110 are applied. The voltage VS is a relationship of VG> VS.

一方、ゲート電極１０７に印加される電圧ＶGが閾値以下であり、また、ドレイン電極１１１に印加される電圧ＶD及びソース電極１１０に印加される電圧ＶSとがＶD＞ＶSの関係であるが、ＶDがＶSに比較して非常に高い電圧である場合、ベース領域１０２とドリフト層１０１との接合面がｐｎ接合であるため空乏層が延びる。
同様に、柱状拡散層部１０５にもベース領域１０２を介して電位が伝達されるため、柱状拡散層部１０５とドリフト層１０１との接合面もｐｎ接合であるため、空乏層が延びる。
上述した空乏層の延びは、柱状拡散層部１０５が絶縁体１０６により制限されるため、ドリフト層１０１がより空乏層化されることとなる。 On the other hand, the voltage VG applied to the gate electrode 107 is equal to or lower than the threshold value, and the voltage VD applied to the drain electrode 111 and the voltage VS applied to the source electrode 110 have a relationship of VD> VS. Is a very high voltage compared to VS, the depletion layer extends because the junction surface between the base region 102 and the drift layer 101 is a pn junction.
Similarly, since the potential is transmitted to the columnar diffusion layer part 105 through the base region 102, the junction surface between the columnar diffusion layer part 105 and the drift layer 101 is also a pn junction, so that the depletion layer extends.
The extension of the depletion layer described above is that the columnar diffusion layer portion 105 is limited by the insulator 106, so that the drift layer 101 is further depleted.

また、セル領域のトランジスタにおけるベース領域１０２と、絶縁体１０６により分離されている外周側拡散層１０２Ｂとは、ソース電極１１０で接続されており、ソース電極１１０に印加された高電圧の電位が伝達され、外周側拡散層１０２Ｂとドリフト層１０１とで形成されるｐｎ接合部、及び柱状拡散層部１０５にも外周側拡散層１０２Ｂを介して電位が伝達されるため、この外周側拡散層１０２Ｂ下部の柱状拡散層部１０５とドリフト層１０１とで形成されるｐｎ接合部各々にて空乏層化が起こる。
そして、この空乏層が外周側に隣接する柱状領域Ｐ１方向に延び、この隣接する柱状領域Ｐ１の内周側拡散層１０２Ａ及びこの内周側拡散層１０２Ａ下部の柱状拡散層部１０５へ到達することにより、空乏層化に対応する電位が導電体１０を介して外周側拡散層１０２Ｂへ伝達される。 In addition, the base region 102 in the transistor in the cell region and the outer peripheral diffusion layer 102B separated by the insulator 106 are connected by the source electrode 110, and a high-voltage potential applied to the source electrode 110 is transmitted. Since the potential is transmitted to the pn junction part formed by the outer peripheral side diffusion layer 102B and the drift layer 101 and the columnar diffusion layer part 105 via the outer peripheral side diffusion layer 102B, the lower part of the outer peripheral side diffusion layer 102B. Depletion layers occur at each pn junction formed by the columnar diffusion layer portion 105 and the drift layer 101.
The depletion layer extends in the direction of the columnar region P1 adjacent to the outer peripheral side, and reaches the inner peripheral diffusion layer 102A of the adjacent columnar region P1 and the columnar diffusion layer portion 105 below the inner peripheral diffusion layer 102A. Thus, a potential corresponding to depletion layer formation is transmitted to the outer peripheral diffusion layer 102B through the conductor 10.

これにより、柱状領域Ｐ１における外周側拡散層１０２Ｂとドリフト層１０１とで形成されるｐｎ接合、及び柱状拡散層部１０５にも外周側拡散層１０２Ｂを介して電位が伝達されるため、この外周側拡散層１０２Ｂ下部の柱状拡散層部１０５とドリフト層１０１とで形成されるｐｎ接合各々にて空乏層化が起こる。
そして、この空乏層が外周側に隣接する柱状領域Ｐ２方向に延び、この隣接する柱状領域Ｐ２の内周側拡散層１０２Ａ及びこの内周側拡散層１０２Ａ下部の柱状拡散層部１０５へ到達することにより、空乏層化に対応する電位が導電体１０を介して外周側拡散層１０２Ｂへ伝達される。
これは、図４に示すシミュレーション結果（空乏層の電位分布を示す）からも、最外周の柱状領域（リサーフ層）まで電位が伝達され、すなわち空乏層の素子外周側への広がりが良好に実現されていることが判る。このシミュレーションは、従来例の場合と同様に、二次元デバイスシミュレータで行った。 As a result, the potential is transmitted to the pn junction formed by the outer peripheral diffusion layer 102B and the drift layer 101 in the columnar region P1 and the columnar diffusion layer portion 105 via the outer peripheral diffusion layer 102B. Depletion layers occur at each pn junction formed by the columnar diffusion layer portion 105 and the drift layer 101 below the diffusion layer 102B.
The depletion layer extends in the direction of the columnar region P2 adjacent to the outer peripheral side, and reaches the inner peripheral diffusion layer 102A of the adjacent columnar region P2 and the columnar diffusion layer portion 105 below the inner peripheral diffusion layer 102A. Thus, a potential corresponding to depletion layer formation is transmitted to the outer peripheral diffusion layer 102B through the conductor 10.
This is because the potential is transmitted to the outermost columnar region (Resurf layer) from the simulation results shown in FIG. 4 (showing the potential distribution of the depletion layer), that is, the depletion layer is well spread to the device outer periphery side. It can be seen that This simulation was performed with a two-dimensional device simulator as in the case of the conventional example.

上述したように、各柱状領域において、内周側拡散層１０２Ａと外周側拡散層１０２Ｂとを接続する導電体１０を設けることにより、ソース電極１１０とドレイン電極１１１との間に印加される電位が、ソース電極１１０の内周側から外周側に対して、電位が空乏層により良好に順次伝達され、ＦＬＲ領域における隣接する柱状領域に対して空乏層が延び、素子の周縁部の高耐圧特性を向上させることができる。   As described above, in each columnar region, by providing the conductor 10 that connects the inner peripheral diffusion layer 102A and the outer peripheral diffusion layer 102B, the potential applied between the source electrode 110 and the drain electrode 111 is reduced. In addition, the potential is successively transmitted through the depletion layer from the inner periphery side to the outer periphery side of the source electrode 110, the depletion layer extends to the adjacent columnar region in the FLR region, and the high breakdown voltage characteristics of the peripheral portion of the element are increased. Can be improved.

次に、図面を参照し、上述したセル領域のトランジスタ及び柱状領域の製造方法の説明を行う。主要な製造工程の終了した段階での、トランジスタ及び柱状領域の断面を示す概念図である図５〜図１６を参照して説明する。
ここで、ＦＬＲ領域に形成される柱状領域もトランジスタと製造工程がほぼ同様であるため、トランジスタの製造工程を例に説明し、柱状領域が異なる点を必要に応じて説明する。また、上記トランジスタ及び柱状領域は、素子の周縁部に沿った環状に、各々複数個からなるストライプ状に形成される。 Next, with reference to the drawings, the above-described method for manufacturing the transistor in the cell region and the columnar region will be described. A description will be given with reference to FIGS. 5 to 16 which are conceptual diagrams showing cross sections of the transistor and the columnar region at the end of the main manufacturing process.
Here, since the columnar region formed in the FLR region has substantially the same manufacturing process as that of the transistor, the transistor manufacturing process will be described as an example, and the difference between the columnar regions will be described as necessary. The transistors and the columnar regions are formed in a plurality of stripes in a ring shape along the peripheral edge of the element.

図５において示すように、 Ｎ型基板（例えば、シリコン基板）にドレイン層１００及びドリフト層１０１を形成する。例えば、ドレイン層１００上部にＣＶＤ（化学気相成長）法でドリフト層１０１を堆積させても良いし、Ｎ−型のドリフト層１０１の下部にＮ型不純物を拡散させ、Ｎ＋型のドレイン層１００を形成させても良い。以下、素子の形成面として、ドリフト層１０１の露出した面（図５の上方向の面）を表面とし、ドレイン層１００の露出した面（図５の下方向の面）を下部として説明する。
そして、ドリフト層１０１の表面及びドレイン層１００の裏面に、所定の厚さの絶縁膜（シリコン酸化膜；ＳiＯ2）を、基板の熱酸化またはＣＶＤにより形成する。 As shown in FIG. 5, the drain layer 100 and the drift layer 101 are formed on an N-type substrate (for example, a silicon substrate). For example, the drift layer 101 may be deposited on the drain layer 100 by a CVD (chemical vapor deposition) method, or an N-type impurity is diffused below the N− type drift layer 101, so that the N + type drain layer 100. May be formed. Hereinafter, as an element formation surface, the exposed surface of the drift layer 101 (upper surface in FIG. 5) is used as the surface, and the exposed surface of the drain layer 100 (lower surface in FIG. 5) is used as the lower portion.
Then, an insulating film (silicon oxide film; SiO2) having a predetermined thickness is formed on the surface of the drift layer 101 and the back surface of the drain layer 100 by thermal oxidation of the substrate or CVD.

次に、図６において示すように、ドリフト層１０１表面上の絶縁膜にレジストを塗布し、フォトリソ技術により、このレジストをパターニングして、所定の領域の上記絶縁膜をエッチングする。
そして、続けて、図７に示すように、エッチングの施された上記絶縁膜をマスクとして、ＲＩＥ（異方性エッチング）により、素子表面に対して垂直方向に、所定の深さのトレンチ１０４を形成する。ここで、トランジスタと柱状領域とのトレンチは、各々異なったマスクにてＲＩＥを行い、異なった深さに形成しても良い（すなわち、各々の領域をレジストによりマスクして、エッチングする深さの異なるエッチング処理を２回行う）。また、本実施形態においては、トレンチ１０４はドリフト層１０１を貫通していないが、貫通する深さまでエッチングして形成しても良い。 Next, as shown in FIG. 6, a resist is applied to the insulating film on the surface of the drift layer 101, this resist is patterned by photolithography, and the insulating film in a predetermined region is etched.
Then, as shown in FIG. 7, a trench 104 having a predetermined depth is formed in a direction perpendicular to the element surface by RIE (anisotropic etching) using the etched insulating film as a mask. Form. Here, the trenches of the transistor and the columnar region may be formed at different depths by performing RIE using different masks (that is, each region is masked with a resist and etched to a depth of etching). 2 different etching processes are performed). In this embodiment, the trench 104 does not penetrate the drift layer 101, but may be formed by etching to a depth that penetrates the drift layer 101.

次に、図８に示すように、上記レジストをマスクとして、表面に対して垂直な軸方向からではなく、斜め方向から、すなわちこの垂直な軸方向に対して所定の角度を持たせた方向からＰ型不純物（例えば、基板がシリコンであるとするとボロン）を、トレンチ１０４内における素子の内側方向及び外側方向の双方の側壁に対してイオン注入を行う。
そして、図９に示すように、レジストを除去した後、ＣＶＤ等によりトレンチ１０４内部に絶縁体１０６を堆積させて、充填させる。そして、所定の温度でアニール処理を行い、絶縁体１０６の組成を改善させるとともに、イオン注入した不純物を拡散させ、リサーフ層としての柱状部拡散層１０５を形成する。 Next, as shown in FIG. 8, the resist is used as a mask, not from an axial direction perpendicular to the surface, but from an oblique direction, that is, from a direction having a predetermined angle with respect to the perpendicular axial direction. P-type impurities (for example, boron if the substrate is silicon) are ion-implanted into both the inner and outer sidewalls of the device in the trench 104.
Then, as shown in FIG. 9, after removing the resist, an insulator 106 is deposited and filled in the trench 104 by CVD or the like. Then, annealing is performed at a predetermined temperature to improve the composition of the insulator 106 and diffuse the ion-implanted impurities to form a columnar portion diffusion layer 105 as a RESURF layer.

次に、図１０に示すように、セル領域において、ゲート酸化膜を形成するため、トレンチ１０４上部の絶縁膜を除いて、エッチングによりドリフト層１０１表面の絶縁層を除去し、所定の厚さのゲート酸化膜を形成する。このとき、ＦＬＲ領域における絶縁膜も同様に除去される。
次に、図１１に示すように、ドリフト層１０１表面に表面Ｎ＋層１１２を、Ｎ型不純物（例えば、リンまたはヒ素）をイオン注入することによりり形成する。このとき、ＦＬＲ領域及び外周領域上には、レジストをマスクとして形成し、Ｎ型不純物が注入されて、表面Ｎ＋層１１２が形成されないようにする。そして、上記レジストを除去した後、ドリフト層１０１表面にポリシリコンの層をＣＶＤ等により形成する。 Next, as shown in FIG. 10, in order to form a gate oxide film in the cell region, the insulating layer on the surface of the drift layer 101 is removed by etching except for the insulating film on the upper part of the trench 104, and a predetermined thickness is obtained. A gate oxide film is formed. At this time, the insulating film in the FLR region is similarly removed.
Next, as shown in FIG. 11, a surface N + layer 112 is formed on the surface of the drift layer 101 by ion implantation of an N-type impurity (for example, phosphorus or arsenic). At this time, a resist is formed as a mask on the FLR region and the outer peripheral region, and N-type impurities are implanted so that the surface N + layer 112 is not formed. Then, after removing the resist, a polysilicon layer is formed on the surface of the drift layer 101 by CVD or the like.

次に、図１２に示すように、セル領域においては、上記ポリシリコンの層上にトランジスタのゲート電極１０７のパターンに形成されたレジストパターンを、フォトリソ技術を用いて形成する。また、ＦＬＲ領域及び外周領域のポリシリコン上のレジストは全て除去する。上記形成したレジストのパターンをマスクとしてエッチング処理を行い、ゲート電極１０７を形成するとともに、ＦＬＲ領域及び外周領域上のポリシリコンの層を除去する。
そして、レジストを塗布し、フォトリソ技術を用いて、ゲート電極１０７上と、ＦＬＲ領域上に、ベース領域を形成するためのパターンを形成する。ゲート電極１０７上のレジストのパターンは、平面視においてほぼゲート電極１０７のパターンに重なる。
上記レジストのパターンをマスクとして、Ｐ型不純物をイオン注入した後に、レジストを除去する。その後、所定の温度にてアニール処理を行い、トランジスタにおけるベース領域１０２と、柱状領域におけるベース領域１０２（トレンチ１０４の内周側に位置する内周側拡散層１０２Ａ及び、トレンチ１０４の外周側に位置する外周側拡散層１０２Ｂ）とを形成する。 Next, as shown in FIG. 12, in the cell region, a resist pattern formed in the pattern of the gate electrode 107 of the transistor is formed on the polysilicon layer by using a photolithography technique. Also, all the resist on the polysilicon in the FLR region and the outer peripheral region is removed. Etching is performed using the formed resist pattern as a mask to form the gate electrode 107, and the polysilicon layer on the FLR region and the outer peripheral region is removed.
Then, a resist is applied, and a pattern for forming a base region is formed on the gate electrode 107 and the FLR region by using a photolithography technique. The resist pattern on the gate electrode 107 substantially overlaps the pattern of the gate electrode 107 in plan view.
Using the resist pattern as a mask, P-type impurities are ion-implanted, and then the resist is removed. Thereafter, annealing is performed at a predetermined temperature, and the base region 102 in the transistor, the base region 102 in the columnar region (the inner peripheral side diffusion layer 102A located on the inner peripheral side of the trench 104, and the outer peripheral side of the trench 104 are positioned. Outer peripheral diffusion layer 102B).

次に、図１３に示すように、レジストを塗布し、フォトリソ技術を用いて、セル領域におけるソース領域を形成するレジストのパターンを形成し、ＦＬＲ領域全面をこのレジストでマスクし、外周領域におけるガードリングを形成するレジストのパターンを形成する。
そして、上記レジストのパターンをマスクとして、Ｎ型不純物をイオン注入し、レジストを除去した後にアニールを行い、トランジスタのソース領域１０３及び外周領域のガードリング１１３を形成する。このとき、ＦＬＲ領域はレジストによりマスクされているため、Ｎ型不純物がイオン注入されず、ソース領域１０３が形成されない。 Next, as shown in FIG. 13, a resist is applied, and a resist pattern for forming a source region in the cell region is formed by using a photolithography technique. The entire FLR region is masked with this resist, and a guard in the outer peripheral region is formed. A resist pattern for forming a ring is formed.
Then, using the resist pattern as a mask, N-type impurities are ion-implanted, and after removing the resist, annealing is performed to form the source region 103 of the transistor and the guard ring 113 in the outer peripheral region. At this time, since the FLR region is masked by the resist, the N-type impurity is not ion-implanted and the source region 103 is not formed.

次に、図１４に示すように、ドリフト層１０１の表面上部に、ＣＶＤ法などにより、層間絶縁膜１０８を形成する。
そして、上記層間絶縁膜１０８上にレジストを塗布し、フォトリソ技術により、トランジスタにおけるベース層１０２及びソース領域１０３に対するコンタクトと、柱状領域における内周側拡散層１０２Ａ及び外周側拡散層１０２Ｂに対するコンタクトと、外周領域におけるガードリング１１３に対するコンタクトとを形成するレジストのパターンを形成する。そして、上記レジストのパターンをマスクとして、層間絶縁膜１０８のエッチングを行い、上述した各コンタクトの穴を形成する。 Next, as shown in FIG. 14, an interlayer insulating film 108 is formed on the surface of the drift layer 101 by CVD or the like.
Then, a resist is applied on the interlayer insulating film 108, and contacts to the base layer 102 and the source region 103 in the transistor, contacts to the inner peripheral diffusion layer 102A and the outer peripheral diffusion layer 102B in the columnar region, by photolithography, A resist pattern for forming a contact with the guard ring 113 in the outer peripheral region is formed. Then, using the resist pattern as a mask, the interlayer insulating film 108 is etched to form the above-described contact holes.

次に、図１５に示すように、層間絶縁膜１０８及び形成されたコンタクトの穴に対して、電極材料の導電体層をスパッタリングやＣＶＤ等により形成する。
そして、上記導電体層上にレジストを塗布し、フォトリソ技術により、セル領域，ＦＬＲ領域及び外周領域各々に、電極に対応したレジストのパターンを形成する。このレジストのパターンをマスクとして、エッチングを行うことで、セル領域におけるトランジスタのソース電極１１０，ＦＬＲ領域における柱状領域の導電体１０，及び外周領域におけるガードリング電極１１９が形成される。 Next, as shown in FIG. 15, a conductor layer of an electrode material is formed by sputtering, CVD, or the like, with respect to the interlayer insulating film 108 and the formed contact hole.
Then, a resist is applied on the conductor layer, and a resist pattern corresponding to the electrode is formed in each of the cell region, the FLR region, and the outer peripheral region by photolithography. Etching is performed using the resist pattern as a mask to form the source electrode 110 of the transistor in the cell region, the conductor 10 in the columnar region in the FLR region, and the guard ring electrode 119 in the outer peripheral region.

ソース電極１１０はベース領域１０２及びソース領域１０３に対してソース電位を与え、導電体１０は柱状領域単位で内周側拡散層１０２Ａ及び外周側拡散層１０２Ｂを電気的に接続し、ガードリング電極１１９はガードリング１１３に対してドレイン電位を与える。
また、各電極上及び露出している層間絶縁膜１０８上に、保護膜をＣＶＤ等によりデポジションする（堆積させる）。この保護膜は、各電極及び層間絶縁膜１０８の段差を超えて、エッチングした後に、膜厚が薄くなる部分（すなわち各電極の上部）において、保護機能に十分な厚さが残る厚さに堆積させる。そして、上記保護膜を異方性エッチングによりエッチングし、保護膜表面の凹凸が規定の範囲とする。 The source electrode 110 applies a source potential to the base region 102 and the source region 103, and the conductor 10 electrically connects the inner peripheral diffusion layer 102A and the outer peripheral diffusion layer 102B in units of columnar regions, and the guard ring electrode 119. Gives a drain potential to the guard ring 113.
Further, a protective film is deposited (deposited) on each electrode and the exposed interlayer insulating film 108 by CVD or the like. This protective film is deposited so as to leave a sufficient thickness for the protective function in the portion where the film thickness becomes thin (that is, the upper part of each electrode) after etching beyond the step between each electrode and the interlayer insulating film 108. Let And the said protective film is etched by anisotropic etching, and the unevenness | corrugation on the surface of a protective film is made into a defined range.

次に、図１６に示すように、バックグラインダーにより、ドレイン層１００裏面の絶縁膜及びドレイン層１００の裏面を全面エッチングする。
そして、ドレイン層１００の裏面にドレイン電極１１１として、金属をスパッタリングにより堆積させる。
また、上述した製造工程において、導電体１０をソース電極１１０と同一プロセスにて形成したが、柱状領域におけるトレンチ１０４内に充填された絶縁体の表面部を、部分的にエッチングし、導電体１０がドリフト層１０１に埋設されるように形成しても良い。 Next, as shown in FIG. 16, the whole surface of the insulating film on the back surface of the drain layer 100 and the back surface of the drain layer 100 is etched by a back grinder.
Then, a metal is deposited on the back surface of the drain layer 100 as the drain electrode 111 by sputtering.
In the manufacturing process described above, the conductor 10 is formed by the same process as that of the source electrode 110. However, the surface portion of the insulator filled in the trench 104 in the columnar region is partially etched to obtain the conductor 10 May be embedded in the drift layer 101.

＜第２の実施形態＞
第２の実施形態は、第１の実施形態と異なり、導電体１０を電極として形成せずに、ベース領域１０２の拡散層を導電体１０として用いている。
すなわち、図１７の柱状領域の構造を斜視した概念図に示されるように、トレンチ１０４を部分的に形成せずに、内周側拡散層１０２Ａと外周側拡散層１０２Ｂとを、ベース領域１０２と同一の拡散層により形成した導電層１１により短絡したものである
これにより、各柱状領域において、内周側拡散層１０２Ａと外周側拡散層１０２Ｂとが電気的に接続されているため、第１の実施形態と同様に、ドレイン電極１１１に対して、高電圧が印加された場合、外周部方向に空乏層が延び、順次電位が外側方向の柱状領域に伝達され、耐圧を向上させることができる。 <Second Embodiment>
Unlike the first embodiment, the second embodiment uses the diffusion layer of the base region 102 as the conductor 10 without forming the conductor 10 as an electrode.
That is, as shown in the conceptual diagram in which the structure of the columnar region in FIG. 17 is perspectiveed, the inner peripheral diffusion layer 102A and the outer peripheral diffusion layer 102B are formed with the base region 102 without forming the trench 104 partially. This is short-circuited by the conductive layer 11 formed of the same diffusion layer. As a result, in each columnar region, the inner peripheral diffusion layer 102A and the outer peripheral diffusion layer 102B are electrically connected. As in the embodiment, when a high voltage is applied to the drain electrode 111, a depletion layer extends in the outer peripheral direction, and the potential is sequentially transmitted to the columnar region in the outer direction, so that the breakdown voltage can be improved.

製造工程としては、図７の工程において、環状に連続した溝としてトレンチ１０４を形成するのではなく、間欠的に、すなわち所定の間隔を有してトレンチを形成する。この間隔は、柱状部拡散層１０５の素子表面に平行方向の厚さと同様な厚さが望ましい。
また、図１２の工程において、このトレンチ１０４が形成されない部分にも、Ｐ型不純物をイオン注入して、導電層１１を形成する。
そして、図１５の工程において、電極を形成しない以外は、第１の実施形態の製造方法と同様であるため、説明を省略する。 As a manufacturing process, in the process of FIG. 7, the trench 104 is not formed as an annular continuous groove, but is formed intermittently, that is, with a predetermined interval. This distance is desirably the same thickness as the thickness of the columnar diffusion layer 105 in the direction parallel to the element surface.
In the step of FIG. 12, the conductive layer 11 is formed by ion-implanting a P-type impurity in a portion where the trench 104 is not formed.
And since it is the same as that of the manufacturing method of 1st Embodiment except not forming an electrode in the process of FIG. 15, description is abbreviate | omitted.

本発明の第１及び第２の実施形態による高耐圧半導体装置の素子の平面構造を示す概念図である。It is a conceptual diagram which shows the planar structure of the element of the high voltage semiconductor device by the 1st and 2nd embodiment of this invention. 本発明の第１の実施形態による高耐圧半導体装置の素子の平面構造を示す概念図である。It is a conceptual diagram which shows the planar structure of the element of the high voltage semiconductor device by the 1st Embodiment of this invention. 図２における線Ｃ−Ｃにおける線視断面を示す概念図である。FIG. 3 is a conceptual diagram showing a cross-sectional view taken along line CC in FIG. 2. 図３に示すＦＬＲ構造における空乏層の延びを示すシミュレーション結果を示す概念図である。It is a conceptual diagram which shows the simulation result which shows extension of the depletion layer in the FLR structure shown in FIG. 本発明の第１の実施形態による素子の製造方法を説明する、工程後の素子のの断面を示す概念図である。It is a conceptual diagram which shows the cross section of the element after a process explaining the manufacturing method of the element by the 1st Embodiment of this invention. 本発明の第１の実施形態による素子の製造方法を説明する、工程後の素子のの断面を示す概念図である。It is a conceptual diagram which shows the cross section of the element after a process explaining the manufacturing method of the element by the 1st Embodiment of this invention. 本発明の第１の実施形態による素子の製造方法を説明する、工程後の素子のの断面を示す概念図である。It is a conceptual diagram which shows the cross section of the element after a process explaining the manufacturing method of the element by the 1st Embodiment of this invention. 本発明の第１の実施形態による素子の製造方法を説明する、工程後の素子のの断面を示す概念図である。It is a conceptual diagram which shows the cross section of the element after a process explaining the manufacturing method of the element by the 1st Embodiment of this invention. 本発明の第１の実施形態による素子の製造方法を説明する、工程後の素子のの断面を示す概念図である。It is a conceptual diagram which shows the cross section of the element after a process explaining the manufacturing method of the element by the 1st Embodiment of this invention. 本発明の第１の実施形態による素子の製造方法を説明する、工程後の素子のの断面を示す概念図である。It is a conceptual diagram which shows the cross section of the element after a process explaining the manufacturing method of the element by the 1st Embodiment of this invention. 本発明の第１の実施形態による素子の製造方法を説明する、工程後の素子のの断面を示す概念図である。It is a conceptual diagram which shows the cross section of the element after a process explaining the manufacturing method of the element by the 1st Embodiment of this invention. 本発明の第１の実施形態による素子の製造方法を説明する、工程後の素子のの断面を示す概念図である。It is a conceptual diagram which shows the cross section of the element after a process explaining the manufacturing method of the element by the 1st Embodiment of this invention. 本発明の第１の実施形態による素子の製造方法を説明する、工程後の素子のの断面を示す概念図である。It is a conceptual diagram which shows the cross section of the element after a process explaining the manufacturing method of the element by the 1st Embodiment of this invention. 本発明の第１の実施形態による素子の製造方法を説明する、工程後の素子のの断面を示す概念図である。It is a conceptual diagram which shows the cross section of the element after a process explaining the manufacturing method of the element by the 1st Embodiment of this invention. 本発明の第１の実施形態による素子の製造方法を説明する、工程後の素子のの断面を示す概念図である。It is a conceptual diagram which shows the cross section of the element after a process explaining the manufacturing method of the element by the 1st Embodiment of this invention. 本発明の第１の実施形態による素子の製造方法を説明する、工程後の素子のの断面を示す概念図である。It is a conceptual diagram which shows the cross section of the element after a process explaining the manufacturing method of the element by the 1st Embodiment of this invention. 本発明の第２の実施形態の柱状領域を説明する、柱状領域を斜視した概念図である。It is the conceptual diagram which looked at the columnar area | region explaining the columnar area | region of the 2nd Embodiment of this invention. 本発明の各実施形態及び従来例におけるトランジスタの断面構造を示す概念図である。It is a conceptual diagram which shows the cross-sectional structure of the transistor in each embodiment of this invention, and a prior art example. 従来例におけるＦＬＲにおける柱状領域の断面構造を示す概念図である。It is a conceptual diagram which shows the cross-section of the columnar area | region in FLR in a prior art example. 従来例のＦＬＲの構造において、ドレイン電極１１１に高電圧が印加された場合の空乏層の延びをシミュレーションした結果を示す概念図である。FIG. 11 is a conceptual diagram showing a result of simulating the extension of a depletion layer when a high voltage is applied to the drain electrode 111 in the conventional FLR structure.

符号の説明Explanation of symbols

１０…導電体 １１…導電層
１００…ドレイン層 １０１…ドリフト層
１０２…ベース層 １０２Ａ…内周側拡散層
１０２Ｂ…外周側拡散層 １０３…ソース領域
１０４…トレンチ １０５…柱状部拡散層
１０６…絶縁体 １０７…ゲート電極
１０８…層間絶縁膜 １１０…ソース電極
１１１…ドレイン電極 １１２…表面Ｎ＋層
１１３…ガードリング １１９…ガードリング電極
DESCRIPTION OF SYMBOLS 10 ... Conductor 11 ... Conductive layer 100 ... Drain layer 101 ... Drift layer 102 ... Base layer 102A ... Inner peripheral side diffused layer 102B ... Outer peripheral side diffused layer 103 ... Source region 104 ... Trench 105 ... Columnar part diffused layer 106 ... Insulator DESCRIPTION OF SYMBOLS 107 ... Gate electrode 108 ... Interlayer insulating film 110 ... Source electrode 111 ... Drain electrode 112 ... Surface N + layer 113 ... Guard ring 119 ... Guard ring electrode

Claims (10)

素子が形成されたセル領域の外周に隣接した終端部において、リサーフ構造を有するＦＬＲが所定の間隔にて複数設けられた高耐圧半導体装置であり、
前記ＦＬＲが、
第１導電型の基板表面に、環状に連続して設けられたトレンチと、
該トレンチ外周面に沿って設けられた第２の導電型の第１の拡散領域と、
前記トレンチ内部に充填された絶縁体と、
前記絶縁体により、内周側拡散層と外周側拡散層とに分割された、半導体装置の各辺に沿うように環状に連続して設けられた第２導電型の第２の拡散領域と、
前記第２の拡散領域における内周側拡散領域と外周側拡散領域とに介挿された導電体と
を有することを特徴とする高耐圧半導体装置。 A high withstand voltage semiconductor device in which a plurality of FLRs having a RESURF structure are provided at a predetermined interval at a terminal portion adjacent to the outer periphery of a cell region where an element is formed
The FLR is
A trench continuously provided in an annular shape on the surface of the first conductivity type substrate;
A first diffusion region of a second conductivity type provided along the outer peripheral surface of the trench;
An insulator filled inside the trench;
A second diffusion region of a second conductivity type, which is divided into an inner peripheral side diffusion layer and an outer peripheral side diffusion layer by the insulator, and is provided continuously in an annular shape along each side of the semiconductor device;
A high breakdown voltage semiconductor device comprising: a conductor interposed between an inner peripheral diffusion region and an outer peripheral diffusion region in the second diffusion region. 前記ＦＬＲがそれぞれ電気的に分離されて形成されていることを特徴とする請求項１記載の高耐圧半導体装置。   2. The high breakdown voltage semiconductor device according to claim 1, wherein each of the FLRs is formed to be electrically separated. 前記導電体が金属で構成され、前記第２の拡散領域の内周側拡散領域及び外周側拡散領域各々にコンタクトにて接続されていることを特徴とする請求項１または請求項２記載の高耐圧半導体装置。   3. The high circuit according to claim 1, wherein the conductor is made of metal and is connected to each of an inner peripheral side diffusion region and an outer peripheral side diffusion region of the second diffusion region by a contact. High voltage semiconductor device. 前記導電体が第２導電型の半導体部で構成され、前記第２の拡散領域の内周側拡散領域及び外周側拡散領域各々に接続されていることを特徴とする請求項１または請求項２に記載の高耐圧半導体装置。   The said conductor is comprised with the semiconductor part of a 2nd conductivity type, and is connected to each of the inner periphery side diffusion region and outer periphery side diffusion region of the said 2nd diffusion region. A high breakdown voltage semiconductor device according to 1. 前記トレンチが間欠に形成され、トレンチが間欠された領域に第２の導電体の拡散層が形成され、この拡散層により前記第２の拡散領域の内周側拡散領域及び外周側拡散領域とが接続されていることを特徴とする請求項４に記載の高圧半導体装置。   The trench is intermittently formed, and a diffusion layer of a second conductor is formed in the region where the trench is intermittent, and the diffusion layer forms an inner peripheral side diffusion region and an outer peripheral side diffusion region of the second diffusion region. The high voltage semiconductor device according to claim 4, wherein the high voltage semiconductor device is connected. 素子が形成されたセル領域の外周に隣接した終端部において、リサーフ構造を有するＦＬＲが所定の間隔にて複数設けられた高耐圧半導体装置の製造方法であり、
前記ＦＬＲの形成において、
第１導電型の基板表面トレンチを環状に連続して設ける第１の工程と、
該トレンチの外周面に沿って第２導電型の第１の拡散層を形成する第２の工程と、
前記トレンチ内部に絶縁体を充填する第３の工程と、
前記絶縁体により、内周側拡散層と外周側拡散層とに分割され、半導体装置の各辺に沿うように環状に連続して設けられる第２導電型の第２の拡散領域を形成する第４の工程と、
前記第２の拡散領域の内周側拡散領域及び外周側拡散領域を接続する導電部を形成する第５の工程と
を有することを特徴とする高耐圧半導体装置の製造方法 A method of manufacturing a high voltage semiconductor device in which a plurality of FLRs having a RESURF structure are provided at a predetermined interval at a terminal portion adjacent to the outer periphery of a cell region where an element is formed,
In forming the FLR,
A first step of providing a first conductive type substrate surface trench continuously in an annular shape;
A second step of forming a first conductivity type first diffusion layer along the outer peripheral surface of the trench;
A third step of filling the trench with an insulator;
A second conductive type second diffusion region is formed by the insulator, which is divided into an inner peripheral diffusion layer and an outer peripheral diffusion layer, and is continuously provided in an annular shape along each side of the semiconductor device. 4 steps,
And a fifth step of forming a conductive portion connecting the inner periphery side diffusion region and the outer periphery side diffusion region of the second diffusion region. 前記第５の工程が、
金属を堆積させる工程と、
該金属をＦＬＲ各々における第２の拡散領域の内周側拡散領域と外周側拡散領域とを接続する導電部としてパターニングする工程と
を有することを特徴とする請求項６に記載の高耐圧半導体装置の製造方法。 In the fifth step,
Depositing a metal;
7. The high breakdown voltage semiconductor device according to claim 6, further comprising a step of patterning the metal as a conductive portion that connects the inner diffusion region and the outer diffusion region of the second diffusion region in each FLR. Manufacturing method. 前記第１の工程において、前記トレンチを、間欠的に形成し、
前記第５の工程が前記トレンチの間欠部分に、第２の拡散領域の内周側拡散領域と外周側拡散領域とを接続する第２の導電体の拡散層を形成する工程と
を有することを特徴とする請求項６に記載の高耐圧半導体装置の製造方法。 In the first step, the trench is formed intermittently;
The fifth step includes a step of forming a diffusion layer of a second conductor connecting the inner side diffusion region and the outer side diffusion region of the second diffusion region in the intermittent portion of the trench. The method of manufacturing a high voltage semiconductor device according to claim 6. 各ＦＬＲの前記導電部が、他のＦＬＲの導電部に対して絶縁されたパターンとして形成されることを特徴とする請求項６から請求項８のいずれかに記載の高耐圧半導体装置の製造方法。   9. The method for manufacturing a high voltage semiconductor device according to claim 6, wherein the conductive portion of each FLR is formed as a pattern insulated from the conductive portions of other FLRs. . 前記第２の工程が、
第２の導電型の不純物をイオン注入または拡散源を用いた拡散処理により第１の拡散層を形成する工程を有することを特徴とする請求項６から請求項９のいずれかに記載の高耐圧半導体装置の製造方法。
The second step includes
10. The high breakdown voltage according to claim 6, further comprising a step of forming a first diffusion layer by ion implantation of a second conductivity type impurity or diffusion treatment using a diffusion source. A method for manufacturing a semiconductor device.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008066473A (en) * 2006-09-06 2008-03-21 Toyota Motor Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008066473A (en) * 2006-09-06 2008-03-21 Toyota Motor Corp Semiconductor device

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