JP2007110353A - Communication apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a communication apparatus capable of preventing malfunction and suppressing the occurrence of noises in communication. <P>SOLUTION: The communication apparatus includes a DC voltage generating means for generating a voltage where Va is larger than Vcc, a switch means for closing or opening between the DC voltage generating means and the power line, and the switch means which is turned on/off by control from a device 1. A detection circuit consisting of a resistor connected in series to a Zener diode whose breakdown voltage Vz means in the descending relation of Va, Vz and Vcc is inserted between GND and Vcc of the DC power line. The system also comprises a waveform shaping means that shapes changing of voltage of the resistor in the detection circuit into communication signals and outputs it to a device 2. Communication is performed from the device 1 to the device 2 by shaping and outputting as communication signals to the device 2, using the waveform shaping means and the detection circuit connected to the DC power line, under the control of on/off with the switch means by the device 1. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a communication apparatus using a DC voltage power line.

  Conventionally, in a power line communication apparatus, communication is performed by superimposing a tone burst signal on a power line.

Alternatively, a signal obtained by modulating a communication signal is superimposed and demodulated on the receiving side for transmission / reception.
Japanese Patent Laid-Open No. 11-127092 (page 6, FIG. 1) JP-A-10-065799 (page 14, FIG. 1, FIG. 2)

  However, the prior art has the following problems.

  There are many configurations for fulfilling the function, which may increase the cost.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a communication apparatus that can prevent malfunction in communication and suppress noise.

In order to achieve the above object, the present invention provides a communication apparatus that performs communication via a DC power line that supplies Vcc and GND as DC power supplies to both the device 1 and the device 2,
DC voltage generating means for generating a voltage Va>Vcc;
Switch means for connecting or opening the DC voltage generating means and the power line;
The switch means controlled on / off by the device 1;
In the power line, a detection circuit composed of a resistor connected in series with a Zener diode having a breakdown voltage Vz in a relationship of Va> Vz ≧ Vcc is inserted between the DC power line Vcc and GND, and the detection Waveform shaping means for shaping and outputting a change in voltage of the resistance of the circuit to the device 2 as a communication signal, and the waveform of the detection circuit connected to the DC power line by the on / off control of the switch means performed by the device 1 Communication from the device 1 to the device 2 is performed by shaping and outputting as a communication signal to the device 2 from the shaping means.

  According to the present invention, it is possible to communicate with the power line without increasing the dedicated communication signal line from the device 1 to the device 2. Therefore, a thick power source can be used for cost reduction by reducing the number of wires and for communication on the board. Since the communication signal is superimposed at a low frequency using this substrate pattern, it is possible to prevent malfunction and noise from occurring in communication.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

  The block circuit diagram shown in FIG. 1 is an explanatory diagram of a block circuit for carrying out the present invention. The DC power line Vcc is a power line to which a DC voltage supplied to the device 1 and the device 2 is applied. In FIG. 1, the DC power line Vcc is indicated by a bold line.

  This DC power line Vcc uses a transistor TR1 (hereinafter referred to as a switching means) which is a switching means, and a voltage Va of the voltage generation circuit, Va> Vcc, is connected to the DC power line Vcc.

  The device 1 controls this switching means. The device 1 is a CPU in the present embodiment, and has a built-in ROM for storing programs and data, a RAM for writing and reading calculation results, and the like. The device 1 stores a program and data for performing communication according to the present invention in the ROM. Similarly to the device 1, the device 2 is composed of a CPU.

  A Zener diode ZD and a resistor R4 are connected in series between the DC power line Vcc and GND. This part is a voltage detection circuit. The breakdown voltage Vz of the Zener diode ZD used in the voltage detection circuit is set such that Va> Vz ≧ Vcc. Therefore, when the switch means is not turned on, the voltage of the DC power line Vcc is kept at Vcc.

  In order for the device 1 to control the switching means, the transistor TR2 is turned on / off by outputting an on / off control signal via the resistor R3. Since the transistor TR2 performs on // off in accordance with the on // off control signal, the switch means which is the transistor TR1 is turned on / off through the resistors R1 and R2. As a result, the Va voltage is applied to the DC power line Vcc according to the on / off control signal.

  As a result of the application of Va, since the voltage exceeds the breakdown voltage Vz of the Zener diode of the voltage detection circuit, a current flows through the Zener diode ZD and the resistor R4. The voltage flowing through R4 is detected and converted into a pulse signal by the waveform forming means. The pulse signal that has been shaped and output is connected to the device 2 as an input signal, converted from information 1 and 0 of the pulse to communication information, and the device 2 performs control according to the communication information. These are the objects of the present invention and the whole picture. Hereinafter, the circuit configuration of the embodiment of the waveform shaping means will be described with reference to FIG.

  FIG. 2 is a circuit configuration example of an embodiment of the waveform shaping means. Q1 is a comparator that outputs “H” at the logic level when the voltage at the plus terminal is higher than the potential at the minus terminal, and outputs the “L” level when the potential is the same potential (GND potential in this case). Q1 is a circuit for outputting an “H” level signal only when a current flows through the resistor R4. Q2 and Q3 are circuits using a Schmitt buffer shaped so as to eliminate noise. is there.

  Q4 and Q5 are D flip-flops. VR represents a signal of a voltage generated by the resistor R4 (which is connected to the anode side of ZD). The CLK2 signal is a clock signal output from the device 2, and is a signal that is an integral multiple of the frequency at which the device 1 performs the on / off control signal (twice in this embodiment). The CLK1 signal is a clock signal obtained by multiplying the CLK2 signal by 1 / integer (in this embodiment, divided by 2), that is, a clock signal having the same frequency as the on / off control signal output from the device 1.

  The RESET signal is a reset signal for the devices 1 and 2, and when the communication device is turned on, the "L" level is maintained for the time specified by the devices 1 and 2 after the power is turned on after the power is turned on. This signal is used to perform a hard reset operation when the devices 1 and 2 are powered on. Usually, voltage monitoring is performed using a reset IC or the like, and a reset signal is output.

  FIG. 3 is a timing chart showing the state of signal waveform shaping performed by the circuit of FIG. FIG. 3 shows a timing chart when 8-bit “01” HEX is communicated. Hereinafter, a description will be given with reference to FIGS. 2 and 3.

  In this embodiment, as a signal for starting communication, “H”, that is, “1” is detected twice, 8 bits of transmission data is sent, and finally, “L”, that is, “0” is sent as a stop bit. It is a specification to send 11 bits by communication.

  In other words, the data can be expressed in the form of a binary number such as 11XXXXXXXXX0. The first 11 is a start bit indicating the start of communication, the eight X portions are “XX” HEX portions serving as communication data, and 0 indicates a stop bit. FIG. 3 is a timing chart in the case of transmitting “01” HEX.

  When the switch means of FIG. 1 is turned on by the on / off control signal, the voltage of the DC power line Vcc exceeds Vcc, so that a current flows from the Zener diode ZD to the resistor R4. At this time, the voltage generated by the resistor R4 (which is connected to the anode side of ZD) is connected to the comparator Q1 (hereinafter referred to as Q1) as VR in FIG. While current flows through R4 in FIG. 1, Q1 in FIG. 2 outputs a logic level “H” state. A signal obtained by shaping the output of Q1 by the inverters Q2 and Q3 with the Schmitt function is shown as S1 in the timing chart of FIG. The S1 signal is input to the D terminal of a D flip-flop Q4 (hereinafter referred to as Q4).

  In addition, since the Q4, D flip-flop Q5 (hereinafter referred to as Q5) and D flip-flop Q6 (hereinafter referred to as Q6) are always initialized by the RESET signal, the logic level at the output Q terminal is initially set to “L”. Is output. Therefore, "H" is output from the Q terminal of Q4 at the rising edge to the clock terminal to Q4. That is, Q4 is a portion where the rising edge of the S1 signal is detected at the frequency of CLK2, and the output of Q4 is changed each time it is detected.

  For example, at the rising edge of S1 in FIG. 3, S2 becomes "H" as indicated by the arrow A, and at the rising edge of arrow A, the signal of S2 falls and becomes "L".

  Next, in Q5, the S22 signal is generated at CLK2 from the level of the S2 signal. This S22 signal is input to the device 2. In the device 2, the state of the S22 signal is detected at the rising edge of the CLK1 signal obtained by dividing CLK2. In other words, the level of the S22 signal is confirmed at each rising edge marked with the arrow symbol of “S” to “N” in FIG. In this case, since the S and S portions are at the “H” level, since “1” has continued twice in the device 2, it is detected that the start bit has been input, and the following 8 Receive bits. The level of the S22 signal is detected and input at the timing of the arrow head. Then, it is understood that “0000001”, that is, “01” HEX data is received. The sending order is such that transmission / reception is performed from the MSB to the last LSB. Finally, “0”, which is a stop bit, is detected by the device 2 at the timing indicated by an arrow, thereby detecting the completion of reception.

  Therefore, by outputting the on / off signal of the device 1 on the pulse with the period of CLK1, the voltage of Va is superimposed on the DC power line Vcc in a pulsed manner, the change in voltage is detected by the detection circuit, and the waveform shaping is performed. By generating a pulse signal by the means, the device 2 can receive the signal as a communication signal.

  The pattern for sending data from “00” HEX to “FF” HEX is stored on the ROM of the device 1, and the device 1 selects the communication information corresponding to the content commanded from the ROM, and the pattern. The on / off control signal is output according to

  The device 2 detects whether or not a start bit has been sent by checking the S22 signal in synchronization with CLK1, and if it can be detected, synchronizes the 8-bit received data with CLK1 and sends the S22 signal. Receive data from. Further, the stop bit “0” is confirmed, and the device 2 performs control according to the received 8-bit content. FIG. 4 shows a general flow performed by the device 1. FIG. 5 shows a general flow performed by the device 2.

  FIG. 4 is a general flow regarding on / off control, which is a timer routine performed at a cycle of CLK1.

  First, in step S1, it is determined whether on / off control is being performed (transmitting). If transmission is in progress, in step S2, an on / off control signal output at that timing is output from the pattern stored in the ROM. If it is to be turned on, a signal on the pulse is output, and the voltage Va is superimposed on the power line Vcc. Otherwise, it remains off and the voltage of Vcc is maintained. In step S3, it is determined whether or not the output is a stop bit. If it is a stop bit process, in step S4, the transmission flag is reset to prepare for the next transmission. Then, this control is exited. If not finished in S3, the process proceeds to the next control. If the transmission is not in progress at step S1, the process goes to step 5. In step S5, it is checked whether or not transmission data is ready to be sent. If it is not ready, this control is exited and the next control is started. If preparation is complete, a transmission flag indicating that transmission is in progress is set, and the process proceeds to step S2. Subsequent processing is the same as described above, and a description thereof will be omitted.

  FIG. 5 shows reception control performed by the device 2. Similar to FIG. 4, this is a timer routine performed at a cycle of CLK1.

  First, in S11, if the level of the S22 signal is continuously detected twice as the "H" level, it is determined that a start bit has been transmitted, and the process proceeds to step S12. Step S12 is a subroutine for storing 8-bit data. If the level of the S22 signal is “H” level, it is converted to “1”, and if it is “L” level, it is converted to “0”, shifted and stored in the RAM as 8-bit data in order. It is confirmed whether the 9th bit is the “L” level which is a stop bit. If it is not “L” level, it is determined that the received data is invalid, and the received data is discarded in step S15. If the stop bit is at “L” level, it is valid, so the process proceeds to the next control, and the device 2 performs control according to the received data. In this way, the device 2 performs control according to the 8-bit received data communicated from the device 1 to the device 2.

It is a block circuit diagram of the communication part which is this invention. It is a block diagram of the circuit of a waveform shaping means. It is a timing chart when performing power line communication which is the present invention. It is the general flow regarding on / off control. It is a control flow of reception performed by the device.

Explanation of symbols

Q1 comparator Q4, Q5 D flip-flop R3, R4 resistance TR1, TR2 transistor Va voltage generation circuit voltage Vcc DC power line Vz breakdown voltage ZD Zener diode

Claims (1)

In a communication apparatus that performs communication via a DC power line that supplies Vcc and GND as DC power sources to both the device 1 and the device 2,
DC voltage generating means for generating a voltage Va>Vcc;
Switch means for connecting or opening the DC voltage generating means and the power line;
The switch means controlled on / off by the device 1;
In the power line, a detection circuit composed of a resistor connected in series with a Zener diode having a breakdown voltage Vz in a relationship of Va> Vz ≧ Vcc is inserted between the DC power line Vcc and GND, and the detection Waveform shaping means for shaping and outputting a change in voltage of the resistance of the circuit to the device 2 as a communication signal, and the waveform of the detection circuit connected to the DC power line by the on / off control of the switch means performed by the device 1 A communication apparatus that performs communication from the device 1 to the device 2 by shaping and outputting as a communication signal to the device 2 from the shaping means.

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