JP2007110071A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device and the semiconductor device which can improve the film quality of an insulating film. <P>SOLUTION: The method of manufacturing the semiconductor device 100 having the gate of a MOS (Metal-Oxide Semiconductor) structure has: a vapor phase oxidation step of forming a gas phase oxide film 31 on a semiconductor substrate 10 by a vapor growth; and an additional thermal oxidation step of thermally oxidizing the formation of the gas phase oxide film 31 after the vapor phase oxidation step, and forming a thermal oxidation film 32 between a gas phase oxide film 30 and the semiconductor substrate 10. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly to a semiconductor device having a MOS structure gate, a semiconductor device having a capacitor, and a semiconductor device manufacturing method and a semiconductor device having a nonvolatile memory.

  Conventionally, in a semiconductor device having, for example, a MOS structure trench gate, a method of stacking a thermal oxide film and a CVD oxide film to form a gate insulating film is disclosed in order to secure a gate breakdown voltage (for example, Patent Document 1). , 2).

  In Patent Document 1, after forming the trench, a thermal oxide film (first insulating film) is formed by thermal oxidation on the inner surface of the trench and the uppermost portion of the impurity region as a gate insulating film, and on the surface of the thermal oxide film. A CVD oxide film (second insulating film) is formed by vapor deposition (CVD). Then, a gate electrode is formed through the gate insulating film.

In Patent Document 2, after forming the CVD oxide film shown in Patent Document 1, the gate insulating film including both oxide films is annealed to form a gate electrode.
JP 7-245400 A JP 2001-85686 A

  However, according to the manufacturing method disclosed in Patent Document 1, the CVD oxide film is not densified in the formed semiconductor device, and its composition is shifted from the stoichiometric state (chemical stoichiometric state). . That is, dangling bonds (unbonded hands) that serve as carrier traps exist in the film. As a result, the film quality (breakdown voltage, lifetime, etc.) of the gate insulating film is lowered.

  According to the manufacturing method disclosed in Patent Document 2, annealing is performed after forming the gate insulating film, so that the CVD oxide film is densified. However, there is a risk of densification with dangling bonds (unbonded hands) remaining in the CVD oxide film. Further, at least two heating steps of thermal oxide film formation and annealing are required.

  In view of the above problems, an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device capable of improving the quality of an insulating film.

  In order to achieve the above object, the invention described in claims 1 to 32 relates to a method of manufacturing a semiconductor device. In the first aspect of the present invention, a vapor phase oxidation step for forming a vapor phase oxide film on a semiconductor substrate by a vapor phase growth method, and after the vapor phase oxidation step, a formation site of the vapor phase oxide film is thermally oxidized. An additional thermal oxidation step is provided.

According to the present invention, thermal oxidation is performed after the formation of the vapor phase oxide film. Therefore, oxygen or water vapor in the thermal oxidation atmosphere diffuses to the interface between silicon (Si) and the gas phase oxide film (SiO ₂ ) constituting the semiconductor substrate via the gas phase oxide film before being densified, An oxide film can be additionally formed by reacting with Si. Thereby, the Si—SiO ₂ interface can be moved to the Si side rather than the time of forming the vapor-phase oxide film, and the insulating film can have a predetermined film thickness. Further, the interface state density is set to the level of an oxide film formed by thermal oxidation, and good interface characteristics can be obtained. Further, in parallel with the above, oxygen or water vapor in the thermal oxidation atmosphere reacts with dangling bonds (unbonded hands) in the gas phase oxide film, and the gas phase oxide film is in a stoichiometric state (chemically). Stoichiometric state). That is, traps in the vapor phase oxide film can be reduced. Therefore, the film quality of the insulating film can be improved.

  In addition, by making thermal oxidation a post-process of vapor phase oxidation, the vapor phase oxide film is brought into a stoichiometric state and the interface characteristics are improved. That is, the manufacturing process is simplified.

  Since an SOI structure semiconductor substrate has higher stress than single crystal silicon, crystal defects are likely to occur. In addition, since it has a buried oxide film, it is difficult to form an IG (Intrinsic Gettering) layer (the effect of gettering on the support substrate side is blocked by the buried oxide film), and impurities that reduce the breakdown voltage of crystal defects and gate insulating films ( For example, Fe or the like) remains in the substrate as it is. Therefore, when the crystal defects and impurities are taken into the oxide film formed by thermal oxidation, the defect density of the insulating film including the oxide film increases. That is, the quality of the insulating film is likely to deteriorate. However, according to the above-described invention, the film quality of the insulating film can be improved even when the SOI structure semiconductor substrate having the buried oxide film is used as the semiconductor substrate.

  According to a third aspect of the present invention, in the vapor phase oxidation step, a vapor phase oxide film may be formed on a portion of the semiconductor substrate including a conductive type region having boron or antimony as an impurity. In the conductive type region having boron or antimony as an impurity, the atomic radius of silicon (117 pm) constituting the semiconductor substrate is greatly different from the atomic radius of boron (80 pm) and the atomic radius of antimony (141 pm). Is likely to occur. That is, the quality of the insulating film is likely to deteriorate. However, according to the above-described invention, the quality of the insulating film can be improved even in such a portion. The conductive type region is not limited to the above example.

  The invention according to any one of claims 1 to 3 is suitable for forming a gate insulating film, for example, in a semiconductor device having a MOS structure gate (that is, including a MOS transistor or IGBT). It is.

  In addition, as described in claim 5, in the additional thermal oxidation step, the oxide film thickness additionally formed by thermal oxidation is preferably in the range of 1 nm to 12 nm. When the thickness is 1 nm or more, the interface state density of the additionally formed oxide film and the insulating film formed of the vapor phase oxide film can be made substantially equal to that of the oxide film formed by thermal oxidation. If the thickness is 12 nm or less, the B mode defect rate of the oxide film can be suppressed to 5% or less. That is, if it is in the said range, the film quality of a more preferable insulating film can be ensured.

  According to a sixth aspect of the present invention, a pre-process of the vapor phase oxidation step includes a trench formation step of forming a trench in the semiconductor substrate, and in the vapor phase oxidation step, a vapor phase oxide film is formed on the surface of the trench. good. Specifically, a trench for a gate electrode can be applied as described in claim 7. Thus, the film quality of the gate insulating film can be improved and the required quality can be ensured. The trench is not limited to the trench constituting the gate electrode. In addition to the above, for example, when applied to a trench constituting a trench isolation region, the film quality of the isolation insulating film formed in the trench can be improved.

  When the trench is formed, the opening corner of the trench is angular. If an insulating film is formed on the trench surface in this state, the film thickness of the insulating film at the corners becomes thin, and there is a risk that electric field concentration may occur. Therefore, as described in claim 8, in the additional thermal oxidation step, it is preferable to make the radius of curvature of at least the opening corner of the trench larger than that at the time of trench formation together with thermal oxidation. By performing thermal oxidation at a temperature at which viscous flow occurs (for example, 1000 ° C. or higher), in addition to the effect of the invention of claim 1, at least the radius of curvature of the opening corner is made larger (rounded). A gentle shape). If comprised in this way, it is more effective with respect to electric field concentration suppression. Further, since the curvature of the opening corner can be increased together with the thermal oxidation, the manufacturing process can be simplified. In addition, you may enlarge not only the opening corner but also the curvature radius of the bottom corner.

  Further, as described in claim 9, there may be provided a bending step for increasing the radius of curvature of at least the opening corner of the trench larger than that at the time of trench formation between the trench forming step and the gas phase oxidation step. good. That is, a step of rounding corners of the trench may be provided before the vapor phase oxidation step.

  Specifically, the bending process may include a sacrificial oxidation process for forming a sacrificial oxide film on the trench surface by thermal oxidation and a removal process for removing the sacrificial oxide film as described in claim 10. good. Further, as described in claim 11, it may be configured to include a chamfering step of chamfering the opening corner by isotropic etching. In the case of chamfering, as described in claim 12, when the chamfering amount in the planar direction of the semiconductor substrate is 50 nm or more, the electric field strength of the insulating film at the opening corner portion with respect to the insulating film on the flat portion (substrate surface) is It can be 1.1 times or less. Therefore, it is possible to reduce electric field concentration (that is, improve film quality) at the opening corner.

  The invention according to any one of claims 1 to 3 is a semiconductor device having a capacitor, wherein a capacitor oxide film as a dielectric is interposed between a pair of electrodes. This is suitable for forming an oxide film. In this case, since the variation in the relative dielectric constant of the capacitor oxide film can be made equal to that of the thermal oxide film, it is possible to obtain a capacitor with a uniform capacitance while ensuring a withstand voltage.

  The pair of electrodes is composed of an upper electrode and a lower electrode, and the lower electrode forming the lower electrode, which is one electrode composed of hemispherical crystal grains, as a pre-process of the vapor phase oxidation process as described in claim 14 It is particularly effective for an apparatus including an electrode forming process and including an upper electrode forming process for forming an upper electrode as the other electrode as a subsequent process of the additional thermal oxidation process.

  When the lower electrode is made of hemispherical grains as described above, if the thermal oxidation is performed first, an oxide film having a sufficient thickness cannot be formed between the crystal grains. However, according to the above-described invention, an oxide film having a sufficient film thickness can be formed also between the crystal grains, so that a breakdown voltage can be ensured.

  Further, as described in claim 15, when the capacitor is a trench structure capacitor and includes a trench formation step of forming a capacitor trench in the semiconductor substrate as a pre-step of the vapor phase oxidation step, in the vapor phase oxidation step, A vapor phase oxide film may be formed on the surface of the trench. Thus, even a trench capacitor can be a capacitor having a uniform capacitance while ensuring a withstand voltage.

  In addition, since the effect of Claims 16-19 is the same as the effect of Claims 8-11, respectively, the description is abbreviate | omitted.

  The invention according to any one of claims 1 to 3 is the semiconductor device having a non-volatile memory including a two-layer gate electrode of a floating gate and a control gate, as defined in claim 20, wherein the floating gate and the control gate It is suitable for forming an inter-gate oxide film disposed between the two. In this case, by improving the film quality of the inter-gate oxide film while ensuring the withstand voltage, the Vt fluctuation caused by the trapping of charge during rewriting can be made comparable to that of the thermal oxide film.

  In addition, as described in claim 21, a floating gate forming step for forming a floating gate made of hemispherical crystal grains is provided as a pre-step of the gas phase oxidation step, and a control gate is provided as a post-step of the additional thermal oxidation step. This is particularly effective for a device provided with a control gate forming step for forming.

  Thus, even when the floating gate is made of hemispherical grains, an inter-gate oxide film having a sufficient thickness can be formed between the crystal grains. In addition, the intergranularity can be expanded by additional thermal oxidation. Therefore, carriers accumulated in the floating gate can be prevented from moving to adjacent crystal grains or control gates, that is, carrier retention characteristics can be improved (a change in the memory state over time can be suppressed).

  In addition, as described in claim 22, in the gas phase oxidation step, it is preferable that the film thickness of the gas phase oxide film is larger than the interval between adjacent crystal grains. Thereby, an oxide film can be reliably arranged between crystal grains.

  Next, the invention according to claim 23 is an oxide film forming step for forming an oxide film on a semiconductor substrate, and a region in which the nitrogen concentration continuously increases on the oxide film in a direction away from the interface with the oxide film. And a nitrogen-containing film forming step of forming a nitrogen-containing film containing

  In the case of a nitrogen-containing film, the dielectric constant can be made higher than that of the oxide film. Therefore, if the transistor characteristics are equivalent, the structure having a nitrogen-containing film can be made thicker than the single oxide film, so that the electric field strength (effective) in the film can be increased compared to the oxide film. Electric field) can be reduced. In addition, the nitrogen-containing film is formed so as to include a region where the nitrogen concentration continuously increases in a direction away from the interface with the oxide film. In other words, a nitrogen-containing film in which the nitrogen concentration continuously increases is formed on the oxide film so that the interface between the oxide film and the nitride film does not become discontinuous. In this case, for example, unlike the known ONO film, no discontinuous interface exists in the gate insulating film, so that carriers are not trapped in the film. Therefore, variation in threshold voltage can be prevented. Thus, according to the present invention, the quality of the insulating film can be improved.

Specifically, as described in claim 24, the CVD method is applied in the nitrogen-containing film forming step, and the gas composition is changed over time so that the nitrogen concentration continuously increases in a direction away from the interface with the oxide film. It is sufficient to change it. For example, in a mixed gas of silane (including silane-based compounds such as dichlorosilane) and N ₂ O, the partial pressure of N ₂ O is lowered over time, and instead, NH ₃ is introduced into the reaction system and the partial pressure is increased. Thus, a nitrogen-containing film in which the nitrogen concentration continuously increases can be formed on the oxide film so that the interface between the oxide film and the nitride film does not become discontinuous.

  In the inventions described in claims 25 to 30, in the inventions described in claims 6, 7, and 9 to 12, if the gas phase oxidation (film, process) is replaced with oxidation (film, film formation process), the effect is obtained. Since it is the same, the description is omitted.

  The invention described in claims 31 to 48 relates to a semiconductor device manufactured by the above manufacturing method, and the function and effect thereof are the same as those of the corresponding inventions described in claims 1 to 30 respectively. The description is omitted.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a cross-sectional view showing a schematic configuration of the semiconductor device according to the present embodiment. As shown in FIG. 1, a semiconductor device 100 according to this embodiment is a semiconductor device including a semiconductor substrate 10 including a vertical MOS transistor having a trench gate structure.

The semiconductor substrate 10 is an SOI (Silicon On Insulator) substrate with an insulating film embedded therein, and includes a supporting substrate 11 made of single crystal silicon (Si), an insulating film 12 made of silicon oxide film (SiO ₂ ), and an n−. The semiconductor layer 13 is of a type.

A vertical MOS transistor having a trench gate structure is configured as a P-channel transistor having, for example, a P conductivity type region as a source and a drain. In the P-channel transistor, a p-type diffusion region 14 which is a drain region is formed in the surface layer portion of the n − -type semiconductor layer 13, and a trench 15 is formed in the diffusion region 14. A gate electrode 16 is buried in the trench 15 via a gate insulating film (not shown in FIG. 1) formed on the surface. Further, an impurity is added by ion implantation or the like using the gate electrode 16 as a mask, and then thermally diffused to reach the trench sidewall, and an n-type diffusion region 17 (well region) is formed with a diffusion depth shallower than the trench 15. In the surface layer portion of the semiconductor layer 13, a p + type diffusion region 18 as a source region is formed. In FIG. 1, reference numeral 19 denotes an interlayer insulating film, and reference numeral 20 denotes a source electrode connected to the diffusion region 18 which is a source region via the interlayer insulating film 19. Reference numeral 21 denotes a trench isolation region reaching the insulating film 12 on the main surface side of the insulating film 12, and reference numeral 22 denotes a LOCOS oxide film. A drain electrode (not shown) is also connected to the diffusion region 14 which is a drain region.

Here, the gate insulating film, which is a characteristic part of the semiconductor device 100 according to the present embodiment, will be described with reference to FIG. FIG. 2 is an enlarged view around the trench. As shown in FIG. 2, a gate insulating film 30 is formed on the surface of the trench 15 and the surface of the semiconductor layer 13 corresponding to the formation site of the gate electrode 16.

  The gate insulating film 30 includes a CVD oxide film 31 formed as a vapor-phase oxide film on the surface of the trench 15 and the surface of the semiconductor layer 13, and the CVD oxide film 31 and the surfaces of the CVD oxide film 31 and the trench 15 after the formation of the CVD oxide film 31. The thermal oxide film 32 is additionally formed between the surface of the semiconductor layer 13. As described above, the semiconductor device 100 according to this embodiment is characterized in that the CVD oxide film 31 is formed first, and then the thermal oxide film 32 is additionally formed by thermal oxidation.

  Next, a method for manufacturing the semiconductor device 100 configured as described above will be described with reference to FIGS. 1, 2, 3 </ b> A to 3 </ b> E, and FIGS. 4A and 4B. FIGS. 3A to 3E are cross-sectional views for explaining the formation process of the gate insulating film 30, wherein FIG. 3A is a trench formation, FIG. 3B is a sacrificial oxide film formation, and FIG. (D) is CVD oxide film formation, (e) is a figure which shows thermal oxide film formation. 4A and 4B are cross-sectional views for each process after the formation of the gate insulating film 30, wherein FIG. 4A shows a gate electrode forming process and FIG. 4B shows a diffusion region forming process. Note that the manufacturing of the semiconductor device 100 according to the present embodiment is characterized by the formation of the gate insulating film 30, and other than that, since a known manufacturing technique is used, the formation process of the gate insulating film 30 will be described mainly. To do.

  First, an SOI structure semiconductor substrate 10 having an n − type semiconductor layer 13 is prepared, and a p-type diffusion region 14 serving as a drain region is formed in a P-channel transistor formation region of the semiconductor layer 13. Further, a trench isolation region 21 and a LOCOS oxide film 22 reaching the insulating film 12 are formed as element isolation regions for isolating each element (see FIG. 1).

  Next, in order to form the gate electrode 16 having a trench gate structure, as shown in FIG. 3A, for example, an oxide film formed on the surface of the semiconductor layer 13 is patterned to form a mask (not shown) and dry. A trench 15 having a predetermined depth is formed in the p-type diffusion region 14 by etching.

  After the trench 15 is formed, the shape of the opening corner (shoulder) and the bottom corner of the trench 15 is square as shown in FIG. Therefore, as shown in FIG. 3B, thermal oxidation is performed at a temperature at which viscous flow occurs (for example, 1000 ° C. or more), and a sacrificial oxide film 40 is formed on the surface of the trench 15. In this embodiment, thermal oxidation was performed at 1150 ° C., and a sacrificial oxide film 40 having a thickness of 100 nm was formed in the flat portion. Then, as shown in FIG. 3C, by removing the sacrificial oxide film 40 (for example, hydrofluoric acid treatment), the curvature radii of the opening corners and the bottom corners are made larger (rounded and loosely rounded). Shape). If comprised in this way, it is more effective with respect to electric field concentration suppression. The steps shown in FIGS. 3B and 3C correspond to the enlargement step shown in the claims.

  After the bending process, a CVD oxide film 31 is formed on the surface of the trench 15 by using a CVD method (LPCVD method in this embodiment) as shown in FIG. At this time, the composition of the CVD oxide film 31 has deviated from the stoichiometric state (chemical stoichiometric state). That is, dangling bonds (unbonded hands) that serve as carrier traps exist in the film. Further, the CVD oxide film 31 is not densified, and the interface state density is larger than that of the oxide film formed by thermal oxidation.

  After the CVD oxide film 31 is formed, thermal oxidation is performed, and a thermal oxide film 32 is additionally formed between the previously formed CVD oxide film 31 and the surface of the trench 15 as shown in FIG. In the present embodiment, additional thermal oxidation was performed at 850 ° C. in a mixed gas of oxygen and water vapor. Thus, the gate insulating film 30 is formed.

  After forming the gate insulating film 30, as shown in FIG. 4A, the gate electrode material is embedded in the trench 15 via the gate insulating film 30 (not shown) to form the gate electrode 16. Then, an impurity is added by ion implantation or the like using the formed gate electrode 16 as a mask, and thermal diffusion is performed to reach the trench side wall, and an n-type diffusion region 17 (well region) having a diffusion depth shallower than the trench 15. And a p + -type diffusion region 18 as a source region is formed in the surface layer portion of the semiconductor layer 13. After forming the diffusion regions 17 and 18, the interlayer insulating film 19, the source electrode 220, the drain electrode (not shown), wirings, and the like are formed, and the semiconductor device 100 shown in FIG. 1 is manufactured.

Thus, in this embodiment, the CVD oxide film 31 is formed first, and then the thermal oxide film 32 is formed by thermal oxidation. In the case of the CVD method, the CVD oxide film 31 is formed on the substrate surface by deposition, so that it is not affected by crystal defects in the p-type diffusion region 14. Therefore, the defect density in the film can be reduced. In the present embodiment, since the CVD oxide film 31 is formed before the thermal oxide film 32, the film quality can be improved. Further, by the thermal oxidation after the CVD oxide film 31 is formed, the diffusion region 14 is configured through the CVD oxide film 31 before oxygen (O ₂ ) or water vapor (H ₂ 0) in the thermal oxidation atmosphere is densified. The thermal oxide film 32 can be additionally formed by diffusing to the interface between silicon (Si) and the CVD oxide film 31 and reacting with Si. As a result, the Si—SiO ₂ interface can be moved to the Si side rather than the CVD oxide film formation, and the gate insulating film 30 can have a predetermined thickness. Further, the interface state density is set to the level of an oxide film formed by thermal oxidation, and good interface characteristics can be obtained. Furthermore, in parallel with the above, oxygen or water vapor in the thermal oxidation atmosphere reacts with dangling bonds (unbonded hands) in the CVD oxide film 31 to cause the CVD oxide film 31 to be stoichiometric (chemically). Stoichiometric state). That is, traps in the CVD oxide film 31 can be reduced. Therefore, the film quality of the gate insulating film 30 can be further improved.

  When confirmed by TEM, the film thickness of the opening corner of the gate insulating film 30 was approximately 33 nm, and the film thickness of the flat portion on the surface of the semiconductor layer 13 was approximately 30 nm. This is because the amount of oxygen supplied to the opening corner of the trench 15 is larger than that of the flat portion during the additional thermal oxidation. Thus, in the gate insulating film 30, the film thickness of the opening corner is thicker than that of the flat portion, so that electric field concentration occurring in the opening corner can be suppressed. In particular, when the surface of the semiconductor layer 13 which is a flat portion and the trench sidewall are the (100) plane orientation, the (100) plane has a slow oxidation rate, and thus the film thickness of the opening corner portion different from the (100) plane is flat. It can be thicker than the part.

  In the semiconductor device 100 having the above configuration, the present inventor confirmed the effect. FIG. 5 is a diagram showing the relationship between the distance from the trench isolation region and the crystal defects. FIG. 6 is a diagram showing a Weibull distribution of the breakdown voltage of the gate insulating film 30 in the semiconductor device 100 according to the present embodiment. In addition, as a comparative example, the result in the case of being constituted only by thermal oxidation is also shown.

  In the present embodiment, the atomic radius (80 pm) of boron introduced into the p-type diffusion region 14 that is the drain region is significantly different from the atomic radius (117 pm) of silicon constituting the semiconductor layer 13. 14 is distorted. In addition, a trench 15 is formed in the diffusion region 14, but damage (defect, stress) caused by etching or the like occurs in the vicinity of the trench 15, so that a crystal defect is likely to occur due to interaction with the strain. Further, since damage (defects, stress) caused by etching or the like is also present in the trench isolation region 21, if the trench isolation region 21 exists in the vicinity of the diffusion region 14, crystal defects are caused by interaction as shown in FIG. Is likely to occur. In the present embodiment, an SOI structure semiconductor substrate is applied as the semiconductor substrate 10. Since the semiconductor substrate 10 having an SOI structure has a higher stress than single crystal silicon, crystal defects are likely to occur. In addition, since the insulating film 12 is included, an IG (Intrinsic Gettering) layer is difficult to form (the effect of gettering on the support substrate 11 side is blocked by the insulating film 12), and crystal breakdown and the breakdown voltage of the gate insulating film 30 are reduced. Impurities (for example, metal atoms such as Fe) remain in the substrate 10 (semiconductor layer 13) as they are.

  In such a configuration, when an oxide film is first formed by a thermal oxidation method, the defect density of the oxide film increases and the interface state also increases. That is, as shown in FIG. 6, many B-mode defects due to crystal quality occur, and the film quality (breakdown voltage) of the gate insulating film 30 decreases. On the other hand, according to the configuration and the manufacturing method of the semiconductor device 100 shown in the present embodiment, even if the configuration is such that crystal defects are likely to occur and the film quality of the gate insulating film 30 is difficult to ensure, the configuration shown in FIG. Thus, it was shown that the B mode failure can be suppressed and the film quality of the gate insulating film 30 can be improved.

  Next, the present inventor confirmed the relationship between the additional oxidation due to thermal oxidation and the occurrence rate of B-mode defects. The result is shown in FIG. As shown in FIG. 7, it is clear that the occurrence rate of B-mode defects decreases as the thickness of the thermal oxide film 32 formed by the additional oxidation decreases. For example, in order to realize a B mode defect occurrence rate of 5% or less, the film thickness is preferably 12 nm or less from FIG.

  In addition, the inventor measured the interface state density of the gate insulating film 30 in the semiconductor device 100 according to the present embodiment. The result is shown in FIG. In FIG. 8, together with the result of the configuration (on the p-type region) shown in the present embodiment in which the trench 15 is formed in the p-type diffusion region 14, a configuration in which the trench 15 is formed on the n-type region as a reference example. Is also shown. As shown in FIG. 8, when the thickness of the thermal oxide film 32 by additional oxidation is 1 nm or more, it has been clarified that the interface state density is substantially equal to the thermal oxide film formed only by thermal oxidation. .

  Therefore, from the results shown in FIGS. 7 and 8, in the method for manufacturing the semiconductor device 100 according to the present embodiment, the thickness of the thermal oxide film 32 additionally formed in the additional thermal oxidation step is within the range of 1 nm to 12 nm. Then, it is clear that more preferable film quality of the insulating film can be ensured. In the present embodiment, the thickness of the additionally formed thermal oxide film 32 is 12 nm.

  Further, the inventor measured the film thickness of the gate insulating film 30 in the semiconductor device 100 according to the present embodiment. The result is shown in FIG. FIG. 9 also shows the oxide film thickness formed only by CVD and the oxide film thickness formed only by thermal oxidation. As shown in FIG. 9, according to the manufacturing method according to the present embodiment, the film thickness variation of the gate insulating film 30 is reduced. This is because the CVD oxide film 31 has a composition deviating from a stoichiometric state (chemical stoichiometric state) and is non-uniform in the film, but the stoichiometric state is obtained by additional thermal oxidation. This shows that the film is homogeneous in the film. That is, also from this result, it is apparent that the film quality of the gate insulating film 30 can be improved according to the semiconductor device 100 and the manufacturing method thereof according to the present embodiment.

  In the present embodiment, as shown in FIG. 3, after the trench 15 is formed, the sacrificial oxide film 40 is formed by thermal oxidation in order to increase the radius of curvature of the opening corner (and the bottom corner) of the trench 15. Although an example including a magnifying process for forming and removing has been shown, the magnifying process may be omitted. That is, at least after the trench formation, the CVD oxide film 31 is first formed, and then the thermal oxide film 32 is formed by thermal oxidation. However, when the bend is increased, the gate insulating film 30 can be thickened, which is effective in suppressing electric field concentration at the corners.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG. 10A and 10B are cross-sectional views showing the formation process of the gate insulating film 30 in the semiconductor device 100 according to the present embodiment, where FIG. 10A is a trench formation, FIG. 10B is a CVD oxide film formation, and FIG. It is a figure which shows oxide film formation.

  Since the semiconductor device 100 and the manufacturing method thereof in the second embodiment are often in common with those according to the first embodiment, detailed description of the common parts will be omitted, and different parts will be described mainly.

  The present embodiment is characterized in that after the CVD oxide film 31 is formed, a process of additionally forming a thermal oxide film 32 by thermal oxidation is used, and in this process, the trench corner is also enlarged. To do.

  Specifically, first, as in the first embodiment, the trench 15 is formed as shown in FIG. Then, as shown in FIG. 10B, a CVD oxide film 31 is formed on the surface of the formed trench 15 and the surface of the diffusion region 14. After the CVD oxide film 31 is formed, thermal oxidation is performed, and as shown in FIG. 10C, a thermal oxide film 32 is formed between the previously formed CVD oxide film 31 and the surface of the trench 15 and the surface of the diffusion region 14. Additional formation.

  At this time, in this embodiment, additional thermal oxidation was performed at 1150 ° C. in a mixed gas of oxygen and water vapor. In this way, by performing thermal oxidation at a temperature at which viscous flow occurs (for example, 1000 ° C. or more), in addition to the effect shown in the first embodiment, at least the radius of curvature of the opening corner is made larger. (With a rounded and gentle shape). If comprised in this way, it is more effective with respect to electric field concentration suppression. Further, since the curvature of the opening corner can be increased together with the thermal oxidation, the manufacturing process can be simplified. In addition, not only the opening corner but also the radius of curvature of the bottom corner can be increased.

(Third embodiment)
Next, a third embodiment of the present invention will be described based on FIG. 11 and FIG. FIG. 11 is a schematic cross-sectional view showing a part of the process of forming the gate insulating film 30 in the semiconductor device 100 according to the present embodiment. 12A and 12B are diagrams illustrating the effect of chamfering, in which FIG. 12A illustrates the chamfering amount X, and FIG. 12B illustrates the relationship between the chamfering amount X and the electric field strength ratio (opening corner / flat portion). FIG.

  Since the semiconductor device 100 and the manufacturing method thereof in the third embodiment are often in common with those of the first embodiment, detailed description of the common parts will be omitted, and different parts will be described mainly.

  In the present embodiment, as shown in FIG. 11, as a step of enlarging the radius of curvature of at least the opening corner of the trench larger than that at the time of forming the trench between the trench forming step and the CVD oxide film forming step. In addition, the structure includes a chamfering step of chamfering the opening corners by isotropic etching. Specifically, after the trench 15 is formed, isotropic etching is performed as shown in FIG. 11 with the trench opening corner exposed, and the angular opening corner is chamfered. Then, after the chamfering, as shown in the first embodiment, the sacrificial oxide film 40 is formed and removed by thermal oxidation to form the CVD oxide film 31, and then the thermal oxide film 32 is additionally formed by thermal oxidation. .

  As described above, according to the manufacturing method of the semiconductor device 100 according to the present embodiment, the opening corners can be chamfered by isotropic etching, and therefore the film thickness of the opening corners of the gate insulating film 30 of the semiconductor device 100. Thus, the electric field concentration can be suppressed. In particular, as shown in the present embodiment, when the thermal oxidation is performed at a temperature at which viscous flow occurs (for example, 1000 ° C. or more) after performing isotropic etching, the opening corners are rounded and have a gentle shape. It can be. However, only the chamfering process may be performed and the formation / removal process of the sacrificial oxide film 40 may be omitted.

  The inventors have confirmed that, as shown in FIGS. 12A and 12B, when the chamfering amount X in the planar direction of the semiconductor substrate 10 is 50 nm or more, the gate insulating film on the flat portion (substrate surface) The electric field strength of the gate insulating film 30 at the opening corner with respect to 30 can be made 1.1 times or less. Therefore, it is more effective in reducing the electric field concentration (that is, improving the film quality) at the opening corner. Note that the chamfering process may be applied to the configuration shown in the second embodiment. Specifically, chamfering may be performed after the trench 15 is formed, and then the CVD oxide film 31 and the thermal oxide film 32 by thermal oxidation may be sequentially formed.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described with reference to FIG. 13A and 13B are diagrams showing a schematic configuration of the gate insulating film 30 according to the present embodiment, in which FIG. 13A is an enlarged sectional view of a corner portion of the trench opening, and FIG. 13B is a composition in the AA ′ section of FIG. It is a schematic diagram which shows.

  Since the semiconductor device 100 and the manufacturing method thereof according to the fourth embodiment are often in common with those according to the first embodiment, detailed description of the common parts will be omitted, and different parts will be described mainly.

  The semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 shown in FIGS. 1 and 2 shown in the first embodiment in that the gate insulating film 30 is a thermal oxide film formed by thermal oxidation as shown in FIG. 33 and a nitrogen-containing film 34 containing nitrogen formed as an upper layer thereof. In the case of the nitrogen-containing film 34, the dielectric constant can be made higher than that of the oxide film. Therefore, if the transistor characteristics are equivalent, the thickness of the structure further including the nitrogen-containing film 34 can be increased as compared with the single oxide film layer. That is, since the electric field strength (effective electric field) in the film can be lowered as compared with the configuration in which the thermal oxide film 33 alone is the gate insulating film 30, the reliability can be improved.

  In the present embodiment, as shown in FIG. 13B, the nitrogen-containing film 34 is a region in which the nitrogen concentration continuously increases in a direction away from the interface with the thermal oxide film 33 (Th.OX). CVD SiON) is included. In other words, the nitrogen-containing film 34 in which the nitrogen concentration continuously increases is provided on the thermal oxide film 33 formed by thermal oxidation so that the interface between the oxide film and the nitride film does not become discontinuous. In this case, since a non-continuous interface does not exist in the gate insulating film 30 as in, for example, a known ONO film, carriers are not trapped in the film. Therefore, variation in threshold voltage can be prevented. Thus, according to the semiconductor device 100 according to the present embodiment, the film quality of the gate insulating film 30 can be improved.

As a manufacturing method of the gate insulating film 30 having the above-described configuration, as shown in the first embodiment, after forming the trench 15, the sacrificial oxide film 40 is formed by thermal oxidation and removed (FIG. 3A to FIG. 3). (See (c)). Thereafter, a thermal oxide film 33 is formed on the surface of the trench 15 whose corners are rounded by thermal oxidation and the surface of the diffusion region 14, and then a nitrogen-containing film 34 is formed by a CVD method. In this CVD method, the gas composition may be changed with time so that the nitrogen concentration continuously increases in the direction away from the interface with the thermal oxide film 33. For example, in a mixed gas of silane (for example, dichlorosilane) and N ₂ O, thermal oxidation is performed by lowering the partial pressure of N ₂ O with time and increasing the partial pressure while introducing NH ₃ into the reaction system instead. A nitrogen-containing film 34 in which the nitrogen concentration continuously increases can be formed on the thermal oxide film 33 formed by the above process so that the interface between the oxide film and the nitride film does not become discontinuous.

  In the present embodiment, an example in which the nitrogen-containing film 34 is stacked on the thermal oxide film 33 to form the gate insulating film 30 is shown. However, the nitrogen-containing film 34 may be laminated on the CVD oxide film. That is, the manufacturing method of the oxide film that is the lower layer of the nitrogen-containing film 34 is not particularly limited. Further, the oxide film may be a plurality of layers instead of a single layer. When the gate insulating film 30 is formed by stacking the nitrogen-containing film 34 shown in the present embodiment on the oxide film composed of the CVD oxide film 31 and the thermal oxide film 32 shown in the first to third embodiments, a manufacturing process will be described. However, the film quality of the gate insulating film 30 can be further improved.

  Further, in the present embodiment, an example in which the nitrogen-containing film 34 is formed by the CVD method after the thermal oxide film 33 is formed by thermal oxidation is shown. However, as shown in the first to third embodiments, the nitrogen-containing film 34 may be formed first by the CVD method, and then the thermal oxide film 33 may be formed by thermal oxidation. In this case, the nitrogen-containing film 34 can be densified and brought into a stoichiometric state.

  In each of the above embodiments, an example in which the film quality is improved in the gate insulating film 30 of the vertical MOS transistor having the trench gate structure has been described. However, the structure of the semiconductor device 100 is not limited to the configuration shown in the above embodiments. Any semiconductor device having a MOS structure gate may be used. That is, the gate insulating film 30 is not limited to the structure formed on the surface of the trench 15. Also, the element is not limited to a MOS transistor. Furthermore, the object of improving the film quality is not limited to the gate insulating film 30. Application examples other than the gate insulating film 30 will be described below.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described with reference to FIGS. FIG. 14 is a cross-sectional view showing a schematic configuration of the semiconductor device according to the present embodiment. 15A and 15B are cross-sectional views showing a manufacturing method of a main part of the semiconductor device, where FIG. 15A is a lower electrode forming step, FIG. 15B is a CVD oxide film forming step, and FIG. 15C is an additional thermal oxidation step. It is.

  Since the semiconductor device and the manufacturing method thereof according to the fifth embodiment are in common with those according to the first embodiment, detailed description of the common parts will be omitted below, and different parts will be described mainly.

The semiconductor device according to the present embodiment has a capacitor in which a capacitor oxide film as a dielectric is interposed between a pair of electrodes as an element, and the film quality of the capacitor oxide film is improved. Such a capacitor is applied not only as a capacitor itself but also as a part of an element such as a DRAM. As shown in FIG. 14, the semiconductor device 200 according to the present embodiment includes a trench capacitor in which the lower electrode 115 is made of hemispherical grains as an example of a capacitor. As in the first embodiment, the semiconductor substrate 110 is an SOI (Silicon On Insulator) substrate with an insulating film embedded therein, and is a support substrate 111 made of single crystal silicon (Si) and an insulation made of silicon oxide film (SiO ₂ ). A film 112 and a p-type semiconductor layer 113 are included. A trench 114 is formed in the semiconductor layer 113. A lower electrode 115 is formed on the surface of the trench 114, and an upper electrode 117 is embedded on the lower electrode 115 with respect to the trench 114 via a capacitor oxide film 116. That is, a capacitor is constituted by the upper electrode 117 and the lower electrode 115 forming a pair and the capacitor oxide film 116 disposed between the electrodes 115 and 117 formed on the trench 114.

  Here, the capacitor oxide film 116 includes a CVD oxide film 116a formed as a vapor-phase oxide film on the surface of the lower electrode 115, and the CVD oxide film 116a and the surface of the lower electrode 115 after the formation of the CVD oxide film 116a. And a thermal oxide film 116b additionally formed between them. As described above, the semiconductor device 200 according to the present embodiment is characterized in that the CVD oxide film 116a is formed first, and then the thermal oxide film 116b is additionally formed by thermal oxidation. Note that reference numeral 118 shown in FIG. 14 is a p + type diffusion region for preventing the depletion layer from spreading from the lower electrode 115 when the reverse potential is applied, that is, for preventing capacitance fluctuation.

  Next, a method for manufacturing the semiconductor device 200 configured as described above will be described. First, an SOI structure semiconductor substrate 110 having an n − type semiconductor layer 113 is prepared, and a trench 114 having a predetermined depth is formed in the capacitor formation region of the semiconductor layer 113 by dry etching. As described above, after the trench 114 is formed, the shape of the opening corner (shoulder) and the bottom corner of the trench 114 is both angular. Therefore, also in the present embodiment, by performing thermal oxidation at a temperature at which viscous flow occurs (for example, 1000 ° C. or more) to form a sacrificial oxide film and removing the sacrificial oxide film, the opening corner portion and the bottom surface corner are formed. The radius of curvature of the portion is made larger (a rounded, gentle shape).

  Next, an impurity is added by ion implantation or the like to form a p + -type diffusion region 118 on the surface of the trench 115. Then, as shown in FIG. 15A, a lower electrode 115 made of hemispherical grains is formed on the surface by a known manufacturing method (for example, an amorphous silicon layer doped with impurities). And then agglomerates and hemispheres by annealing. In this manner, when the lower electrode 115 made of hemispherical crystal grains is configured, the amount of accumulated charge is greatly improved, so that the capacity can be improved with the same cell area.

  After the formation of the lower electrode 115, as shown in FIG. 15B, a CVD oxide film 116a is formed on the surface of the lower electrode 115 by using a CVD method (LPCVD method in this embodiment). At this time, the composition of the CVD oxide film 116a is deviated from the stoichiometric state (chemical stoichiometric state), and dangling bonds (unbonded hands) serving as carrier traps exist in the film. Further, the CVD oxide film 116a is not densified, and the interface state density is larger than that of the oxide film formed by thermal oxidation.

  After the CVD oxide film 116a is formed, thermal oxidation is performed, and as shown in FIG. 15C, a thermal oxide film 116b is additionally formed between the previously formed CVD oxide film 116a and the surface of the lower electrode 115. In the present embodiment, additional thermal oxidation was performed at 850 ° C. in a mixed gas of oxygen and water vapor. Thus, the capacitor oxide film 116 is formed.

  After the formation of the capacitor oxide film 116, as shown in FIG. 14, the upper electrode 117 is formed by embedding an electrode material (for example, polysilicon doped with impurities) in the trench 114 via the capacitor oxide film 116. . Thereby, the semiconductor device 200 shown in FIG. 14 is manufactured.

As described above, in the capacitor oxide film 116 according to the present embodiment, the CVD oxide film 116a is first formed, and then the thermal oxide film 116b is formed by thermal oxidation, similarly to the gate insulating film 30 shown in the first embodiment. Form. Therefore, the defect density in the film can be reduced. Further, by the thermal oxidation after the formation of the CVD oxide film 116a, the lower electrode 115 is formed through the CVD oxide film 116a before oxygen (O ₂ ) or water vapor (H ₂ 0) in the thermal oxidation atmosphere is densified. The thermal oxide film 116b can be additionally formed by diffusing to the interface between the amorphous silicon to be formed and the CVD oxide film 116a and reacting with Si. Thereby, the Si—SiO ₂ interface can be moved to the Si side rather than the time of forming the CVD oxide film, and the capacitive oxide film 116 can have a predetermined thickness. Further, the interface state density is set to the level of an oxide film formed by thermal oxidation, and good interface characteristics can be obtained. Furthermore, in parallel with the above, oxygen or water vapor in the thermal oxidation atmosphere reacts with dangling bonds (unbonded hands) in the CVD oxide film 116a, causing the CVD oxide film 116a to be in a stoichiometric state (chemically). Stoichiometric state). That is, the traps in the CVD oxide film 116a can be reduced, the film quality of the capacitor oxide film 116 can be improved, and at the same time, the variation in relative dielectric constant of the capacitor oxide film 116 can be made equal to that of the thermal oxide film. Therefore, a capacitor with a uniform capacitance can be obtained.

  In addition to the effects described above, effects similar to or equivalent to the effects described in the first embodiment can be expected.

  In addition, as shown in the present embodiment, in the configuration in which the lower electrode 115 is formed of hemispherical crystal grains, if thermal oxidation is performed first, an oxide film having a sufficient thickness can be formed between the crystal grains. Can not. However, according to the manufacturing method described above, a 116 oxide film having a sufficient film thickness can be formed also between the crystal grains, so that a desired breakdown voltage can be ensured.

  Further, in the present embodiment, the lower capacitor 115 has been described by taking as an example a train capacitor having a configuration composed of hemispherical crystal grains. However, the configuration of the capacitor is not limited to the above example. For example, the same effect can be expected even when the lower electrode 115 has a configuration (for example, layered) that does not include hemispherical crystal grains. Further, the lower electrode 115 may be constituted by the semiconductor layer 113 (substrate). That is, a capacitor may be configured by the capacitor oxide film 116 disposed between the semiconductor layer 113 and the upper electrode 117. The capacitor is not limited to a trench structure, and a so-called planar structure capacitor can be applied to a capacitor oxide film disposed between electrodes.

  In this embodiment, the example in which the same configuration and manufacturing method as the gate insulating film 30 shown in the first embodiment is applied to the capacitor oxide film of the capacitor is shown. However, you may apply the structure and manufacturing method which were shown to 2nd Embodiment and 3rd Embodiment. Thereby, the effect similar to or equivalent to the effect described in each embodiment can be expected.

(Sixth embodiment)
Next, a sixth embodiment of the present invention will be described with reference to FIGS. FIG. 16 is a cross-sectional view showing a schematic configuration of the semiconductor device according to the present embodiment. 17A and 17B are cross-sectional views showing a manufacturing method of a main part of the semiconductor device, wherein FIG. 17A is a CVD oxide film forming step and FIG. 17B is an additional thermal oxidation step.

  Since the semiconductor device and the manufacturing method thereof according to the sixth embodiment are often in common with those according to the first embodiment, the detailed description of the common parts will be omitted below, and different parts will be mainly described.

  The semiconductor device according to the present embodiment has a nonvolatile memory including a two-layer gate electrode of a floating gate and a control gate as an element, and an inter-gate oxide film disposed between the floating gate and the control gate. The film quality is improved. Examples of such non-volatile memory include EPROM, EEPROM, flash memory, and the like. As shown in FIG. 16, in the semiconductor device 300 according to the present embodiment, the floating gate 217 has a nonvolatile memory made of hemispherical crystal grains. In the case of a floating gate having a layered structure, if a part of the insulating film (tunnel film 216, inter-gate oxide film 218) insulation is broken, for example, all the charged carriers escape. On the other hand, if the structure is composed of hemispherical crystal grains (including intergate oxide film 218 between the grains), even if the insulating properties of a part of the insulating films (tunnel film 216, intergate oxide film 218) are broken, Since carriers can only escape from the floating gate 217 (crystal grains) in the portion, a highly reliable memory can be obtained.

As in the first embodiment, the semiconductor substrate 210 is an SOI (Silicon On Insulator) substrate with an insulating film embedded therein, and is a support substrate 211 made of single crystal silicon (Si) and an insulation made of silicon oxide film (SiO ₂ ). A film 212 and a p-type semiconductor layer 213 are included. An n + -type diffusion region 214 that is a source region and an n + -type diffusion region 215 that is a drain region are selectively formed on the surface layer portion of the semiconductor layer 213. Further, the floating gate 217 made of the above-described hemispherical crystal grains is formed on the semiconductor layer 213 via the tunnel film 216. A control gate 219 is formed on the floating gate 217 via an inter-gate oxide film 218.

  Here, the inter-gate oxide film 218 includes a CVD oxide film 218a formed as a vapor-phase oxide film on the surface of the floating gate 217, and the CVD oxide film 218a and the surface of the floating gate 217 after the formation of the CVD oxide film 218a. And thermal oxidation 218b additionally formed between the two. As described above, the semiconductor device 300 according to this embodiment is characterized in that the CVD oxide film 218a is formed first, and then the thermal oxide film 218b is additionally formed by thermal oxidation.

  Next, a method for manufacturing the semiconductor device 300 configured as described above will be described. First, an SOI structure semiconductor substrate 210 having an n − -type semiconductor layer 213 is prepared, and a tunnel film 216 is formed on the surface of an element formation region of the semiconductor layer 213. Then, an amorphous silicon layer to which an impurity to be the floating gate 217 is added later is formed on the tunnel film 216 by CVD (LPCVD in this embodiment). Then, the floating gate 217 (however, before patterning) made of hemispherical crystal grains is formed by a known manufacturing method (for example, the amorphous silicon layer is aggregated by annealing to be hemispherical).

  After the formation of the floating gate 217, as shown in FIG. 17A, a CVD oxide film 218a is formed on the surface of the floating gate 217 by using a CVD method (LPCVD method in this embodiment). At this point, the composition of the CVD oxide film 218a deviates from the stoichiometric state (chemical stoichiometric state). That is, dangling bonds (unbonded hands) that serve as carrier traps exist in the film. Further, the CVD oxide film 218a is not densified, and the interface state density is larger than that of the oxide film formed by thermal oxidation. In the formation of the CVD oxide film 218a, as shown in FIG. 17A, the film thickness t of the CVD oxide film 218a is made larger than the distance d1 between adjacent crystal grains of the floating gate 217. Is preferred. Thereby, the CVD oxide film 218a (inter-gate oxide film 218) can be reliably disposed between the crystal grains.

  After the CVD oxide film 218a is formed, thermal oxidation is performed, and as shown in FIG. 17B, a thermal oxide film 218b is additionally formed between the previously formed CVD oxide film 218a and the surface of the floating gate 217. In the present embodiment, additional thermal oxidation was performed at 850 ° C. in a mixed gas of oxygen and water vapor. Thus, the inter-gate oxide film 218 is formed.

  After the formation of the inter-gate oxide film 218, as shown in FIG. 16, the control gate 219 (but before patterning) is formed on the inter-gate oxide film 218 by using the CVD method (LPCVD method in this embodiment). Form. Then, the floating gate 217 and the control gate 219 are patterned by photolithography.

  After the patterning, ion implantation is performed using the floating gate 217 and the control gate 219 as masks to form diffusion regions 214 and 215 which are a source region and a drain region, respectively. Thereby, the semiconductor device 300 shown in FIG. 16 is manufactured.

As described above, in the intergate oxide film 218 according to the present embodiment, the CVD oxide film 218a is first formed, and then the thermal oxide film 218b is formed by thermal oxidation, similarly to the gate insulating film 30 shown in the first embodiment. Form. Therefore, the defect density in the film can be reduced. In addition, by the thermal oxidation after the CVD oxide film 218a is formed, the floating gate 217 is formed through the CVD oxide film 218a before the oxygen (O ₂ ) or water vapor (H ₂ 0) in the thermal oxidation atmosphere is densified. The thermal oxide film 218 can be additionally formed by diffusing to the interface between the amorphous silicon to be formed and the CVD oxide film 218a and reacting with Si. Thereby, the Si—SiO ₂ interface can be moved to the Si side rather than the time of forming the CVD oxide film, and a predetermined film thickness can be obtained. That is, as shown in FIG. 17 (b), the inter-grain space is expanded from d1 to d2 by the additional thermal oxidation, so that carriers accumulated in the floating gate 217 are prevented from moving to the adjacent crystal grains and the control gate 219. In other words, carrier retention characteristics can be improved (a memory state change with time can be suppressed). Further, the interface state density is set to the level of an oxide film formed by thermal oxidation, and good interface characteristics can be obtained.

  Further, in parallel with the above, oxygen or water vapor in the thermal oxidation atmosphere reacts with dangling bonds (unbonded hands) in the CVD oxide film 218a, causing the CVD oxide film 218a to be in a stoichiometric state (chemically). Stoichiometric state). That is, traps in the CVD oxide film 218a can be reduced and the film quality of the inter-gate oxide film 218 can be improved. Therefore, the Vt fluctuation caused by trapping the charge at the time of rewriting can be made similar to that of the thermal oxide film.

  In addition to the effects described above, effects similar to or equivalent to the effects described in the first embodiment can be expected.

  Further, as shown in the present embodiment, in the configuration in which the floating gate 217 is formed of hemispherical crystal grains, if thermal oxidation is performed first, an oxide film having a sufficient thickness can be formed between the crystal grains. Can not. However, according to the manufacturing method described above, an oxide film having a sufficient thickness can be formed also between the crystal grains. Further, since the intergranularity can be expanded (d1 → d2) by additional thermal oxidation, a desired breakdown voltage can be ensured.

  Further, in the present embodiment, the description has been given by taking as an example a nonvolatile memory having a configuration in which the floating gate 217 is formed of hemispherical crystal grains. However, the configuration of the nonvolatile memory is not limited to the above example. For example, the same effect can be expected even when the floating gate 217 has a configuration (eg, a layer) that does not include hemispherical crystal grains.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

In the present embodiment, as the semiconductor substrates 10, 110, 210, support substrates 11, 111, 211 made of single crystal silicon (Si), insulating films 12, 112, 212 made of silicon oxide film (SiO ₂ ), and n An example in which a semiconductor substrate having an SOI structure including the − type semiconductor layers 13, 113, and 213 is applied has been shown. However, the semiconductor substrates 10, 110, and 210 are not limited to the above example.

  Further, in the present embodiment, an example in which the structure and manufacturing method of the oxide film which is a main part is applied to the gate insulating film 30, the capacitor oxide film 116, and the inter-gate oxide film 218 has been shown. However, it is not limited to the above example. For example, the present invention can be applied to an insulating film formed on the trench surface in the trench isolation region.

  In the first to fourth embodiments, as a configuration example in which crystal defects are likely to occur, a trench 15 is formed in a p-type diffusion region 14 that is a drain region into which boron having a greatly different atomic radius from silicon is introduced. The configuration was shown. However, not only boron but a material having a large difference in atomic radius with respect to silicon (for example, antimony) is likely to cause crystal defects in the semiconductor substrate 10. Even in such a configuration, the film quality of the gate insulating film 30 can be improved according to the semiconductor device 100 and the manufacturing method thereof shown in the present embodiment. The same applies to the semiconductor devices 200 and 300.

It is sectional drawing which shows schematic structure of the semiconductor device which concerns on 1st Embodiment. It is an enlarged view around a trench. It is sectional drawing according to process for demonstrating the formation process of a gate insulating film, (a) is trench formation, (b) is sacrificial oxide film formation, (c) Sacrificial oxide film removal, (d) is CVD oxide film formation. (E) is a figure which shows thermal oxide film formation. It is sectional drawing according to process after gate insulating film formation, (a) is a gate electrode formation process. (B) shows the diffusion region forming step. It is a figure which shows the relationship between the distance from a trench isolation | separation area | region, and a crystal defect. It is a figure which shows the Weibull distribution of the proof pressure of a gate insulating film. It is a figure which shows the relationship between the additional oxidation by thermal oxidation, and the incidence rate of B mode defect. It is a figure which shows the interface state density of a gate insulating film. It is a figure which shows the film thickness of a gate insulating film. In the semiconductor device which concerns on 2nd Embodiment, it is sectional drawing according to process which shows the formation process of a gate insulating film, (a) is trench formation, (b) is CVD oxide film formation, (c) is thermal oxide film formation. FIG. In the semiconductor device concerning 3rd Embodiment, it is a schematic sectional drawing which shows a part of formation process of a gate insulating film. It is a figure which shows the effect of chamfering, (a) is a figure explaining chamfering amount X, (b) is a figure which shows the relationship between chamfering amount X and electric field strength ratio (opening corner | angular part / flat part). It is a figure which shows schematic structure of the gate insulating film which concerns on 4th Embodiment, (a) is an expanded sectional view of a trench opening corner | angular part, (b) is a model which shows the composition in the AA 'cross section of (a). FIG. It is sectional drawing which shows schematic structure of the semiconductor device which concerns on 5th Embodiment. It is sectional drawing according to process which shows the manufacturing method of the principal part among semiconductor devices, (a) is a lower electrode formation process, (b) is a CVD oxide film formation process, (c) is an additional thermal oxidation process. It is sectional drawing which shows schematic structure of the semiconductor device which concerns on 6th Embodiment. It is sectional drawing according to process which shows the manufacturing method of the principal part among semiconductor devices, (a) is a CVD oxide film formation process, (b) is an additional thermal oxidation process.

Explanation of symbols

10, 110, 210 ... semiconductor substrates 13, 113, 213 ... semiconductor layers 15, 114 ... trench 30 ... gate insulating films 31, 116a, 218a ... CVD oxide films (vapor phase oxide films) )
32, 116b, 218b ... thermal oxide film 115 ... lower electrode 116 ... capacitor oxide film 217 ... floating gate 218 ... inter-gate oxide film 100, 200, 300 ... semiconductor device

Claims (48)

A vapor phase oxidation step of forming a vapor phase oxide film on a semiconductor substrate by vapor phase growth;
A method of manufacturing a semiconductor device, comprising an additional thermal oxidation step of thermally oxidizing a formation portion of the vapor phase oxide film after the vapor phase oxidation step.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is an SOI structure semiconductor substrate having a buried oxide film.   3. The semiconductor according to claim 1, wherein, in the vapor phase oxidation step, the vapor phase oxide film is formed in a portion of the semiconductor substrate including a conductive type region having boron or antimony as an impurity. Device manufacturing method.   The method for manufacturing a semiconductor device according to claim 1, further comprising a gate having a MOS structure.   5. The method of manufacturing a semiconductor device according to claim 4, wherein, in the additional thermal oxidation step, an oxide film thickness additionally formed by thermal oxidation is in a range of 1 nm to 12 nm. As a pre-process of the vapor phase oxidation process, comprising a trench formation step of forming a trench in the semiconductor substrate,
6. The method of manufacturing a semiconductor device according to claim 4, wherein the vapor phase oxide film is formed on a surface of the trench in the vapor phase oxidation step.   The method of manufacturing a semiconductor device according to claim 6, wherein the trench is a trench for a gate electrode.   8. The method of manufacturing a semiconductor device according to claim 6, wherein, in the additional thermal oxidation step, a curvature radius of at least an opening corner portion of the trench is made larger than that at the time of trench formation together with thermal oxidation. .   7. The bending step of increasing the radius of curvature of at least the opening corner portion of the trench larger than that at the time of forming the trench between the trench forming step and the gas phase oxidation step. Item 8. A method for manufacturing a semiconductor device according to Item 7.   The semiconductor device according to claim 9, wherein the bending step includes a sacrificial oxidation step of forming a sacrificial oxide film on the trench surface by thermal oxidation, and a removal step of removing the sacrificial oxide film. Production method.   11. The method of manufacturing a semiconductor device according to claim 9, wherein the bending step includes a chamfering step of chamfering the opening corner by isotropic etching.   12. The method for manufacturing a semiconductor device according to claim 11, wherein, in the chamfering step, a chamfering amount in a planar direction of the semiconductor substrate is set to 50 nm or more. A capacitor having a capacitor oxide film as a dielectric between a pair of electrodes;
The method for manufacturing a semiconductor device according to claim 1, wherein the capacitor oxide film is formed by the vapor phase oxidation step and the additional thermal oxidation step. As a pre-process of the gas phase oxidation process, comprising a lower electrode forming process of forming a lower electrode that is one of the electrodes made of hemispherical crystal grains,
14. The method of manufacturing a semiconductor device according to claim 13, further comprising an upper electrode forming step of forming an upper electrode which is the other electrode as a subsequent step of the additional thermal oxidation step. The capacitor is a trench structure capacitor,
As a pre-process of the vapor phase oxidation process, comprising a trench formation step of forming a trench of the capacitor in the semiconductor substrate,
15. The method of manufacturing a semiconductor device according to claim 13, wherein the vapor phase oxide film is formed on a surface of the trench in the vapor phase oxidation step.   16. The method of manufacturing a semiconductor device according to claim 15, wherein, in the additional thermal oxidation step, the curvature radius of at least the opening corner portion of the trench is made larger than that at the time of trench formation together with thermal oxidation.   16. The bending step of increasing the radius of curvature of at least the opening corner of the trench larger than that at the time of forming the trench between the trench formation step and the vapor phase oxidation step. Semiconductor device manufacturing method.   18. The semiconductor device according to claim 17, wherein the bending step includes a sacrificial oxidation step of forming a sacrificial oxide film on the trench surface by thermal oxidation and a removal step of removing the sacrificial oxide film. Production method.   19. The method of manufacturing a semiconductor device according to claim 17, wherein the bending step includes a chamfering step of chamfering the opening corner by isotropic etching. A non-volatile memory including a two-layer gate electrode of a floating gate and a control gate;
The inter-gate oxide film disposed between the floating gate and the control gate is formed by the vapor phase oxidation step and the additional thermal oxidation step. Semiconductor device manufacturing method. As a pre-process of the vapor phase oxidation process, a floating gate forming process for forming the floating gate composed of hemispherical crystal grains,
21. The method of manufacturing a semiconductor device according to claim 20, further comprising a control gate forming step of forming the control gate as a subsequent step of the additional thermal oxidation step.   The method of manufacturing a semiconductor device according to claim 21, wherein, in the vapor phase oxidation step, the thickness of the vapor phase oxide film is made larger than the interval between the adjacent crystal grains. A method of manufacturing a semiconductor device having a MOS structure gate,
An oxide film forming step of forming an oxide film on the semiconductor substrate;
And a nitrogen-containing film forming step of forming a nitrogen-containing film including a region in which the nitrogen concentration continuously increases in a direction away from the interface with the oxide film on the oxide film. Method. Applying a CVD method in the nitrogen-containing film forming step,
24. The method of manufacturing a semiconductor device according to claim 23, wherein the gas composition is changed with time so that the nitrogen concentration continuously increases in a direction away from the interface with the oxide film. As a pre-process of the oxide film forming process, comprising a trench forming process of forming a trench in the semiconductor substrate,
26. The method of manufacturing a semiconductor device according to claim 24, wherein the oxide film is formed on a surface of the trench in the oxide film forming step.   26. The method of manufacturing a semiconductor device according to claim 25, wherein the trench is a trench for a gate electrode.   26. The method according to claim 25, further comprising a bending step of increasing a radius of curvature of at least an opening corner portion of the trench larger than that at the time of forming the trench between the trench forming step and the oxide film forming step. Item 27. A method for manufacturing a semiconductor device according to Item 26.   28. The semiconductor device according to claim 27, wherein the bending step includes a sacrificial oxidation step of forming a sacrificial oxide film on the trench surface by thermal oxidation, and a removal step of removing the sacrificial oxide film. Production method.   29. The method of manufacturing a semiconductor device according to claim 27, wherein the bending step includes a chamfering step of chamfering the opening corner by isotropic etching.   30. The method of manufacturing a semiconductor device according to claim 29, wherein, in the chamfering step, a chamfering amount in a planar direction of the semiconductor substrate is set to 50 nm or more. A vapor-phase oxide film formed on a semiconductor substrate;
A semiconductor device comprising a thermal oxide film additionally formed between the vapor phase oxide film and the semiconductor substrate after the vapor phase oxide film is formed.   31. The semiconductor device according to claim 30, wherein the semiconductor substrate is an SOI structure semiconductor substrate having a buried oxide film. The semiconductor substrate has a conductive region having boron or antimony as an impurity,
33. The semiconductor device according to claim 31, wherein the vapor phase oxide film and the thermal oxide film are formed on the conductivity type region.   The semiconductor device according to claim 31, further comprising a gate having a MOS structure.   35. The semiconductor device according to claim 34, wherein an oxide film thickness of the thermal oxide film is in a range of 1 nm to 12 nm. The semiconductor substrate has a trench;
36. The semiconductor device according to claim 34, wherein the vapor phase oxide film and the thermal oxide film are formed on a surface of the trench.   37. The semiconductor device according to claim 36, wherein the trench is a trench for a gate electrode.   38. The semiconductor device according to claim 36, wherein at least an opening corner portion of the trench has a rounded and gentle shape. A capacitor having a capacitor oxide film as a dielectric between a pair of electrodes;
The semiconductor device according to claim 31, wherein the capacitor oxide film includes the vapor-phase oxide film and the thermal oxide film. The pair of electrodes includes an upper electrode and a lower electrode,
40. The semiconductor device according to claim 39, wherein the lower electrode is made of hemispherical crystal grains. The capacitor is a trench structure capacitor,
41. The semiconductor device according to claim 39, wherein the vapor-phase oxide film and the thermal oxide film are formed on a surface of the trench.   42. The semiconductor device according to claim 41, wherein at least an opening corner portion of the trench has a rounded and gentle shape. A non-volatile memory including a two-layer gate electrode of a floating gate and a control gate;
The semiconductor according to any one of claims 31 to 33, wherein an inter-gate oxide film disposed between the floating gate and the control gate includes the vapor-phase oxide film and the thermal oxide film. apparatus.   44. The semiconductor device according to claim 43, wherein the floating gate is made of hemispherical crystal grains. A semiconductor device having a MOS structure gate,
An oxide film formed on a semiconductor substrate;
A semiconductor device comprising a nitrogen-containing film formed on the oxide film and including a region where the nitrogen concentration continuously increases in a direction away from the interface with the oxide film. The semiconductor substrate has a trench;
46. The semiconductor device according to claim 45, wherein the oxide film and the nitrogen-containing film are stacked on a surface of the trench.   The semiconductor device according to claim 46, wherein the trench is a trench for a gate electrode.   48. The semiconductor device according to claim 46, wherein at least an opening corner of the trench has a rounded and gentle shape.

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