JP2003124233A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that reliability in a semiconductor device having a MISFET of a trench gate structure is lowered. SOLUTION: In a method for manufacturing a semiconductor device having a MISFET of a trench gate structure, a groove 4 is formed of a main plane of a first conductive type semiconductor layer 1B as a drain area to the depth direction thereof, and a gate insulating film 5 composed of a thermal oxide film 5A and a deposited film 5B on the internal plane of the groove 4 is formed, and a gate electrode 6A is formed in the groove 4. Thereafter, impurities are introduced into the first conductive type semiconductor layer 1B to form a second conductive type semiconductor area 8 as a channel forming area, and impurities are introduced into the second conductive type semiconductor area 8 to form a first conductive type semiconductor area 9 as a source area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a transistor element having a trench gate structure.

[0002]

2. Description of the Related Art A power transistor (semiconductor device) is used as a switching element of a power amplification circuit, a power supply circuit and the like. This type of power transistor has a structure in which a plurality of transistor elements are electrically connected in parallel. Transistor element, for example, MISFET of trench gate structure (M etal I nsulator S emicon
It is composed of a ductor F ield E ffect T ransistor) . Hereinafter, a method for manufacturing a power transistor having a trench gate structure MISFET will be described.

First, an n ⁻ type semiconductor layer is formed on the main surface of an n ⁺ type semiconductor substrate made of single crystal silicon by an epitaxial growth method. The n ⁺ type semiconductor substrate and the n ⁻ type semiconductor layer are used as a drain region. Next, p-type impurities are introduced into the entire main surface of the n ⁻ -type semiconductor layer by ion implantation to form a p-type semiconductor region used as a channel formation region. Next, an n-type impurity is selectively introduced into the main surface of the p-type semiconductor region by an ion implantation method to form an n ⁺ type semiconductor region as a source region.

Next, after forming, for example, a silicon oxide film on the main surface of the n ⁻ type semiconductor layer, the silicon oxide film is patterned to form an opening on the groove forming region of the n ⁻ type semiconductor layer. Forming a mask having Next, using the mask as an etching mask, a groove is formed in the depth direction from the main surface of the n ⁻ type semiconductor layer. The groove is formed by an anisotropic dry etching method.

Then, a wet etching process is performed to retract the mask from the upper edge portion of the groove (the portion where the side surface of the groove intersects with the main surface of the n ^-- type semiconductor layer). Next, an isotropic dry etching process is performed to make the upper edge portion and the bottom edge portion (the portion where the side surface of the groove and the bottom surface thereof intersect) of the groove gentle. Next, the mask is removed.

Next, a thermal oxidation process is performed to form a sacrificial thermal oxide film on the inner surface of the groove, and then the sacrificial thermal oxide film is removed. The formation and removal of this sacrificial thermal oxide film is carried out for the purpose of removing defects, distortions, contamination, etc., which have occurred when forming the groove.

Next, a thermal oxidation process is performed to form a gate insulating film made of a thermal oxide film on the inner surface of the groove. Next, a polycrystalline silicon film is formed on the entire main surface of the n ⁻ type semiconductor layer including the inside of the groove by a chemical vapor deposition method. Impurities that reduce the resistance value are introduced into the polycrystalline silicon film during or after the deposition.

Next, an etch back process is performed to flatten the surface of the polycrystalline silicon film. Next, the polycrystalline silicon film is selectively subjected to an etching treatment to form a gate electrode in the groove, and is integrated with the gate electrode on the peripheral region of the main surface of the n ⁻ type semiconductor layer. An electrode for leading out the gate is formed. By this step, a MISFET having a trench gate structure in which a gate electrode is formed with a gate insulating film interposed in the groove of the n ⁻ type semiconductor layer is formed.

Next, an interlayer insulating film is formed on the entire main surface of the n ^-- type semiconductor layer including on the gate electrode, then a connection hole is formed in the interlayer insulating film, and then the source wiring and the gate are formed. Forming wiring, then forming a final protective film,
After that, a bonding opening is formed in the final protective film,
Then, a drain electrode is formed on the back surface of the n ⁺ -type semiconductor substrate to form a trench gate structure MISFE.
The power transistor having T is almost completed.

Since the MISFET having the trench gate structure configured as described above can occupy a smaller area than the MISFET in which the gate electrode is formed on the main surface of the semiconductor layer with the gate insulating film interposed, the size of the power transistor is small. And low on-resistance.

A MISFET having a trench gate structure
The power transistor having the above is described in, for example, Japanese Patent Application Laid-Open No. 7-263692.

[0012]

The present inventors have found the following problems as a result of examining the above-mentioned power transistor (semiconductor device).

In the power transistor, a p-type semiconductor region which is a channel forming region is formed in an n ⁻ type semiconductor layer which is a drain region, and an n ⁺ type semiconductor region which is a source region is formed in the p type semiconductor region, After forming a groove in the n ⁻ type semiconductor layer, a thermal oxidation process is performed to form a thermal oxide film as a gate insulating film on the inner surface of the groove. For this reason,
Impurities (for example, boron (B)) in the p-type semiconductor region and impurities (for example, arsenic (As)) in the n ⁺ -type semiconductor region are taken into the thermal oxide film, and the breakdown voltage of the gate insulating film is likely to deteriorate. Therefore, the reliability of the power transistor is reduced.

Further, the impurities of the p-type semiconductor region on the side surface of the groove are taken into the thermal oxide film, and the impurity concentration of the channel forming region on the side surface of the groove varies.
The threshold voltage (Vth) of the MISFET fluctuates,
It is impossible to provide stable characteristics with good reproducibility.

Further, due to the heat treatment temperature at the time of forming the thermal oxide film, the impurities in the n ⁺ type semiconductor region, which is the source region, are accelerated and diffused, the effective channel length of the MISFET is shortened, and the punch through breakdown voltage is lowered. So 950
By forming the thermal oxide film at a heat treatment temperature as low as about [° C.], accelerated diffusion of impurities in the n ⁺ type semiconductor region that is the source region can be suppressed, and the punch through breakdown voltage of the MISFET can be secured. However, when the thermal oxide film is formed at a low heat treatment temperature, the upper edge of the groove is deformed into an angular shape due to the compressive stress generated during the growth of the thermal oxide film, and the film thickness of the thermal oxide film at the upper edge is changed. Since it becomes thin locally, MI
The gate breakdown voltage of the SFET decreases. So 1100
If the thermal oxide film is formed at a heat treatment temperature as high as [° C.], the deformation at the upper edge of the groove can be suppressed, and the MISFET can be suppressed.
However, when the thermal oxide film is formed at a high heat treatment temperature of about 1100 [° C.], the impurity in the n ⁺ type semiconductor region, which is the source region, diffuses more rapidly as described above, and the MISFET The punch-through breakdown voltage of is reduced.
That is, the punch-through breakdown voltage and the gate breakdown voltage of the MISFET cannot be secured, so that the reliability of the power transistor is lowered.

An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device and obtaining stable and reproducible FET characteristics.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0018]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

A method of manufacturing a semiconductor device having a MISFET having a trench gate structure, wherein a groove is formed in a depth direction from a main surface of a first conductivity type semiconductor layer which is a drain region, and an inner surface of the groove is formed. After forming a gate insulating film composed of a thermal oxide film and a deposited film and forming a gate electrode in the groove, impurities are introduced into the first conductive type semiconductor layer to form a second conductive type semiconductor which is a channel formation region. While forming the region, impurities are introduced into the second conductive type semiconductor region to form a first conductive type semiconductor region which is a source region. The thermal oxide film is formed in an oxygen gas atmosphere or a water vapor atmosphere, and the deposited film is formed by a chemical vapor deposition method.
The deposited film is formed of a silicon oxide film, a silicon nitride film, or an oxynitride film.

According to the above-mentioned means, after the thermal oxide film which is the gate insulating film is formed, the second conductivity type semiconductor region which is the channel formation region and the first conductivity type semiconductor region which is the source region are formed. Impurities in the second conductivity type semiconductor region and impurities in the first conductivity type semiconductor region are not incorporated into the thermal oxide film, and deterioration of the dielectric strength of the gate insulating film due to the incorporation of impurities can be suppressed. As a result, the reliability of the semiconductor device can be improved.

Further, since the second semiconductor region which is the channel forming region is formed after the thermal oxide film which is the gate insulating film is formed, the impurities of the second conductivity type semiconductor region on the side surface of the groove are contained in the thermal oxide film. MISFET that is not captured and is caused by variations in the impurity concentration in the channel formation region.
Of the threshold voltage (Vth) can be suppressed. As a result, stable FET characteristics can be obtained with good reproducibility.

Further, since the first conductivity type semiconductor region which is the source region is formed after the thermal oxide film which is the gate insulating film is formed, the thermal oxide film is formed at a high thermal oxidation treatment temperature of about 1100 [° C.]. Even if it is formed, the impurities in the first conductivity type semiconductor region do not diffuse more rapidly, the reduction of the effective channel length can be suppressed, and the punch-through breakdown voltage of the MISFET can be secured. Further, the thermal oxide film is formed at a low thermal oxidation treatment temperature of about 950 [° C.], and the upper edge portion of the groove (the side surface of the groove and the first conductivity type semiconductor layer Even if the part where the main surface intersects) is deformed into an angular shape and the film thickness of the thermal oxide film at this upper edge part is locally thinned, that part can be supplemented by the deposited film,
The gate breakdown voltage of the MISFET can be secured. As a result, the reliability of the semiconductor device can be improved.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments of the invention, components having the same function are designated by the same reference numeral, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a plan view of a main part of a power transistor (semiconductor device) according to Embodiment 1 of the present invention, and FIG. 2 is a sectional view taken along line AA shown in FIG. 3 is a sectional view taken along line BB in FIG. 1. In FIG. 1, a source wiring 12A and a gate wiring 12 which will be described later are shown to make the drawing easy to see.
B, the final protective film 13 and the like are not shown. In addition, in FIGS. 2 and 3, some hatching (diagonal lines) showing the cross section is omitted for easy understanding of the drawings.

The power transistor of this embodiment is shown in FIG.
And as shown in FIG. 2, for example, n made of single crystal silicon
The main structure is a semiconductor substrate in which an n ⁻ type semiconductor layer 1B is formed on the main surface of a ⁺ type semiconductor substrate 1A. n
^{The −} type semiconductor layer 1B is formed by, for example, an epitaxial growth method and is made of single crystal silicon.

A plurality of transistor elements are formed on the semiconductor substrate, and the plurality of transistor elements are electrically connected in parallel. The transistor element of this embodiment is composed of a MISFET.

The MISFET is mainly used for channel formation.
Region, gate insulating film 5, gate electrode 6A, source region and
And a drain region. Channel formation area
Is n ⁻Type semiconductor region 8 formed in the type semiconductor layer 1B
It is composed of. The source region is the p-type semiconductor region 8.
N formed⁺It is composed of the type semiconductor region 9. Drain
The in area is n⁺Type semiconductor substrates 1A and n⁻Type semiconductor layer
It is composed of 1B. The gate insulating film 5 is n⁻Mold
Grooves formed in the depth direction from the main surface of the body layer 1B
4 is formed on the inner surface. The gate electrode 6A is in the groove 4.
Consists of a conductive film embedded in the gate insulating film 5
Has been done. As the conductive film, for example, the resistance value is reduced.
It is formed of a polycrystalline silicon film into which impurities are introduced. Immediately
MISFET is n⁻From the main surface of the type semiconductor layer 1B
Toward the depth direction of the source region, channel formation region,
It is composed of a vertical structure in which each of the rain regions is sequentially arranged,
Furthermore, n⁻Gate in the groove 4 formed in the semiconductor layer 1B
A trench gate formed with the insulating film 5 and the gate electrode 6A, respectively.
It is composed of a card structure. In addition, MISFET is a groove
4 is a channel forming region
And an n-channel conductivity type.

Although not limited to this, the gate insulating film 5 of the MISFET is composed of, for example, a multilayer film in which the thermal oxide film 5A and the deposited film 5B are sequentially arranged from the inner surface of the groove 4. The thermal oxide film 5A is formed with a film thickness of, for example, about 20 [nm], and the deposited film 5B is formed with a film thickness of, for example, about 50 [nm]. The thermal oxide film 5A is formed by forming the groove 4 in the n ⁻ type semiconductor layer 1B and then performing a heat treatment at about 950 ° C. in an oxygen gas atmosphere or a water vapor atmosphere, for example. The deposited film 5B is formed of, for example, a silicon oxide film deposited by a chemical vapor deposition (Chemical Vapor Deposition) method. This silicon oxide film is formed of silane (S
It is formed by reacting iH ₄ ) with oxygen (O ₂ ).

The element forming region on the main surface of the n ^-- type semiconductor layer 1B is divided into a plurality of island regions by the groove 4. Each of the plurality of island regions is regularly arranged in a matrix, and its planar shape is a flat octagon. That is, groove 4
Is formed by dividing the element formation region of the main surface of the n ⁻ -type semiconductor layer 1B into a plurality of island regions, and the planar shape of these island regions is a flat octagon. MISFE
The n ⁺ type semiconductor region 9 which is the source region of T is formed on the main surface of the island region of the n ⁻ type semiconductor layer 1B divided by the trench 4.

The upper edge portion of the groove 4 (the portion where the side surface of the groove 4 and the main surface of the n ⁻ type semiconductor layer 1B intersect) and the bottom edge portion (the portion where the side surface of the groove 4 intersects with the bottom surface thereof) are It has a gentle shape. The shapes of the upper edge portion and the lower surface edge portion of the groove 4 are formed by forming the groove 4 in the n ⁻ type semiconductor layer 1B and then performing chemical dry etching using a mixed gas of chlorine gas and oxygen gas. It

A connection hole 11 formed in the interlayer insulating film 10 is formed in each of the n ⁺ type semiconductor region 9 and the p type semiconductor region 8.
The source wiring 12A is electrically connected through A. The interlayer insulating film 10 includes the gate electrode 6A and the source wiring 1
2A provided between the gate electrode 6A and the source wiring 1
2A is insulated and separated. The source wiring 12A is formed of, for example, an aluminum (Al) film or an aluminum alloy film. The gate electrode 6A and the interlayer insulating film 10
An insulating film 7 is provided between and.

As shown in FIGS. 1 and 3, the gate electrode 6A is led out to a peripheral region of the main surface of the n ^-- type semiconductor layer 1 and is integrated with a gate lead electrode 6B formed on the main surface. Has been converted. The gate wiring 12B is electrically connected to the gate extraction electrode 6B through a connection hole 11B formed in the interlayer insulating film 10. The gate wiring 12B is formed in the same layer as the source wiring 12A and is electrically isolated from each other.

On the source wiring 12A and the gate wiring 1
2B, on the entire main surface of the n ⁻ type semiconductor layer 1B,
As shown in FIGS. 2 and 3, the final protective film 13 is formed. The final protective film 13 is, for example, a plasma chemical vapor deposition (Plasma Chemical Vap) using tetraethoxysilane (TEOS) gas as a main source gas.
or deposition) method is used to form the silicon oxide film. The final protective film 13 has a bonding opening that exposes a part of the surface of the source wiring 12A and a bonding opening that exposes a part of the surface of the gate wiring 12B.

A drain electrode 14 is formed on the back surface of the n ⁺ type semiconductor substrate 1.

Next, a method of manufacturing the power transistor will be described with reference to FIGS. 4 to 14 (cross-sectional views of a main part for explaining the manufacturing method). 8 to 14
In FIG. 3, hatching (diagonal lines) representing the cross section is partially omitted for easy viewing of the drawing.

First, an n ⁺ type semiconductor substrate 1A made of single crystal silicon is prepared. The n ⁺ type semiconductor substrate 1 is 2 × 10 ¹⁹
The impurity concentration is set to about [atoms / cm ³ ].
As impurities, for example, arsenic (As) is introduced.

Next, as shown in FIG. 4, an n ⁻ type semiconductor layer 1B is formed on the main surface of the n ⁺ type semiconductor substrate 1A by an epitaxial growth method. As the n ⁻ type semiconductor layer 1B, for example, a specific resistance value of about 0.4 [Ωcm] and 6 [μ
m]. By this step, a semiconductor substrate composed of the n ⁺ type semiconductor substrate 1A and the n ⁻ type semiconductor substrate 1B is formed.

Next, a silicon oxide film having a thickness of about 500 [nm] is formed on the main surface of the n ⁻ type semiconductor layer 1B. This silicon oxide film is formed by, for example, a thermal oxidation method.

Next, the silicon oxide film is patterned to form a mask 2 having an opening 3 on the groove forming region of the n ^-- type semiconductor layer 1B, as shown in FIG. The mask 2 is formed in a pattern in which the planar shape of the region defined by the opening 3 is a flat octagon in the element forming region of the main surface of the n ⁻ type semiconductor layer 1B.

Next, the mask 2 is used as an etching mask.
Used as shown in FIG. ⁻Of the type semiconductor layer 1B
Grooves 4 are formed from the main surface in the depth direction. This groove
The formation of 4 uses, for example, chlorine gas or hydrogen bromide gas.
Yes, RF (RadioFrequency) Power set high
The anisotropic etching method is used. The groove 4 has a depth of 1.5 to 2
About [μm] and width should be about 0.5 to 2 [μm]
To form.

Next, a wet etching process is performed to expose the mask 2 from the upper edge portion of the groove 4 (the portion where the side surface of the groove 4 and the main surface of the n ^-- type semiconductor layer 1B intersect) to 200 nm.
Move back about.

Next, a chemical dry etching process using a mixed gas of chlorine gas and oxygen gas is performed, and as shown in FIG. 7, the upper edge portion and the bottom edge portion of the groove 4 (the side surface of the groove 4 and the bottom surface thereof). (The part where and intersect) is made into a gentle shape. By this step, the groove 4 having the shape of the top edge portion and the bottom edge portion which are gentle is obtained. Then, the mask 2 is removed.

Next, a thermal oxidation process is performed to form a sacrificial thermal oxide film having a film thickness of about 100 nm on the inner surface of the groove 4, and then the sacrificial thermal oxide film is removed. The formation and removal of this sacrificial oxide film is performed by removing defects, strains,
This is done for the purpose of removing contamination and the like. The sacrificial thermal oxide film is formed in an oxygen gas atmosphere at a high temperature of about 1100 [° C.]. When the sacrificial thermal oxide film is formed at a low thermal oxidation temperature of about 950 [° C.], the compressive stress generated during the growth of the sacrificial thermal oxide film causes the upper surface of the groove 4 processed into a gentle shape. Since the edge portion is deformed into an angular shape, the sacrificial thermal oxide film is formed at a thermal oxidation treatment temperature of 1000 [° C.] or higher. The sacrificial oxide film is formed by
You may perform in the oxygen gas atmosphere diluted with nitrogen gas.

Next, a thermal oxidation process is performed, and as shown in FIG. 8, the thermal oxide film 5 having a film thickness of about 20 [nm] is formed on the inner surface of the groove 4.
After forming A, as shown in FIG. 9, the thermal oxide film 5A is formed.
A gate insulating film 5 is formed by depositing a deposition film 5B made of a silicon oxide film with a thickness of about 50 [nm] on the surface of the substrate by chemical vapor deposition. The thermal oxide film 5A is formed in an oxygen gas atmosphere or a steam atmosphere at a low temperature of about 950 [° C.].
The deposition film 5B is deposited in a low temperature atmosphere of about 800 [° C.]. In the process of forming the gate insulating film 5,
Thermal oxide film 5 at a thermal oxidation processing temperature as low as 950 [° C.]
Since A is formed, the upper edge portion of the groove 4 (the side surface of the groove 4 and the n ⁻ -type semiconductor layer 1B is processed into a gentle shape in the previous step due to the compressive stress generated during the growth of the thermal oxide film 5A.
The portion where the main surface of the thermal oxide film 5A is deformed into an angular shape, and the film thickness of the thermal oxide film 5A at this upper edge portion is locally thinned, but since that portion is supplemented by the deposited film 5B, the gate insulation The withstand voltage of the film 5 is secured.

Next, the n ^-- type semiconductor layer 1 including the inside of the groove 4 is formed.
A polycrystalline silicon film, for example, is formed on the entire main surface of B as a conductive film by chemical vapor deposition. Impurities (for example, phosphorus (P)) that reduce the resistance value are introduced into the polycrystalline silicon film during or after the deposition. The polycrystalline silicon film is, for example, 1 [μ
The film thickness is about m].

Next, the surface of the polycrystalline silicon film is flattened. The planarization, for example etch-back method or chemical mechanical polishing (CMP: C hemical M echanical P olishing)
Do by law.

Next, the polycrystal silicon film is selectively subjected to an etching treatment to form a gate electrode 6A in the groove 4 as shown in FIG. 10, and at the same time, the n ^-- type semiconductor layer 1 is formed.
A gate extraction electrode (shown in FIG. 3) 6B integrated with the gate electrode 6A is formed on the peripheral region of the main surface of B.

Next, after removing the deposited film 5B and the thermal oxide film 5A remaining on the main surface of the n ⁻ type semiconductor layer 1B, respectively, as shown in FIG. An insulating film 7 made of, for example, a silicon oxide film is formed on the entire main surface of the n ⁻ type semiconductor layer 1B including the working electrode 6B. The insulating film 7 is formed by a thermal oxidation method or a chemical vapor deposition method.

Next, after introducing a p-type impurity (for example, boron) into the entire main surface of the n ⁻ -type semiconductor layer 1B by an ion implantation method, an extension diffusion process is performed to form a channel as shown in FIG. A p-type semiconductor region 8 which is a region is formed. The stretching diffusion process is performed for about 1 hour in an N ₂ gas atmosphere at a temperature of about 1100 [° C.].

Next, after selectively introducing an n-type impurity (for example, arsenic) into the main surface of the p-type semiconductor layer 8 which is the main surface of the n ^-- type semiconductor layer 1B by an ion implantation method, 950
Annealing treatment is performed at a temperature of [° C.] for about 20 minutes to form an n ⁺ type semiconductor region 9 as a source region, as shown in FIG. The introduction of the n-type impurity is performed under the conditions that the final introduction amount is set to about 5 × 10 ¹⁵ [atoms / cm ² ] and the energy amount at the time of introduction is set to 80 [KeV]. By this step, the groove 4 of the n ⁻ type semiconductor layer 1B is formed.
A MISFET having a trench gate structure in which the gate insulating film 5 and the gate electrode 6A are formed is formed.

In the steps up to this point, the p-type semiconductor region 8 which is the channel forming region and the n ⁺ -type semiconductor region 9 which is the source region are formed after the thermal oxide film 5A which is the gate insulating film 5 is formed. There is. Therefore, the thermal oxide film 5A
In the step of forming the p-type semiconductor region, impurities in the p-type semiconductor region 8 and n ⁺
Impurities in the type semiconductor region 9 are not taken into the thermal oxide film 5A, and the gate insulating film 5 due to the inclusion of impurities is not included.
It is possible to suppress the deterioration of the withstand voltage.

The p-type semiconductor region 8 which is the channel forming region is formed after the thermal oxide film 5A which is the gate insulating film 5 is formed. Therefore, the impurity of the p-type semiconductor region 8 on the side surface of the groove 4 is not taken into the thermal oxide film 5A, and the variation of the threshold voltage (Vth) of the MISFET due to the variation of the impurity concentration of the channel forming region can be suppressed. .

The n ⁺ type semiconductor region 9 which is the source region is formed after the thermal oxide film 5A which is the gate insulating film 5 is formed. Therefore, even if the thermal oxide film 5A is formed at a high thermal oxidation processing temperature of about 1100 [° C.],
Impurities in the n ⁺ type semiconductor region 9 do not diffuse at an accelerated rate, reduction of the effective channel length can be suppressed, and the punch-through breakdown voltage of the MISFET can be secured. Further, the thermal oxide film 5A is formed at a low thermal oxidation processing temperature of about 950 [° C.], and the upper edge portion of the groove 4 (the side surface of the groove 4 and the n ⁻ -type is formed by the compressive stress generated during the growth of the thermal oxide film 5A). Even if the portion where the main surface of the semiconductor layer 1B intersects) is deformed into an angular shape and the film thickness of the thermal oxide film 5A at this upper edge portion becomes locally thin, that portion can be supplemented by the deposited film 5B. Because I can, MISF
The gate breakdown voltage of ET can be secured.

Next, as shown in FIG. 13, an interlayer insulating film 10 having a film thickness of, for example, about 500 [nm] is formed on the entire surface of the n ⁻ type semiconductor layer 1B. The interlayer insulating film 10, for example, BPSG (B ron P hospho S ilicate G las
s) Form with a film.

Next, an anisotropic dry etching process using CHF ₃ gas is performed to form a connection hole 11A and a connection hole (shown in FIG. 3) 1 in the interlayer insulating film 10 as shown in FIG.
Form 1B.

Then, a conductive film made of, for example, an aluminum film or an aluminum alloy film is formed on the entire main surface of the n ^-- type semiconductor layer 1B including the inside of the connection hole, and then the conductive film is patterned. A source wiring 12 electrically connected to each of the p-type semiconductor region 8 and the n ⁺ -type semiconductor region 9.
A is formed, and at the same time, a gate wiring 12B that is electrically connected to the gate lead electrode 6B is formed.

Next, a final protective film 13 is formed on the entire main surface of the n ^-- type semiconductor layer 1B including the source wiring 12A and the gate leading electrode 6B. The final protective film 13 is formed of, for example, a silicon oxide film deposited by a plasma chemical vapor deposition method using tetraethoxysilane (TEOS) gas as a main source gas.

Then, a bonding opening exposing a part of the surface of the source wiring 12A and a bonding opening exposing a part of the surface of the gate wiring 12B are formed in the final protective film 13, and then the n ⁺ type is formed. By grinding the back surface of the semiconductor substrate 1A and then forming the drain electrode 14 on the back surface of the n ⁺ type semiconductor substrate 1, a power transistor having a MISFET having a trench gate structure is almost completed.

As described above, according to this embodiment, the following effects can be obtained.

A method of manufacturing a semiconductor device having a MISFET having a trench gate structure, in which a groove 4 is formed from a surface of an n ⁻ type semiconductor layer 1B which is a drain region in a depth direction thereof, and an inner surface of the groove 4 is formed. Thermal oxide film 5A and deposited film 5
After forming the gate insulating film 5 made of B and forming the gate electrode 6A in the groove 4, the n ⁻ type semiconductor layer 1B is formed.
An impurity is introduced into the p-type semiconductor region 8 to form a channel forming region, and an impurity is introduced into the p-type semiconductor region 8 to form an n ⁺ type semiconductor region 9 to form a source region.

As a result, the p-type semiconductor region 8 which is the channel forming region and the n ⁺ -type semiconductor region 9 which is the source region are formed after the thermal oxide film 5A which is the gate insulating film 5 is formed. Impurities in the region 8 and n ⁺ type semiconductor regions 9 are not taken into the thermal oxide film 5A, and deterioration of the dielectric strength of the gate insulating film 5 due to the taken-in impurities can be suppressed. As a result, the reliability of the power transistor (semiconductor device) can be improved.

Further, the thermal oxide film 5A which is the gate insulating film 5
Since the p-type semiconductor region 8 which is the channel formation region is formed after the formation of the impurity, the impurity of the p-type semiconductor region 8 on the side surface of the groove 4 is not taken into the thermal oxide film 5A, and the impurity of the channel formation region is not formed. M due to variation in concentration
The fluctuation of the threshold voltage (Vth) of the ISFET can be suppressed. As a result, stable FET characteristics can be obtained with good reproducibility.

Further, the thermal oxide film 5A which is the gate insulating film 5
After forming the n ^- type semiconductor region 9 which is the source region
Therefore, even if the thermal oxide film 5A is formed at a high temperature of about 1100 [° C.], the impurity in the n ⁺ type semiconductor region 9 does not diffuse faster and the effective channel length of The reduction can be suppressed, and the punch-through breakdown voltage of the MISFET can be secured. Further, the thermal oxide film 5A is formed at a low thermal oxidation processing temperature of about 950 [° C.].
The upper edge portion of the groove 4 (the groove 4
Side surface of the n ⁻ type semiconductor layer 1B and a main surface of the n ⁻ type semiconductor layer 1B) are deformed into an angular shape, and the thermal oxide film 5 at the upper edge is formed.
Even if the film thickness of A is locally thinned, that portion is deposited film 5
Since it can be compensated by B, the gate breakdown voltage of the MISFET can be secured. As a result, the reliability of the power transistor (semiconductor device) can be improved.

In this embodiment, the example in which the deposited film 5B is formed of a silicon oxide film has been described, but the deposited film 5B may be formed of a silicon nitride film or an oxynitride film.

(Embodiment 2) In this embodiment, an example in which a mask used as an etching mask at the time of forming a groove is formed of a multi-layered film including a silicon oxide film / a silicon nitride film / a silicon oxide film will be described. The reason is that when the mask used as the etching mask when forming the groove is formed of a single layer film made of a silicon oxide film as in the first embodiment, the reactive deposition generated during the anisotropic etching is performed. It is necessary to use a hydrofluoric acid-based etching solution to remove the substance. At this time, if the mask 2 shown in FIG. 6 is too thin, the mask 2 is removed after etching,
It becomes impossible to process the upper edge of the groove into a gentle shape by isotropic etching.

Further, depending on the anisotropic etching conditions,
As a result of thick reactive deposits being formed on the sides of the groove, it is necessary to perform hydrofluoric acid-based etching for a long time in order to remove them, so the upper edge of the groove is processed into a gentle shape. There is a sufficient possibility that there will be no mask during isotropic etching for this purpose. In the present embodiment, a silicon nitride (Si ₃ N ₄ ) film that is not etched at all by a hydrofluoric acid-based etching solution is used as a mask material during groove formation, so that sufficient hydrofluoric acid-based etching can be performed after the groove is formed. As a result, the silicon oxide film which is the lower layer film of the silicon nitride film can be left during the isotropic etching.
The shape of the upper edge of the groove can be processed into a gentle shape.

Hereinafter, a method of manufacturing the power transistor according to the second embodiment of the present invention will be described with reference to FIGS. It should be noted that in FIGS. 19 to 26, in order to make the drawings easy to see, some hatching (diagonal lines) representing cross sections is omitted.

First, an n ⁻ type semiconductor layer 1B is formed by an epitaxial growth method on the main surface of an n ⁺ type semiconductor substrate 1A made of single crystal silicon. The n ⁻ type semiconductor layer 1B is formed with a specific resistance value of about 0.4 [Ωcm] and a thickness of about 6 μm, for example. By this step, a semiconductor substrate composed of the n ⁺ type semiconductor substrate 1A and the n ⁻ type semiconductor substrate 1B is formed.

Next, as shown in FIG. 15, a silicon oxide film 2A having a film thickness of about 100 [nm] and a nitriding film having a film thickness of about 200 [nm] are formed on the main surface of the n ⁻ type semiconductor layer 1B. A silicon film 2B and a silicon oxide film 2C having a thickness of about 400 [nm] are sequentially formed. The silicon oxide film 2A is formed by a thermal oxidation method, and the silicon nitride film 2B and the silicon oxide film 2C are formed by a chemical vapor deposition method.

Then, the silicon oxide film 2C and the silicon nitride film 2 are anisotropically dry-etched using a gas such as CHF _3.
B and the silicon oxide film 2A are sequentially patterned to form a mask 2 having an opening 3 on the groove forming region of the n ⁻ type semiconductor layer 1B as shown in FIG.

Next, using the mask 2 as an etching mask, as shown in FIG. 17, an n ^-- type semiconductor layer 1B is formed.
The groove 4 is formed from the main surface of the same in the depth direction. The formation of the grooves 4, for example, using a chlorine gas or hydrogen bromide gas is carried out at a RF (R adio F requency) anisotropic etching method set high power. The groove 4 has a depth of 1.5 to 2
The width is about [μm] and the width is about 0.5 to 2 [μm].

Next, a wet etching process is performed to remove the silicon oxide film 2A of the mask 2 from the upper edge portion of the groove 4 (the groove 4).
(The portion where the side surface of the n ⁻ type semiconductor layer 1B intersects with the main surface of the n ⁻ type semiconductor layer 1B) is retracted by about 500 [nm] to 1 [μm]. In this step, the reactive deposit formed on the side surface of the groove 4 and the silicon oxide film 2C are entirely removed, and the surface of the silicon nitride film 2B is exposed.

Next, a chemical dry etching process using a mixed gas of chlorine gas and oxygen gas is performed, and as shown in FIG. 18, the upper edge portion and the bottom edge portion of the groove 4 (the side surface of the groove 4 and the bottom surface thereof). (The part where and intersect) is made into a gentle shape.
By this step, the groove 4 having the shape of the upper edge portion and the bottom edge portion which are gentle is formed.

Next, a thermal oxidation process is performed to form a sacrificial thermal oxide film with a thickness of about 100 nm on the inner surface of the groove 4, and then the sacrificial thermal oxide film is removed. The sacrificial thermal oxide film is formed in an oxygen gas atmosphere at a high temperature of about 1100 [° C.]. When the sacrificial thermal oxide film is formed at a low thermal oxidation temperature of about 950 [° C.], the compressive stress generated during the growth of the sacrificial thermal oxide film causes the upper surface of the groove 4 processed into a gentle shape. Since the edge portion is deformed into an angular shape, the sacrificial thermal oxide film is formed at a thermal oxidation treatment temperature of 1000 [° C.] or higher. The sacrificial oxide film may be formed in an oxygen gas atmosphere diluted with nitrogen gas.

Next, a thermal oxidation process is performed to form a thermal oxide film 5A having a film thickness of about 20 [nm] on the inner surface of the groove 4 as shown in FIG. 19, and then, as shown in FIG. A gate insulating film 5 is formed on the surface of the thermal oxide film 5A by depositing a deposited film 5B made of a silicon oxide film having a thickness of about 50 [nm] by chemical vapor deposition. The formation of the thermal oxide film 5A is 950
It is performed in an oxygen gas atmosphere or a water vapor atmosphere at a low temperature of about [° C.]. The deposition film 5B is deposited in a low temperature atmosphere of about 800 [° C.]. In the step of forming the gate insulating film 5, since the thermal oxide film 5A is formed at a low temperature of about 950 [° C.], the compressive stress generated during the growth of the thermal oxide film 5A causes the former step to proceed. Then, the upper edge portion of the groove 4 (the portion where the side surface of the groove 4 and the main surface of the n ⁻ type semiconductor layer 1B intersect) is processed into an angular shape, and the thermal oxide film 5A at this upper edge portion is deformed. The thickness of the gate insulating film 5 is locally thinned, but since the portion is supplemented by the deposited film 5B, the withstand voltage of the gate insulating film 5 is secured.

Next, the n ^-- type semiconductor layer 1 including the inside of the groove 4 is formed.
A polycrystalline silicon film, for example, is formed on the entire main surface of B as a conductive film by chemical vapor deposition. Impurities (for example, phosphorus) that reduce the resistance value are introduced into the polycrystalline silicon film during or after the deposition. The polycrystalline silicon film is formed with a film thickness of, for example, about 1 [μm].

Next, the surface of the polycrystalline silicon film is flattened. This flattening is performed by, for example, an etch back method or a chemical mechanical polishing method.

Next, the polycrystalline silicon film is selectively subjected to an etching treatment to form a gate electrode 6A in the groove 4 as shown in FIG. 21, and at the same time, the n ^-- type semiconductor layer 1 is formed.
A gate lead electrode (6B shown in FIG. 3) integrated with the gate electrode 6A is formed on the peripheral region of the main surface of B.

Next, the deposited film 5B remaining on the silicon nitride film 2B is removed, and further the silicon nitride film 2B is removed. Then, as shown in FIG. 22, an insulating film 7 made of, for example, a silicon oxide film is formed on the entire main surface of the n ⁻ type semiconductor layer 1B including the gate electrode 6A and the gate lead-out electrode. The insulating film 7 is formed by a thermal oxidation method or a chemical vapor deposition method.

Next, after introducing a p-type impurity (for example, boron) into the entire main surface of the n ⁻ -type semiconductor layer 1B by an ion implantation method, an extension diffusion process is performed to form a channel as shown in FIG. A p-type semiconductor region 8 which is a region is formed. The stretching diffusion process is performed at a temperature of 1100 [° C.]
Approximately 1 hour in a ₂ gas atmosphere.

Then, after selectively introducing an n-type impurity (for example, arsenic) into the main surface of the p-type semiconductor layer 8 which is the main surface of the n ^-- type semiconductor layer 1B by an ion implantation method, 950
An annealing process is performed at a temperature of [° C.] for about 20 minutes to form an n ⁺ type semiconductor region 9 which is a source region, as shown in FIG. The introduction of the n-type impurity is performed under the conditions that the final introduction amount is set to about 5 × 10 ¹⁵ [atoms / cm ² ] and the energy amount at the time of introduction is set to 80 [KeV]. By this step, the groove 4 of the n ⁻ type semiconductor layer 1B is formed.
A MISFET having a trench gate structure in which the gate insulating film 5 and the gate electrode 6A are formed is formed.

Next, as shown in FIG. 24, an interlayer insulating film 10 having a film thickness of, for example, about 500 [nm] is formed on the entire surface of the n ⁻ type semiconductor layer 1B. The interlayer insulating film 10, for example, BPSG (B ron P hospho S ilicate G las
s) Form with a film.

Next, anisotropic dry etching treatment using CHF ₃ gas is performed, and as shown in FIG. 25, the interlayer insulating film 10 is provided with a connection hole 11A and a connection hole (11 shown in FIG. 3).
B) is formed.

Next, a conductive film made of, for example, an aluminum film or an aluminum alloy film is formed on the entire main surface of the n ^-- type semiconductor layer 1B including the inside of the connection hole, and then the conductive film is patterned. A source wiring 12 electrically connected to each of the p-type semiconductor region 8 and the n ⁺ -type semiconductor region 9.
A is formed, and at the same time, a gate wiring (12B shown in FIG. 3) electrically connected to the gate lead electrode is formed.

Next, a final protective film 13 is formed on the entire main surface of the n ^-- type semiconductor layer 1B including the source wiring 12A and the gate leading electrode 6B. The final protective film 13 is formed of, for example, a silicon oxide film deposited by a plasma chemical vapor deposition method using tetraethoxysilane (TEOS) gas as a main source gas.

Next, a bonding opening exposing a part of the surface of the source wiring 12A and a bonding opening exposing a part of the surface of the gate wiring 12B are formed in the final protective film 13, and then the n ⁺ type is formed. By grinding the back surface of the semiconductor substrate 1A and then forming the drain electrode 14 on the back surface of the n ⁺ type semiconductor substrate 1 as shown in FIG. 26, a power transistor having a MISFET having a trench gate structure is almost formed. Complete.

As described above, according to the manufacturing method of this embodiment, the groove 4 is formed in the depth direction from the main surface of the n ⁻ type semiconductor layer 1B which is the drain region, as in the first embodiment. After forming the gate insulating film 5 including the thermal oxide film 5A and the deposited film 5B on the inner surface of the groove 4 and forming the gate electrode 6A in the groove 4, impurities are introduced into the n ⁻ type semiconductor layer 1B. Then, the p-type semiconductor region 8 which is the channel forming region is formed, and at the same time, the impurity is introduced into the p-type semiconductor region 8 to form the n ⁺ type semiconductor region 9 which is the source region. The same effect can be obtained.

As described above, the inventions made by the present inventor are
Although specifically described based on the above embodiment, the present invention is
It is needless to say that the present invention is not limited to the above embodiment, and various changes can be made without departing from the scope of the invention.

For example, the present invention can be applied to a power transistor (semiconductor device) having a p-channel conductivity type MISFET having a trench gate structure.

The present invention also relates to the trench gate structure I.
It can be applied to a power transistor (semiconductor device) having a GBT (I nsulated G ate B ipolar T ransistor).

[0091]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

It is possible to improve the reliability of a semiconductor device having a transistor element having a trench gate structure and obtain stable and reproducible FET characteristics.

[Brief description of drawings]

FIG. 1 is a plan view of a main part of a power transistor (semiconductor device) according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA shown in FIG.

FIG. 3 is a cross-sectional view taken along the line BB shown in FIG.

FIG. 4 is a cross-sectional view of a main part for explaining a method for manufacturing the power transistor.

FIG. 5 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 6 is a cross-sectional view of a main part for explaining a method for manufacturing the power transistor.

FIG. 7 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 8 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 9 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 10 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 11 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 12 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 13 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 14 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 15 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor according to the second embodiment of the present invention.

FIG. 16 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 17 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 18 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 19 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 20 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 21 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 22 is a fragmentary cross-sectional view for explaining the method for manufacturing the power transistor.

FIG. 23 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 24 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 25 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 26 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

[Explanation of symbols]

1A ... n ⁺ type semiconductor substrate, 1B ... n ⁻ type semiconductor layer, 2 ...
Mask, 3 ... Opening, 4 ... Trench, 5 ... Gate insulating film, 5A ...
Thermal oxide film, 5B ... Deposited film, 6A ... Gate electrode, 6B ... Gate extraction electrode, 7 ... Insulating film, 8 ... P-type semiconductor region, 9
... n ⁺ type semiconductor region, 10 ... Insulating film, 11 ... Opening, 12
A ... Source wiring, 12B ... Gate wiring, 13 ... Final protective film, 14 ... Drain electrode.

Continued front page    (72) Inventor Sumito Numazawa             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within (72) Inventor Yoshito Nakazawa             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Masayoshi Kobayashi             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Satoshi Kudo             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Yasuo Imai             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Sakae Kubo             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Takashi Shigematsu             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within (72) Inventor Shohiro Onishi             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within (72) Inventor Kozo Uesawa             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within (72) Inventor Kentaro Oishi             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within F-term (reference) 5F058 BA01 BD01 BE10 BF02 BF55

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device having a transistor element having a trench gate structure, wherein a groove is formed from a main surface of a semiconductor layer in a depth direction thereof, and a sacrificial thermal oxide film is formed on an inner surface of the groove. After the formation, the sacrificial thermal oxide film is removed, a gate insulating film made of a deposited film is formed on the inner surface of the groove from which the sacrificial thermal oxide film is removed, and a gate electrode is formed in the groove, A method of manufacturing a semiconductor device, comprising forming a semiconductor region by introducing impurities into the semiconductor layer. 2. A method of manufacturing a semiconductor device having a MISFET having a trench gate structure, wherein a groove is formed from a main surface of a semiconductor layer in a depth direction thereof, and a sacrificial thermal oxide film is formed on an inner surface of the groove. Then, the sacrificial thermal oxide film is removed, a gate insulating film made of a deposited film is formed on the inner surface of the groove from which the sacrificial thermal oxide film has been removed, and a gate electrode is formed in the groove. Impurity is introduced into the semiconductor layer to form a first conductivity type semiconductor region which becomes a channel formation region, and impurities are introduced into the first conductivity type semiconductor region to form a second conductivity type semiconductor region which is a source region. A method for manufacturing a semiconductor device, comprising: 3. The formation of the sacrificial thermal oxide film is 1000 times.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the method is performed in an oxygen gas atmosphere of [° C.] or higher or in an oxygen gas atmosphere diluted with nitrogen gas.