JP2007109770A - Plasma treatment apparatus and plasma treatment method - Google Patents

Plasma treatment apparatus and plasma treatment method Download PDF

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JP2007109770A
JP2007109770A JP2005297378A JP2005297378A JP2007109770A JP 2007109770 A JP2007109770 A JP 2007109770A JP 2005297378 A JP2005297378 A JP 2005297378A JP 2005297378 A JP2005297378 A JP 2005297378A JP 2007109770 A JP2007109770 A JP 2007109770A
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substrate
tray
plasma processing
processing apparatus
placement
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JP4361045B2 (en
JP2007109770A5 (en
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Shogo Okita
尚吾 置田
Hiromi Asakura
浩海 朝倉
Akizo Watanabe
彰三 渡邉
Riyuuzou Houchin
隆三 宝珍
Hiroyuki Suzuki
宏之 鈴木
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2005297378A priority Critical patent/JP4361045B2/en
Priority to PCT/JP2006/320216 priority patent/WO2007043528A1/en
Priority to US12/090,214 priority patent/US7736528B2/en
Priority to KR1020097025501A priority patent/KR101153118B1/en
Priority to KR1020087008556A priority patent/KR100964775B1/en
Priority to TW098136303A priority patent/TW201015638A/en
Priority to TW095137303A priority patent/TWI326468B/en
Publication of JP2007109770A publication Critical patent/JP2007109770A/en
Publication of JP2007109770A5 publication Critical patent/JP2007109770A5/ja
Priority to US12/578,844 priority patent/US8231798B2/en
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Publication of JP4361045B2 publication Critical patent/JP4361045B2/en
Priority to US13/527,807 priority patent/US8591754B2/en
Priority to US14/061,984 priority patent/US20140048527A1/en
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Abstract

<P>PROBLEM TO BE SOLVED: To improve the cooling efficiency of a substrate by holding the substrate with high adhesiveness to a substrate susceptor in a plasma treatment apparatus, and to uniformize treatment in the entire region on the surface of the substrate including a portion near the periphery edge. <P>SOLUTION: A tray 15 of a dry etching device 1 has substrate housing holes 19A-19D passing through in a thickness direction, and a substrate support 21 for supporting the periphery edge of the lower surface 2a of the substrate 2. A dielectric plate 23 has a tray support surface 28 for supporting the lower surface of the tray 15; and substrate placement parts 29A-29D that are inserted into the substrate housing holes 19A-19D from the lower-surface side of the tray 15, and allow the substrate 2 to be placed on the substrate placement surface 31 of an upper end face. A DC voltage application mechanism 43 applies a DC voltage to an electrode 40 for electrostatic adsorption. A heat transfer gas supply mechanism 45 supplies a heat transfer gas between the substrate 2 and the substrate placement surface 31. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、ドライエッチング装置、CVD装置等のプラズマ処理装置及びプラズマ処理方法に関する。   The present invention relates to a plasma processing apparatus such as a dry etching apparatus and a CVD apparatus, and a plasma processing method.

特許文献1には、基板を収容した有底のトレイを下部電極として機能する基板サセプタ上に配置し、トレイを介して間接的に基板を基板サセプタに対して静電吸着する構成のプラズマ処理装置が開示されている。基板サセプタの冷却機構が設けられており、基板はトレイを介した基板サセプタとの間接的な熱伝導により冷却される。   Patent Document 1 discloses a plasma processing apparatus having a configuration in which a bottomed tray containing a substrate is disposed on a substrate susceptor that functions as a lower electrode, and the substrate is indirectly electrostatically attracted to the substrate susceptor via the tray. Is disclosed. A substrate susceptor cooling mechanism is provided, and the substrate is cooled by indirect heat conduction with the substrate susceptor via the tray.

特許文献2には、基板を収容した有底のトレイを基板サセプタ上に配置すると共に、基板の外周縁付近をクランプリングにより基板サセプタ側に押し付け、それによって基板を基板サセプタに対して固定する構成のプラズマ処理装置が開示されている。トレイを貫通して基板の下面に達する流路が設けられており、この流路を介して供給される冷却ガスにより基板の裏面が冷却される。   In Patent Document 2, a bottomed tray containing a substrate is arranged on a substrate susceptor, and the vicinity of the outer periphery of the substrate is pressed against the substrate susceptor side by a clamp ring, thereby fixing the substrate to the substrate susceptor. A plasma processing apparatus is disclosed. A flow path that penetrates the tray and reaches the lower surface of the substrate is provided, and the back surface of the substrate is cooled by the cooling gas supplied through the flow path.

しかし、特許文献1に記載のプラズマ処理装置では、基板はトレイを介して間接的に基板サセプタに対して静電吸着され、トレイを介した基板サセプタとの間接的な熱伝導により冷却されるに過ぎないので、効率的に基板を冷却できない。   However, in the plasma processing apparatus described in Patent Document 1, the substrate is electrostatically attracted to the substrate susceptor indirectly via the tray, and is cooled by indirect heat conduction with the substrate susceptor via the tray. Therefore, the substrate cannot be cooled efficiently.

一方、特許文献2に記載にプラズマ処理装置では、クランプリングが存在する基板の外周縁付近で特にプラズマの状態が不安的となる傾向があり、基板の中央部分と外周縁付近で処理を均一化できない。例えば、ドライエッチングの場合、クランプリングが存在する基板の外周縁付近にはエッチングパターンを形成できない。   On the other hand, in the plasma processing apparatus described in Patent Document 2, there is a tendency that the state of plasma is particularly uneasy near the outer peripheral edge of the substrate where the clamp ring exists, and the processing is made uniform between the central portion and the outer peripheral edge of the substrate. Can not. For example, in the case of dry etching, an etching pattern cannot be formed near the outer periphery of the substrate where the clamp ring exists.

さらに、特許文献1及び2に開示されたものを含め、従来提案されている基板を収容したトレイを基板サセプタに配置する方式のプラズマ処理装置では、基板サセプタに対する基板の位置決め精度に充分な考慮がなされていない。しかし、基板サセプタに対する基板の位置決め精度は、特に1つのトレイに収容された複数の基板のバッチ処理を実現する上で重要である。   Furthermore, in the plasma processing apparatuses of the type in which conventionally proposed trays containing substrates, including those disclosed in Patent Documents 1 and 2, are arranged on the substrate susceptor, sufficient consideration is given to the positioning accuracy of the substrate with respect to the substrate susceptor. Not done. However, the substrate positioning accuracy with respect to the substrate susceptor is particularly important in realizing batch processing of a plurality of substrates accommodated in one tray.

特開2000−58514号公報JP 2000-58514 A 特開2003−197607号公報JP 2003-197607 A

本発明は、基板を収容したトレイを基板サセプタ上に配置するプラズマ処理装置において、基板サセプタに対して基板を高い密着度で保持することによる基板の冷却効率の向上、外周縁付近を含む基板表面の全領域での処理の均一化、及び基板サセプタに対する基板の位置決め精度の向上を図ることを課題とする。   The present invention relates to a plasma processing apparatus in which a tray containing a substrate is disposed on a substrate susceptor, thereby improving the cooling efficiency of the substrate by holding the substrate with high adhesion to the substrate susceptor, and the substrate surface including the vicinity of the outer periphery. It is an object of the present invention to make the processing uniform in all the regions and improve the positioning accuracy of the substrate relative to the substrate susceptor.

第1の発明は、厚み方向に貫通する基板収容孔が設けられ、この基板収容孔の孔壁から突出し、前記基板収容孔内に収容された基板の下面の外周縁部分を支持する基板支持部を備えるトレイと、前記トレイの下面を支持するトレイ支持部と、このトレイ支持部から上向きに突出し、前記トレイの下面側から前記基板収容孔に挿入され、かつその上端面である基板載置面に前記基板の下面が載置される基板載置部とを備え、前記基板を前記基板載置面に静電吸着するための静電吸着用電極が内蔵された誘電体部材と、前記静電吸着用電極に直流電圧を印加する直流電圧印加機構と、前記基板と前記基板載置面との間に伝熱ガスを供給する伝熱ガス供給機構とを備えることを特徴とする、プラズマ処理装置を提供する。   A first aspect of the present invention is a substrate support portion provided with a substrate accommodation hole penetrating in the thickness direction, protruding from a hole wall of the substrate accommodation hole, and supporting an outer peripheral edge portion of a lower surface of the substrate accommodated in the substrate accommodation hole. A tray supporting portion that supports the lower surface of the tray, a substrate mounting surface that protrudes upward from the tray supporting portion, is inserted into the substrate receiving hole from the lower surface side of the tray, and is the upper end surface of the tray A dielectric plate member having an electrostatic chucking electrode for electrostatically attracting the substrate to the substrate mounting surface, and a substrate mounting portion on which the lower surface of the substrate is mounted. A plasma processing apparatus comprising: a DC voltage application mechanism that applies a DC voltage to the adsorption electrode; and a heat transfer gas supply mechanism that supplies a heat transfer gas between the substrate and the substrate mounting surface. I will provide a.

基板の下面は、トレイを介することなく誘電体部材上に直接載置される。詳細には、トレイの下面側から基板収容孔に誘電体部材の基板載置部が挿入され、基板載置部の上端面である基板載置面に基板が載置される。従って、直流電圧印加機構から静電吸着用電極に直流電圧が印加されると、基板は基板載置面に対して高い密着度で保持される。その結果、伝熱ガスを介した基板と基板載置面との間の熱伝導性が良好で、高い冷却効率で基板を冷却できると共に、基板温度を高精度で制御できる。   The lower surface of the substrate is placed directly on the dielectric member without going through the tray. Specifically, the substrate placement portion of the dielectric member is inserted into the substrate accommodation hole from the lower surface side of the tray, and the substrate is placed on the substrate placement surface which is the upper end surface of the substrate placement portion. Therefore, when a DC voltage is applied to the electrostatic chucking electrode from the DC voltage application mechanism, the substrate is held with high adhesion to the substrate mounting surface. As a result, the thermal conductivity between the substrate and the substrate mounting surface through the heat transfer gas is good, the substrate can be cooled with high cooling efficiency, and the substrate temperature can be controlled with high accuracy.

基板は基板載置面に直接載置され、かつ静電吸着されるので、基板の上面の外周縁部分を誘電体部材に対して機械的に押圧するためのクランプリング等の部材は不要である。換言すれば、プラズマ処理の対象となる基板の上面には、その中央部分だけでなく外周縁付近にもプラズマの状態が不安定化する原因となる部材が存在しない。従って、外周縁付近を含む基板表面の全領域で均一なプラズマ処理を実現できる。   Since the substrate is directly mounted on the substrate mounting surface and is electrostatically attracted, a member such as a clamp ring for mechanically pressing the outer peripheral edge portion of the upper surface of the substrate against the dielectric member is unnecessary. . In other words, there is no member on the upper surface of the substrate to be subjected to plasma processing that causes the plasma state to become unstable not only in the central portion but also in the vicinity of the outer peripheral edge. Therefore, uniform plasma processing can be realized in the entire region of the substrate surface including the vicinity of the outer peripheral edge.

トレイの基板収容孔内に基板載置部が進入することにより、基板が基板載置面に載置される。従って、基板載置面に高い位置決め精度で基板を保持できる。   The substrate is placed on the substrate placement surface by the substrate placement portion entering the substrate accommodation hole of the tray. Accordingly, the substrate can be held on the substrate mounting surface with high positioning accuracy.

具体的には、前記トレイの下面から前記基板支持部の上面までの距離は、前記トレイ支持部から前記基板載置面までの距離よりも短い。   Specifically, the distance from the lower surface of the tray to the upper surface of the substrate support portion is shorter than the distance from the tray support portion to the substrate placement surface.

また、プラズマ処理装置は、上面に前記誘電体部材が固定された支持部材と、前記支持部材を冷却する冷却機構とをさらに備える。   The plasma processing apparatus further includes a support member having the dielectric member fixed on an upper surface thereof, and a cooling mechanism for cooling the support member.

前記基板支持部は、前記トレイの下面側から上面側に向けて、前記基板収容孔の孔壁からの突出量が増大していることが好ましい。また、前記基板載置部は、前記基板載置面側から前記トレイ支持部に向けて前記基板収容孔の貫通方向から見た外形寸法が増大していることが好ましい。   It is preferable that the amount of protrusion of the substrate support portion from the hole wall of the substrate accommodation hole increases from the lower surface side to the upper surface side of the tray. Moreover, it is preferable that the said board | substrate mounting part is increasing the external dimension seen from the penetration direction of the said board | substrate accommodation hole toward the said tray support part from the said board | substrate mounting surface side.

基板載置部はトレイの下面側から基板収容孔に挿入される。従って、基板支持部の突出量や基板載置部の外形寸法を、このように設定することにより、基板収容孔と基板載置部との間に仮に微細なずれが存在している場合でも、基板載置部は基板収容孔内に円滑かつ確実に挿入され、基板載置面に対する基板の位置決め精度がさらに向上する。   The substrate placement portion is inserted into the substrate accommodation hole from the lower surface side of the tray. Therefore, by setting the protrusion amount of the substrate support part and the outer dimensions of the substrate mounting part in this way, even if there is a minute deviation between the substrate accommodation hole and the substrate mounting part, The substrate placement portion is smoothly and reliably inserted into the substrate accommodation hole, and the positioning accuracy of the substrate with respect to the substrate placement surface is further improved.

例えば、前記基板支持部は、前記基板収容孔の孔壁の全周に設けられた環状である。   For example, the substrate support portion has an annular shape provided on the entire circumference of the hole wall of the substrate accommodation hole.

また、前記基板支持部は、前記基板収容孔の前記孔壁に周方向に間隔を開けて複数個設けられていてもよい。この場合、前記基板載置部の外周面に、前記基板載置面から前記トレイ支持部に向けて延び、前記基板支持部が収容される収容溝が形成されていることが好ましい。基板載置部に対する基板収容孔の位置が比較的大きくずれている場合、基板支持部と基板載置部が干渉するので基板収容孔に対する基板載置部の進入が妨げられる。従って、収容溝を設けることにより、誘電体部材の基板載置面に対する基板の位置決め精度がさらに向上する。   In addition, a plurality of the substrate support portions may be provided at intervals in the circumferential direction on the hole wall of the substrate accommodation hole. In this case, it is preferable that an accommodation groove that extends from the substrate placement surface toward the tray support portion and accommodates the substrate support portion is formed on the outer peripheral surface of the substrate placement portion. When the position of the substrate accommodation hole with respect to the substrate placement portion is relatively largely shifted, the substrate support portion and the substrate placement portion interfere with each other, so that the substrate placement portion enters the substrate accommodation hole. Therefore, by providing the accommodation groove, the positioning accuracy of the substrate with respect to the substrate mounting surface of the dielectric member is further improved.

プラズマ処理装置は、前記基板載置部を取り囲む環状であって、かつ内周面が下面から上面に向けて拡がる環状のガイドプレートをさらに備え、前記トレイの外周面は、下面側から上面側に向けて外形寸法が増大し、かつ前記トレイの下面を前記トレイ支持部に載置すると前記ガイドプレートの内周面と密接してもよい。トレイを誘電体部材に載置する際に、トレイの外周面がガイドプレートの内周面に案内されるので、誘電体部材の基板載置面に対する基板の位置決め精度がさらに向上する。   The plasma processing apparatus further includes an annular guide plate having an annular shape surrounding the substrate mounting portion and an inner peripheral surface extending from the lower surface toward the upper surface, and the outer peripheral surface of the tray extends from the lower surface side to the upper surface side. When the outer dimension of the tray increases and the lower surface of the tray is placed on the tray support, the guide plate may be in close contact with the inner peripheral surface. When the tray is mounted on the dielectric member, the outer peripheral surface of the tray is guided by the inner peripheral surface of the guide plate, so that the positioning accuracy of the substrate with respect to the substrate mounting surface of the dielectric member is further improved.

記直流電圧印加機構により印加される前記直流電圧に重畳して、バイアス電圧としての高周波を前記静電吸着用電極に印加する高周波印加機構をさらに備えてもよい。かかる構成によりトレイの消耗を低減できる。 A high-frequency application mechanism that applies a high frequency as a bias voltage to the electrode for electrostatic attraction may be further provided so as to be superimposed on the DC voltage applied by the DC voltage application mechanism. With this configuration, the consumption of the tray can be reduced.

また、前記誘電体部材に内蔵され、前記静電吸着用電極と電気的に絶縁されたバイアス印加用電極と、前記バイアス印加用電極に高周波を印加する高周波印加機構とをさらに備えてもよい。   Further, a bias applying electrode built in the dielectric member and electrically insulated from the electrostatic attraction electrode, and a high frequency applying mechanism for applying a high frequency to the bias applying electrode may be further provided.

静電吸着用電極は、単極型であっても、双極型であってもよい。   The electrode for electrostatic attraction may be a monopolar type or a bipolar type.

例えば、前記トレイに前記基板収容孔が1個設けられ、前記誘電体部材には前記基板載置部が1個設けられている。かかる構成により枚葉処理が可能である。   For example, the tray is provided with one substrate accommodation hole, and the dielectric member is provided with one substrate mounting portion. With this configuration, single wafer processing is possible.

あるいは、前記トレイに前記基板収容孔が複数個設けられ、前記誘電体部材は前記基板載置部を複数個備え、個々の前記基板載置部がそれぞれ個々の前記基板収容孔に挿入されてもよい。かかる構成により、複数の基板のバッチ処理が可能である。   Alternatively, a plurality of the substrate accommodation holes are provided in the tray, the dielectric member includes a plurality of the substrate placement portions, and each of the substrate placement portions is inserted into each of the substrate accommodation holes. Good. With this configuration, batch processing of a plurality of substrates is possible.

基板収容孔と基板載置部が複数ある場合、前記基板載置部は、前記基板載置面の外周縁から上向きに突出し、その上端面で前記基板の下面を支持する環状突出部を備え、前記基板の下面と前記環状突出部で囲まれた空間に前記伝熱ガス供給機構によって前記伝熱ガスが供給されることが好ましい。個々の基板毎に基板の下面と環状突出部で囲まれた空間に伝熱ガスが充填されるので、個々の基板と誘電体部材との間の熱伝導性がより向上する。   When there are a plurality of substrate receiving holes and substrate mounting portions, the substrate mounting portion includes an annular protrusion that protrudes upward from the outer peripheral edge of the substrate mounting surface and supports the lower surface of the substrate at its upper end surface, It is preferable that the heat transfer gas is supplied to the space surrounded by the lower surface of the substrate and the annular protrusion by the heat transfer gas supply mechanism. Since the heat transfer gas is filled in the space surrounded by the lower surface of the substrate and the annular protrusion for each individual substrate, the thermal conductivity between the individual substrate and the dielectric member is further improved.

また、基板収容孔と基板載置部が複数ある場合、前記基板載置部毎に、個別に制御可能な前記伝熱ガス供給機構が設けられていることが好ましい。基板毎に伝熱ガスを制御することにより、基板の冷却効率と基板温度の制御精度がさらに向上する。   In addition, when there are a plurality of substrate receiving holes and substrate mounting portions, it is preferable that the heat transfer gas supply mechanism that can be individually controlled is provided for each of the substrate mounting portions. By controlling the heat transfer gas for each substrate, the cooling efficiency of the substrate and the control accuracy of the substrate temperature are further improved.

さらに、基板収容孔と基板載置部が複数ある場合、前記複数の基板載置部に電気的に絶縁された前記静電吸着用電極がそれぞれ内蔵されていることが好ましい。特に、前記静電吸着用電極毎に、個別に制御可能な前記直流電圧印加機構が設けられていることが好ましい。静電吸着用電極毎に個別に直流電圧を調整できるので、複数の基板間での静電吸着力のばらつきをなくし、均一化できる。   Furthermore, when there are a plurality of substrate receiving holes and a plurality of substrate placement portions, it is preferable that the plurality of substrate placement portions each include the electrostatic attraction electrodes electrically insulated. In particular, it is preferable that the DC voltage application mechanism that can be individually controlled is provided for each of the electrostatic adsorption electrodes. Since the DC voltage can be individually adjusted for each electrostatic chucking electrode, variations in electrostatic chucking force among a plurality of substrates can be eliminated and uniformized.

また、前記静電吸着用電極毎に、前記直流電圧印加機構により印加される前記直流電圧に重畳して、プラズマ発生用の高周波を前記静電吸着用電圧に印加する個別に制御可能な高周波印加機構をさらに備えることが好ましい。個々の基板の特性に応じて静電吸着用電極毎に個別にバイアス電圧として印加される高周波のパワーを調整できるので、複数の基板間でばらつきのない均一なプラズマ処理を実現できる。   In addition, for each of the electrostatic adsorption electrodes, an individually controllable high frequency application that applies a high frequency for plasma generation to the electrostatic adsorption voltage superimposed on the DC voltage applied by the DC voltage application mechanism. It is preferable to further include a mechanism. Since the high frequency power applied as a bias voltage can be adjusted individually for each electrode for electrostatic attraction according to the characteristics of each substrate, uniform plasma processing without variation among a plurality of substrates can be realized.

第2の発明は、厚み方向に貫通する基板収容孔が設けられ、この基板収容孔の孔壁から突出する基板支持部を有するトレイを準備し、前記トレイの前記基板収容孔に基板を収容し、前記トレイの下面側から見ると前記基板収容孔により前記基板の下面が露出するように、前記基板支持部で前記基板の下面の外周縁部分を支持させ、真空容器内に収容された誘電体部材の上方に前記基板を収容した前記トレイを配置し、前記トレイを前記誘電体部材に向けて降下させ、前記トレイの下面を前記絶縁部材のトレイ支持部で支持させると共に、前記トレイ支持部から突出する基板載置部を前記トレイの下面側から前記基板収容孔に侵入させ、前記基板載置部の上端面である基板載置面に基板の下面を載置し、前記誘電体部材に内蔵された静電吸着用電極に直流電圧を印加して、前記基板載置面に前記基板を静電吸着させ、前記基板の下面と前記基板載置面との間に伝熱ガスを供給し、前記真空容器内にプラズマを発生させる、プラズマ処理方法を提供する。   According to a second aspect of the present invention, there is provided a tray having a substrate accommodation hole penetrating in the thickness direction and having a substrate support portion protruding from a hole wall of the substrate accommodation hole, and accommodating the substrate in the substrate accommodation hole of the tray. The dielectric supported in the vacuum container by supporting the outer peripheral edge portion of the lower surface of the substrate by the substrate support portion so that the lower surface of the substrate is exposed by the substrate accommodation hole when viewed from the lower surface side of the tray The tray containing the substrate is disposed above the member, the tray is lowered toward the dielectric member, and the lower surface of the tray is supported by the tray support portion of the insulating member, and from the tray support portion. The protruding substrate mounting portion is made to enter the substrate receiving hole from the lower surface side of the tray, the lower surface of the substrate is mounted on the substrate mounting surface which is the upper end surface of the substrate mounting portion, and is built in the dielectric member For electrostatic adsorption A DC voltage is applied to the electrode, the substrate is electrostatically adsorbed on the substrate mounting surface, a heat transfer gas is supplied between the lower surface of the substrate and the substrate mounting surface, and plasma is generated in the vacuum container. A plasma processing method is provided.

本発明に係るプラズマ処理装置及びプラズマ処理方法によれば、基板はトレイを介することなく誘電体部材の基板載置面に直接載置され、かつ静電吸着されるので、基板載置面に対して基板を高い密着度で保持でき、基板の冷却効率を向上し、基板温度を高精度で制御できる。また、基板の上面の外周縁部分を誘電体部材に対して機械的に押圧するためのクランプリング等の部材は不要であるので、外周縁付近を含む基板表面の全領域での均一なプラズマ処理を実現できる。さらに、トレイの基板収容孔内に基板載置部が挿入されることにより基板が基板載置面に載置されるので、誘電体部材に対する基板の位置決め精度を向上できる。   According to the plasma processing apparatus and the plasma processing method according to the present invention, the substrate is directly placed on the substrate placement surface of the dielectric member without passing through the tray, and is electrostatically adsorbed. The substrate can be held with high adhesion, the cooling efficiency of the substrate can be improved, and the substrate temperature can be controlled with high accuracy. In addition, since a member such as a clamp ring for mechanically pressing the outer peripheral edge portion of the upper surface of the substrate against the dielectric member is unnecessary, uniform plasma processing in the entire area of the substrate surface including the vicinity of the outer peripheral edge. Can be realized. Further, since the substrate is placed on the substrate placement surface by inserting the substrate placement portion into the substrate accommodation hole of the tray, the positioning accuracy of the substrate with respect to the dielectric member can be improved.

(第1実施形態)
図1及び図2は、本発明の第1実施形態に係るICP(誘導結合プラズマ)型のドライエッチング装置1を示す。
(First embodiment)
1 and 2 show an ICP (inductively coupled plasma) type dry etching apparatus 1 according to a first embodiment of the present invention.

ドライエッチング装置1は、その内部が基板2にプラズマ処理を行う処理室を構成するチャンバ(真空容器)3を備える。チャンバ3の上端開口は石英等の誘電体からなる天板4により密閉状態で閉鎖されている。天板4上にはICPコイル5が配設されている。ICPコイル5にはマッチング回路6を介して、高周波電源7が電気的に接続されている。天板4と対向するチャンバ3内の底部側には、バイアス電圧が印加される下部電極としての機能及び基板2の保持台としての機能を有する基板サセプタ9が配設されている。チャンバ3には、隣接するロードドック室10(図2参照)と連通する開閉可能な搬入出用のゲート3aが設けられている。また、チャンバ3に設けられたエッチングガス供給口3bには、エッチングガス供給源12が接続されている。エッチングガス供給源12はMFC(マスフローコントローラ)等を備え、エッチングガス供給口3bから所望の流量でエッチングガスを供給できる。さらに、チャンバ3に設けられた排気口3cには、真空ポンプ等を備える真空排気装置13が接続されている。   The dry etching apparatus 1 includes a chamber (vacuum container) 3 that constitutes a processing chamber in which plasma processing is performed on the substrate 2. The upper end opening of the chamber 3 is closed in a sealed state by a top plate 4 made of a dielectric material such as quartz. An ICP coil 5 is disposed on the top plate 4. A high frequency power source 7 is electrically connected to the ICP coil 5 via a matching circuit 6. A substrate susceptor 9 having a function as a lower electrode to which a bias voltage is applied and a function as a holding table for the substrate 2 is disposed on the bottom side in the chamber 3 facing the top plate 4. The chamber 3 is provided with a loading / unloading gate 3a that can be opened and closed and communicates with an adjacent load dock chamber 10 (see FIG. 2). An etching gas supply source 12 is connected to the etching gas supply port 3 b provided in the chamber 3. The etching gas supply source 12 includes an MFC (mass flow controller) or the like, and can supply an etching gas at a desired flow rate from the etching gas supply port 3b. Further, a vacuum exhaust device 13 including a vacuum pump or the like is connected to the exhaust port 3 c provided in the chamber 3.

本実施形態では、図3から図4Bに示す1個のトレイ15に4枚の基板2が収容され、トレイ15はゲート3aを通ってロードドック室10からチャンバ3内(処理室)に搬入される。図2を参照すると、水平方向の直進移動(矢印A参照)と水平面内での回転(矢印B参照)が可能な搬送アーム16が設けられている。また、チャンバ3内には、基板サセプタ9を貫通し、かつ駆動装置17で駆動されて昇降する昇降ピン18が設けられている。トレイ15の搬入時には、トレイ15を支持した搬送アーム16がゲート3aを通ってロードドック室10からチャンバ3内に進入する。この際、図1において二点鎖線で示すように昇降ピン18は上昇位置にあり、チャンバ3内に進入した搬送アーム16から昇降ピン18の上端にトレイ15が移載される。この状態では、トレイ15は基板サセプタ9の上方に間隔をあけて位置している。続いて、昇降ピン18が図1において実線で示す降下位置に降下し、それによってトレイ15と基板2が基板サセプタ9上に載置される。一方、プラズマ処理終了後のトレイ15の搬出時には、昇降ピン18が上昇位置まで上昇し、続いてロードドック室10からチャンバ3内に進入した搬送アーム16にトレイ15が移載される。   In this embodiment, four substrates 2 are accommodated in one tray 15 shown in FIGS. 3 to 4B, and the tray 15 is carried into the chamber 3 (processing chamber) from the load dock chamber 10 through the gate 3a. The Referring to FIG. 2, there is provided a transfer arm 16 that can move in a horizontal direction (see arrow A) and rotate in a horizontal plane (see arrow B). In the chamber 3, lift pins 18 that pass through the substrate susceptor 9 and are driven by a drive device 17 to move up and down are provided. When the tray 15 is carried in, the transfer arm 16 that supports the tray 15 enters the chamber 3 from the load dock chamber 10 through the gate 3a. At this time, as shown by a two-dot chain line in FIG. 1, the lifting pins 18 are in the raised position, and the tray 15 is transferred from the transfer arm 16 that has entered the chamber 3 to the upper end of the lifting pins 18. In this state, the tray 15 is positioned above the substrate susceptor 9 with a gap. Subsequently, the elevating pins 18 are lowered to the lowered position indicated by the solid line in FIG. 1, whereby the tray 15 and the substrate 2 are placed on the substrate susceptor 9. On the other hand, when the tray 15 is unloaded after the plasma processing, the elevating pins 18 are raised to the raised position, and then the tray 15 is transferred from the load dock chamber 10 to the transfer arm 16 that has entered the chamber 3.

次に、図3から図5Bを参照して、トレイ15について説明する。トレイ15は薄板円板状のトレイ本体15aを備える。トレイ15の材質としては、例えばアルミナ(Al2O3)、窒化アルミニウム(AlN)、ジルコニア(ZrO)、イットリア(Y2O3)、窒化シリコン(SiN)、炭化シリコン(SiC)等のセラミクス材や、アルマイトで被覆したアルミニウム、表面にセラミクスを溶射したアルミニウム、樹脂材料で被覆したアルミニウム等の金属がある。Cl系プロセスの場合にはアルミナ、イットリア、炭化シリコン、窒化アルミニウム等、F系プロセスの場合には石英、水晶、イットリア、炭化シリコン、アルマイトを容射したアルミニウム等を採用することが考えられる。 Next, the tray 15 will be described with reference to FIGS. 3 to 5B. The tray 15 includes a thin disc-shaped tray body 15a. Examples of the material of the tray 15 include ceramic materials such as alumina (Al 2 O 3 ), aluminum nitride (AlN), zirconia (ZrO), yttria (Y 2 O 3 ), silicon nitride (SiN), and silicon carbide (SiC). There are also metals such as aluminum coated with alumite, aluminum coated with ceramics on the surface, and aluminum coated with a resin material. It is conceivable to employ alumina, yttria, silicon carbide, aluminum nitride or the like in the case of a Cl-based process, and aluminum or the like which applies quartz, quartz, yttria, silicon carbide, anodized or the like in the case of an F-based process.

トレイ本体15aには、上面15bから下面15cまで厚み方向に貫通する4個の基板収容孔19A〜19Dが設けられている。基板収容孔19A〜19Dは、上面15b及び下面15cから見てトレイ本体15aの中心に対して等角度間隔で配置されている。図5A及び図5Bに最も明瞭に示すように、基板収容孔19A〜19Dの孔壁15dの下面15c側には、基板収容孔19A〜19Dの中心に向けて突出する基板支持部21が設けられている。本実施形態では、基板支持部21は孔壁15dの全周に設けられており、平面視で円環状である。   The tray body 15a is provided with four substrate accommodation holes 19A to 19D that penetrate in the thickness direction from the upper surface 15b to the lower surface 15c. The substrate accommodation holes 19A to 19D are arranged at equiangular intervals with respect to the center of the tray body 15a when viewed from the upper surface 15b and the lower surface 15c. As shown most clearly in FIGS. 5A and 5B, a substrate support portion 21 that protrudes toward the center of the substrate accommodation holes 19A to 19D is provided on the lower surface 15c side of the hole wall 15d of the substrate accommodation holes 19A to 19D. ing. In this embodiment, the board | substrate support part 21 is provided in the perimeter of the hole wall 15d, and is annular | circular shape by planar view.

個々の基板収容孔19A〜19Bにはそれぞれ1枚の基板2が収容される。図5Aに示すように、基板収容孔19A〜19Bに収容された基板2は、その下面2aの外周縁部分が基板支持部21の上面21aに支持される。また、前述のように基板収容孔19A〜19Dはトレイ本体15aを厚み方向に貫通するように形成されているので、トレイ本体15aの下面15c側から見ると、基板収容孔19A〜19Dにより基板2の下面2aが露出している。   One substrate 2 is accommodated in each of the substrate accommodation holes 19A to 19B. As shown in FIG. 5A, the outer peripheral edge portion of the lower surface 2 a of the substrate 2 accommodated in the substrate accommodation holes 19 </ b> A to 19 </ b> B is supported by the upper surface 21 a of the substrate support portion 21. Further, as described above, the substrate accommodation holes 19A to 19D are formed so as to penetrate the tray main body 15a in the thickness direction. Therefore, when viewed from the lower surface 15c side of the tray main body 15a, the substrate accommodation holes 19A to 19D allow the substrate 2 to pass through. The lower surface 2a is exposed.

トレイ本体15aには、外周縁を部分的に切り欠いた位置決め切欠15eが設けられている。図2に示すように、前述の搬入出用の搬送アーム16にトレイを載置する際に、位置決め切欠15eに搬送アーム16の位置決め突起16aが嵌め込まれる。位置決め切欠15e及び位置決め突起16aをロードドック室10内に設けられたセンサ22A,22Bで検出することにより、トレイ15の回転角度位置を検出できる。   The tray body 15a is provided with a positioning cutout 15e in which the outer peripheral edge is partially cut out. As shown in FIG. 2, when the tray is placed on the carry-in / out carrying arm 16, the positioning protrusion 16a of the carrying arm 16 is fitted into the positioning notch 15e. By detecting the positioning notches 15e and the positioning protrusions 16a with the sensors 22A and 22B provided in the load dock chamber 10, the rotational angle position of the tray 15 can be detected.

次に、図1、図3、及び図5Aから図6Bを参照して、基板サセプタ9について説明する。まず、図1を参照すると、基板サセプタ9は、セラミクス等からなる誘電体板(誘電体部材)23、表面にアルマイト被覆を形成したアルミニウム等からなり、本実施形態ではペデスタル電極として機能する金属板(支持部材)24、セラミクス等からなるスペーサ板25、セラミクス等からなるガイド筒体26、及び金属製のアースシールド27を備える。基板サセプタ9の最上部を構成する誘電体板23は、金属板24の上面に固定されている。また、金属板24はスペーサ板25上に固定されている。さらに、誘電体板23と金属板24の外周をガイド筒26が覆い、その外側とスペーサ板25の外周をアースシールド27が覆っている。   Next, the substrate susceptor 9 will be described with reference to FIGS. 1, 3, and 5A to 6B. First, referring to FIG. 1, the substrate susceptor 9 is made of a dielectric plate (dielectric member) 23 made of ceramics or the like, aluminum having an alumite coating on the surface, etc., and in this embodiment, a metal plate that functions as a pedestal electrode (Support member) 24, a spacer plate 25 made of ceramics or the like, a guide cylinder 26 made of ceramics or the like, and a metal earth shield 27 are provided. The dielectric plate 23 constituting the uppermost part of the substrate susceptor 9 is fixed to the upper surface of the metal plate 24. The metal plate 24 is fixed on the spacer plate 25. Further, the guide cylinder 26 covers the outer periphery of the dielectric plate 23 and the metal plate 24, and the earth shield 27 covers the outer periphery thereof and the outer periphery of the spacer plate 25.

図3及び図5Aから図6Bを参照すると、誘電体板23は全体として薄い円板状であり、平面視での外形が円形である。誘電体板23の上端面は、トレイ15の下面15cを支持するトレイ支持面(トレイ支持部)28を構成する。また、それぞれトレイ15の基板収容孔19A〜19Dと対応する短円柱状の4個の基板載置部29A〜29Dがトレイ支持面28から上向きに突出している。   Referring to FIGS. 3 and 5A to 6B, the dielectric plate 23 has a thin disk shape as a whole and has a circular outer shape in plan view. The upper end surface of the dielectric plate 23 constitutes a tray support surface (tray support portion) 28 that supports the lower surface 15 c of the tray 15. Further, four short columnar substrate placement portions 29A to 29D respectively corresponding to the substrate accommodation holes 19A to 19D of the tray 15 protrude upward from the tray support surface 28.

基板載置部29A〜29Dの上端面は、基板2の下面2aが載置される基板載置面31を構成する。また、基板載置部29A〜29Dには、基板載置面31の外周縁から上向きに突出し、その上端面が基板2の下面2aを支持する円環状突出部32が設けられている。また、基板載置面31の円環状突出部32で囲まれた部分には、基板載置面31よりも十分径が小さい円柱状突起33が、均一に分布するように複数個設けられている。円柱状突起33と円環状突出部32の基板載置面31からの突出量は同一であり、円環状突出部32のみでなく円柱状突起33の上端面も基板2の下面2aを支持する。   The upper end surfaces of the substrate placement portions 29A to 29D constitute a substrate placement surface 31 on which the lower surface 2a of the substrate 2 is placed. Further, the substrate placement portions 29 </ b> A to 29 </ b> D are provided with an annular protrusion 32 that protrudes upward from the outer peripheral edge of the substrate placement surface 31 and whose upper end surface supports the lower surface 2 a of the substrate 2. In addition, a plurality of columnar projections 33 having a sufficiently smaller diameter than the substrate mounting surface 31 are provided in a portion surrounded by the annular protrusion 32 of the substrate mounting surface 31 so as to be uniformly distributed. . The protruding amount of the cylindrical protrusion 33 and the annular protrusion 32 from the substrate mounting surface 31 is the same, and not only the annular protrusion 32 but also the upper end surface of the cylindrical protrusion 33 supports the lower surface 2 a of the substrate 2.

図5A及び図5Bを参照すると、基板載置部29A〜29Dの外径R1は、基板支持部21の先端面21bで囲まれた円形開口36の径R2よりも小さく設定されている。従って、前述の搬入時にトレイ15が誘電体板23に向けて降下すると、個々の基板載置部29A〜29Dは対応する基板収容孔19A〜19Dにトレイ本体15aの下面15c側から進入し、トレイ15の下面15cは誘電体板23のトレイ支持面28上に載置される。また、トレイ本体15aの下面15cからの基板支持部21の上面21aの高さH1は、トレイ支持面28からの基板載置面31の高さH2よりも低く設定している。従って、トレイ15の下面15cがトレイ支持面28上に載置された状態では、基板載置部29A〜29Dの上端の基板載置面31で押し上げられ、トレイ15の基板支持部21から浮き上がっている。換言すれば、基板収容孔19A〜19Dに基板2を収容しているトレイ15を誘電体板23上に載置すると、基板収容孔19A〜19Dに収容された基板2は基板支持部21の上面21aから浮き上がり、下面2aが基板載置面31上に載置される。   5A and 5B, the outer diameter R1 of the substrate placement portions 29A to 29D is set to be smaller than the diameter R2 of the circular opening 36 surrounded by the front end surface 21b of the substrate support portion 21. Accordingly, when the tray 15 is lowered toward the dielectric plate 23 at the time of carrying in, the individual substrate placement portions 29A to 29D enter the corresponding substrate accommodation holes 19A to 19D from the lower surface 15c side of the tray main body 15a, and the tray. The lower surface 15 c of 15 is placed on the tray support surface 28 of the dielectric plate 23. Further, the height H1 of the upper surface 21a of the substrate support portion 21 from the lower surface 15c of the tray body 15a is set lower than the height H2 of the substrate placement surface 31 from the tray support surface 28. Therefore, in a state where the lower surface 15 c of the tray 15 is placed on the tray support surface 28, the tray 15 is pushed up by the substrate placement surface 31 at the upper end of the substrate placement portions 29 </ b> A to 29 </ b> D and lifts from the substrate support portion 21 of the tray 15. Yes. In other words, when the tray 15 that accommodates the substrate 2 in the substrate accommodation holes 19 </ b> A to 19 </ b> D is placed on the dielectric plate 23, the substrate 2 accommodated in the substrate accommodation holes 19 </ b> A to 19 </ b> D becomes the upper surface of the substrate support portion 21. The lower surface 2 a is placed on the substrate placement surface 31.

また、図5A及び図5Bに示すように、基板載置部29A〜29Dの外周面38と基板載置面31との接続部分は丸面に面取りしている。従って、基板載置部29A〜29Dの上端側では基板収容孔19A〜19Dの貫通方向から見た外径が、基板載置面31側からトレイ支持面28に向けて増大している。一方、基板載置部29A〜29Dの外周面38の下端側では基板収容孔19A〜19Dの貫通方向から見た外径が一定できる。   Further, as shown in FIGS. 5A and 5B, the connection portion between the outer peripheral surface 38 of the substrate placement portions 29 </ b> A to 29 </ b> D and the substrate placement surface 31 is chamfered into a round surface. Therefore, on the upper end side of the substrate placement portions 29A to 29D, the outer diameter viewed from the through direction of the substrate accommodation holes 19A to 19D increases from the substrate placement surface 31 side toward the tray support surface 28. On the other hand, on the lower end side of the outer peripheral surface 38 of the substrate placement portions 29A to 29D, the outer diameter viewed from the penetration direction of the substrate accommodation holes 19A to 19D can be constant.

図1を参照すると、誘電体板23の個々の基板載置部29A〜29Dの基板載置面31付近には単極型の静電吸着用電極40が内蔵されている。これらの静電吸着用電極40は電気的に互いに絶縁されており、直流電源41と調整用の抵抗42等を備える共通の直流電圧印加機構43から静電吸着用の直流電圧が印加される。   Referring to FIG. 1, a monopolar electrostatic attraction electrode 40 is built in the vicinity of the substrate placement surface 31 of each of the substrate placement portions 29 </ b> A to 29 </ b> D of the dielectric plate 23. These electrostatic chucking electrodes 40 are electrically insulated from each other, and a DC voltage for electrostatic chucking is applied from a common DC voltage applying mechanism 43 including a DC power supply 41 and an adjusting resistor 42.

図3、図6A、及び図6Bを参照すると、個々の基板載置部29A〜29Dの基板載置面31には、伝熱ガス(本実施形態ではヘリウム)の供給孔44が設けられている。これらの供給孔44は共通の伝熱ガス供給機構45(図1に図示する)に接続されている。伝熱ガス供給機構45は、伝熱ガス源(本実施形態ではヘリウムガス源)46、伝熱ガス源46から供給孔44に到る供給流路47、供給流路47の伝熱ガス源46側から順に設けられた流量計48、流量制御バルブ49、及び圧力計50を備える。また、伝熱ガス供給機構45は、供給流路47から分岐する排出流路51と、この排出流路51に設けられたカットオフバルブ52を備える。さらに、伝熱ガス供給機構45は、供給流路47の圧力計50よりも供給孔44側と排出流路51を接続するバイパス流路53を備える。個々の基板載置部29A〜29Dの基板載置面31とその上に載置された基板2の下面2aとの間、詳細には基板2の下面2aと円環状突出部32で囲まれた閉鎖された空間に、伝熱ガス供給機構45によって伝熱ガスが供給される。伝熱ガスの供給時にはカットオフバルブ52は閉弁され、伝熱ガス供給源46から供給路47を経て供給孔44へ伝熱ガスが送られる。流量計48と圧力計50で検出される供給流路47の流量及び圧力に基づき、後述するコントローラ63が流量制御バルブ49を制御する。一方、伝熱ガスの排出時にはカットオフバルブ52が開弁され、基板2の下面2aと基板載置面31の間の伝熱ガスは、供給孔44、供給流路47、及び排出流路51を経て排気口54から排気される。   Referring to FIGS. 3, 6A, and 6B, the substrate placement surface 31 of each of the substrate placement portions 29A to 29D is provided with a supply hole 44 for heat transfer gas (helium in the present embodiment). . These supply holes 44 are connected to a common heat transfer gas supply mechanism 45 (shown in FIG. 1). The heat transfer gas supply mechanism 45 includes a heat transfer gas source (in this embodiment, a helium gas source) 46, a supply channel 47 from the heat transfer gas source 46 to the supply hole 44, and a heat transfer gas source 46 in the supply channel 47. A flow meter 48, a flow control valve 49, and a pressure gauge 50 are provided in this order from the side. The heat transfer gas supply mechanism 45 includes a discharge flow channel 51 that branches from the supply flow channel 47 and a cut-off valve 52 provided in the discharge flow channel 51. Furthermore, the heat transfer gas supply mechanism 45 includes a bypass channel 53 that connects the supply channel 44 side to the discharge channel 51 with respect to the pressure gauge 50 of the supply channel 47. Between the substrate placement surface 31 of each of the substrate placement portions 29A to 29D and the lower surface 2a of the substrate 2 placed thereon, in detail, it is surrounded by the lower surface 2a of the substrate 2 and the annular protrusion 32. The heat transfer gas is supplied to the closed space by the heat transfer gas supply mechanism 45. When supplying the heat transfer gas, the cutoff valve 52 is closed, and the heat transfer gas is sent from the heat transfer gas supply source 46 to the supply hole 44 through the supply path 47. Based on the flow rate and pressure of the supply flow path 47 detected by the flow meter 48 and the pressure gauge 50, the controller 63 described later controls the flow rate control valve 49. On the other hand, when the heat transfer gas is discharged, the cut-off valve 52 is opened, and the heat transfer gas between the lower surface 2a of the substrate 2 and the substrate placement surface 31 passes through the supply hole 44, the supply flow path 47, and the discharge flow path 51. Then, the air is exhausted from the exhaust port 54.

金属板24には、バイアス電圧としての高周波を印加する高周波印加機構56が電気的に接続されている。高周波印加機構56は、高周波電源57とマッチング用の可変容量コンデンサ58とを備える。   A high frequency applying mechanism 56 that applies a high frequency as a bias voltage is electrically connected to the metal plate 24. The high frequency applying mechanism 56 includes a high frequency power source 57 and a matching variable capacitor 58.

また、金属板24を冷却する冷却機構59が設けられている。冷却機構59は金属板24内に形成された冷媒流路60と、温調された冷媒を冷媒流路60中で循環させる冷媒循環装置61とを備える。   Further, a cooling mechanism 59 for cooling the metal plate 24 is provided. The cooling mechanism 59 includes a refrigerant flow path 60 formed in the metal plate 24 and a refrigerant circulation device 61 that circulates the temperature-controlled refrigerant in the refrigerant flow path 60.

図1にのみ模式的に示すコントローラ63は、流量計48及び圧力計50を含む種々のセンサや操作入力に基づいて、高周波電源7、エッチングガス供給源12、搬送アーム16、真空排気装置13、駆動装置17、直流電圧印加機構43、伝熱ガス供給機構45、高周波電圧印加機構56、及び冷却機構59を含むドライエッチング装置1全体の動作を制御する。   The controller 63 schematically shown only in FIG. 1 is based on various sensors and operation inputs including a flow meter 48 and a pressure gauge 50, and a high-frequency power source 7, an etching gas supply source 12, a transfer arm 16, a vacuum exhaust device 13, The operation of the entire dry etching apparatus 1 including the drive device 17, the DC voltage application mechanism 43, the heat transfer gas supply mechanism 45, the high frequency voltage application mechanism 56, and the cooling mechanism 59 is controlled.

次に、本実施形態のドライエッチング装置1を使用したドライエッチング方法を説明する。   Next, a dry etching method using the dry etching apparatus 1 of the present embodiment will be described.

まず、トレイ1の基板収容孔19A〜19Dにそれぞれ基板2が収容される。トレイ1の基板支持部21aで支持された基板2は、トレイ本体15aの下面側から見ると基板収容孔19A〜19Dによりトレイ本体15aの下面15cから露出している。   First, the board | substrate 2 is accommodated in the board | substrate accommodation holes 19A-19D of the tray 1, respectively. The substrate 2 supported by the substrate support portion 21a of the tray 1 is exposed from the lower surface 15c of the tray body 15a through the substrate housing holes 19A to 19D when viewed from the lower surface side of the tray body 15a.

次に、基板収容孔19A〜19Dにそれぞれ基板2が収容されたトレイ15が搬送アーム16で支持され、ロードドック室10からゲート3aを通ってチャンバ3内に搬入される。図1において二点鎖線で示すように、トレイ1は基板サセプタ9の上方に間隔をあけて配置される。   Next, the tray 15 that accommodates the substrate 2 in each of the substrate accommodation holes 19A to 19D is supported by the transfer arm 16, and is carried into the chamber 3 from the load dock chamber 10 through the gate 3a. As shown by a two-dot chain line in FIG. 1, the tray 1 is disposed above the substrate susceptor 9 with a gap.

駆動装置7によって駆動された昇降ピン18が上昇し、搬送アーム16から昇降ピン18の上端にトレイ15が移載される。トレイ15の移載後、搬送アーム16はロードロック室10に待避し、ゲート3aが閉鎖される。   The elevating pins 18 driven by the driving device 7 are raised, and the tray 15 is transferred from the transfer arm 16 to the upper end of the elevating pins 18. After the transfer of the tray 15, the transfer arm 16 is retracted to the load lock chamber 10, and the gate 3a is closed.

上端にトレイ15を支持した昇降ピン18は、図1において二点鎖線で示す上昇位置から基板サセプタ9に向けて降下する。図5A及び図5Bを参照すると、トレイ15は下面15cが基板サセプタ9の誘電体板23のトレイ支持面28まで降下し、トレイ15は誘電体板23のトレイ支持面28によって支持される。トレイ15がトレイ支持面28に向けて降下する際に、誘電体板23の基板載置部29A〜29Dがトレイ15の対応する基板収容孔19A〜19D内にトレイ15の下面15c側から進入する。トレイ15の下面15cがトレイ支持面28に近付くのに伴い、基板載置部29A〜29Dの先端の基板載置面31は基板収容孔19A〜19D内をトレイ15の上面15bに向かって進む。図5Bに示すように、トレイ15の下面15cが誘電体板23のトレイ支持面28に載置されると、個々の基板収容孔19A〜19D内の基板2は基板載置部29A〜29Dによって基板支持部21の上面21aから持ち上げられる。詳細には、基板2はその下面2aが基板載置部29A〜29Dの基板載置面31に載置され、トレイ15の基板支持部21の上面21aに対して間隔をあけて上方に配置される。   The raising / lowering pins 18 that support the tray 15 at the upper end are lowered toward the substrate susceptor 9 from the raised position indicated by a two-dot chain line in FIG. 5A and 5B, the lower surface 15c of the tray 15 is lowered to the tray support surface 28 of the dielectric plate 23 of the substrate susceptor 9, and the tray 15 is supported by the tray support surface 28 of the dielectric plate 23. When the tray 15 descends toward the tray support surface 28, the substrate placement portions 29A to 29D of the dielectric plate 23 enter the corresponding substrate accommodation holes 19A to 19D of the tray 15 from the lower surface 15c side of the tray 15. . As the lower surface 15c of the tray 15 approaches the tray support surface 28, the substrate placement surface 31 at the tip of the substrate placement portions 29A to 29D advances in the substrate accommodation holes 19A to 19D toward the upper surface 15b of the tray 15. As shown in FIG. 5B, when the lower surface 15c of the tray 15 is placed on the tray support surface 28 of the dielectric plate 23, the substrates 2 in the individual substrate accommodation holes 19A to 19D are moved by the substrate placement portions 29A to 29D. It is lifted from the upper surface 21 a of the substrate support portion 21. Specifically, the lower surface 2a of the substrate 2 is placed on the substrate placement surface 31 of the substrate placement portions 29A to 29D, and is disposed above the upper surface 21a of the substrate support portion 21 of the tray 15 with a gap. The

このようにトレイ15の基板収容孔19A〜19D内に基板載置部29A〜29Dが進入することにより、基板2は基板載置面31に載置される。従って、トレイ15に収容された4枚の基板2は、いずれも高い位置決め精度で基板載置部29A〜29Dの基板載置面31に載置される。また、前述のように基板載置部29A〜29Dの外周面38と基板載置面31との接続部分は丸面に面取りしているので、仮に基板収容孔19A〜19Dと基板載置部29A〜29Dの平面視での位置に微細なずれが存在している場合でも、基板載置部29A〜29Dの面取りされた部分が基板支持部21の先端面21bと接触する。その結果、基板載置部29A〜29Dが基板収容孔19A〜19D内に円滑かつ確実に挿入される。この点でも基板2は基板載置面31に対して高い位置決め精度で載置される。   As described above, the substrate placement portions 29A to 29D enter the substrate accommodation holes 19A to 19D of the tray 15, so that the substrate 2 is placed on the substrate placement surface 31. Accordingly, the four substrates 2 accommodated in the tray 15 are all placed on the substrate placement surfaces 31 of the substrate placement portions 29A to 29D with high positioning accuracy. Further, as described above, since the connection portion between the outer peripheral surface 38 of the substrate placement portions 29A to 29D and the substrate placement surface 31 is chamfered into a round surface, the substrate accommodation holes 19A to 19D and the substrate placement portion 29A are temporarily assumed. Even when there is a slight shift in the position in plan view of .about.29D, the chamfered portions of the substrate mounting portions 29A to 29D are in contact with the front end surface 21b of the substrate support portion 21. FIG. As a result, the substrate platforms 29A to 29D are smoothly and reliably inserted into the substrate accommodation holes 19A to 19D. Also in this respect, the substrate 2 is placed with high positioning accuracy with respect to the substrate placement surface 31.

次に、誘電体板23に内蔵された静電吸着用電極40に対して直流電圧印加機構43から直流電圧が印加され、個々の基板載置部29A〜29Dの基板載置面31に基板2が静電吸着される。基板2の下面2aはトレイ15を介することなく基板載置面31上に直接載置されている。従って、基板2は基板載置面31に対して高い密着度で保持される。   Next, a DC voltage is applied from the DC voltage application mechanism 43 to the electrostatic attraction electrode 40 built in the dielectric plate 23, and the substrate 2 is applied to the substrate placement surfaces 31 of the individual substrate placement portions 29 </ b> A to 29 </ b> D. Is electrostatically adsorbed. The lower surface 2 a of the substrate 2 is directly placed on the substrate placement surface 31 without using the tray 15. Accordingly, the substrate 2 is held with a high degree of adhesion to the substrate placement surface 31.

続いて、個々の基板載置部29A〜29Dの円環状突出部32と基板2の下面2aで囲まれた空間に、供給孔44を通って伝熱ガス供給装置45から伝熱ガスが供給され、この空間に伝熱ガスが充填される。   Subsequently, the heat transfer gas is supplied from the heat transfer gas supply device 45 through the supply hole 44 to the space surrounded by the annular protrusions 32 of the individual substrate placement portions 29 </ b> A to 29 </ b> D and the lower surface 2 a of the substrate 2. This space is filled with heat transfer gas.

その後、エッチングガス供給源12からチャンバ3内にエッチングガスが供給され、真空排気装置13によりチャンバ3内は所定圧力に維持される。続いて、高周波電源7からICPコイル5に高周波電圧を印加すると共に、高周波印加機構56により基板サセプタ9の金属板24にバイアス電圧を印加し、チャンバ3内にプラズマを発生させる。このプラズマにより基板2がエッチングされる。1枚のトレイ15で4枚の基板2を基板サセプタ9上に載置できるので、バッチ処理が可能である。   Thereafter, an etching gas is supplied from the etching gas supply source 12 into the chamber 3, and the inside of the chamber 3 is maintained at a predetermined pressure by the vacuum exhaust device 13. Subsequently, a high frequency voltage is applied from the high frequency power supply 7 to the ICP coil 5, and a bias voltage is applied to the metal plate 24 of the substrate susceptor 9 by the high frequency application mechanism 56 to generate plasma in the chamber 3. The substrate 2 is etched by this plasma. Since four substrates 2 can be placed on the substrate susceptor 9 with one tray 15, batch processing is possible.

エッチング中は、冷媒循環装置61によって冷媒流路60中で冷媒を循環させて金属板24を冷却し、それによって誘電体板23及び誘電体板23の基板載置面31に保持された基板2を冷却する。前述のように、基板2はその下面2aがトレイ15を介することなく基板載置面31に直接載置され、高い密着度で保持されている。従って、円環状突出部32と基板2の下面2aで囲まれた伝熱ガスが充填されている空間の密閉度が高く、伝熱ガスを介した基板2と基板載置面31との間の熱伝導性が良好である。その結果、個々の基板載置部29A〜29Dの基板載置面31に保持された基板2を高い冷却効率で冷却できると共に、基板2の温度を高精度で制御できる。また、個々の基板2毎に基板載置部29A〜29Dの円環状突出部32と下面2aで囲まれた空間に伝熱ガスが充填される。換言すれば、伝熱ガスが充填される空間は個々の基板2毎に異なる。この点でも個々の基板2と誘電体板23の基板載置面31との熱伝導性が良好であり、高い冷却効率と高精度の温度制御を実現できる。   During the etching, the refrigerant is circulated in the refrigerant flow path 60 by the refrigerant circulation device 61 to cool the metal plate 24, thereby the substrate 2 held on the dielectric plate 23 and the substrate mounting surface 31 of the dielectric plate 23. Cool down. As described above, the lower surface 2a of the substrate 2 is directly placed on the substrate placement surface 31 without the tray 15 and is held with a high degree of adhesion. Therefore, the sealing degree of the space filled with the heat transfer gas surrounded by the annular protrusion 32 and the lower surface 2a of the substrate 2 is high, and the space between the substrate 2 and the substrate placement surface 31 through the heat transfer gas is high. Good thermal conductivity. As a result, the substrate 2 held on the substrate placement surfaces 31 of the individual substrate placement units 29A to 29D can be cooled with high cooling efficiency, and the temperature of the substrate 2 can be controlled with high accuracy. In addition, a heat transfer gas is filled in the space surrounded by the annular protrusion 32 and the lower surface 2a of the substrate placement portions 29A to 29D for each individual substrate 2. In other words, the space filled with the heat transfer gas is different for each substrate 2. Also in this respect, the thermal conductivity between the individual substrates 2 and the substrate mounting surface 31 of the dielectric plate 23 is good, and high cooling efficiency and high-accuracy temperature control can be realized.

前述のように、基板2は個々の基板載置部29A〜29Dの基板載置面31に直接載置され、かつ静電吸着されるので、基板載置面31に対する密着度が高い。従って、基板2の上面の外周縁部分を誘電体板23に対して機械的に加熱するためのクランプリング等の部材は不要である。換言すれば、基板2の上面には、その中央部分だけでなく外周縁付近にもプラズマの状態が不安定化する原因となる部材が存在しない。従って、外周縁付近を含む基板2の表面の全領域で均一なプラズマ処理を実現できる。   As described above, since the substrate 2 is directly placed on the substrate placement surfaces 31 of the individual substrate placement portions 29A to 29D and is electrostatically attracted, the degree of adhesion to the substrate placement surface 31 is high. Therefore, a member such as a clamp ring for mechanically heating the outer peripheral edge portion of the upper surface of the substrate 2 with respect to the dielectric plate 23 is unnecessary. In other words, there is no member on the upper surface of the substrate 2 that causes the plasma state to become unstable not only in the central portion but also in the vicinity of the outer periphery. Therefore, uniform plasma processing can be realized in the entire region of the surface of the substrate 2 including the vicinity of the outer peripheral edge.

基板載置面31に対する基板2の位置決め精度を確保しつつ、エッチング処理中にプラズマが基板2の下面2a側に回り込むのを防止するためには、基板2の外周縁とトレイ15の基板収容孔19A〜19Dの孔壁15dとの間の隙間δ1が0.1〜0.2mm程度、基板2の下面2aとトレイ15の基板支持部21の上面21aとの間の隙間δ2が0.2〜0.3mm程度、基板載置部29A〜29Dの側壁と基板支持部21の先端との隙間δ3が0.5mm程度であることが好ましい。   In order to prevent the plasma from flowing to the lower surface 2a side of the substrate 2 during the etching process while ensuring the positioning accuracy of the substrate 2 with respect to the substrate mounting surface 31, the outer peripheral edge of the substrate 2 and the substrate accommodation hole of the tray 15 are used. The gap δ1 between the hole walls 15d of 19A to 19D is about 0.1 to 0.2 mm, and the gap δ2 between the lower surface 2a of the substrate 2 and the upper surface 21a of the substrate support portion 21 of the tray 15 is 0.2 to It is preferable that the gap δ3 between the side walls of the substrate placement portions 29A to 29D and the tip of the substrate support portion 21 is about 0.5 mm.

エッチング終了後、高周波電源7からICPコイル5への高周波電圧の印加と、高周波印加機構56から金属板24へのバイアス電圧の印加を停止する。続いて、真空排気装置13によりエッチングガスをチャンバ3内から排気する。また、伝熱ガス供給機構45により基板載置面31と基板2の下面2aから伝熱ガスを排気する。さらに、直流電圧印加機構43から静電吸着用電極40への直流電圧の印加を停止して基板2の静電吸着を解除する。   After the etching is finished, the application of the high frequency voltage from the high frequency power source 7 to the ICP coil 5 and the application of the bias voltage from the high frequency application mechanism 56 to the metal plate 24 are stopped. Subsequently, the etching gas is exhausted from the chamber 3 by the vacuum exhaust device 13. Further, the heat transfer gas is exhausted from the substrate placement surface 31 and the lower surface 2 a of the substrate 2 by the heat transfer gas supply mechanism 45. Further, the application of the DC voltage from the DC voltage application mechanism 43 to the electrostatic chucking electrode 40 is stopped to release the electrostatic chucking of the substrate 2.

次に、駆動装置17により昇降ピン18を上昇させる。昇降ピン18が上昇すると、その上端でトレイ15の下面15cが押し上げられ誘電体板23のトレイ支持面28から浮き上がる。昇降ピン18と共にトイレ15がさらに上昇すると、図5Aに示すように、トレイ15の基板支持部21により基板2の下面2cが押し上げられ、基板2は基板載置部29A〜29Dの基板載置面31から浮き上がる。昇降ピン18は図1において二点鎖線で示す上昇位置に上昇する。   Next, the elevating pins 18 are raised by the driving device 17. When the elevating pin 18 is raised, the lower surface 15c of the tray 15 is pushed up at the upper end of the elevating pin 18 and is lifted from the tray support surface 28 of the dielectric plate 23. When the toilet 15 is further lifted together with the lift pins 18, the lower surface 2c of the substrate 2 is pushed up by the substrate support portion 21 of the tray 15 as shown in FIG. 5A, and the substrate 2 is placed on the substrate placement surfaces of the substrate placement portions 29A to 29D. From 31 The raising / lowering pin 18 rises to a raised position indicated by a two-dot chain line in FIG.

その後、ゲート3aを通ってロードドック室10からチャンバ3内に進入した搬送アーム16に、トレイ15が移載される。トレイ15は搬送アーム16によってロードドック室10へ搬出される。   Thereafter, the tray 15 is transferred to the transfer arm 16 that has entered the chamber 3 from the load dock chamber 10 through the gate 3a. The tray 15 is carried out to the load dock chamber 10 by the transfer arm 16.

図7から図10は、トレイ15の基板支持部21と誘電体板23の基板載置部4に関する種々の代案を示す。   7 to 10 show various alternatives relating to the substrate support portion 21 of the tray 15 and the substrate placement portion 4 of the dielectric plate 23.

図7の例では、基板載置部29A〜29Dの外周面38と基板載置面31との接続部分を丸面に面取りしているだけでなく、トレイ15の基板支持部21の先端面21bを、トレイ15の下面15c側から上面15b側に向けて孔壁15dからの突出量が増大するテーパ面としている。基板支持部21の先端面21bをかかるテーパ面とすれば、基板収容孔19A〜19Dと基板載置部29A〜29Dの平面視での位置に微細なずれが存在している場合でも、基板載置部29A〜29Dは基板収容孔19A〜19Dに対してより確実かつ円滑に挿入できる。   In the example of FIG. 7, the connection portion between the outer peripheral surface 38 of the substrate placement portions 29 </ b> A to 29 </ b> D and the substrate placement surface 31 is not only chamfered into a round surface, but also the front end surface 21 b of the substrate support portion 21 of the tray 15. Is a tapered surface in which the amount of protrusion from the hole wall 15d increases from the lower surface 15c side of the tray 15 toward the upper surface 15b side. If the front end surface 21b of the substrate support portion 21 is such a tapered surface, the substrate mounting portion 19A to 19D and the substrate placement portions 29A to 29D can be mounted on the substrate even when there is a slight shift in the plan view. The placement portions 29A to 29D can be more reliably and smoothly inserted into the substrate housing holes 19A to 19D.

図8の例では、基板載置部29A〜29Dの外周面38は、基板載置面31側からトレイ支持部21に向けて外径寸法が拡大するテーパ面である。また、トレイ15の基板支持部21の先端面21bは、トレイ15の下面15c側から上面15b側に向けて孔壁15dからの突出量が増大するテーパ面である。このように基板載置部29A〜29Dの外周面と基板支持部21の先端面21bの両方をテーパ面としても、基板載置部29A〜29Dを基板収容孔19A〜19Dに対してより確実かつ円滑に挿入できる。   In the example of FIG. 8, the outer peripheral surfaces 38 of the substrate placement portions 29 </ b> A to 29 </ b> D are tapered surfaces whose outer diameter increases from the substrate placement surface 31 toward the tray support portion 21. Further, the front end surface 21b of the substrate support portion 21 of the tray 15 is a tapered surface in which the protruding amount from the hole wall 15d increases from the lower surface 15c side of the tray 15 toward the upper surface 15b side. As described above, even when both the outer peripheral surfaces of the substrate placement portions 29A to 29D and the front end surface 21b of the substrate support portion 21 are tapered surfaces, the substrate placement portions 29A to 29D can be more reliably and more easily configured with respect to the substrate accommodation holes 19A to 19D. Can be inserted smoothly.

図9及び図10の例では、基板載置部29A〜29Dの外周面38と基板載置面31との接続部分を丸面に面取りしているだけでなく、基板支持21の先端面21aをトレイ15の下面15c側から上面15b側に向けて孔壁15dからの突出量が増大する円弧状面としている。図9の例では、先端面21aを構成する円弧の曲率半径を比較的大きく設定し、基板支持部21の下面21cから上面21aまでの高さを大きく設定している。一方、図10の例では、先端面21aを構成する円弧の曲率半径を比較的小さく設定し、基板支持21の高さを小さく設定している。   In the example of FIGS. 9 and 10, not only is the connection portion between the outer peripheral surface 38 of the substrate mounting portions 29 </ b> A to 29 </ b> D and the substrate mounting surface 31 chamfered into a round surface, but also the front end surface 21 a of the substrate support 21 is formed. The tray 15 has an arcuate surface in which the amount of protrusion from the hole wall 15d increases from the lower surface 15c side to the upper surface 15b side. In the example of FIG. 9, the radius of curvature of the arc that forms the tip surface 21a is set to be relatively large, and the height from the lower surface 21c to the upper surface 21a of the substrate support portion 21 is set to be large. On the other hand, in the example of FIG. 10, the radius of curvature of the arc constituting the tip surface 21 a is set to be relatively small, and the height of the substrate support 21 is set to be small.

第1実施形態(図5A及び図5B)や図7から図10に示す種々の代案において、基板支持部21の先端面21bと基板載置部29A〜29Dの外周面38のうちの一方又は両方の表面をイットリアのような比較的硬質な材料で被覆してもよい。かかる被覆を設けることにより、誘電体板23にトレイ15を載置する際や、誘電体板23からトレイ15を降ろす際に、トレイ15の基板支持部21と誘電体板23の基板載置部29A〜29Dとの接触によりダストが発生するのを防止できる。   In the first embodiment (FIGS. 5A and 5B) and various alternatives shown in FIGS. 7 to 10, one or both of the front end surface 21b of the substrate support portion 21 and the outer peripheral surface 38 of the substrate placement portions 29A to 29D. The surface may be coated with a relatively hard material such as yttria. By providing such a coating, when the tray 15 is placed on the dielectric plate 23 or when the tray 15 is lowered from the dielectric plate 23, the substrate support portion 21 of the tray 15 and the substrate placement portion of the dielectric plate 23 are placed. Generation of dust due to contact with 29A to 29D can be prevented.

(第2実施形態)
図11から図13Bに示す本発明の第2実施形態は、トレイ15と基板サセプタ9の誘電体板23の構造が第1実施形態と異なる。
(Second Embodiment)
The second embodiment of the present invention shown in FIGS. 11 to 13B is different from the first embodiment in the structure of the tray 15 and the dielectric plate 23 of the substrate susceptor 9.

トレイ本体15aに形成された個々の基板収容孔19A〜19Dの孔壁15dの下面15c側には、周方向に間隔をあけて突起状の4個の基板支持部21が設けられている。詳細には、基板収容孔19A〜19Dの貫通方向から見ると、基板収容孔19A〜19Dの中心に対して等角過度間隔(90°間隔)で4個の基板支持部21が設けられている。一方、誘電体板23の個々の基板載置部29A〜29Dの外周面38には、基板載置面31からトレイ支持面28に向けて延びる4個の収容溝65が形成されている。平面視では、個々の基板載置部29A〜29Dの中心に対して等角度間隔で4個の収容溝65が設けられている。収容溝65の平面視での寸法及び形状は、突起状の基板支持部21よりもわずかに大きく設定されている。   On the lower surface 15c side of the hole wall 15d of each of the substrate housing holes 19A to 19D formed in the tray main body 15a, four protruding substrate support portions 21 are provided at intervals in the circumferential direction. Specifically, when viewed from the penetration direction of the substrate accommodation holes 19A to 19D, the four substrate support portions 21 are provided at equiangular excess intervals (90 ° intervals) with respect to the centers of the substrate accommodation holes 19A to 19D. . On the other hand, four receiving grooves 65 extending from the substrate mounting surface 31 toward the tray support surface 28 are formed on the outer peripheral surface 38 of each of the substrate mounting portions 29A to 29D of the dielectric plate 23. In plan view, four receiving grooves 65 are provided at equiangular intervals with respect to the centers of the individual substrate placement portions 29A to 29D. The size and shape of the receiving groove 65 in plan view are set slightly larger than the protruding substrate support 21.

図11に示すように誘電体板23の個々の基板載置部29A〜29Dの上方にトレイ15の基板収容孔19A〜19Dのいずれかが位置していれば、トレイ15が誘電体板23に向けて降下すると、個々の基板収容孔19A〜19Dの4個の基板支持部21が対応する基板載置部29A〜29Dの収容溝65に嵌り込む。従って、この場合、トレイ15の下面15cがトレイ支持面28に達し、かつ基板2の下面2aが基板載置面31上に載置されるまでトレイ15を降下させることができる。しかし、図11において矢印C1,C2で示すように、トレイ15のそれ自体の中心周りの角度が比較的大きくずれている場合、基板支持部21と収容溝56の平面視での位置がずれるので、基板支持部21は収容溝65に嵌り込まず、基板載置部29A〜29Dと干渉する。その結果、基板収容孔19A〜19Dに対する基板載置部29A〜29Dの進入が妨げられる。従って、周方向に間隔をあけて配置した突起状の基板支持部21と収容溝65とを設けることにより、誘電体板23の基板載置面31に対する基板2の位置決め精度がさらに向上する。   As shown in FIG. 11, if any of the substrate accommodation holes 19 </ b> A to 19 </ b> D of the tray 15 is positioned above the individual substrate placement portions 29 </ b> A to 29 </ b> D of the dielectric plate 23, the tray 15 is placed on the dielectric plate 23. When descending, the four substrate support portions 21 of the individual substrate accommodation holes 19A to 19D are fitted into the accommodation grooves 65 of the corresponding substrate placement portions 29A to 29D. Accordingly, in this case, the tray 15 can be lowered until the lower surface 15 c of the tray 15 reaches the tray support surface 28 and the lower surface 2 a of the substrate 2 is placed on the substrate placement surface 31. However, as shown by arrows C1 and C2 in FIG. 11, when the angle around the center of the tray 15 is relatively large, the positions of the substrate support portion 21 and the receiving groove 56 are shifted in plan view. The substrate support portion 21 does not fit into the accommodation groove 65 and interferes with the substrate placement portions 29A to 29D. As a result, the substrate placement portions 29A to 29D are prevented from entering the substrate accommodation holes 19A to 19D. Therefore, by providing the protruding substrate support portions 21 and the accommodation grooves 65 arranged at intervals in the circumferential direction, the positioning accuracy of the substrate 2 with respect to the substrate placement surface 31 of the dielectric plate 23 is further improved.

第2実施形態のその他の構成及び作用は第1実施形態と同様であるので、同一の要素には同一の符号を付して説明を省略する。   Since other configurations and operations of the second embodiment are the same as those of the first embodiment, the same elements are denoted by the same reference numerals and description thereof is omitted.

図14及び図15は、トレイ15に関する種々の代案を示す。図14の例では、トレイ本体15aに、外周縁の一部を直線状に切り欠いたオリエンテーションフラットを備える基板をそれぞれ収容するための7個の基板収容孔19A〜19Gが形成されている。基板収容孔19A〜19Gの孔壁15dは第1実施形態と同様の円筒面であるが、その一部はオリエンテーションフラットと対応して平坦面としている。図15の例では、トレイ本体15aに矩形状の基板を収容するための9個の基板収容孔19A〜19Iが形成されている。これら図14及び図15に限定されず、トレイ15の基板収容孔の形状及び個数は、収容する基板の形状や個数に応じて種々設定することが可能である。また、基板サセプタ9の誘電体板23に設ける基板載置部の形状や個数も、基板収容孔の形状及び個数に応じて種々設定できる。   14 and 15 show various alternatives for the tray 15. In the example of FIG. 14, seven substrate housing holes 19 </ b> A to 19 </ b> G are formed in the tray body 15 a for housing substrates each having an orientation flat in which a part of the outer peripheral edge is cut out linearly. The hole walls 15d of the substrate housing holes 19A to 19G have the same cylindrical surface as that of the first embodiment, but a part thereof is a flat surface corresponding to the orientation flat. In the example of FIG. 15, nine substrate housing holes 19 </ b> A to 19 </ b> I for housing a rectangular substrate are formed in the tray body 15 a. 14 and 15, the shape and number of the substrate accommodation holes of the tray 15 can be variously set according to the shape and number of the substrates accommodated. In addition, the shape and number of substrate placement portions provided on the dielectric plate 23 of the substrate susceptor 9 can be variously set according to the shape and number of substrate accommodation holes.

(第3実施形態)
図16に示す本発明の第3実施形態は、トレイ15を誘電体板23に対して位置決めするための円環状のガイドプレート67を備える。ガイドプレート67はガイド筒体26の上面に固定されており、誘電体板23の4つの基板載置部29A〜29Dの周囲を取り囲んでいる。ガイドプレート67の内周面67aは下面67bから上面67cに向けて拡がるテーパ面である。また、ガイドプレート67の厚みはトレイ15の厚みとほぼ同程度に設定されている。
(Third embodiment)
The third embodiment of the present invention shown in FIG. 16 includes an annular guide plate 67 for positioning the tray 15 with respect to the dielectric plate 23. The guide plate 67 is fixed to the upper surface of the guide cylinder 26 and surrounds the four substrate placement portions 29A to 29D of the dielectric plate 23. The inner peripheral surface 67a of the guide plate 67 is a tapered surface that extends from the lower surface 67b toward the upper surface 67c. The thickness of the guide plate 67 is set to be approximately the same as the thickness of the tray 15.

図17を併せて参照すると、本実施形態では、トレイ15の外周面15fは下面15cから上面15bに向けて外径が拡大するテーパ面である。ガイドプレート67の内周面67aとトレイ15の外周面15fのテーパ度を含む寸法及び形状は、トレイ15の下面15cをトレイ支持面28上に載置する時、ガイドプレート67の内周面67aによりトレイ15の外周面15fが位置決め案内されるように設定されている。   Referring also to FIG. 17, in this embodiment, the outer peripheral surface 15f of the tray 15 is a tapered surface whose outer diameter increases from the lower surface 15c toward the upper surface 15b. The dimensions and shape including the taper degree of the inner peripheral surface 67a of the guide plate 67 and the outer peripheral surface 15f of the tray 15 are such that when the lower surface 15c of the tray 15 is placed on the tray support surface 28, the inner peripheral surface 67a of the guide plate 67. Thus, the outer peripheral surface 15f of the tray 15 is set so as to be positioned and guided.

図16において二点鎖線で示す上昇位置からトレイ15が誘電体板23に向けて降下すると、トレイ15の外周面15fがガイドプレート67の内周面67aに案内される。基板載置部29A〜29Dがトレイ15の基板収容孔19A〜19Fに挿入されることにより基板収容孔19A〜19D内の基板2が誘電体板23の基板載置面31に対して位置決めされるだけでなく、基板2を保持したトレイ15自体がガイドプレート67により誘電体板23に対して位置決めされる。その結果、誘電体部材23の基板載置面31に対する基板2の位置決め精度がさらに向上する。   In FIG. 16, when the tray 15 is lowered toward the dielectric plate 23 from the rising position indicated by the two-dot chain line, the outer peripheral surface 15 f of the tray 15 is guided to the inner peripheral surface 67 a of the guide plate 67. The substrate placement portions 29A to 29D are inserted into the substrate accommodation holes 19A to 19F of the tray 15 so that the substrate 2 in the substrate accommodation holes 19A to 19D is positioned with respect to the substrate placement surface 31 of the dielectric plate 23. In addition, the tray 15 itself holding the substrate 2 is positioned with respect to the dielectric plate 23 by the guide plate 67. As a result, the positioning accuracy of the substrate 2 with respect to the substrate mounting surface 31 of the dielectric member 23 is further improved.

図18A及び図18Bは、トレイ15及びガイドプレート67の代案を示す。図18Aの例では、トレイ15の外周面15fは下面15cから上面15bに向けて外径が拡大するテーパ面であるが、ガイドプレート67の内周面67aは鉛直方向に延びる平坦面であり上面67bとの接続部分を丸面に面取りしている。一方、図18Bの例では、トレイ15の外周面15fは鉛直方向に延びる平坦面であり下面15cとの接続部分を丸面に面取りし、ガイドプレート67の内周面67aは下面67bから上面67aに向けて外径が拡大するテーパ面としている。図18Aや図18Bに示すトレイ15の外周面15fとガイドプレート67の内周面67aの形状の組み合わせを採用しても、トレイ15の誘電体板23に対して位置決め精度をさらに向上できる。なお、トレイ15の外周面15fとガイドプレート67の内周面67aの面取りは丸面に限定されず、角面に面取りしてもよい。   18A and 18B show alternatives to the tray 15 and the guide plate 67. FIG. In the example of FIG. 18A, the outer peripheral surface 15f of the tray 15 is a tapered surface whose outer diameter increases from the lower surface 15c toward the upper surface 15b. However, the inner peripheral surface 67a of the guide plate 67 is a flat surface extending in the vertical direction. The connecting portion with 67b is rounded off. On the other hand, in the example of FIG. 18B, the outer peripheral surface 15f of the tray 15 is a flat surface extending in the vertical direction, the connecting portion with the lower surface 15c is chamfered to a round surface, and the inner peripheral surface 67a of the guide plate 67 is changed from the lower surface 67b to the upper surface 67a. The taper surface has an outer diameter that increases toward the surface. Even if the combination of the shapes of the outer peripheral surface 15f of the tray 15 and the inner peripheral surface 67a of the guide plate 67 shown in FIGS. 18A and 18B is employed, the positioning accuracy with respect to the dielectric plate 23 of the tray 15 can be further improved. The chamfering of the outer peripheral surface 15f of the tray 15 and the inner peripheral surface 67a of the guide plate 67 is not limited to a round surface, and may be chamfered to a square surface.

第3実施形態のその他の構成及び作用は第1実施形態と同様であるので、同一の要素には同一の符号を付して説明を省略する。   Since other configurations and operations of the third embodiment are the same as those of the first embodiment, the same elements are denoted by the same reference numerals and description thereof is omitted.

(第4実施形態)
図19に示す本発明の第4実施形態では、ドライエッチング装置1は、誘電体部材4が備える4個の基板載置部29A〜29D毎に伝熱ガス供給機構45A〜45Dを備えている。伝熱ガス供給機構45A〜45Dは、共通の伝熱ガス源46を備える。しかし、供給流路47、流量計48、流量制御バルブ49、圧力計50、排出流路51、カットオフバルブ52、バイパス流路53、及び排気口54は、個々の伝熱ガス供給機構45A〜45D毎に別個に設けられている。従って、個々の伝熱ガス供給機構45A〜45Dは、基板載置面31と基板2の間に対する伝熱ガスの供給と排出を個別に制御可能である。基板載置面31と基板2の間への伝熱ガスの供給を、4個の基板載置部29A〜29Dの基板載置面31に載置された4枚の基板2毎に別個に調整できる。その結果、基板2の冷却効率と基板温度の制御精度をさらに向上し、それによってエッチング精度を向上できる。
(Fourth embodiment)
In the fourth embodiment of the present invention illustrated in FIG. 19, the dry etching apparatus 1 includes the heat transfer gas supply mechanisms 45 </ b> A to 45 </ b> D for each of the four substrate mounting portions 29 </ b> A to 29 </ b> D included in the dielectric member 4. The heat transfer gas supply mechanisms 45 </ b> A to 45 </ b> D include a common heat transfer gas source 46. However, the supply flow path 47, the flow meter 48, the flow control valve 49, the pressure gauge 50, the discharge flow path 51, the cutoff valve 52, the bypass flow path 53, and the exhaust port 54 are individually connected to the heat transfer gas supply mechanisms 45 </ b> A to 45 </ b> A. It is provided separately for each 45D. Accordingly, each of the heat transfer gas supply mechanisms 45 </ b> A to 45 </ b> D can individually control the supply and discharge of the heat transfer gas between the substrate placement surface 31 and the substrate 2. The supply of heat transfer gas between the substrate placement surface 31 and the substrate 2 is adjusted separately for each of the four substrates 2 placed on the substrate placement surfaces 31 of the four substrate placement portions 29A to 29D. it can. As a result, the cooling efficiency of the substrate 2 and the control accuracy of the substrate temperature can be further improved, thereby improving the etching accuracy.

また、ドライエッチング装置1は、基板載置部29A〜29Dに内蔵された4個の静電吸着用電極40毎に、個別に制御可能な直流電圧印加機構43A〜43Dを備える。個々の直流電圧印加機構43A〜43Dは、直流電源41と調整用の抵抗42を備える。個々の基板載置部29A〜29Dに内蔵された静電吸着用電極40に印加される直流電圧を個別に制御できるので、4つの基板載置部29A〜29Dの基板載置面31に載置された4枚の基板2間で静電吸着力のばらつきをなくし、均一化できる。   Further, the dry etching apparatus 1 includes DC voltage application mechanisms 43A to 43D that can be individually controlled for each of the four electrostatic chucking electrodes 40 built in the substrate platforms 29A to 29D. Each of the DC voltage application mechanisms 43 </ b> A to 43 </ b> D includes a DC power supply 41 and an adjusting resistor 42. Since the DC voltage applied to the electrostatic attraction electrodes 40 incorporated in the individual substrate placement portions 29A to 29D can be individually controlled, the placement is performed on the substrate placement surfaces 31 of the four substrate placement portions 29A to 29D. It is possible to eliminate the variation in electrostatic attraction force between the four substrates 2 thus made uniform.

第4実施形態のその他の構成及び作用は第1実施形態と同様であるので、同一の要素には同一の符号を付して説明を省略する。   Since the other configurations and operations of the fourth embodiment are the same as those of the first embodiment, the same elements are denoted by the same reference numerals and description thereof is omitted.

(第5実施形態)
図20に示す本発明の第5実施形態のドライエッチング装置1では、高周波印加機構56は、金属板24ではなく、誘電体部材4の個々の基板載置部29A〜29Dに内蔵された静電吸着用電極40に電気的に接続されている。個々の静電吸着用電極40には、直流電圧印加機構43により印加される静電吸着用の直流電圧に重畳して、バイアス電圧としての高周波が高周波印加機構56により印加される。バイアス電圧を金属板27ではなく静電吸着用電極40に印加することによりトレイ15の消耗を低減できる。また、第4実施形態と同様に、個々の基板載置部29A〜29D毎に、個別に制御可能な伝熱ガス供給機構45A〜45Dが設けられている。
(Fifth embodiment)
In the dry etching apparatus 1 according to the fifth embodiment of the present invention shown in FIG. 20, the high-frequency applying mechanism 56 is not a metal plate 24 but electrostatics built in the individual substrate mounting portions 29 </ b> A to 29 </ b> D of the dielectric member 4. It is electrically connected to the adsorption electrode 40. A high frequency as a bias voltage is applied to each of the electrostatic attraction electrodes 40 by the high frequency application mechanism 56 so as to be superimposed on the electrostatic attraction DC voltage applied by the DC voltage application mechanism 43. By applying the bias voltage to the electrostatic chucking electrode 40 instead of the metal plate 27, the consumption of the tray 15 can be reduced. Further, similarly to the fourth embodiment, individually controllable heat transfer gas supply mechanisms 45A to 45D are provided for the individual substrate placement units 29A to 29D.

第5実施形態のその他の構成及び作用は第1実施形態と同様であるので、同一の要素には同一の符号を付して説明を省略する。   Since other configurations and operations of the fifth embodiment are the same as those of the first embodiment, the same elements are denoted by the same reference numerals and description thereof is omitted.

(第6実施形態)
図21に示す本発明の第6実施形態のドライエッチング装置1では、個々の基板載置部29A〜29Dに内蔵された静電吸着用電極40毎に、直流電圧印加機構43により印加される静電吸着用の直流電圧と重畳して、バイアス電圧として高周波を印加するための高周波印加機構56A〜56Dが設けられている。高周波印加機構56A〜56Dはそれぞれ高周波電源57と可変容量コンデンサ58を備え、個別に制御可能である。4つの基板載置部29A〜29Dの基板載置面31に載置された4枚の基板2の特性に応じて、静電吸着用電極40に印加するバイアス電圧として印加される高周波のパワーを調整できるので、4枚の基板2間でばらつきのない均一なエッチング処理を実現できる。
(Sixth embodiment)
In the dry etching apparatus 1 according to the sixth embodiment of the present invention shown in FIG. 21, a static voltage applied by the DC voltage application mechanism 43 is provided for each electrostatic attraction electrode 40 built in each of the substrate mounting portions 29A to 29D. High frequency application mechanisms 56 </ b> A to 56 </ b> D for applying a high frequency as a bias voltage are provided so as to overlap with the DC voltage for electroadsorption. Each of the high frequency application mechanisms 56A to 56D includes a high frequency power source 57 and a variable capacitor 58, and can be individually controlled. According to the characteristics of the four substrates 2 placed on the substrate placement surfaces 31 of the four substrate placement portions 29A to 29D, high frequency power applied as a bias voltage to be applied to the electrostatic chucking electrode 40 is obtained. Since the adjustment can be performed, a uniform etching process with no variation among the four substrates 2 can be realized.

第6実施形態のその他の構成及び作用は第1実施形態と同様であるので、同一の要素には同一の符号を付して説明を省略する。   Since the other configuration and operation of the sixth embodiment are the same as those of the first embodiment, the same elements are denoted by the same reference numerals and description thereof is omitted.

(第7実施形態)
図22に示す本発明の第7実施形態のドライエッチング装置1では、個々の基板載置部29A〜29Dに内蔵された静電吸着用電極40毎に、個別に制御可能な直流電圧印加機構43A〜43Dを備える。また、個々の基板載置部29A〜29Dに内蔵された静電吸着用電極40にバイアス電圧として高周波を印加するための共通の高周波印加機構56が設けられている。個々の基板載置部29A〜29Dに内蔵された静電吸着用電極40に印加される直流電圧を個別に制御できるので、4つの基板載置部29A〜29Dの基板載置面31に載置された4枚の基板2間で静電吸着力のばらつきをなくし、均一化できる。
(Seventh embodiment)
In the dry etching apparatus 1 according to the seventh embodiment of the present invention shown in FIG. 22, a DC voltage application mechanism 43 </ b> A that can be individually controlled for each electrostatic attraction electrode 40 built in each of the substrate mounting portions 29 </ b> A to 29 </ b> D. ˜43D. In addition, a common high-frequency application mechanism 56 is provided for applying a high frequency as a bias voltage to the electrostatic attraction electrodes 40 built in the individual substrate placement units 29A to 29D. Since the DC voltage applied to the electrostatic attraction electrodes 40 incorporated in the individual substrate placement portions 29A to 29D can be individually controlled, the placement is performed on the substrate placement surfaces 31 of the four substrate placement portions 29A to 29D. It is possible to eliminate the variation in electrostatic attraction force between the four substrates 2 thus made uniform.

第7実施形態のその他の構成及び作用は第1実施形態と同様であるので、同一の要素には同一の符号を付して説明を省略する。   Since the other configuration and operation of the seventh embodiment are the same as those of the first embodiment, the same elements are denoted by the same reference numerals and description thereof is omitted.

(第8実施形態)
図23に示す本発明の第8実施形態のドライエッチング装置1では、個々の基板載置部29A〜29Dに静電吸着用電極40が内蔵されている。また、個々の基板載置部29A〜29Dには、静電吸着用電極40よりも金属板24側(図において下側)にバイアス印加用電極68が内蔵されている。バイアス印加用電圧68は静電吸着用電極40とは電気的に絶縁されている。個々の基板載置部29A〜29Dに内蔵されたバイアス印加用電極68には共通の高周波印加機構56からバイアス電圧としての高周波が印加される。
(Eighth embodiment)
In the dry etching apparatus 1 according to the eighth embodiment of the present invention shown in FIG. 23, the electrostatic chucking electrode 40 is built in each of the substrate mounting portions 29A to 29D. Each of the substrate mounting portions 29A to 29D includes a bias applying electrode 68 on the metal plate 24 side (lower side in the drawing) with respect to the electrostatic attraction electrode 40. The bias application voltage 68 is electrically insulated from the electrostatic adsorption electrode 40. A high frequency as a bias voltage is applied from a common high frequency applying mechanism 56 to the bias applying electrode 68 incorporated in each of the substrate mounting portions 29A to 29D.

個々の基板載置部29A〜29Dのバイアス電圧用電極68毎に、個別に制御可能な高周波印加機構を設けてもよい。4個の基板載置部29A〜29Dに内蔵されたバイアス電極68毎にバイアス電圧として印加される高周波を個別に調整することで、4つの基板載置部29A〜29Dの基板載置面31に載置された4枚の基板2間でばらつきのない均一なエッチング処理を実現できる。   A high-frequency application mechanism that can be individually controlled may be provided for each bias voltage electrode 68 of each of the substrate placement portions 29A to 29D. By individually adjusting the high frequency applied as the bias voltage for each of the bias electrodes 68 incorporated in the four substrate placement units 29A to 29D, the substrate placement surfaces 31 of the four substrate placement units 29A to 29D are adjusted. A uniform etching process with no variation among the four substrates 2 placed thereon can be realized.

第8実施形態のその他の構成及び作用は第1実施形態と同様であるので、同一の要素には同一の符号を付して説明を省略する。   Since the other configurations and operations of the eighth embodiment are the same as those of the first embodiment, the same elements are denoted by the same reference numerals and description thereof is omitted.

(第9実施形態)
図24は本発明の第9実施形態のドライエッチング装置1を示す。図25から図26Bに示すように、トレイ15には厚み方向に貫通する単一の基板収容孔19が形成されている。また、基板収容孔19の孔壁15dから円環状の基板支持部21が突出している。この基板収容孔19内に収容された1枚の基板2は、この基板支持部21の上面21aに支持される。また、図25、図27A、及び図27Bに示すように、基板サセプタ9の誘電体板23は、単一の基板載置部29を備える。トレイ15を誘電体板23上に載置すると、基板載置部29がトレイ15の下面15c側から基板収容孔19に進入し、トレイ15の下面が誘電体板23のトレイ支持面28で支持されると共に、基板載置部29の上端の基板載置面31上に基板2が載置される。
(Ninth embodiment)
FIG. 24 shows a dry etching apparatus 1 according to the ninth embodiment of the present invention. As shown in FIGS. 25 to 26B, the tray 15 is formed with a single substrate accommodation hole 19 penetrating in the thickness direction. An annular substrate support portion 21 protrudes from the hole wall 15 d of the substrate accommodation hole 19. One substrate 2 accommodated in the substrate accommodation hole 19 is supported by the upper surface 21 a of the substrate support portion 21. As shown in FIGS. 25, 27A, and 27B, the dielectric plate 23 of the substrate susceptor 9 includes a single substrate mounting portion 29. When the tray 15 is placed on the dielectric plate 23, the substrate placement portion 29 enters the substrate accommodation hole 19 from the lower surface 15 c side of the tray 15, and the lower surface of the tray 15 is supported by the tray support surface 28 of the dielectric plate 23. At the same time, the substrate 2 is placed on the substrate placement surface 31 at the upper end of the substrate placement portion 29.

基板2を静電吸着する静電吸着用電極は双極型である。具体的には、基板載置部29には2個の静電吸着用電極40A,40Bが内蔵されている。また、個々の静電吸着用電極40A,40B毎に直流電圧印加機構43E,43Fが設けられており、個々の静電吸着用電極40A,40Bには互いに逆極性の直流電圧が印加される。なお、第1から第8実施形態において静電吸着用電極を双極型としてもよい。逆に、本実施形態において静電吸着用電極を単極型としてもよい。   The electrode for electrostatic attraction that electrostatically attracts the substrate 2 is a bipolar type. Specifically, the substrate mounting portion 29 includes two electrostatic adsorption electrodes 40A and 40B. Further, DC voltage application mechanisms 43E and 43F are provided for the individual electrostatic attraction electrodes 40A and 40B, and DC voltages having opposite polarities are applied to the individual electrostatic attraction electrodes 40A and 40B. In the first to eighth embodiments, the electrostatic chucking electrode may be a bipolar type. On the contrary, in this embodiment, the electrostatic chucking electrode may be a single electrode type.

本実施形態のドライエッチング装置1では、トレイ15に収容される基板2は1枚であるので、枚葉処理が可能である。また、比較的面積の大きい基板2の処理に適している。   In the dry etching apparatus 1 of the present embodiment, since the substrate 2 accommodated in the tray 15 is one sheet, single wafer processing is possible. Moreover, it is suitable for processing the substrate 2 having a relatively large area.

第9実施形態のその他の構成及び作用は第1実施形態と同様であるので、同一の要素には同一の符号を付して説明を省略する。   Since the other configurations and operations of the ninth embodiment are the same as those of the first embodiment, the same elements are denoted by the same reference numerals and description thereof is omitted.

(実験1)
本発明により基板の冷却効率が向上することを確認するためのシミュレーションを行った。具体的には、実験例、比較例1、及び比較例2についてバイアスパワーの増加と基板温度の上昇の関係をシミュレーションした。
(Experiment 1)
A simulation was performed to confirm that the cooling efficiency of the substrate is improved by the present invention. Specifically, the relationship between the increase in bias power and the increase in substrate temperature was simulated for Experimental Example, Comparative Example 1, and Comparative Example 2.

実験例は、本発明の第9実施形態に対応する。基板2は2インチサイズのシリコンウェハとした。トレイ15を厚み方向に貫通した基板収容孔19内に基板2を収容したトレイ15を基板サセプタ9の誘電体板23上に載置し、基板2の下面2aを基板載置面31上に直接載置し、双極型の静電吸着用電極40A,40Bで静電吸着した。個々の静電吸着用電極40A,40Bに印加する直流電圧は±900Vとした。また、基板載置面31と基板2の下面2aとの間に伝熱ガスとしてヘリウムガスを供給し、その圧力は800Paとした。   The experimental example corresponds to the ninth embodiment of the present invention. The substrate 2 was a 2-inch silicon wafer. The tray 15 containing the substrate 2 is placed on the dielectric plate 23 of the substrate susceptor 9 in the substrate accommodation hole 19 penetrating the tray 15 in the thickness direction, and the lower surface 2 a of the substrate 2 is directly on the substrate placement surface 31. The electrode was placed and electrostatically attracted by bipolar electrostatic attracting electrodes 40A and 40B. The DC voltage applied to each of the electrostatic attraction electrodes 40A and 40B was ± 900V. Further, helium gas was supplied as a heat transfer gas between the substrate placement surface 31 and the lower surface 2a of the substrate 2, and the pressure was 800 Pa.

比較例1は、基板が載置された有底のトレイを基板サセプタ上に配置し、トレイを介して間接的に基板を基板サセプタに対して静電吸着する例である。基板は2インチサイズのシリコンウェハとした。また、静電吸着用電極に印加する直流電圧は±900Vとし、トレイの下面に伝熱ガスとしてヘリウムガスを供給し、その圧力は800Paとした。   Comparative Example 1 is an example in which a bottomed tray on which a substrate is placed is placed on a substrate susceptor, and the substrate is indirectly electrostatically attracted to the substrate susceptor via the tray. The substrate was a 2 inch size silicon wafer. The DC voltage applied to the electrostatic chucking electrode was ± 900 V, helium gas was supplied as the heat transfer gas to the lower surface of the tray, and the pressure was 800 Pa.

比較例2は、基板が載置された有底のトレイを基板サセプタ上に配置すると共に、基板の外周縁付近をクランプリングにより基板サセプタ側に機械的に押し付け、それによって基板を基板サセプタに対して固定する例である。基板は4インチサイズのシリコンウェハとした。また、基板の下面に伝熱ガスとしてヘリウムを供給し、その圧力は600Paとした。   In Comparative Example 2, a bottomed tray on which a substrate is placed is placed on a substrate susceptor, and the vicinity of the outer peripheral edge of the substrate is mechanically pressed to the substrate susceptor side by a clamp ring, whereby the substrate is pressed against the substrate susceptor. This is an example of fixing. The substrate was a 4 inch size silicon wafer. Moreover, helium was supplied to the lower surface of the substrate as a heat transfer gas, and the pressure was 600 Pa.

以下の条件は、実験例及び比較例1、2について統一した。エッチングガスは塩素ガス(Cl2)で流量は50sccm、圧力は2Paとした。ICPコイルに投入する高周波パワーは300Wとした。放電時間は60秒とした。また、天板、チャンバ、及び基板サセプタ(電極)の温度をそれぞれ、100℃、100℃、及び20℃とした。 The following conditions were unified for the experimental example and comparative examples 1 and 2. The etching gas was chlorine gas (Cl 2 ), the flow rate was 50 sccm, and the pressure was 2 Pa. The high frequency power supplied to the ICP coil was 300 W. The discharge time was 60 seconds. The temperatures of the top plate, chamber, and substrate susceptor (electrode) were 100 ° C., 100 ° C., and 20 ° C., respectively.

図28にシミュレーション結果を示す。比較例1ではバイアスパワーを約50Wとすると、レジスト焼けが起こる約110℃に基板温度が上昇する。また、比較例2では、バイアスパワーを約200Wとすると、レジスト焼けが起こる約110℃に基板温度が上昇する。これに対して実験例では、バイアスパワーを400Wに設定しても基板温度は、レジスト焼けが起こる約110℃に達しない。このシミュレーション結果は、従来例1及び2と比較して、実験例(本発明)における基板の冷却効率が大幅に高いことを示している。   FIG. 28 shows the simulation result. In Comparative Example 1, when the bias power is about 50 W, the substrate temperature rises to about 110 ° C. where resist burning occurs. In Comparative Example 2, when the bias power is about 200 W, the substrate temperature rises to about 110 ° C. where resist burning occurs. On the other hand, in the experimental example, even when the bias power is set to 400 W, the substrate temperature does not reach about 110 ° C. where resist burning occurs. This simulation result shows that the cooling efficiency of the substrate in the experimental example (the present invention) is significantly higher than in the conventional examples 1 and 2.

(実験2)
本発明により基板表面の全領域でのプラズマ処理が均一化されることを確認するためのシミュレーションを行った。前述の実験例と比較例2について基板表面に基板の中心を原点とした直交座標(X−Y座標系)を設定し、これらについてエッチング速度(E/R)の分布をシミュレートした。また、実験例及び比較例2のいずれについても基板の材質はニッケルコバルト(NiCo)とした。
(Experiment 2)
A simulation for confirming that the plasma treatment in the entire region of the substrate surface is made uniform by the present invention was performed. In the above experimental example and comparative example 2, orthogonal coordinates (XY coordinate system) with the center of the substrate as the origin were set on the substrate surface, and the etching rate (E / R) distribution was simulated for these. In both the experimental example and the comparative example 2, the material of the substrate was nickel cobalt (NiCo).

図29に比較例2のシミュレーション結果を示し、図30に実験例のシミュレーション結果を示す。比較例2では、基板の中心付近と比較すると基板の外周縁付近でエッチング速度が低く、基板の外周縁にクランプリングが存在することによりエッチング速度の分布が不均一となっている。詳細には、基板の中心からX方向に5mmとY方向に5mmの位置でのエッチング速度の平均値が42.5nm/minであるのに対して、基板の中心からX方向に10mmとY方向に10mmの位置でのエッチング速度の平均値が43.9nm/minであり、両者の間には1.4nm/minの差がある。これに対して、実験例では、基板の中心付近から外周縁付近にわたる全領域でエッチング速度が均一化されている。詳細には、基板の中心からX方向に5mmとY方向に5mmの位置でのエッチング速度の平均値が44.5nm/min、基板の中心からX方向に10mmとY方向に10mmの位置でのエッチング速度の平均値が43.9nm/minであり、両者の差は0.6nm/minの差に過ぎない。比較例2と比較すると、実験例(本発明)では基板の中心から5mmの位置と10mmの位置におけるエッチング速度の平均値の差が1/2未満に低減されている。   FIG. 29 shows the simulation result of Comparative Example 2, and FIG. 30 shows the simulation result of the experimental example. In Comparative Example 2, the etching rate is low near the outer periphery of the substrate as compared with the vicinity of the center of the substrate, and the distribution of the etching rate is non-uniform due to the presence of the clamp ring at the outer periphery of the substrate. Specifically, the average value of the etching rate at the position of 5 mm in the X direction and 5 mm in the Y direction from the center of the substrate is 42.5 nm / min, whereas it is 10 mm in the X direction from the center of the substrate and the Y direction. The average value of the etching rate at a position of 10 mm is 43.9 nm / min, and there is a difference of 1.4 nm / min between the two. On the other hand, in the experimental example, the etching rate is uniform in the entire region from the vicinity of the center of the substrate to the vicinity of the outer periphery. Specifically, the average value of the etching rate at a position of 5 mm in the X direction and 5 mm in the Y direction from the center of the substrate is 44.5 nm / min, 10 mm in the X direction and 10 mm in the Y direction from the center of the substrate. The average value of the etching rate is 43.9 nm / min, and the difference between them is only a difference of 0.6 nm / min. Compared to Comparative Example 2, in the experimental example (the present invention), the difference between the average values of the etching rates at the position of 5 mm and the position of 10 mm from the center of the substrate is reduced to less than ½.

本発明は前記実施形態に限定されず、種々の変形が可能である。例えば、ICP型のドライエッチング処理装置を例に本発明を説明したが、RI(リアクティブイオン)型のドライエッチング、プラズマCVD用プラズマ処理装置及びプラズマ処理方法に本発明を適用できる。   The present invention is not limited to the above embodiment, and various modifications can be made. For example, the present invention has been described by taking an ICP type dry etching processing apparatus as an example, but the present invention can be applied to an RI (reactive ion) type dry etching, a plasma processing apparatus for plasma CVD, and a plasma processing method.

本発明の第1実施形態に係るドライエッチング装置の模式的な断面図。1 is a schematic cross-sectional view of a dry etching apparatus according to a first embodiment of the present invention. 本発明の第1実施形態に係るドライエッチング装置の模式的な平面図。1 is a schematic plan view of a dry etching apparatus according to a first embodiment of the present invention. トレイ及び誘電体板を示す斜視図。The perspective view which shows a tray and a dielectric material board. トレイの平面図。The top view of a tray. 図4AのIV−IV線での断面図。Sectional drawing in the IV-IV line of FIG. 4A. トレイ及び誘電体板の部分拡大断面図(トレイ載置前)。The partial expanded sectional view of a tray and a dielectric material board (before tray mounting). トレイ及び誘電体板の部分拡大断面図(トレイ載置後)。The partial expanded sectional view of a tray and a dielectric material board (after tray mounting). 誘電体板の平面図。The top view of a dielectric material board. 図6のVI−VI線での断面図。Sectional drawing in the VI-VI line of FIG. トレイ及び誘電体板の第1の代案の部分拡大断面図。The partial expanded sectional view of the 1st alternative of a tray and a dielectric material board. トレイ及び誘電体板の第2の代案の部分拡大断面図。The partial expanded sectional view of the 2nd alternative of a tray and a dielectric material board. トレイ及び誘電体板の第3の代案の部分拡大断面図。The partial expanded sectional view of the 3rd alternative of a tray and a dielectric material board. トレイ及び誘電体板の第4の代案の部分拡大断面図。The partial expanded sectional view of the 4th alternative of a tray and a dielectric material board. 本発明の第2実施形態に係るドライエッチング装置が備えるトレイ及び誘電体板を示す断面図。Sectional drawing which shows the tray and dielectric plate with which the dry etching apparatus which concerns on 2nd Embodiment of this invention is provided. トレイの平面図。The top view of a tray. 図12AのXII−XXII線での断面図。Sectional drawing in the XII-XXII line | wire of FIG. 12A. 誘電体板の平面図。The top view of a dielectric material board. 図13のXIII−XIII線での断面図。Sectional drawing in the XIII-XIII line | wire of FIG. トレイの第1の代案を示す平面図。The top view which shows the 1st alternative of a tray. トレイの第2の代案を示す平面図。The top view which shows the 2nd alternative of a tray. 本発明の第3実施形態に係るドライエッチング装置を示す模式的な断面図。The typical sectional view showing the dry etching device concerning a 3rd embodiment of the present invention. 図16の部分XVIIの部分拡大図。The elements on larger scale of the part XVII of FIG. トレイ及びガイドプレートの第1の代案を示す部分拡大断面図。The partial expanded sectional view which shows the 1st alternative of a tray and a guide plate. トレイ及びガイドプレートの第2の代案を示す部分拡大断面図。The partial expanded sectional view which shows the 2nd alternative of a tray and a guide plate. 本発明の第4実施形態に係るドライエッチング装置を示す模式的な断面図。The typical sectional view showing the dry etching device concerning a 4th embodiment of the present invention. 本発明の第5実施形態に係るドライエッチング装置を示す模式的な断面図。Typical sectional drawing which shows the dry etching apparatus which concerns on 5th Embodiment of this invention. 本発明の第6実施形態に係るドライエッチング装置を示す模式的な断面図。Typical sectional drawing which shows the dry etching apparatus which concerns on 6th Embodiment of this invention. 本発明の第7実施形態に係るドライエッチング装置を示す模式的な断面図。Typical sectional drawing which shows the dry etching apparatus which concerns on 7th Embodiment of this invention. 本発明の第8実施形態に係るドライエッチング装置を示す模式的な断面図。Typical sectional drawing which shows the dry etching apparatus which concerns on 8th Embodiment of this invention. 本発明の第9実施形態に係るドライエッチング装置を示す模式的な断面図。Typical sectional drawing which shows the dry etching apparatus which concerns on 9th Embodiment of this invention. 本発明の第9実施形態に係るドライエッチング装置が備えるトレイ及び誘電体板を示す模式的な斜視図。The typical perspective view showing the tray and dielectric board with which the dry etching apparatus concerning a 9th embodiment of the present invention is provided. 本発明の第9実施形態に係るドライエッチング装置が備えるトレイの平面図。The top view of the tray with which the dry etching apparatus which concerns on 9th Embodiment of this invention is provided. 図26AのXXVI−XXVI線での断面図。FIG. 26B is a sectional view taken along line XXVI-XXVI in FIG. 26A. 誘電体板の平面図。The top view of a dielectric material board. 図27AのXXVII−XXVII線での断面図。FIG. 27B is a sectional view taken along line XXVII-XXVII in FIG. 27A. バイアスパワーと基板温度の関係を示すグラフ。The graph which shows the relationship between bias power and substrate temperature. 比較例2におけるエッチング速度の分布を示すグラフ。9 is a graph showing the etching rate distribution in Comparative Example 2. 実験例におけるエッチング速度の分布を示すグラフ。The graph which shows distribution of the etching rate in an experiment example.

符号の説明Explanation of symbols

1 ドライエッチング装置
2 基板
2a 下面
3 チャンバ
3a ゲート
3b エッチングガス供給口
3c 排気口
4 天板
5 ICPコイル
6 マッチング回路
7 高周波電源
9 基板サセプタ
10 ロードドック室
12 エッチングガス供給源
13 真空排気装置
15 トレイ
15a トレイ本体
15b 上面
15c 下面
15d 孔壁
15e 位置決め切欠
15f 外周面
16 搬送アーム
16a 位置決め突起
17 駆動装置
18 昇降ピン
19,19A〜19D 基板収容孔
21 基板支持部
21a 上面
21b 先端面
21c 下面
22A,22B センサ
23 誘電体板
24 金属板
25 スペーサ板
26 ガイド筒体
27 アースシールド
28 トレイ支持面
29,29A〜29D 基板載置部
31 基板載置面
32 円環状突出部
33 円柱状突起
36 円形開口
38 外周面
40,40A,40B 静電吸着用電極
41 直流電源
42 抵抗
43,43A〜43F 直流電圧印加機構
44 供給孔
45,45A〜45D 伝熱ガス供給機構
46 伝熱ガス源
47 供給流路
48 流量計
49 流量制御バルブ
50 圧力計
51 排出流路
52 カットオフバルブ
53 バイパス流路
54 排気口
56,56A〜56D 高周波印加機構
57 高周波電源
58 可変容量コンデンサ
59 冷却機構
60 冷媒流路
61 冷媒循環装置
63 コントローラ
65 収容溝
67 ガイドプレート
67a 内周面
67b 下面
67c 上面
68 バイアス印加用電極
DESCRIPTION OF SYMBOLS 1 Dry etching apparatus 2 Substrate 2a Lower surface 3 Chamber 3a Gate 3b Etching gas supply port 3c Exhaust port 4 Top plate 5 ICP coil 6 Matching circuit 7 High frequency power supply 9 Substrate susceptor 10 Load dock chamber 12 Etching gas supply source 13 Vacuum exhaust device 15 Tray 15a tray body 15b upper surface 15c lower surface 15d hole wall 15e positioning notch 15f outer peripheral surface 16 transfer arm 16a positioning protrusion 17 driving device 18 lift pins 19, 19A to 19D substrate accommodation hole 21 substrate support portion 21a upper surface 21b distal end surface 21c lower surface 22A, 22B Sensor 23 Dielectric plate 24 Metal plate 25 Spacer plate 26 Guide cylinder 27 Ground shield 28 Tray support surface 29, 29A to 29D Substrate placement portion 31 Substrate placement surface 32 Annular protrusion 33 Cylindrical protrusion 36 Circular opening 38 Outer peripheral surface 40, 40A, 40B Electrostatic adsorption electrode 41 DC power supply 42 Resistance 43, 43A-43F DC voltage application mechanism 44 Supply hole 45, 45A-45D Heat transfer gas supply mechanism 46 Heat transfer gas source 47 Supply flow Channel 48 Flow meter 49 Flow control valve 50 Pressure gauge 51 Discharge flow path 52 Cut-off valve 53 Bypass flow path 54 Exhaust port 56, 56A to 56D High frequency application mechanism 57 High frequency power supply 58 Variable capacity capacitor 59 Cooling mechanism 60 Refrigerant flow path 61 Refrigerant Circulating device 63 Controller 65 Housing groove 67 Guide plate 67a Inner peripheral surface 67b Lower surface 67c Upper surface 68 Bias application electrode

Claims (26)

厚み方向に貫通する基板収容孔(19,19A〜19I)が設けられ、この基板収容孔の孔壁(15d)から突出し、前記基板収容孔内に収容された基板(2)の下面(2a)の外周縁部分を支持する基板支持部(21)を備えるトレイ(15)と、
前記トレイの下面(15c)を支持するトレイ支持部(28)と、このトレイ支持部から上向きに突出し、前記トレイの下面側から前記基板収容孔に挿入され、かつその上端面である基板載置面(31)に前記基板の下面が載置される基板載置部(29,29A〜29D)とを備え、前記基板を前記基板載置面に静電吸着するための静電吸着用電極(40,40A,40B)が内蔵された誘電体部材(23)と、
前記静電吸着用電極に直流電圧を印加する直流電圧印加機構(43,43A〜43F)と、
前記基板と前記基板載置面との間に伝熱ガスを供給する伝熱ガス供給機構(45,45A〜45D)と
を備えることを特徴とする、プラズマ処理装置。
Substrate accommodation holes (19, 19A to 19I) penetrating in the thickness direction are provided, projecting from the hole walls (15d) of the substrate accommodation holes, and the lower surface (2a) of the substrate (2) accommodated in the substrate accommodation holes A tray (15) comprising a substrate support (21) for supporting the outer peripheral edge portion of
A tray support portion (28) that supports the lower surface (15c) of the tray, and a substrate placement that protrudes upward from the tray support portion, is inserted into the substrate accommodation hole from the lower surface side of the tray, and is the upper end surface thereof A substrate placement portion (29, 29A to 29D) on which the lower surface of the substrate is placed on the surface (31), and an electrostatic adsorption electrode (for electrostatically attracting the substrate to the substrate placement surface) 40, 40A, 40B) with a built-in dielectric member (23);
A DC voltage application mechanism (43, 43A to 43F) for applying a DC voltage to the electrode for electrostatic attraction;
A plasma processing apparatus comprising: a heat transfer gas supply mechanism (45, 45A to 45D) for supplying a heat transfer gas between the substrate and the substrate mounting surface.
前記トレイの下面から前記基板支持部の上面(21a)までの距離(H1)は、前記トレイ支持部から前記基板載置面までの距離(H2)よりも短いことを特徴とする請求項1に記載のプラズマ処理装置。   The distance (H1) from the lower surface of the tray to the upper surface (21a) of the substrate support portion is shorter than the distance (H2) from the tray support portion to the substrate placement surface. The plasma processing apparatus as described. 上面に前記誘電体部材が固定された支持部材(24)と、
前記支持部材を冷却する冷却機構(59)と
をさらに備えることを特徴とする請求項1又は請求項2に記載のプラズマ処理装置。
A support member (24) having the dielectric member fixed to the upper surface;
The plasma processing apparatus according to claim 1, further comprising: a cooling mechanism that cools the support member.
前記基板支持部は、前記トレイの下面側から上面側に向けて、前記基板収容孔の孔壁からの突出量が増大していることを特徴とする請求項1から請求項3のいずれか1項に記載プラズマ処理装置。   The protrusion amount from the hole wall of the said board | substrate accommodation hole is increasing the said board | substrate support part from the lower surface side of the said tray toward the upper surface side. The plasma processing apparatus according to item. 前記基板載置部は、前記基板載置面側から前記トレイ支持部に向けて前記基板収容孔の貫通方向から見た外形寸法が増大していることを特徴とする請求項1から請求項4のいずれか1項に記載のプラズマ処理装置。   5. The outer dimensions of the substrate mounting portion are increased from the substrate mounting surface side toward the tray support portion when viewed from the penetration direction of the substrate receiving hole. The plasma processing apparatus of any one of these. 前記基板支持部は、前記基板収容孔の孔壁の全周に設けられた環状であることを特徴とする、請求項1から請求項5のいずれか1項に記載のプラズマ処理装置。   The plasma processing apparatus according to any one of claims 1 to 5, wherein the substrate support portion is an annular shape provided around the entire circumference of the hole wall of the substrate accommodation hole. 前記基板支持部は、前記基板収容孔の前記孔壁に周方向に間隔を開けて複数個設けられていることを特徴とする、請求項1から請求項5のいずれか1項に記載のプラズマ処理装置。   6. The plasma according to claim 1, wherein a plurality of the substrate support portions are provided in the hole wall of the substrate accommodation hole at intervals in the circumferential direction. Processing equipment. 前記基板載置部の外周面に、前記基板載置面から前記トレイ支持部に向けて延び、前記基板支持部が収容される収容溝(65)が形成されていることを特徴とする、請求項7に記載のプラズマ処理装置。   An accommodation groove (65) that extends from the substrate placement surface toward the tray support portion and accommodates the substrate support portion is formed on an outer peripheral surface of the substrate placement portion. Item 8. The plasma processing apparatus according to Item 7. 前記基板載置部を取り囲む環状であって、かつ内周面が下面から上面に向けて拡がる環状のガイドプレート(67)をさらに備え、
前記トレイの外周面は、下面側から上面側に向けて外形寸法が増大し、かつ前記トレイの下面を前記トレイ支持部に載置すると前記ガイドプレートの内周面と密接することを特徴とする、請求項1から請求項8のいずれか1項に記載のプラズマ処理装置。
An annular guide plate (67) that surrounds the substrate mounting portion and has an inner peripheral surface that extends from the lower surface toward the upper surface;
The outer peripheral surface of the tray is increased in outer dimension from the lower surface side to the upper surface side, and when the lower surface of the tray is placed on the tray support portion, the outer peripheral surface is in close contact with the inner peripheral surface of the guide plate. The plasma processing apparatus according to any one of claims 1 to 8.
前記直流電圧印加機構により印加される前記直流電圧に重畳して、バイアス電圧としての高周波を前記静電吸着用電極に印加する高周波印加機構(56A〜56D)をさらに備えることを特徴とする請求項1から請求項9のいずれか1項に記載のプラズマ処理装置。   The high frequency application mechanism (56A-56D) which superimposes on the said DC voltage applied by the said DC voltage application mechanism, and applies the high frequency as a bias voltage to the said electrode for electrostatic attraction is characterized by the above-mentioned. The plasma processing apparatus of any one of Claims 1-9. 前記誘電体部材に内蔵され、前記静電吸着用電極と電気的に絶縁されたバイアス印加用電極(68)と、
前記バイアス印加用電極に高周波を印加する高周波印加機構(56)と
をさらに備えることを特徴とする、請求項1から請求項9のいずれか1項に記載のプラズマ処理装置。
A bias application electrode (68) that is built in the dielectric member and is electrically insulated from the electrostatic adsorption electrode;
The plasma processing apparatus according to any one of claims 1 to 9, further comprising: a high-frequency application mechanism (56) configured to apply a high frequency to the bias application electrode.
前記静電吸着用電極は単極型であることを特徴とする、請求項1から請求項11のいずれか1項に記載のプラズマ処理装置。   The plasma processing apparatus according to claim 1, wherein the electrostatic adsorption electrode is a single electrode type. 前記静電吸着用電極は双極型であることを特徴とする、請求項1から請求項11のいずれか1項に記載のプラズマ処理装置。   The plasma processing apparatus according to claim 1, wherein the electrostatic adsorption electrode is a bipolar type. 前記トレイに前記基板収容孔が1個設けられ、
前記誘電体部材には前記基板載置部が1個設けられていることを特徴とする、請求項1から請求項13のいずれか1項に記載プラズマ処理装置。
One of the substrate accommodation holes is provided in the tray,
14. The plasma processing apparatus according to claim 1, wherein the dielectric member is provided with a single substrate mounting portion. 15.
前記トレイに前記基板収容孔が複数個設けられ、
前記誘電体部材は前記基板載置部を複数個備え、個々の前記基板載置部がそれぞれ個々の前記基板収容孔に挿入されることを特徴とする、請求項1から請求項13のいずれか1項に記載のプラズマ処理装置。
A plurality of the substrate accommodation holes are provided in the tray,
The dielectric member includes a plurality of the substrate mounting portions, and each of the substrate mounting portions is inserted into each of the substrate receiving holes. 2. The plasma processing apparatus according to item 1.
前記基板載置部は、前記基板載置面の外周縁から上向きに突出し、その上端面で前記基板の下面を支持する環状突出部(32)を備え、
前記基板の下面と前記環状突出部で囲まれた空間に前記伝熱ガス供給機構によって前記伝熱ガスが供給されることを特徴とする、請求項15に記載のプラズマ処理装置。
The substrate mounting portion includes an annular protrusion (32) that protrudes upward from an outer peripheral edge of the substrate mounting surface and supports the lower surface of the substrate at an upper end surface thereof.
The plasma processing apparatus according to claim 15, wherein the heat transfer gas is supplied by the heat transfer gas supply mechanism into a space surrounded by a lower surface of the substrate and the annular protrusion.
前記基板載置部毎に、個別に制御可能な前記伝熱ガス供給機構が設けられていることを特徴とする、請求項15又は請求項16に記載のプラズマ処理装置。   The plasma processing apparatus according to claim 15, wherein the heat transfer gas supply mechanism that can be individually controlled is provided for each of the substrate placement units. 前記複数の基板載置部に電気的に絶縁された前記静電吸着用電極がそれぞれ内蔵されていることを特徴とする請求項15から請求項17のいずれか1項に記載プラズマ処理装置。   18. The plasma processing apparatus according to claim 15, wherein the electrostatic chucking electrodes that are electrically insulated are respectively incorporated in the plurality of substrate placement units. 前記静電吸着用電極毎に、個別に制御可能な前記直流電圧印加機構が設けられていることを特徴とする、請求項18に記載のプラズマ処理装置。   19. The plasma processing apparatus according to claim 18, wherein the DC voltage application mechanism that can be individually controlled is provided for each of the electrostatic adsorption electrodes. 前記静電吸着用電極毎に、前記直流電圧印加機構により印加される前記直流電圧に重畳して、プラズマ発生用の高周波を前記静電吸着用電圧に印加する個別に制御可能な高周波印加機構をさらに備えることを特徴とする、請求項18又は請求項19に記載のプラズマ処理装置。   An individually controllable high frequency application mechanism that applies a high frequency for plasma generation to the electrostatic adsorption voltage superimposed on the DC voltage applied by the DC voltage application mechanism for each of the electrostatic adsorption electrodes The plasma processing apparatus according to claim 18 or 19, further comprising: 厚み方向に貫通する基板収容孔(19,19A〜19D)が設けられ、この基板収容孔の孔壁(15d)から突出する基板支持部(21)を有するトレイ(15)を準備し、
前記トレイの前記基板収容孔に基板(2)を収容し、前記トレイの下面側から見ると前記基板収容孔により前記基板の下面(2a)が露出するように、前記基板支持部で前記基板の下面(2a)の外周縁部分を支持させ、
真空容器(3)内に収容された誘電体部材(23)の上方に前記基板を収容した前記トレイを配置し、
前記トレイを前記誘電体部材に向けて降下させ、前記トレイの下面を前記絶縁部材のトレイ支持部(28)で支持させると共に、前記トレイ支持部から突出する基板載置部(29,29A〜29D)を前記トレイの下面側から前記基板収容孔に侵入させ、前記基板載置部の上端面である基板載置面(31)に基板の下面を載置し、
前記誘電体部材に内蔵された静電吸着用電極(40,40A,40B)に直流電圧を印加して、前記基板載置面に前記基板を静電吸着させ、
前記基板の下面と前記基板載置面との間に伝熱ガスを供給し、
前記真空容器内にプラズマを発生させる、プラズマ処理方法。
A tray (15) having a substrate support portion (21) provided with substrate accommodation holes (19, 19A to 19D) penetrating in the thickness direction and projecting from the hole wall (15d) of the substrate accommodation hole is prepared,
A substrate (2) is accommodated in the substrate accommodation hole of the tray, and when viewed from the lower surface side of the tray, the lower surface (2a) of the substrate is exposed by the substrate accommodation hole. Support the outer peripheral edge of the lower surface (2a),
Placing the tray containing the substrate above the dielectric member (23) housed in the vacuum vessel (3);
The tray is lowered toward the dielectric member, the lower surface of the tray is supported by the tray support portion (28) of the insulating member, and the substrate placement portions (29, 29A to 29D) protruding from the tray support portion. ) From the lower surface side of the tray into the substrate accommodation hole, and the lower surface of the substrate is placed on the substrate placement surface (31) which is the upper end surface of the substrate placement portion,
Applying a DC voltage to the electrostatic chucking electrodes (40, 40A, 40B) incorporated in the dielectric member to electrostatically attract the substrate to the substrate mounting surface;
Supplying a heat transfer gas between the lower surface of the substrate and the substrate mounting surface;
A plasma processing method for generating plasma in the vacuum vessel.
前記真空容器内で前記プラズマが発生中に、前記誘電体部材が固定された支持部材を冷却することを特徴とする請求項21に記載のプラズマ処理方法。   The plasma processing method according to claim 21, wherein the support member to which the dielectric member is fixed is cooled while the plasma is generated in the vacuum vessel. 前記トレイには前記基板収容孔が複数個設けられると共に、前記誘電体部材は前記基板載置部を複数個備え、
前記基板を前記誘電体部材に載置すると、個々の前記基板載置部がそれぞれ個々の基板収容孔に挿入されることを特徴とする、請求項21又は請求項22に記載のプラズマ処理方法。
The tray is provided with a plurality of the substrate accommodation holes, and the dielectric member includes a plurality of the substrate mounting portions,
23. The plasma processing method according to claim 21, wherein when the substrate is placed on the dielectric member, each of the substrate placement portions is inserted into each of the substrate accommodation holes.
前記基板の下面と前記基板載置面との間への前記伝熱ガスの供給を、前記基板載置部毎に個別に制御することを特徴とする請求項23に記載のプラズマ処理装置。   24. The plasma processing apparatus according to claim 23, wherein supply of the heat transfer gas between the lower surface of the substrate and the substrate mounting surface is individually controlled for each of the substrate mounting portions. 前記複数の基板載置部に電気的に絶縁された前記静電吸着用電極がそれぞれ内蔵され、
個々の前記基板載置部に内蔵された前記静電吸着用電極に印加する直流電圧を個別に制御することを特徴とする請求項23又は請求項24に記載のプラズマ処理装置。
The electrostatic chucking electrodes that are electrically insulated from each of the plurality of substrate mounting parts are incorporated, respectively.
25. The plasma processing apparatus according to claim 23, wherein a direct-current voltage applied to the electrostatic attraction electrode built in each of the substrate placement units is individually controlled.
前記複数の基板載置部に電気的に絶縁された前記静電吸着用電極がそれぞれ内蔵され、
個々の前記基板載置部に内蔵された前記静電吸着用電極にバイアス電圧としての高周波を印加し、かつ個々の前記基板載置部に内蔵された前記静電吸着用電極に印加される高周波を個別に制御することを特徴とする請求項23から請求項25のいずれか1項に記載のプラズマ処理装置。
The electrostatic chucking electrodes that are electrically insulated from each of the plurality of substrate mounting parts are incorporated, respectively.
A high frequency applied as a bias voltage to the electrostatic chucking electrode built in each of the substrate mounting parts and applied to the electrostatic chucking electrode built in each of the substrate mounting parts The plasma processing apparatus according to any one of claims 23 to 25, wherein the plasma processing apparatuses are individually controlled.
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